1
2
3
4
5
6
7
8
9
10
11
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15
16#include <linux/kernel.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/vmalloc.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/dma-mapping.h>
29#include <linux/bitops.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <linux/delay.h>
33#include <asm/byteorder.h>
34#include <asm/page.h>
35#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
38#include <linux/if_vlan.h>
39#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
40#define BCM_VLAN 1
41#endif
42#include <net/ip.h>
43#include <net/tcp.h>
44#include <net/checksum.h>
45#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
48#include <linux/cache.h>
49#include <linux/firmware.h>
50#include <linux/log2.h>
51#include <linux/list.h>
52
53#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
54#define BCM_CNIC 1
55#include "cnic_if.h"
56#endif
57#include "bnx2.h"
58#include "bnx2_fw.h"
59
60#define DRV_MODULE_NAME "bnx2"
61#define PFX DRV_MODULE_NAME ": "
62#define DRV_MODULE_VERSION "2.0.3"
63#define DRV_MODULE_RELDATE "Dec 03, 2009"
64#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j3.fw"
65#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
66#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j3.fw"
67#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j3.fw"
68#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j3.fw"
69
70#define RUN_AT(x) (jiffies + (x))
71
72
73#define TX_TIMEOUT (5*HZ)
74
75static char version[] __devinitdata =
76 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
77
78MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
79MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
80MODULE_LICENSE("GPL");
81MODULE_VERSION(DRV_MODULE_VERSION);
82MODULE_FIRMWARE(FW_MIPS_FILE_06);
83MODULE_FIRMWARE(FW_RV2P_FILE_06);
84MODULE_FIRMWARE(FW_MIPS_FILE_09);
85MODULE_FIRMWARE(FW_RV2P_FILE_09);
86MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
87
88static int disable_msi = 0;
89
90module_param(disable_msi, int, 0);
91MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
92
93typedef enum {
94 BCM5706 = 0,
95 NC370T,
96 NC370I,
97 BCM5706S,
98 NC370F,
99 BCM5708,
100 BCM5708S,
101 BCM5709,
102 BCM5709S,
103 BCM5716,
104 BCM5716S,
105} board_t;
106
107
108static struct {
109 char *name;
110} board_info[] __devinitdata = {
111 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
112 { "HP NC370T Multifunction Gigabit Server Adapter" },
113 { "HP NC370i Multifunction Gigabit Server Adapter" },
114 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
115 { "HP NC370F Multifunction Gigabit Server Adapter" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
117 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
118 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
119 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
120 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
121 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
122 };
123
124static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
126 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
128 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
131 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
133 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
134 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
135 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
137 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
139 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
141 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
143 { PCI_VENDOR_ID_BROADCOM, 0x163b,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
145 { PCI_VENDOR_ID_BROADCOM, 0x163c,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
147 { 0, }
148};
149
150static const struct flash_spec flash_table[] =
151{
152#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
153#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
154
155 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
156 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
157 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
158 "EEPROM - slow"},
159
160 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
161 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
162 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
163 "Entry 0001"},
164
165
166 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
167 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
168 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
169 "Non-buffered flash (128kB)"},
170
171
172 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
175 "Non-buffered flash (256kB)"},
176
177 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
178 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
179 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
180 "Entry 0100"},
181
182 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
183 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
184 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
185 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
186
187 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
188 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
189 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
190 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
191
192
193 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
194 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
195 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
196 "Non-buffered flash (64kB)"},
197
198 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
199 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
200 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
201 "EEPROM - fast"},
202
203 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
204 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
205 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
206 "Entry 1001"},
207
208 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
210 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
211 "Entry 1010"},
212
213 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
214 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
215 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
216 "Buffered flash (128kB)"},
217
218 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
221 "Entry 1100"},
222
223 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
226 "Entry 1101"},
227
228 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
230 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
231 "Entry 1110 (Atmel)"},
232
233 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
234 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
235 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
236 "Buffered flash (256kB)"},
237};
238
239static const struct flash_spec flash_5709 = {
240 .flags = BNX2_NV_BUFFERED,
241 .page_bits = BCM5709_FLASH_PAGE_BITS,
242 .page_size = BCM5709_FLASH_PAGE_SIZE,
243 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
244 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
245 .name = "5709 Buffered flash (256kB)",
246};
247
248MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
249
250static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
251{
252 u32 diff;
253
254 smp_mb();
255
256
257
258
259 diff = txr->tx_prod - txr->tx_cons;
260 if (unlikely(diff >= TX_DESC_CNT)) {
261 diff &= 0xffff;
262 if (diff == TX_DESC_CNT)
263 diff = MAX_TX_DESC_CNT;
264 }
265 return (bp->tx_ring_size - diff);
266}
267
268static u32
269bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
270{
271 u32 val;
272
273 spin_lock_bh(&bp->indirect_lock);
274 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
275 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
276 spin_unlock_bh(&bp->indirect_lock);
277 return val;
278}
279
280static void
281bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
282{
283 spin_lock_bh(&bp->indirect_lock);
284 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
285 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
286 spin_unlock_bh(&bp->indirect_lock);
287}
288
289static void
290bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
291{
292 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
293}
294
295static u32
296bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
297{
298 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
299}
300
301static void
302bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
303{
304 offset += cid_addr;
305 spin_lock_bh(&bp->indirect_lock);
306 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
307 int i;
308
309 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
310 REG_WR(bp, BNX2_CTX_CTX_CTRL,
311 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
312 for (i = 0; i < 5; i++) {
313 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
314 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
315 break;
316 udelay(5);
317 }
318 } else {
319 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
320 REG_WR(bp, BNX2_CTX_DATA, val);
321 }
322 spin_unlock_bh(&bp->indirect_lock);
323}
324
325#ifdef BCM_CNIC
326static int
327bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
328{
329 struct bnx2 *bp = netdev_priv(dev);
330 struct drv_ctl_io *io = &info->data.io;
331
332 switch (info->cmd) {
333 case DRV_CTL_IO_WR_CMD:
334 bnx2_reg_wr_ind(bp, io->offset, io->data);
335 break;
336 case DRV_CTL_IO_RD_CMD:
337 io->data = bnx2_reg_rd_ind(bp, io->offset);
338 break;
339 case DRV_CTL_CTX_WR_CMD:
340 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
341 break;
342 default:
343 return -EINVAL;
344 }
345 return 0;
346}
347
348static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
349{
350 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
351 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
352 int sb_id;
353
354 if (bp->flags & BNX2_FLAG_USING_MSIX) {
355 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
356 bnapi->cnic_present = 0;
357 sb_id = bp->irq_nvecs;
358 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
359 } else {
360 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
361 bnapi->cnic_tag = bnapi->last_status_idx;
362 bnapi->cnic_present = 1;
363 sb_id = 0;
364 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
365 }
366
367 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
368 cp->irq_arr[0].status_blk = (void *)
369 ((unsigned long) bnapi->status_blk.msi +
370 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
371 cp->irq_arr[0].status_blk_num = sb_id;
372 cp->num_irq = 1;
373}
374
375static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
376 void *data)
377{
378 struct bnx2 *bp = netdev_priv(dev);
379 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
380
381 if (ops == NULL)
382 return -EINVAL;
383
384 if (cp->drv_state & CNIC_DRV_STATE_REGD)
385 return -EBUSY;
386
387 bp->cnic_data = data;
388 rcu_assign_pointer(bp->cnic_ops, ops);
389
390 cp->num_irq = 0;
391 cp->drv_state = CNIC_DRV_STATE_REGD;
392
393 bnx2_setup_cnic_irq_info(bp);
394
395 return 0;
396}
397
398static int bnx2_unregister_cnic(struct net_device *dev)
399{
400 struct bnx2 *bp = netdev_priv(dev);
401 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
402 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
403
404 mutex_lock(&bp->cnic_lock);
405 cp->drv_state = 0;
406 bnapi->cnic_present = 0;
407 rcu_assign_pointer(bp->cnic_ops, NULL);
408 mutex_unlock(&bp->cnic_lock);
409 synchronize_rcu();
410 return 0;
411}
412
413struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
414{
415 struct bnx2 *bp = netdev_priv(dev);
416 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
417
418 cp->drv_owner = THIS_MODULE;
419 cp->chip_id = bp->chip_id;
420 cp->pdev = bp->pdev;
421 cp->io_base = bp->regview;
422 cp->drv_ctl = bnx2_drv_ctl;
423 cp->drv_register_cnic = bnx2_register_cnic;
424 cp->drv_unregister_cnic = bnx2_unregister_cnic;
425
426 return cp;
427}
428EXPORT_SYMBOL(bnx2_cnic_probe);
429
430static void
431bnx2_cnic_stop(struct bnx2 *bp)
432{
433 struct cnic_ops *c_ops;
434 struct cnic_ctl_info info;
435
436 mutex_lock(&bp->cnic_lock);
437 c_ops = bp->cnic_ops;
438 if (c_ops) {
439 info.cmd = CNIC_CTL_STOP_CMD;
440 c_ops->cnic_ctl(bp->cnic_data, &info);
441 }
442 mutex_unlock(&bp->cnic_lock);
443}
444
445static void
446bnx2_cnic_start(struct bnx2 *bp)
447{
448 struct cnic_ops *c_ops;
449 struct cnic_ctl_info info;
450
451 mutex_lock(&bp->cnic_lock);
452 c_ops = bp->cnic_ops;
453 if (c_ops) {
454 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
455 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
456
457 bnapi->cnic_tag = bnapi->last_status_idx;
458 }
459 info.cmd = CNIC_CTL_START_CMD;
460 c_ops->cnic_ctl(bp->cnic_data, &info);
461 }
462 mutex_unlock(&bp->cnic_lock);
463}
464
465#else
466
467static void
468bnx2_cnic_stop(struct bnx2 *bp)
469{
470}
471
472static void
473bnx2_cnic_start(struct bnx2 *bp)
474{
475}
476
477#endif
478
479static int
480bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
481{
482 u32 val1;
483 int i, ret;
484
485 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
486 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
487 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
488
489 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
490 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
491
492 udelay(40);
493 }
494
495 val1 = (bp->phy_addr << 21) | (reg << 16) |
496 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
497 BNX2_EMAC_MDIO_COMM_START_BUSY;
498 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
499
500 for (i = 0; i < 50; i++) {
501 udelay(10);
502
503 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
504 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
505 udelay(5);
506
507 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
508 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
509
510 break;
511 }
512 }
513
514 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
515 *val = 0x0;
516 ret = -EBUSY;
517 }
518 else {
519 *val = val1;
520 ret = 0;
521 }
522
523 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
524 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
525 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
526
527 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
528 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
529
530 udelay(40);
531 }
532
533 return ret;
534}
535
536static int
537bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
538{
539 u32 val1;
540 int i, ret;
541
542 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
543 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
544 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
545
546 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
547 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
548
549 udelay(40);
550 }
551
552 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
553 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
554 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
555 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
556
557 for (i = 0; i < 50; i++) {
558 udelay(10);
559
560 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
561 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
562 udelay(5);
563 break;
564 }
565 }
566
567 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
568 ret = -EBUSY;
569 else
570 ret = 0;
571
572 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
573 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
574 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
575
576 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
577 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
578
579 udelay(40);
580 }
581
582 return ret;
583}
584
585static void
586bnx2_disable_int(struct bnx2 *bp)
587{
588 int i;
589 struct bnx2_napi *bnapi;
590
591 for (i = 0; i < bp->irq_nvecs; i++) {
592 bnapi = &bp->bnx2_napi[i];
593 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
594 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
595 }
596 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
597}
598
599static void
600bnx2_enable_int(struct bnx2 *bp)
601{
602 int i;
603 struct bnx2_napi *bnapi;
604
605 for (i = 0; i < bp->irq_nvecs; i++) {
606 bnapi = &bp->bnx2_napi[i];
607
608 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
609 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
610 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
611 bnapi->last_status_idx);
612
613 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
614 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
615 bnapi->last_status_idx);
616 }
617 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
618}
619
620static void
621bnx2_disable_int_sync(struct bnx2 *bp)
622{
623 int i;
624
625 atomic_inc(&bp->intr_sem);
626 if (!netif_running(bp->dev))
627 return;
628
629 bnx2_disable_int(bp);
630 for (i = 0; i < bp->irq_nvecs; i++)
631 synchronize_irq(bp->irq_tbl[i].vector);
632}
633
634static void
635bnx2_napi_disable(struct bnx2 *bp)
636{
637 int i;
638
639 for (i = 0; i < bp->irq_nvecs; i++)
640 napi_disable(&bp->bnx2_napi[i].napi);
641}
642
643static void
644bnx2_napi_enable(struct bnx2 *bp)
645{
646 int i;
647
648 for (i = 0; i < bp->irq_nvecs; i++)
649 napi_enable(&bp->bnx2_napi[i].napi);
650}
651
652static void
653bnx2_netif_stop(struct bnx2 *bp)
654{
655 bnx2_cnic_stop(bp);
656 if (netif_running(bp->dev)) {
657 int i;
658
659 bnx2_napi_disable(bp);
660 netif_tx_disable(bp->dev);
661
662 for (i = 0; i < bp->dev->num_tx_queues; i++) {
663 struct netdev_queue *txq;
664
665 txq = netdev_get_tx_queue(bp->dev, i);
666 txq->trans_start = jiffies;
667 }
668 }
669 bnx2_disable_int_sync(bp);
670}
671
672static void
673bnx2_netif_start(struct bnx2 *bp)
674{
675 if (atomic_dec_and_test(&bp->intr_sem)) {
676 if (netif_running(bp->dev)) {
677 netif_tx_wake_all_queues(bp->dev);
678 bnx2_napi_enable(bp);
679 bnx2_enable_int(bp);
680 bnx2_cnic_start(bp);
681 }
682 }
683}
684
685static void
686bnx2_free_tx_mem(struct bnx2 *bp)
687{
688 int i;
689
690 for (i = 0; i < bp->num_tx_rings; i++) {
691 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
692 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
693
694 if (txr->tx_desc_ring) {
695 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
696 txr->tx_desc_ring,
697 txr->tx_desc_mapping);
698 txr->tx_desc_ring = NULL;
699 }
700 kfree(txr->tx_buf_ring);
701 txr->tx_buf_ring = NULL;
702 }
703}
704
705static void
706bnx2_free_rx_mem(struct bnx2 *bp)
707{
708 int i;
709
710 for (i = 0; i < bp->num_rx_rings; i++) {
711 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
712 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
713 int j;
714
715 for (j = 0; j < bp->rx_max_ring; j++) {
716 if (rxr->rx_desc_ring[j])
717 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
718 rxr->rx_desc_ring[j],
719 rxr->rx_desc_mapping[j]);
720 rxr->rx_desc_ring[j] = NULL;
721 }
722 vfree(rxr->rx_buf_ring);
723 rxr->rx_buf_ring = NULL;
724
725 for (j = 0; j < bp->rx_max_pg_ring; j++) {
726 if (rxr->rx_pg_desc_ring[j])
727 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
728 rxr->rx_pg_desc_ring[j],
729 rxr->rx_pg_desc_mapping[j]);
730 rxr->rx_pg_desc_ring[j] = NULL;
731 }
732 vfree(rxr->rx_pg_ring);
733 rxr->rx_pg_ring = NULL;
734 }
735}
736
737static int
738bnx2_alloc_tx_mem(struct bnx2 *bp)
739{
740 int i;
741
742 for (i = 0; i < bp->num_tx_rings; i++) {
743 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
744 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
745
746 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
747 if (txr->tx_buf_ring == NULL)
748 return -ENOMEM;
749
750 txr->tx_desc_ring =
751 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
752 &txr->tx_desc_mapping);
753 if (txr->tx_desc_ring == NULL)
754 return -ENOMEM;
755 }
756 return 0;
757}
758
759static int
760bnx2_alloc_rx_mem(struct bnx2 *bp)
761{
762 int i;
763
764 for (i = 0; i < bp->num_rx_rings; i++) {
765 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
766 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
767 int j;
768
769 rxr->rx_buf_ring =
770 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
771 if (rxr->rx_buf_ring == NULL)
772 return -ENOMEM;
773
774 memset(rxr->rx_buf_ring, 0,
775 SW_RXBD_RING_SIZE * bp->rx_max_ring);
776
777 for (j = 0; j < bp->rx_max_ring; j++) {
778 rxr->rx_desc_ring[j] =
779 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
780 &rxr->rx_desc_mapping[j]);
781 if (rxr->rx_desc_ring[j] == NULL)
782 return -ENOMEM;
783
784 }
785
786 if (bp->rx_pg_ring_size) {
787 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
788 bp->rx_max_pg_ring);
789 if (rxr->rx_pg_ring == NULL)
790 return -ENOMEM;
791
792 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
793 bp->rx_max_pg_ring);
794 }
795
796 for (j = 0; j < bp->rx_max_pg_ring; j++) {
797 rxr->rx_pg_desc_ring[j] =
798 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
799 &rxr->rx_pg_desc_mapping[j]);
800 if (rxr->rx_pg_desc_ring[j] == NULL)
801 return -ENOMEM;
802
803 }
804 }
805 return 0;
806}
807
808static void
809bnx2_free_mem(struct bnx2 *bp)
810{
811 int i;
812 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
813
814 bnx2_free_tx_mem(bp);
815 bnx2_free_rx_mem(bp);
816
817 for (i = 0; i < bp->ctx_pages; i++) {
818 if (bp->ctx_blk[i]) {
819 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
820 bp->ctx_blk[i],
821 bp->ctx_blk_mapping[i]);
822 bp->ctx_blk[i] = NULL;
823 }
824 }
825 if (bnapi->status_blk.msi) {
826 pci_free_consistent(bp->pdev, bp->status_stats_size,
827 bnapi->status_blk.msi,
828 bp->status_blk_mapping);
829 bnapi->status_blk.msi = NULL;
830 bp->stats_blk = NULL;
831 }
832}
833
834static int
835bnx2_alloc_mem(struct bnx2 *bp)
836{
837 int i, status_blk_size, err;
838 struct bnx2_napi *bnapi;
839 void *status_blk;
840
841
842 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
843 if (bp->flags & BNX2_FLAG_MSIX_CAP)
844 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
845 BNX2_SBLK_MSIX_ALIGN_SIZE);
846 bp->status_stats_size = status_blk_size +
847 sizeof(struct statistics_block);
848
849 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
850 &bp->status_blk_mapping);
851 if (status_blk == NULL)
852 goto alloc_mem_err;
853
854 memset(status_blk, 0, bp->status_stats_size);
855
856 bnapi = &bp->bnx2_napi[0];
857 bnapi->status_blk.msi = status_blk;
858 bnapi->hw_tx_cons_ptr =
859 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
860 bnapi->hw_rx_cons_ptr =
861 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
862 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
863 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
864 struct status_block_msix *sblk;
865
866 bnapi = &bp->bnx2_napi[i];
867
868 sblk = (void *) (status_blk +
869 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
870 bnapi->status_blk.msix = sblk;
871 bnapi->hw_tx_cons_ptr =
872 &sblk->status_tx_quick_consumer_index;
873 bnapi->hw_rx_cons_ptr =
874 &sblk->status_rx_quick_consumer_index;
875 bnapi->int_num = i << 24;
876 }
877 }
878
879 bp->stats_blk = status_blk + status_blk_size;
880
881 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
882
883 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
884 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
885 if (bp->ctx_pages == 0)
886 bp->ctx_pages = 1;
887 for (i = 0; i < bp->ctx_pages; i++) {
888 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
889 BCM_PAGE_SIZE,
890 &bp->ctx_blk_mapping[i]);
891 if (bp->ctx_blk[i] == NULL)
892 goto alloc_mem_err;
893 }
894 }
895
896 err = bnx2_alloc_rx_mem(bp);
897 if (err)
898 goto alloc_mem_err;
899
900 err = bnx2_alloc_tx_mem(bp);
901 if (err)
902 goto alloc_mem_err;
903
904 return 0;
905
906alloc_mem_err:
907 bnx2_free_mem(bp);
908 return -ENOMEM;
909}
910
911static void
912bnx2_report_fw_link(struct bnx2 *bp)
913{
914 u32 fw_link_status = 0;
915
916 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
917 return;
918
919 if (bp->link_up) {
920 u32 bmsr;
921
922 switch (bp->line_speed) {
923 case SPEED_10:
924 if (bp->duplex == DUPLEX_HALF)
925 fw_link_status = BNX2_LINK_STATUS_10HALF;
926 else
927 fw_link_status = BNX2_LINK_STATUS_10FULL;
928 break;
929 case SPEED_100:
930 if (bp->duplex == DUPLEX_HALF)
931 fw_link_status = BNX2_LINK_STATUS_100HALF;
932 else
933 fw_link_status = BNX2_LINK_STATUS_100FULL;
934 break;
935 case SPEED_1000:
936 if (bp->duplex == DUPLEX_HALF)
937 fw_link_status = BNX2_LINK_STATUS_1000HALF;
938 else
939 fw_link_status = BNX2_LINK_STATUS_1000FULL;
940 break;
941 case SPEED_2500:
942 if (bp->duplex == DUPLEX_HALF)
943 fw_link_status = BNX2_LINK_STATUS_2500HALF;
944 else
945 fw_link_status = BNX2_LINK_STATUS_2500FULL;
946 break;
947 }
948
949 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
950
951 if (bp->autoneg) {
952 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
953
954 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
955 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
956
957 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
958 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
959 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
960 else
961 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
962 }
963 }
964 else
965 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
966
967 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
968}
969
970static char *
971bnx2_xceiver_str(struct bnx2 *bp)
972{
973 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
974 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
975 "Copper"));
976}
977
978static void
979bnx2_report_link(struct bnx2 *bp)
980{
981 if (bp->link_up) {
982 netif_carrier_on(bp->dev);
983 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
984 bnx2_xceiver_str(bp));
985
986 printk("%d Mbps ", bp->line_speed);
987
988 if (bp->duplex == DUPLEX_FULL)
989 printk("full duplex");
990 else
991 printk("half duplex");
992
993 if (bp->flow_ctrl) {
994 if (bp->flow_ctrl & FLOW_CTRL_RX) {
995 printk(", receive ");
996 if (bp->flow_ctrl & FLOW_CTRL_TX)
997 printk("& transmit ");
998 }
999 else {
1000 printk(", transmit ");
1001 }
1002 printk("flow control ON");
1003 }
1004 printk("\n");
1005 }
1006 else {
1007 netif_carrier_off(bp->dev);
1008 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
1009 bnx2_xceiver_str(bp));
1010 }
1011
1012 bnx2_report_fw_link(bp);
1013}
1014
1015static void
1016bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1017{
1018 u32 local_adv, remote_adv;
1019
1020 bp->flow_ctrl = 0;
1021 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1022 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1023
1024 if (bp->duplex == DUPLEX_FULL) {
1025 bp->flow_ctrl = bp->req_flow_ctrl;
1026 }
1027 return;
1028 }
1029
1030 if (bp->duplex != DUPLEX_FULL) {
1031 return;
1032 }
1033
1034 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1035 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1036 u32 val;
1037
1038 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1039 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1040 bp->flow_ctrl |= FLOW_CTRL_TX;
1041 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1042 bp->flow_ctrl |= FLOW_CTRL_RX;
1043 return;
1044 }
1045
1046 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1047 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1048
1049 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1050 u32 new_local_adv = 0;
1051 u32 new_remote_adv = 0;
1052
1053 if (local_adv & ADVERTISE_1000XPAUSE)
1054 new_local_adv |= ADVERTISE_PAUSE_CAP;
1055 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1056 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1057 if (remote_adv & ADVERTISE_1000XPAUSE)
1058 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1059 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1060 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1061
1062 local_adv = new_local_adv;
1063 remote_adv = new_remote_adv;
1064 }
1065
1066
1067 if (local_adv & ADVERTISE_PAUSE_CAP) {
1068 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1069 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1070 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1071 }
1072 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1073 bp->flow_ctrl = FLOW_CTRL_RX;
1074 }
1075 }
1076 else {
1077 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1078 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1079 }
1080 }
1081 }
1082 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1083 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1084 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1085
1086 bp->flow_ctrl = FLOW_CTRL_TX;
1087 }
1088 }
1089}
1090
1091static int
1092bnx2_5709s_linkup(struct bnx2 *bp)
1093{
1094 u32 val, speed;
1095
1096 bp->link_up = 1;
1097
1098 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1099 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1100 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1101
1102 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1103 bp->line_speed = bp->req_line_speed;
1104 bp->duplex = bp->req_duplex;
1105 return 0;
1106 }
1107 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1108 switch (speed) {
1109 case MII_BNX2_GP_TOP_AN_SPEED_10:
1110 bp->line_speed = SPEED_10;
1111 break;
1112 case MII_BNX2_GP_TOP_AN_SPEED_100:
1113 bp->line_speed = SPEED_100;
1114 break;
1115 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1116 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1117 bp->line_speed = SPEED_1000;
1118 break;
1119 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1120 bp->line_speed = SPEED_2500;
1121 break;
1122 }
1123 if (val & MII_BNX2_GP_TOP_AN_FD)
1124 bp->duplex = DUPLEX_FULL;
1125 else
1126 bp->duplex = DUPLEX_HALF;
1127 return 0;
1128}
1129
1130static int
1131bnx2_5708s_linkup(struct bnx2 *bp)
1132{
1133 u32 val;
1134
1135 bp->link_up = 1;
1136 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1137 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1138 case BCM5708S_1000X_STAT1_SPEED_10:
1139 bp->line_speed = SPEED_10;
1140 break;
1141 case BCM5708S_1000X_STAT1_SPEED_100:
1142 bp->line_speed = SPEED_100;
1143 break;
1144 case BCM5708S_1000X_STAT1_SPEED_1G:
1145 bp->line_speed = SPEED_1000;
1146 break;
1147 case BCM5708S_1000X_STAT1_SPEED_2G5:
1148 bp->line_speed = SPEED_2500;
1149 break;
1150 }
1151 if (val & BCM5708S_1000X_STAT1_FD)
1152 bp->duplex = DUPLEX_FULL;
1153 else
1154 bp->duplex = DUPLEX_HALF;
1155
1156 return 0;
1157}
1158
1159static int
1160bnx2_5706s_linkup(struct bnx2 *bp)
1161{
1162 u32 bmcr, local_adv, remote_adv, common;
1163
1164 bp->link_up = 1;
1165 bp->line_speed = SPEED_1000;
1166
1167 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1168 if (bmcr & BMCR_FULLDPLX) {
1169 bp->duplex = DUPLEX_FULL;
1170 }
1171 else {
1172 bp->duplex = DUPLEX_HALF;
1173 }
1174
1175 if (!(bmcr & BMCR_ANENABLE)) {
1176 return 0;
1177 }
1178
1179 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1180 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1181
1182 common = local_adv & remote_adv;
1183 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1184
1185 if (common & ADVERTISE_1000XFULL) {
1186 bp->duplex = DUPLEX_FULL;
1187 }
1188 else {
1189 bp->duplex = DUPLEX_HALF;
1190 }
1191 }
1192
1193 return 0;
1194}
1195
1196static int
1197bnx2_copper_linkup(struct bnx2 *bp)
1198{
1199 u32 bmcr;
1200
1201 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1202 if (bmcr & BMCR_ANENABLE) {
1203 u32 local_adv, remote_adv, common;
1204
1205 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1206 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1207
1208 common = local_adv & (remote_adv >> 2);
1209 if (common & ADVERTISE_1000FULL) {
1210 bp->line_speed = SPEED_1000;
1211 bp->duplex = DUPLEX_FULL;
1212 }
1213 else if (common & ADVERTISE_1000HALF) {
1214 bp->line_speed = SPEED_1000;
1215 bp->duplex = DUPLEX_HALF;
1216 }
1217 else {
1218 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1219 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1220
1221 common = local_adv & remote_adv;
1222 if (common & ADVERTISE_100FULL) {
1223 bp->line_speed = SPEED_100;
1224 bp->duplex = DUPLEX_FULL;
1225 }
1226 else if (common & ADVERTISE_100HALF) {
1227 bp->line_speed = SPEED_100;
1228 bp->duplex = DUPLEX_HALF;
1229 }
1230 else if (common & ADVERTISE_10FULL) {
1231 bp->line_speed = SPEED_10;
1232 bp->duplex = DUPLEX_FULL;
1233 }
1234 else if (common & ADVERTISE_10HALF) {
1235 bp->line_speed = SPEED_10;
1236 bp->duplex = DUPLEX_HALF;
1237 }
1238 else {
1239 bp->line_speed = 0;
1240 bp->link_up = 0;
1241 }
1242 }
1243 }
1244 else {
1245 if (bmcr & BMCR_SPEED100) {
1246 bp->line_speed = SPEED_100;
1247 }
1248 else {
1249 bp->line_speed = SPEED_10;
1250 }
1251 if (bmcr & BMCR_FULLDPLX) {
1252 bp->duplex = DUPLEX_FULL;
1253 }
1254 else {
1255 bp->duplex = DUPLEX_HALF;
1256 }
1257 }
1258
1259 return 0;
1260}
1261
1262static void
1263bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1264{
1265 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1266
1267 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1268 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1269 val |= 0x02 << 8;
1270
1271 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1272 u32 lo_water, hi_water;
1273
1274 if (bp->flow_ctrl & FLOW_CTRL_TX)
1275 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1276 else
1277 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1278 if (lo_water >= bp->rx_ring_size)
1279 lo_water = 0;
1280
1281 hi_water = bp->rx_ring_size / 4;
1282
1283 if (hi_water <= lo_water)
1284 lo_water = 0;
1285
1286 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1287 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1288
1289 if (hi_water > 0xf)
1290 hi_water = 0xf;
1291 else if (hi_water == 0)
1292 lo_water = 0;
1293 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1294 }
1295 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1296}
1297
1298static void
1299bnx2_init_all_rx_contexts(struct bnx2 *bp)
1300{
1301 int i;
1302 u32 cid;
1303
1304 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1305 if (i == 1)
1306 cid = RX_RSS_CID;
1307 bnx2_init_rx_context(bp, cid);
1308 }
1309}
1310
1311static void
1312bnx2_set_mac_link(struct bnx2 *bp)
1313{
1314 u32 val;
1315
1316 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1317 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1318 (bp->duplex == DUPLEX_HALF)) {
1319 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1320 }
1321
1322
1323 val = REG_RD(bp, BNX2_EMAC_MODE);
1324
1325 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1326 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1327 BNX2_EMAC_MODE_25G_MODE);
1328
1329 if (bp->link_up) {
1330 switch (bp->line_speed) {
1331 case SPEED_10:
1332 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1333 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1334 break;
1335 }
1336
1337 case SPEED_100:
1338 val |= BNX2_EMAC_MODE_PORT_MII;
1339 break;
1340 case SPEED_2500:
1341 val |= BNX2_EMAC_MODE_25G_MODE;
1342
1343 case SPEED_1000:
1344 val |= BNX2_EMAC_MODE_PORT_GMII;
1345 break;
1346 }
1347 }
1348 else {
1349 val |= BNX2_EMAC_MODE_PORT_GMII;
1350 }
1351
1352
1353 if (bp->duplex == DUPLEX_HALF)
1354 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1355 REG_WR(bp, BNX2_EMAC_MODE, val);
1356
1357
1358 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1359
1360 if (bp->flow_ctrl & FLOW_CTRL_RX)
1361 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1362 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1363
1364
1365 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1366 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1367
1368 if (bp->flow_ctrl & FLOW_CTRL_TX)
1369 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1370 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1371
1372
1373 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1374
1375 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1376 bnx2_init_all_rx_contexts(bp);
1377}
1378
1379static void
1380bnx2_enable_bmsr1(struct bnx2 *bp)
1381{
1382 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1383 (CHIP_NUM(bp) == CHIP_NUM_5709))
1384 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1385 MII_BNX2_BLK_ADDR_GP_STATUS);
1386}
1387
1388static void
1389bnx2_disable_bmsr1(struct bnx2 *bp)
1390{
1391 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1392 (CHIP_NUM(bp) == CHIP_NUM_5709))
1393 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1394 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1395}
1396
1397static int
1398bnx2_test_and_enable_2g5(struct bnx2 *bp)
1399{
1400 u32 up1;
1401 int ret = 1;
1402
1403 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1404 return 0;
1405
1406 if (bp->autoneg & AUTONEG_SPEED)
1407 bp->advertising |= ADVERTISED_2500baseX_Full;
1408
1409 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1410 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1411
1412 bnx2_read_phy(bp, bp->mii_up1, &up1);
1413 if (!(up1 & BCM5708S_UP1_2G5)) {
1414 up1 |= BCM5708S_UP1_2G5;
1415 bnx2_write_phy(bp, bp->mii_up1, up1);
1416 ret = 0;
1417 }
1418
1419 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1420 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1421 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1422
1423 return ret;
1424}
1425
1426static int
1427bnx2_test_and_disable_2g5(struct bnx2 *bp)
1428{
1429 u32 up1;
1430 int ret = 0;
1431
1432 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1433 return 0;
1434
1435 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1436 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1437
1438 bnx2_read_phy(bp, bp->mii_up1, &up1);
1439 if (up1 & BCM5708S_UP1_2G5) {
1440 up1 &= ~BCM5708S_UP1_2G5;
1441 bnx2_write_phy(bp, bp->mii_up1, up1);
1442 ret = 1;
1443 }
1444
1445 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1446 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1447 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1448
1449 return ret;
1450}
1451
1452static void
1453bnx2_enable_forced_2g5(struct bnx2 *bp)
1454{
1455 u32 bmcr;
1456
1457 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1458 return;
1459
1460 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1461 u32 val;
1462
1463 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1464 MII_BNX2_BLK_ADDR_SERDES_DIG);
1465 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1466 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1467 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1468 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1469
1470 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1471 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1472 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1473
1474 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1475 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1476 bmcr |= BCM5708S_BMCR_FORCE_2500;
1477 } else {
1478 return;
1479 }
1480
1481 if (bp->autoneg & AUTONEG_SPEED) {
1482 bmcr &= ~BMCR_ANENABLE;
1483 if (bp->req_duplex == DUPLEX_FULL)
1484 bmcr |= BMCR_FULLDPLX;
1485 }
1486 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1487}
1488
1489static void
1490bnx2_disable_forced_2g5(struct bnx2 *bp)
1491{
1492 u32 bmcr;
1493
1494 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1495 return;
1496
1497 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1498 u32 val;
1499
1500 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1501 MII_BNX2_BLK_ADDR_SERDES_DIG);
1502 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1503 val &= ~MII_BNX2_SD_MISC1_FORCE;
1504 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1505
1506 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1507 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1508 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1509
1510 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1511 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1512 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1513 } else {
1514 return;
1515 }
1516
1517 if (bp->autoneg & AUTONEG_SPEED)
1518 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1519 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1520}
1521
1522static void
1523bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1524{
1525 u32 val;
1526
1527 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1528 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1529 if (start)
1530 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1531 else
1532 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1533}
1534
1535static int
1536bnx2_set_link(struct bnx2 *bp)
1537{
1538 u32 bmsr;
1539 u8 link_up;
1540
1541 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1542 bp->link_up = 1;
1543 return 0;
1544 }
1545
1546 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1547 return 0;
1548
1549 link_up = bp->link_up;
1550
1551 bnx2_enable_bmsr1(bp);
1552 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1553 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1554 bnx2_disable_bmsr1(bp);
1555
1556 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1557 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1558 u32 val, an_dbg;
1559
1560 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1561 bnx2_5706s_force_link_dn(bp, 0);
1562 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1563 }
1564 val = REG_RD(bp, BNX2_EMAC_STATUS);
1565
1566 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1567 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1568 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1569
1570 if ((val & BNX2_EMAC_STATUS_LINK) &&
1571 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1572 bmsr |= BMSR_LSTATUS;
1573 else
1574 bmsr &= ~BMSR_LSTATUS;
1575 }
1576
1577 if (bmsr & BMSR_LSTATUS) {
1578 bp->link_up = 1;
1579
1580 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1581 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1582 bnx2_5706s_linkup(bp);
1583 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1584 bnx2_5708s_linkup(bp);
1585 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1586 bnx2_5709s_linkup(bp);
1587 }
1588 else {
1589 bnx2_copper_linkup(bp);
1590 }
1591 bnx2_resolve_flow_ctrl(bp);
1592 }
1593 else {
1594 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1595 (bp->autoneg & AUTONEG_SPEED))
1596 bnx2_disable_forced_2g5(bp);
1597
1598 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1599 u32 bmcr;
1600
1601 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1602 bmcr |= BMCR_ANENABLE;
1603 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1604
1605 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1606 }
1607 bp->link_up = 0;
1608 }
1609
1610 if (bp->link_up != link_up) {
1611 bnx2_report_link(bp);
1612 }
1613
1614 bnx2_set_mac_link(bp);
1615
1616 return 0;
1617}
1618
1619static int
1620bnx2_reset_phy(struct bnx2 *bp)
1621{
1622 int i;
1623 u32 reg;
1624
1625 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1626
1627#define PHY_RESET_MAX_WAIT 100
1628 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1629 udelay(10);
1630
1631 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1632 if (!(reg & BMCR_RESET)) {
1633 udelay(20);
1634 break;
1635 }
1636 }
1637 if (i == PHY_RESET_MAX_WAIT) {
1638 return -EBUSY;
1639 }
1640 return 0;
1641}
1642
1643static u32
1644bnx2_phy_get_pause_adv(struct bnx2 *bp)
1645{
1646 u32 adv = 0;
1647
1648 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1649 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1650
1651 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1652 adv = ADVERTISE_1000XPAUSE;
1653 }
1654 else {
1655 adv = ADVERTISE_PAUSE_CAP;
1656 }
1657 }
1658 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1659 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1660 adv = ADVERTISE_1000XPSE_ASYM;
1661 }
1662 else {
1663 adv = ADVERTISE_PAUSE_ASYM;
1664 }
1665 }
1666 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1667 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1668 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1669 }
1670 else {
1671 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1672 }
1673 }
1674 return adv;
1675}
1676
1677static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1678
1679static int
1680bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1681__releases(&bp->phy_lock)
1682__acquires(&bp->phy_lock)
1683{
1684 u32 speed_arg = 0, pause_adv;
1685
1686 pause_adv = bnx2_phy_get_pause_adv(bp);
1687
1688 if (bp->autoneg & AUTONEG_SPEED) {
1689 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1690 if (bp->advertising & ADVERTISED_10baseT_Half)
1691 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1692 if (bp->advertising & ADVERTISED_10baseT_Full)
1693 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1694 if (bp->advertising & ADVERTISED_100baseT_Half)
1695 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1696 if (bp->advertising & ADVERTISED_100baseT_Full)
1697 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1698 if (bp->advertising & ADVERTISED_1000baseT_Full)
1699 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1700 if (bp->advertising & ADVERTISED_2500baseX_Full)
1701 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1702 } else {
1703 if (bp->req_line_speed == SPEED_2500)
1704 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1705 else if (bp->req_line_speed == SPEED_1000)
1706 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1707 else if (bp->req_line_speed == SPEED_100) {
1708 if (bp->req_duplex == DUPLEX_FULL)
1709 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1710 else
1711 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1712 } else if (bp->req_line_speed == SPEED_10) {
1713 if (bp->req_duplex == DUPLEX_FULL)
1714 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1715 else
1716 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1717 }
1718 }
1719
1720 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1721 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1722 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1723 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1724
1725 if (port == PORT_TP)
1726 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1727 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1728
1729 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1730
1731 spin_unlock_bh(&bp->phy_lock);
1732 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1733 spin_lock_bh(&bp->phy_lock);
1734
1735 return 0;
1736}
1737
1738static int
1739bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1740__releases(&bp->phy_lock)
1741__acquires(&bp->phy_lock)
1742{
1743 u32 adv, bmcr;
1744 u32 new_adv = 0;
1745
1746 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1747 return (bnx2_setup_remote_phy(bp, port));
1748
1749 if (!(bp->autoneg & AUTONEG_SPEED)) {
1750 u32 new_bmcr;
1751 int force_link_down = 0;
1752
1753 if (bp->req_line_speed == SPEED_2500) {
1754 if (!bnx2_test_and_enable_2g5(bp))
1755 force_link_down = 1;
1756 } else if (bp->req_line_speed == SPEED_1000) {
1757 if (bnx2_test_and_disable_2g5(bp))
1758 force_link_down = 1;
1759 }
1760 bnx2_read_phy(bp, bp->mii_adv, &adv);
1761 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1762
1763 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1764 new_bmcr = bmcr & ~BMCR_ANENABLE;
1765 new_bmcr |= BMCR_SPEED1000;
1766
1767 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1768 if (bp->req_line_speed == SPEED_2500)
1769 bnx2_enable_forced_2g5(bp);
1770 else if (bp->req_line_speed == SPEED_1000) {
1771 bnx2_disable_forced_2g5(bp);
1772 new_bmcr &= ~0x2000;
1773 }
1774
1775 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1776 if (bp->req_line_speed == SPEED_2500)
1777 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1778 else
1779 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1780 }
1781
1782 if (bp->req_duplex == DUPLEX_FULL) {
1783 adv |= ADVERTISE_1000XFULL;
1784 new_bmcr |= BMCR_FULLDPLX;
1785 }
1786 else {
1787 adv |= ADVERTISE_1000XHALF;
1788 new_bmcr &= ~BMCR_FULLDPLX;
1789 }
1790 if ((new_bmcr != bmcr) || (force_link_down)) {
1791
1792 if (bp->link_up) {
1793 bnx2_write_phy(bp, bp->mii_adv, adv &
1794 ~(ADVERTISE_1000XFULL |
1795 ADVERTISE_1000XHALF));
1796 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1797 BMCR_ANRESTART | BMCR_ANENABLE);
1798
1799 bp->link_up = 0;
1800 netif_carrier_off(bp->dev);
1801 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1802 bnx2_report_link(bp);
1803 }
1804 bnx2_write_phy(bp, bp->mii_adv, adv);
1805 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1806 } else {
1807 bnx2_resolve_flow_ctrl(bp);
1808 bnx2_set_mac_link(bp);
1809 }
1810 return 0;
1811 }
1812
1813 bnx2_test_and_enable_2g5(bp);
1814
1815 if (bp->advertising & ADVERTISED_1000baseT_Full)
1816 new_adv |= ADVERTISE_1000XFULL;
1817
1818 new_adv |= bnx2_phy_get_pause_adv(bp);
1819
1820 bnx2_read_phy(bp, bp->mii_adv, &adv);
1821 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1822
1823 bp->serdes_an_pending = 0;
1824 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1825
1826 if (bp->link_up) {
1827 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1828 spin_unlock_bh(&bp->phy_lock);
1829 msleep(20);
1830 spin_lock_bh(&bp->phy_lock);
1831 }
1832
1833 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1834 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1835 BMCR_ANENABLE);
1836
1837
1838
1839
1840
1841
1842
1843
1844 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1845 bp->serdes_an_pending = 1;
1846 mod_timer(&bp->timer, jiffies + bp->current_interval);
1847 } else {
1848 bnx2_resolve_flow_ctrl(bp);
1849 bnx2_set_mac_link(bp);
1850 }
1851
1852 return 0;
1853}
1854
1855#define ETHTOOL_ALL_FIBRE_SPEED \
1856 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1857 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1858 (ADVERTISED_1000baseT_Full)
1859
1860#define ETHTOOL_ALL_COPPER_SPEED \
1861 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1862 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1863 ADVERTISED_1000baseT_Full)
1864
1865#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1866 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1867
1868#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1869
1870static void
1871bnx2_set_default_remote_link(struct bnx2 *bp)
1872{
1873 u32 link;
1874
1875 if (bp->phy_port == PORT_TP)
1876 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1877 else
1878 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1879
1880 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1881 bp->req_line_speed = 0;
1882 bp->autoneg |= AUTONEG_SPEED;
1883 bp->advertising = ADVERTISED_Autoneg;
1884 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1885 bp->advertising |= ADVERTISED_10baseT_Half;
1886 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1887 bp->advertising |= ADVERTISED_10baseT_Full;
1888 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1889 bp->advertising |= ADVERTISED_100baseT_Half;
1890 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1891 bp->advertising |= ADVERTISED_100baseT_Full;
1892 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1893 bp->advertising |= ADVERTISED_1000baseT_Full;
1894 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1895 bp->advertising |= ADVERTISED_2500baseX_Full;
1896 } else {
1897 bp->autoneg = 0;
1898 bp->advertising = 0;
1899 bp->req_duplex = DUPLEX_FULL;
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1901 bp->req_line_speed = SPEED_10;
1902 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1903 bp->req_duplex = DUPLEX_HALF;
1904 }
1905 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1906 bp->req_line_speed = SPEED_100;
1907 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1908 bp->req_duplex = DUPLEX_HALF;
1909 }
1910 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1911 bp->req_line_speed = SPEED_1000;
1912 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1913 bp->req_line_speed = SPEED_2500;
1914 }
1915}
1916
1917static void
1918bnx2_set_default_link(struct bnx2 *bp)
1919{
1920 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1921 bnx2_set_default_remote_link(bp);
1922 return;
1923 }
1924
1925 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1926 bp->req_line_speed = 0;
1927 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1928 u32 reg;
1929
1930 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1931
1932 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1933 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1934 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1935 bp->autoneg = 0;
1936 bp->req_line_speed = bp->line_speed = SPEED_1000;
1937 bp->req_duplex = DUPLEX_FULL;
1938 }
1939 } else
1940 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1941}
1942
1943static void
1944bnx2_send_heart_beat(struct bnx2 *bp)
1945{
1946 u32 msg;
1947 u32 addr;
1948
1949 spin_lock(&bp->indirect_lock);
1950 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1951 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1952 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1953 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1954 spin_unlock(&bp->indirect_lock);
1955}
1956
1957static void
1958bnx2_remote_phy_event(struct bnx2 *bp)
1959{
1960 u32 msg;
1961 u8 link_up = bp->link_up;
1962 u8 old_port;
1963
1964 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1965
1966 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1967 bnx2_send_heart_beat(bp);
1968
1969 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1970
1971 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1972 bp->link_up = 0;
1973 else {
1974 u32 speed;
1975
1976 bp->link_up = 1;
1977 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1978 bp->duplex = DUPLEX_FULL;
1979 switch (speed) {
1980 case BNX2_LINK_STATUS_10HALF:
1981 bp->duplex = DUPLEX_HALF;
1982 case BNX2_LINK_STATUS_10FULL:
1983 bp->line_speed = SPEED_10;
1984 break;
1985 case BNX2_LINK_STATUS_100HALF:
1986 bp->duplex = DUPLEX_HALF;
1987 case BNX2_LINK_STATUS_100BASE_T4:
1988 case BNX2_LINK_STATUS_100FULL:
1989 bp->line_speed = SPEED_100;
1990 break;
1991 case BNX2_LINK_STATUS_1000HALF:
1992 bp->duplex = DUPLEX_HALF;
1993 case BNX2_LINK_STATUS_1000FULL:
1994 bp->line_speed = SPEED_1000;
1995 break;
1996 case BNX2_LINK_STATUS_2500HALF:
1997 bp->duplex = DUPLEX_HALF;
1998 case BNX2_LINK_STATUS_2500FULL:
1999 bp->line_speed = SPEED_2500;
2000 break;
2001 default:
2002 bp->line_speed = 0;
2003 break;
2004 }
2005
2006 bp->flow_ctrl = 0;
2007 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2008 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2009 if (bp->duplex == DUPLEX_FULL)
2010 bp->flow_ctrl = bp->req_flow_ctrl;
2011 } else {
2012 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2013 bp->flow_ctrl |= FLOW_CTRL_TX;
2014 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2015 bp->flow_ctrl |= FLOW_CTRL_RX;
2016 }
2017
2018 old_port = bp->phy_port;
2019 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2020 bp->phy_port = PORT_FIBRE;
2021 else
2022 bp->phy_port = PORT_TP;
2023
2024 if (old_port != bp->phy_port)
2025 bnx2_set_default_link(bp);
2026
2027 }
2028 if (bp->link_up != link_up)
2029 bnx2_report_link(bp);
2030
2031 bnx2_set_mac_link(bp);
2032}
2033
2034static int
2035bnx2_set_remote_link(struct bnx2 *bp)
2036{
2037 u32 evt_code;
2038
2039 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2040 switch (evt_code) {
2041 case BNX2_FW_EVT_CODE_LINK_EVENT:
2042 bnx2_remote_phy_event(bp);
2043 break;
2044 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2045 default:
2046 bnx2_send_heart_beat(bp);
2047 break;
2048 }
2049 return 0;
2050}
2051
2052static int
2053bnx2_setup_copper_phy(struct bnx2 *bp)
2054__releases(&bp->phy_lock)
2055__acquires(&bp->phy_lock)
2056{
2057 u32 bmcr;
2058 u32 new_bmcr;
2059
2060 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2061
2062 if (bp->autoneg & AUTONEG_SPEED) {
2063 u32 adv_reg, adv1000_reg;
2064 u32 new_adv_reg = 0;
2065 u32 new_adv1000_reg = 0;
2066
2067 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2068 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2069 ADVERTISE_PAUSE_ASYM);
2070
2071 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2072 adv1000_reg &= PHY_ALL_1000_SPEED;
2073
2074 if (bp->advertising & ADVERTISED_10baseT_Half)
2075 new_adv_reg |= ADVERTISE_10HALF;
2076 if (bp->advertising & ADVERTISED_10baseT_Full)
2077 new_adv_reg |= ADVERTISE_10FULL;
2078 if (bp->advertising & ADVERTISED_100baseT_Half)
2079 new_adv_reg |= ADVERTISE_100HALF;
2080 if (bp->advertising & ADVERTISED_100baseT_Full)
2081 new_adv_reg |= ADVERTISE_100FULL;
2082 if (bp->advertising & ADVERTISED_1000baseT_Full)
2083 new_adv1000_reg |= ADVERTISE_1000FULL;
2084
2085 new_adv_reg |= ADVERTISE_CSMA;
2086
2087 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2088
2089 if ((adv1000_reg != new_adv1000_reg) ||
2090 (adv_reg != new_adv_reg) ||
2091 ((bmcr & BMCR_ANENABLE) == 0)) {
2092
2093 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2094 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2095 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2096 BMCR_ANENABLE);
2097 }
2098 else if (bp->link_up) {
2099
2100
2101
2102 bnx2_resolve_flow_ctrl(bp);
2103 bnx2_set_mac_link(bp);
2104 }
2105 return 0;
2106 }
2107
2108 new_bmcr = 0;
2109 if (bp->req_line_speed == SPEED_100) {
2110 new_bmcr |= BMCR_SPEED100;
2111 }
2112 if (bp->req_duplex == DUPLEX_FULL) {
2113 new_bmcr |= BMCR_FULLDPLX;
2114 }
2115 if (new_bmcr != bmcr) {
2116 u32 bmsr;
2117
2118 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2119 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2120
2121 if (bmsr & BMSR_LSTATUS) {
2122
2123 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2124 spin_unlock_bh(&bp->phy_lock);
2125 msleep(50);
2126 spin_lock_bh(&bp->phy_lock);
2127
2128 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2129 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2130 }
2131
2132 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2133
2134
2135
2136
2137
2138 if (bmsr & BMSR_LSTATUS) {
2139 bp->line_speed = bp->req_line_speed;
2140 bp->duplex = bp->req_duplex;
2141 bnx2_resolve_flow_ctrl(bp);
2142 bnx2_set_mac_link(bp);
2143 }
2144 } else {
2145 bnx2_resolve_flow_ctrl(bp);
2146 bnx2_set_mac_link(bp);
2147 }
2148 return 0;
2149}
2150
2151static int
2152bnx2_setup_phy(struct bnx2 *bp, u8 port)
2153__releases(&bp->phy_lock)
2154__acquires(&bp->phy_lock)
2155{
2156 if (bp->loopback == MAC_LOOPBACK)
2157 return 0;
2158
2159 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2160 return (bnx2_setup_serdes_phy(bp, port));
2161 }
2162 else {
2163 return (bnx2_setup_copper_phy(bp));
2164 }
2165}
2166
2167static int
2168bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2169{
2170 u32 val;
2171
2172 bp->mii_bmcr = MII_BMCR + 0x10;
2173 bp->mii_bmsr = MII_BMSR + 0x10;
2174 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2175 bp->mii_adv = MII_ADVERTISE + 0x10;
2176 bp->mii_lpa = MII_LPA + 0x10;
2177 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2178
2179 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2180 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2181
2182 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2183 if (reset_phy)
2184 bnx2_reset_phy(bp);
2185
2186 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2187
2188 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2189 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2190 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2191 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2192
2193 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2194 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2195 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2196 val |= BCM5708S_UP1_2G5;
2197 else
2198 val &= ~BCM5708S_UP1_2G5;
2199 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2200
2201 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2202 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2203 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2204 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2205
2206 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2207
2208 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2209 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2210 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2211
2212 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2213
2214 return 0;
2215}
2216
2217static int
2218bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2219{
2220 u32 val;
2221
2222 if (reset_phy)
2223 bnx2_reset_phy(bp);
2224
2225 bp->mii_up1 = BCM5708S_UP1;
2226
2227 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2228 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2229 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2230
2231 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2232 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2233 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2234
2235 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2236 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2237 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2238
2239 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2240 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2241 val |= BCM5708S_UP1_2G5;
2242 bnx2_write_phy(bp, BCM5708S_UP1, val);
2243 }
2244
2245 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2246 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2247 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2248
2249 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2250 BCM5708S_BLK_ADDR_TX_MISC);
2251 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2252 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2253 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2254 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2255 }
2256
2257 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2258 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2259
2260 if (val) {
2261 u32 is_backplane;
2262
2263 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2264 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2265 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2266 BCM5708S_BLK_ADDR_TX_MISC);
2267 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2268 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2269 BCM5708S_BLK_ADDR_DIG);
2270 }
2271 }
2272 return 0;
2273}
2274
2275static int
2276bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2277{
2278 if (reset_phy)
2279 bnx2_reset_phy(bp);
2280
2281 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2282
2283 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2284 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2285
2286 if (bp->dev->mtu > 1500) {
2287 u32 val;
2288
2289
2290 bnx2_write_phy(bp, 0x18, 0x7);
2291 bnx2_read_phy(bp, 0x18, &val);
2292 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2293
2294 bnx2_write_phy(bp, 0x1c, 0x6c00);
2295 bnx2_read_phy(bp, 0x1c, &val);
2296 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2297 }
2298 else {
2299 u32 val;
2300
2301 bnx2_write_phy(bp, 0x18, 0x7);
2302 bnx2_read_phy(bp, 0x18, &val);
2303 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2304
2305 bnx2_write_phy(bp, 0x1c, 0x6c00);
2306 bnx2_read_phy(bp, 0x1c, &val);
2307 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2308 }
2309
2310 return 0;
2311}
2312
2313static int
2314bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2315{
2316 u32 val;
2317
2318 if (reset_phy)
2319 bnx2_reset_phy(bp);
2320
2321 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2322 bnx2_write_phy(bp, 0x18, 0x0c00);
2323 bnx2_write_phy(bp, 0x17, 0x000a);
2324 bnx2_write_phy(bp, 0x15, 0x310b);
2325 bnx2_write_phy(bp, 0x17, 0x201f);
2326 bnx2_write_phy(bp, 0x15, 0x9506);
2327 bnx2_write_phy(bp, 0x17, 0x401f);
2328 bnx2_write_phy(bp, 0x15, 0x14e2);
2329 bnx2_write_phy(bp, 0x18, 0x0400);
2330 }
2331
2332 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2333 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2334 MII_BNX2_DSP_EXPAND_REG | 0x8);
2335 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2336 val &= ~(1 << 8);
2337 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2338 }
2339
2340 if (bp->dev->mtu > 1500) {
2341
2342 bnx2_write_phy(bp, 0x18, 0x7);
2343 bnx2_read_phy(bp, 0x18, &val);
2344 bnx2_write_phy(bp, 0x18, val | 0x4000);
2345
2346 bnx2_read_phy(bp, 0x10, &val);
2347 bnx2_write_phy(bp, 0x10, val | 0x1);
2348 }
2349 else {
2350 bnx2_write_phy(bp, 0x18, 0x7);
2351 bnx2_read_phy(bp, 0x18, &val);
2352 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2353
2354 bnx2_read_phy(bp, 0x10, &val);
2355 bnx2_write_phy(bp, 0x10, val & ~0x1);
2356 }
2357
2358
2359 bnx2_write_phy(bp, 0x18, 0x7007);
2360 bnx2_read_phy(bp, 0x18, &val);
2361 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2362 return 0;
2363}
2364
2365
2366static int
2367bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2368__releases(&bp->phy_lock)
2369__acquires(&bp->phy_lock)
2370{
2371 u32 val;
2372 int rc = 0;
2373
2374 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2375 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2376
2377 bp->mii_bmcr = MII_BMCR;
2378 bp->mii_bmsr = MII_BMSR;
2379 bp->mii_bmsr1 = MII_BMSR;
2380 bp->mii_adv = MII_ADVERTISE;
2381 bp->mii_lpa = MII_LPA;
2382
2383 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2384
2385 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2386 goto setup_phy;
2387
2388 bnx2_read_phy(bp, MII_PHYSID1, &val);
2389 bp->phy_id = val << 16;
2390 bnx2_read_phy(bp, MII_PHYSID2, &val);
2391 bp->phy_id |= val & 0xffff;
2392
2393 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2394 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2395 rc = bnx2_init_5706s_phy(bp, reset_phy);
2396 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2397 rc = bnx2_init_5708s_phy(bp, reset_phy);
2398 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2399 rc = bnx2_init_5709s_phy(bp, reset_phy);
2400 }
2401 else {
2402 rc = bnx2_init_copper_phy(bp, reset_phy);
2403 }
2404
2405setup_phy:
2406 if (!rc)
2407 rc = bnx2_setup_phy(bp, bp->phy_port);
2408
2409 return rc;
2410}
2411
2412static int
2413bnx2_set_mac_loopback(struct bnx2 *bp)
2414{
2415 u32 mac_mode;
2416
2417 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2418 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2419 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2420 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2421 bp->link_up = 1;
2422 return 0;
2423}
2424
2425static int bnx2_test_link(struct bnx2 *);
2426
2427static int
2428bnx2_set_phy_loopback(struct bnx2 *bp)
2429{
2430 u32 mac_mode;
2431 int rc, i;
2432
2433 spin_lock_bh(&bp->phy_lock);
2434 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2435 BMCR_SPEED1000);
2436 spin_unlock_bh(&bp->phy_lock);
2437 if (rc)
2438 return rc;
2439
2440 for (i = 0; i < 10; i++) {
2441 if (bnx2_test_link(bp) == 0)
2442 break;
2443 msleep(100);
2444 }
2445
2446 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2447 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2448 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2449 BNX2_EMAC_MODE_25G_MODE);
2450
2451 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2452 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2453 bp->link_up = 1;
2454 return 0;
2455}
2456
2457static int
2458bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2459{
2460 int i;
2461 u32 val;
2462
2463 bp->fw_wr_seq++;
2464 msg_data |= bp->fw_wr_seq;
2465
2466 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2467
2468 if (!ack)
2469 return 0;
2470
2471
2472 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2473 msleep(10);
2474
2475 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2476
2477 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2478 break;
2479 }
2480 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2481 return 0;
2482
2483
2484 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2485 if (!silent)
2486 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2487 "%x\n", msg_data);
2488
2489 msg_data &= ~BNX2_DRV_MSG_CODE;
2490 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2491
2492 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2493
2494 return -EBUSY;
2495 }
2496
2497 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2498 return -EIO;
2499
2500 return 0;
2501}
2502
2503static int
2504bnx2_init_5709_context(struct bnx2 *bp)
2505{
2506 int i, ret = 0;
2507 u32 val;
2508
2509 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2510 val |= (BCM_PAGE_BITS - 8) << 16;
2511 REG_WR(bp, BNX2_CTX_COMMAND, val);
2512 for (i = 0; i < 10; i++) {
2513 val = REG_RD(bp, BNX2_CTX_COMMAND);
2514 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2515 break;
2516 udelay(2);
2517 }
2518 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2519 return -EBUSY;
2520
2521 for (i = 0; i < bp->ctx_pages; i++) {
2522 int j;
2523
2524 if (bp->ctx_blk[i])
2525 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2526 else
2527 return -ENOMEM;
2528
2529 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2530 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2531 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2532 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2533 (u64) bp->ctx_blk_mapping[i] >> 32);
2534 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2535 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2536 for (j = 0; j < 10; j++) {
2537
2538 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2539 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2540 break;
2541 udelay(5);
2542 }
2543 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2544 ret = -EBUSY;
2545 break;
2546 }
2547 }
2548 return ret;
2549}
2550
2551static void
2552bnx2_init_context(struct bnx2 *bp)
2553{
2554 u32 vcid;
2555
2556 vcid = 96;
2557 while (vcid) {
2558 u32 vcid_addr, pcid_addr, offset;
2559 int i;
2560
2561 vcid--;
2562
2563 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2564 u32 new_vcid;
2565
2566 vcid_addr = GET_PCID_ADDR(vcid);
2567 if (vcid & 0x8) {
2568 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2569 }
2570 else {
2571 new_vcid = vcid;
2572 }
2573 pcid_addr = GET_PCID_ADDR(new_vcid);
2574 }
2575 else {
2576 vcid_addr = GET_CID_ADDR(vcid);
2577 pcid_addr = vcid_addr;
2578 }
2579
2580 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2581 vcid_addr += (i << PHY_CTX_SHIFT);
2582 pcid_addr += (i << PHY_CTX_SHIFT);
2583
2584 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2585 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2586
2587
2588 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2589 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2590 }
2591 }
2592}
2593
2594static int
2595bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2596{
2597 u16 *good_mbuf;
2598 u32 good_mbuf_cnt;
2599 u32 val;
2600
2601 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2602 if (good_mbuf == NULL) {
2603 printk(KERN_ERR PFX "Failed to allocate memory in "
2604 "bnx2_alloc_bad_rbuf\n");
2605 return -ENOMEM;
2606 }
2607
2608 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2609 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2610
2611 good_mbuf_cnt = 0;
2612
2613
2614 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2615 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2616 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2617 BNX2_RBUF_COMMAND_ALLOC_REQ);
2618
2619 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2620
2621 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2622
2623
2624 if (!(val & (1 << 9))) {
2625 good_mbuf[good_mbuf_cnt] = (u16) val;
2626 good_mbuf_cnt++;
2627 }
2628
2629 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2630 }
2631
2632
2633
2634 while (good_mbuf_cnt) {
2635 good_mbuf_cnt--;
2636
2637 val = good_mbuf[good_mbuf_cnt];
2638 val = (val << 9) | val | 1;
2639
2640 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2641 }
2642 kfree(good_mbuf);
2643 return 0;
2644}
2645
2646static void
2647bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2648{
2649 u32 val;
2650
2651 val = (mac_addr[0] << 8) | mac_addr[1];
2652
2653 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2654
2655 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2656 (mac_addr[4] << 8) | mac_addr[5];
2657
2658 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2659}
2660
2661static inline int
2662bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2663{
2664 dma_addr_t mapping;
2665 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2666 struct rx_bd *rxbd =
2667 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2668 struct page *page = alloc_page(GFP_ATOMIC);
2669
2670 if (!page)
2671 return -ENOMEM;
2672 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2673 PCI_DMA_FROMDEVICE);
2674 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2675 __free_page(page);
2676 return -EIO;
2677 }
2678
2679 rx_pg->page = page;
2680 pci_unmap_addr_set(rx_pg, mapping, mapping);
2681 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2682 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2683 return 0;
2684}
2685
2686static void
2687bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2688{
2689 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2690 struct page *page = rx_pg->page;
2691
2692 if (!page)
2693 return;
2694
2695 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2696 PCI_DMA_FROMDEVICE);
2697
2698 __free_page(page);
2699 rx_pg->page = NULL;
2700}
2701
2702static inline int
2703bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2704{
2705 struct sk_buff *skb;
2706 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2707 dma_addr_t mapping;
2708 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2709 unsigned long align;
2710
2711 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2712 if (skb == NULL) {
2713 return -ENOMEM;
2714 }
2715
2716 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2717 skb_reserve(skb, BNX2_RX_ALIGN - align);
2718
2719 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2720 PCI_DMA_FROMDEVICE);
2721 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2722 dev_kfree_skb(skb);
2723 return -EIO;
2724 }
2725
2726 rx_buf->skb = skb;
2727 pci_unmap_addr_set(rx_buf, mapping, mapping);
2728
2729 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2730 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2731
2732 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2733
2734 return 0;
2735}
2736
2737static int
2738bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2739{
2740 struct status_block *sblk = bnapi->status_blk.msi;
2741 u32 new_link_state, old_link_state;
2742 int is_set = 1;
2743
2744 new_link_state = sblk->status_attn_bits & event;
2745 old_link_state = sblk->status_attn_bits_ack & event;
2746 if (new_link_state != old_link_state) {
2747 if (new_link_state)
2748 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2749 else
2750 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2751 } else
2752 is_set = 0;
2753
2754 return is_set;
2755}
2756
2757static void
2758bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2759{
2760 spin_lock(&bp->phy_lock);
2761
2762 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2763 bnx2_set_link(bp);
2764 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2765 bnx2_set_remote_link(bp);
2766
2767 spin_unlock(&bp->phy_lock);
2768
2769}
2770
2771static inline u16
2772bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2773{
2774 u16 cons;
2775
2776
2777 barrier();
2778 cons = *bnapi->hw_tx_cons_ptr;
2779 barrier();
2780 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2781 cons++;
2782 return cons;
2783}
2784
2785static int
2786bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2787{
2788 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2789 u16 hw_cons, sw_cons, sw_ring_cons;
2790 int tx_pkt = 0, index;
2791 struct netdev_queue *txq;
2792
2793 index = (bnapi - bp->bnx2_napi);
2794 txq = netdev_get_tx_queue(bp->dev, index);
2795
2796 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2797 sw_cons = txr->tx_cons;
2798
2799 while (sw_cons != hw_cons) {
2800 struct sw_tx_bd *tx_buf;
2801 struct sk_buff *skb;
2802 int i, last;
2803
2804 sw_ring_cons = TX_RING_IDX(sw_cons);
2805
2806 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2807 skb = tx_buf->skb;
2808
2809
2810 prefetch(&skb->end);
2811
2812
2813 if (tx_buf->is_gso) {
2814 u16 last_idx, last_ring_idx;
2815
2816 last_idx = sw_cons + tx_buf->nr_frags + 1;
2817 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2818 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2819 last_idx++;
2820 }
2821 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2822 break;
2823 }
2824 }
2825
2826 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2827 skb_headlen(skb), PCI_DMA_TODEVICE);
2828
2829 tx_buf->skb = NULL;
2830 last = tx_buf->nr_frags;
2831
2832 for (i = 0; i < last; i++) {
2833 sw_cons = NEXT_TX_BD(sw_cons);
2834
2835 pci_unmap_page(bp->pdev,
2836 pci_unmap_addr(
2837 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2838 mapping),
2839 skb_shinfo(skb)->frags[i].size,
2840 PCI_DMA_TODEVICE);
2841 }
2842
2843 sw_cons = NEXT_TX_BD(sw_cons);
2844
2845 dev_kfree_skb(skb);
2846 tx_pkt++;
2847 if (tx_pkt == budget)
2848 break;
2849
2850 if (hw_cons == sw_cons)
2851 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2852 }
2853
2854 txr->hw_tx_cons = hw_cons;
2855 txr->tx_cons = sw_cons;
2856
2857
2858
2859
2860
2861
2862 smp_mb();
2863
2864 if (unlikely(netif_tx_queue_stopped(txq)) &&
2865 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2866 __netif_tx_lock(txq, smp_processor_id());
2867 if ((netif_tx_queue_stopped(txq)) &&
2868 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2869 netif_tx_wake_queue(txq);
2870 __netif_tx_unlock(txq);
2871 }
2872
2873 return tx_pkt;
2874}
2875
2876static void
2877bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2878 struct sk_buff *skb, int count)
2879{
2880 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2881 struct rx_bd *cons_bd, *prod_bd;
2882 int i;
2883 u16 hw_prod, prod;
2884 u16 cons = rxr->rx_pg_cons;
2885
2886 cons_rx_pg = &rxr->rx_pg_ring[cons];
2887
2888
2889
2890
2891
2892 if (skb) {
2893 struct page *page;
2894 struct skb_shared_info *shinfo;
2895
2896 shinfo = skb_shinfo(skb);
2897 shinfo->nr_frags--;
2898 page = shinfo->frags[shinfo->nr_frags].page;
2899 shinfo->frags[shinfo->nr_frags].page = NULL;
2900
2901 cons_rx_pg->page = page;
2902 dev_kfree_skb(skb);
2903 }
2904
2905 hw_prod = rxr->rx_pg_prod;
2906
2907 for (i = 0; i < count; i++) {
2908 prod = RX_PG_RING_IDX(hw_prod);
2909
2910 prod_rx_pg = &rxr->rx_pg_ring[prod];
2911 cons_rx_pg = &rxr->rx_pg_ring[cons];
2912 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2913 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2914
2915 if (prod != cons) {
2916 prod_rx_pg->page = cons_rx_pg->page;
2917 cons_rx_pg->page = NULL;
2918 pci_unmap_addr_set(prod_rx_pg, mapping,
2919 pci_unmap_addr(cons_rx_pg, mapping));
2920
2921 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2922 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2923
2924 }
2925 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2926 hw_prod = NEXT_RX_BD(hw_prod);
2927 }
2928 rxr->rx_pg_prod = hw_prod;
2929 rxr->rx_pg_cons = cons;
2930}
2931
2932static inline void
2933bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2934 struct sk_buff *skb, u16 cons, u16 prod)
2935{
2936 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2937 struct rx_bd *cons_bd, *prod_bd;
2938
2939 cons_rx_buf = &rxr->rx_buf_ring[cons];
2940 prod_rx_buf = &rxr->rx_buf_ring[prod];
2941
2942 pci_dma_sync_single_for_device(bp->pdev,
2943 pci_unmap_addr(cons_rx_buf, mapping),
2944 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2945
2946 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2947
2948 prod_rx_buf->skb = skb;
2949
2950 if (cons == prod)
2951 return;
2952
2953 pci_unmap_addr_set(prod_rx_buf, mapping,
2954 pci_unmap_addr(cons_rx_buf, mapping));
2955
2956 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2957 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2958 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2959 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2960}
2961
2962static int
2963bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2964 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2965 u32 ring_idx)
2966{
2967 int err;
2968 u16 prod = ring_idx & 0xffff;
2969
2970 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2971 if (unlikely(err)) {
2972 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2973 if (hdr_len) {
2974 unsigned int raw_len = len + 4;
2975 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2976
2977 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2978 }
2979 return err;
2980 }
2981
2982 skb_reserve(skb, BNX2_RX_OFFSET);
2983 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2984 PCI_DMA_FROMDEVICE);
2985
2986 if (hdr_len == 0) {
2987 skb_put(skb, len);
2988 return 0;
2989 } else {
2990 unsigned int i, frag_len, frag_size, pages;
2991 struct sw_pg *rx_pg;
2992 u16 pg_cons = rxr->rx_pg_cons;
2993 u16 pg_prod = rxr->rx_pg_prod;
2994
2995 frag_size = len + 4 - hdr_len;
2996 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2997 skb_put(skb, hdr_len);
2998
2999 for (i = 0; i < pages; i++) {
3000 dma_addr_t mapping_old;
3001
3002 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3003 if (unlikely(frag_len <= 4)) {
3004 unsigned int tail = 4 - frag_len;
3005
3006 rxr->rx_pg_cons = pg_cons;
3007 rxr->rx_pg_prod = pg_prod;
3008 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
3009 pages - i);
3010 skb->len -= tail;
3011 if (i == 0) {
3012 skb->tail -= tail;
3013 } else {
3014 skb_frag_t *frag =
3015 &skb_shinfo(skb)->frags[i - 1];
3016 frag->size -= tail;
3017 skb->data_len -= tail;
3018 skb->truesize -= tail;
3019 }
3020 return 0;
3021 }
3022 rx_pg = &rxr->rx_pg_ring[pg_cons];
3023
3024
3025
3026
3027 mapping_old = pci_unmap_addr(rx_pg, mapping);
3028 if (i == pages - 1)
3029 frag_len -= 4;
3030
3031 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3032 rx_pg->page = NULL;
3033
3034 err = bnx2_alloc_rx_page(bp, rxr,
3035 RX_PG_RING_IDX(pg_prod));
3036 if (unlikely(err)) {
3037 rxr->rx_pg_cons = pg_cons;
3038 rxr->rx_pg_prod = pg_prod;
3039 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3040 pages - i);
3041 return err;
3042 }
3043
3044 pci_unmap_page(bp->pdev, mapping_old,
3045 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3046
3047 frag_size -= frag_len;
3048 skb->data_len += frag_len;
3049 skb->truesize += frag_len;
3050 skb->len += frag_len;
3051
3052 pg_prod = NEXT_RX_BD(pg_prod);
3053 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3054 }
3055 rxr->rx_pg_prod = pg_prod;
3056 rxr->rx_pg_cons = pg_cons;
3057 }
3058 return 0;
3059}
3060
3061static inline u16
3062bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3063{
3064 u16 cons;
3065
3066
3067 barrier();
3068 cons = *bnapi->hw_rx_cons_ptr;
3069 barrier();
3070 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3071 cons++;
3072 return cons;
3073}
3074
3075static int
3076bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3077{
3078 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3079 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3080 struct l2_fhdr *rx_hdr;
3081 int rx_pkt = 0, pg_ring_used = 0;
3082
3083 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3084 sw_cons = rxr->rx_cons;
3085 sw_prod = rxr->rx_prod;
3086
3087
3088
3089
3090 rmb();
3091 while (sw_cons != hw_cons) {
3092 unsigned int len, hdr_len;
3093 u32 status;
3094 struct sw_bd *rx_buf;
3095 struct sk_buff *skb;
3096 dma_addr_t dma_addr;
3097 u16 vtag = 0;
3098 int hw_vlan __maybe_unused = 0;
3099
3100 sw_ring_cons = RX_RING_IDX(sw_cons);
3101 sw_ring_prod = RX_RING_IDX(sw_prod);
3102
3103 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3104 skb = rx_buf->skb;
3105
3106 rx_buf->skb = NULL;
3107
3108 dma_addr = pci_unmap_addr(rx_buf, mapping);
3109
3110 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
3111 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3112 PCI_DMA_FROMDEVICE);
3113
3114 rx_hdr = (struct l2_fhdr *) skb->data;
3115 len = rx_hdr->l2_fhdr_pkt_len;
3116 status = rx_hdr->l2_fhdr_status;
3117
3118 hdr_len = 0;
3119 if (status & L2_FHDR_STATUS_SPLIT) {
3120 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3121 pg_ring_used = 1;
3122 } else if (len > bp->rx_jumbo_thresh) {
3123 hdr_len = bp->rx_jumbo_thresh;
3124 pg_ring_used = 1;
3125 }
3126
3127 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3128 L2_FHDR_ERRORS_PHY_DECODE |
3129 L2_FHDR_ERRORS_ALIGNMENT |
3130 L2_FHDR_ERRORS_TOO_SHORT |
3131 L2_FHDR_ERRORS_GIANT_FRAME))) {
3132
3133 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3134 sw_ring_prod);
3135 if (pg_ring_used) {
3136 int pages;
3137
3138 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3139
3140 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3141 }
3142 goto next_rx;
3143 }
3144
3145 len -= 4;
3146
3147 if (len <= bp->rx_copy_thresh) {
3148 struct sk_buff *new_skb;
3149
3150 new_skb = netdev_alloc_skb(bp->dev, len + 6);
3151 if (new_skb == NULL) {
3152 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3153 sw_ring_prod);
3154 goto next_rx;
3155 }
3156
3157
3158 skb_copy_from_linear_data_offset(skb,
3159 BNX2_RX_OFFSET - 6,
3160 new_skb->data, len + 6);
3161 skb_reserve(new_skb, 6);
3162 skb_put(new_skb, len);
3163
3164 bnx2_reuse_rx_skb(bp, rxr, skb,
3165 sw_ring_cons, sw_ring_prod);
3166
3167 skb = new_skb;
3168 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3169 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3170 goto next_rx;
3171
3172 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3173 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3174 vtag = rx_hdr->l2_fhdr_vlan_tag;
3175#ifdef BCM_VLAN
3176 if (bp->vlgrp)
3177 hw_vlan = 1;
3178 else
3179#endif
3180 {
3181 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3182 __skb_push(skb, 4);
3183
3184 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3185 ve->h_vlan_proto = htons(ETH_P_8021Q);
3186 ve->h_vlan_TCI = htons(vtag);
3187 len += 4;
3188 }
3189 }
3190
3191 skb->protocol = eth_type_trans(skb, bp->dev);
3192
3193 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3194 (ntohs(skb->protocol) != 0x8100)) {
3195
3196 dev_kfree_skb(skb);
3197 goto next_rx;
3198
3199 }
3200
3201 skb->ip_summed = CHECKSUM_NONE;
3202 if (bp->rx_csum &&
3203 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3204 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3205
3206 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3207 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3208 skb->ip_summed = CHECKSUM_UNNECESSARY;
3209 }
3210
3211 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3212
3213#ifdef BCM_VLAN
3214 if (hw_vlan)
3215 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3216 else
3217#endif
3218 netif_receive_skb(skb);
3219
3220 rx_pkt++;
3221
3222next_rx:
3223 sw_cons = NEXT_RX_BD(sw_cons);
3224 sw_prod = NEXT_RX_BD(sw_prod);
3225
3226 if ((rx_pkt == budget))
3227 break;
3228
3229
3230 if (sw_cons == hw_cons) {
3231 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3232 rmb();
3233 }
3234 }
3235 rxr->rx_cons = sw_cons;
3236 rxr->rx_prod = sw_prod;
3237
3238 if (pg_ring_used)
3239 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3240
3241 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3242
3243 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3244
3245 mmiowb();
3246
3247 return rx_pkt;
3248
3249}
3250
3251
3252
3253
3254static irqreturn_t
3255bnx2_msi(int irq, void *dev_instance)
3256{
3257 struct bnx2_napi *bnapi = dev_instance;
3258 struct bnx2 *bp = bnapi->bp;
3259
3260 prefetch(bnapi->status_blk.msi);
3261 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3262 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3263 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3264
3265
3266 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3267 return IRQ_HANDLED;
3268
3269 napi_schedule(&bnapi->napi);
3270
3271 return IRQ_HANDLED;
3272}
3273
3274static irqreturn_t
3275bnx2_msi_1shot(int irq, void *dev_instance)
3276{
3277 struct bnx2_napi *bnapi = dev_instance;
3278 struct bnx2 *bp = bnapi->bp;
3279
3280 prefetch(bnapi->status_blk.msi);
3281
3282
3283 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3284 return IRQ_HANDLED;
3285
3286 napi_schedule(&bnapi->napi);
3287
3288 return IRQ_HANDLED;
3289}
3290
3291static irqreturn_t
3292bnx2_interrupt(int irq, void *dev_instance)
3293{
3294 struct bnx2_napi *bnapi = dev_instance;
3295 struct bnx2 *bp = bnapi->bp;
3296 struct status_block *sblk = bnapi->status_blk.msi;
3297
3298
3299
3300
3301
3302
3303
3304 if ((sblk->status_idx == bnapi->last_status_idx) &&
3305 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3306 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3307 return IRQ_NONE;
3308
3309 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3310 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3311 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3312
3313
3314
3315
3316 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3317
3318
3319 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3320 return IRQ_HANDLED;
3321
3322 if (napi_schedule_prep(&bnapi->napi)) {
3323 bnapi->last_status_idx = sblk->status_idx;
3324 __napi_schedule(&bnapi->napi);
3325 }
3326
3327 return IRQ_HANDLED;
3328}
3329
3330static inline int
3331bnx2_has_fast_work(struct bnx2_napi *bnapi)
3332{
3333 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3334 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3335
3336 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3337 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3338 return 1;
3339 return 0;
3340}
3341
3342#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3343 STATUS_ATTN_BITS_TIMER_ABORT)
3344
3345static inline int
3346bnx2_has_work(struct bnx2_napi *bnapi)
3347{
3348 struct status_block *sblk = bnapi->status_blk.msi;
3349
3350 if (bnx2_has_fast_work(bnapi))
3351 return 1;
3352
3353#ifdef BCM_CNIC
3354 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3355 return 1;
3356#endif
3357
3358 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3359 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3360 return 1;
3361
3362 return 0;
3363}
3364
3365static void
3366bnx2_chk_missed_msi(struct bnx2 *bp)
3367{
3368 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3369 u32 msi_ctrl;
3370
3371 if (bnx2_has_work(bnapi)) {
3372 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3373 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3374 return;
3375
3376 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3377 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3378 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3379 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3380 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3381 }
3382 }
3383
3384 bp->idle_chk_status_idx = bnapi->last_status_idx;
3385}
3386
3387#ifdef BCM_CNIC
3388static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3389{
3390 struct cnic_ops *c_ops;
3391
3392 if (!bnapi->cnic_present)
3393 return;
3394
3395 rcu_read_lock();
3396 c_ops = rcu_dereference(bp->cnic_ops);
3397 if (c_ops)
3398 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3399 bnapi->status_blk.msi);
3400 rcu_read_unlock();
3401}
3402#endif
3403
3404static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3405{
3406 struct status_block *sblk = bnapi->status_blk.msi;
3407 u32 status_attn_bits = sblk->status_attn_bits;
3408 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3409
3410 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3411 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3412
3413 bnx2_phy_int(bp, bnapi);
3414
3415
3416
3417
3418 REG_WR(bp, BNX2_HC_COMMAND,
3419 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3420 REG_RD(bp, BNX2_HC_COMMAND);
3421 }
3422}
3423
3424static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3425 int work_done, int budget)
3426{
3427 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3428 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3429
3430 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3431 bnx2_tx_int(bp, bnapi, 0);
3432
3433 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3434 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3435
3436 return work_done;
3437}
3438
3439static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3440{
3441 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3442 struct bnx2 *bp = bnapi->bp;
3443 int work_done = 0;
3444 struct status_block_msix *sblk = bnapi->status_blk.msix;
3445
3446 while (1) {
3447 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3448 if (unlikely(work_done >= budget))
3449 break;
3450
3451 bnapi->last_status_idx = sblk->status_idx;
3452
3453 rmb();
3454 if (likely(!bnx2_has_fast_work(bnapi))) {
3455
3456 napi_complete(napi);
3457 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3458 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3459 bnapi->last_status_idx);
3460 break;
3461 }
3462 }
3463 return work_done;
3464}
3465
3466static int bnx2_poll(struct napi_struct *napi, int budget)
3467{
3468 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3469 struct bnx2 *bp = bnapi->bp;
3470 int work_done = 0;
3471 struct status_block *sblk = bnapi->status_blk.msi;
3472
3473 while (1) {
3474 bnx2_poll_link(bp, bnapi);
3475
3476 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3477
3478#ifdef BCM_CNIC
3479 bnx2_poll_cnic(bp, bnapi);
3480#endif
3481
3482
3483
3484
3485
3486 bnapi->last_status_idx = sblk->status_idx;
3487
3488 if (unlikely(work_done >= budget))
3489 break;
3490
3491 rmb();
3492 if (likely(!bnx2_has_work(bnapi))) {
3493 napi_complete(napi);
3494 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3495 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3496 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3497 bnapi->last_status_idx);
3498 break;
3499 }
3500 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3501 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3502 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3503 bnapi->last_status_idx);
3504
3505 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3506 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3507 bnapi->last_status_idx);
3508 break;
3509 }
3510 }
3511
3512 return work_done;
3513}
3514
3515
3516
3517
3518static void
3519bnx2_set_rx_mode(struct net_device *dev)
3520{
3521 struct bnx2 *bp = netdev_priv(dev);
3522 u32 rx_mode, sort_mode;
3523 struct netdev_hw_addr *ha;
3524 int i;
3525
3526 if (!netif_running(dev))
3527 return;
3528
3529 spin_lock_bh(&bp->phy_lock);
3530
3531 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3532 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3533 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3534#ifdef BCM_VLAN
3535 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3536 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3537#else
3538 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3539 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3540#endif
3541 if (dev->flags & IFF_PROMISC) {
3542
3543 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3544 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3545 BNX2_RPM_SORT_USER0_PROM_VLAN;
3546 }
3547 else if (dev->flags & IFF_ALLMULTI) {
3548 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3549 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3550 0xffffffff);
3551 }
3552 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3553 }
3554 else {
3555
3556 struct dev_mc_list *mclist;
3557 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3558 u32 regidx;
3559 u32 bit;
3560 u32 crc;
3561
3562 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3563
3564 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3565 i++, mclist = mclist->next) {
3566
3567 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3568 bit = crc & 0xff;
3569 regidx = (bit & 0xe0) >> 5;
3570 bit &= 0x1f;
3571 mc_filter[regidx] |= (1 << bit);
3572 }
3573
3574 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3575 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3576 mc_filter[i]);
3577 }
3578
3579 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3580 }
3581
3582 if (dev->uc.count > BNX2_MAX_UNICAST_ADDRESSES) {
3583 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3584 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3585 BNX2_RPM_SORT_USER0_PROM_VLAN;
3586 } else if (!(dev->flags & IFF_PROMISC)) {
3587
3588 i = 0;
3589 list_for_each_entry(ha, &dev->uc.list, list) {
3590 bnx2_set_mac_addr(bp, ha->addr,
3591 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3592 sort_mode |= (1 <<
3593 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3594 i++;
3595 }
3596
3597 }
3598
3599 if (rx_mode != bp->rx_mode) {
3600 bp->rx_mode = rx_mode;
3601 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3602 }
3603
3604 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3605 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3606 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3607
3608 spin_unlock_bh(&bp->phy_lock);
3609}
3610
3611static int __devinit
3612check_fw_section(const struct firmware *fw,
3613 const struct bnx2_fw_file_section *section,
3614 u32 alignment, bool non_empty)
3615{
3616 u32 offset = be32_to_cpu(section->offset);
3617 u32 len = be32_to_cpu(section->len);
3618
3619 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3620 return -EINVAL;
3621 if ((non_empty && len == 0) || len > fw->size - offset ||
3622 len & (alignment - 1))
3623 return -EINVAL;
3624 return 0;
3625}
3626
3627static int __devinit
3628check_mips_fw_entry(const struct firmware *fw,
3629 const struct bnx2_mips_fw_file_entry *entry)
3630{
3631 if (check_fw_section(fw, &entry->text, 4, true) ||
3632 check_fw_section(fw, &entry->data, 4, false) ||
3633 check_fw_section(fw, &entry->rodata, 4, false))
3634 return -EINVAL;
3635 return 0;
3636}
3637
3638static int __devinit
3639bnx2_request_firmware(struct bnx2 *bp)
3640{
3641 const char *mips_fw_file, *rv2p_fw_file;
3642 const struct bnx2_mips_fw_file *mips_fw;
3643 const struct bnx2_rv2p_fw_file *rv2p_fw;
3644 int rc;
3645
3646 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3647 mips_fw_file = FW_MIPS_FILE_09;
3648 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3649 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3650 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3651 else
3652 rv2p_fw_file = FW_RV2P_FILE_09;
3653 } else {
3654 mips_fw_file = FW_MIPS_FILE_06;
3655 rv2p_fw_file = FW_RV2P_FILE_06;
3656 }
3657
3658 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3659 if (rc) {
3660 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3661 mips_fw_file);
3662 return rc;
3663 }
3664
3665 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3666 if (rc) {
3667 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3668 rv2p_fw_file);
3669 return rc;
3670 }
3671 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3672 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3673 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3674 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3675 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3676 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3677 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3678 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3679 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3680 mips_fw_file);
3681 return -EINVAL;
3682 }
3683 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3684 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3685 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3686 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3687 rv2p_fw_file);
3688 return -EINVAL;
3689 }
3690
3691 return 0;
3692}
3693
3694static u32
3695rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3696{
3697 switch (idx) {
3698 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3699 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3700 rv2p_code |= RV2P_BD_PAGE_SIZE;
3701 break;
3702 }
3703 return rv2p_code;
3704}
3705
3706static int
3707load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3708 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3709{
3710 u32 rv2p_code_len, file_offset;
3711 __be32 *rv2p_code;
3712 int i;
3713 u32 val, cmd, addr;
3714
3715 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3716 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3717
3718 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3719
3720 if (rv2p_proc == RV2P_PROC1) {
3721 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3722 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3723 } else {
3724 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3725 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3726 }
3727
3728 for (i = 0; i < rv2p_code_len; i += 8) {
3729 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3730 rv2p_code++;
3731 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3732 rv2p_code++;
3733
3734 val = (i / 8) | cmd;
3735 REG_WR(bp, addr, val);
3736 }
3737
3738 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3739 for (i = 0; i < 8; i++) {
3740 u32 loc, code;
3741
3742 loc = be32_to_cpu(fw_entry->fixup[i]);
3743 if (loc && ((loc * 4) < rv2p_code_len)) {
3744 code = be32_to_cpu(*(rv2p_code + loc - 1));
3745 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3746 code = be32_to_cpu(*(rv2p_code + loc));
3747 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3748 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3749
3750 val = (loc / 2) | cmd;
3751 REG_WR(bp, addr, val);
3752 }
3753 }
3754
3755
3756 if (rv2p_proc == RV2P_PROC1) {
3757 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3758 }
3759 else {
3760 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3761 }
3762
3763 return 0;
3764}
3765
3766static int
3767load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3768 const struct bnx2_mips_fw_file_entry *fw_entry)
3769{
3770 u32 addr, len, file_offset;
3771 __be32 *data;
3772 u32 offset;
3773 u32 val;
3774
3775
3776 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3777 val |= cpu_reg->mode_value_halt;
3778 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3779 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3780
3781
3782 addr = be32_to_cpu(fw_entry->text.addr);
3783 len = be32_to_cpu(fw_entry->text.len);
3784 file_offset = be32_to_cpu(fw_entry->text.offset);
3785 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3786
3787 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3788 if (len) {
3789 int j;
3790
3791 for (j = 0; j < (len / 4); j++, offset += 4)
3792 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3793 }
3794
3795
3796 addr = be32_to_cpu(fw_entry->data.addr);
3797 len = be32_to_cpu(fw_entry->data.len);
3798 file_offset = be32_to_cpu(fw_entry->data.offset);
3799 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3800
3801 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3802 if (len) {
3803 int j;
3804
3805 for (j = 0; j < (len / 4); j++, offset += 4)
3806 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3807 }
3808
3809
3810 addr = be32_to_cpu(fw_entry->rodata.addr);
3811 len = be32_to_cpu(fw_entry->rodata.len);
3812 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3813 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3814
3815 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3816 if (len) {
3817 int j;
3818
3819 for (j = 0; j < (len / 4); j++, offset += 4)
3820 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3821 }
3822
3823
3824 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3825
3826 val = be32_to_cpu(fw_entry->start_addr);
3827 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3828
3829
3830 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3831 val &= ~cpu_reg->mode_value_halt;
3832 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3833 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3834
3835 return 0;
3836}
3837
3838static int
3839bnx2_init_cpus(struct bnx2 *bp)
3840{
3841 const struct bnx2_mips_fw_file *mips_fw =
3842 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3843 const struct bnx2_rv2p_fw_file *rv2p_fw =
3844 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3845 int rc;
3846
3847
3848 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3849 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3850
3851
3852 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3853 if (rc)
3854 goto init_cpu_err;
3855
3856
3857 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3858 if (rc)
3859 goto init_cpu_err;
3860
3861
3862 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3863 if (rc)
3864 goto init_cpu_err;
3865
3866
3867 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3868 if (rc)
3869 goto init_cpu_err;
3870
3871
3872 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3873
3874init_cpu_err:
3875 return rc;
3876}
3877
3878static int
3879bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3880{
3881 u16 pmcsr;
3882
3883 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3884
3885 switch (state) {
3886 case PCI_D0: {
3887 u32 val;
3888
3889 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3890 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3891 PCI_PM_CTRL_PME_STATUS);
3892
3893 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3894
3895 msleep(20);
3896
3897 val = REG_RD(bp, BNX2_EMAC_MODE);
3898 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3899 val &= ~BNX2_EMAC_MODE_MPKT;
3900 REG_WR(bp, BNX2_EMAC_MODE, val);
3901
3902 val = REG_RD(bp, BNX2_RPM_CONFIG);
3903 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3904 REG_WR(bp, BNX2_RPM_CONFIG, val);
3905 break;
3906 }
3907 case PCI_D3hot: {
3908 int i;
3909 u32 val, wol_msg;
3910
3911 if (bp->wol) {
3912 u32 advertising;
3913 u8 autoneg;
3914
3915 autoneg = bp->autoneg;
3916 advertising = bp->advertising;
3917
3918 if (bp->phy_port == PORT_TP) {
3919 bp->autoneg = AUTONEG_SPEED;
3920 bp->advertising = ADVERTISED_10baseT_Half |
3921 ADVERTISED_10baseT_Full |
3922 ADVERTISED_100baseT_Half |
3923 ADVERTISED_100baseT_Full |
3924 ADVERTISED_Autoneg;
3925 }
3926
3927 spin_lock_bh(&bp->phy_lock);
3928 bnx2_setup_phy(bp, bp->phy_port);
3929 spin_unlock_bh(&bp->phy_lock);
3930
3931 bp->autoneg = autoneg;
3932 bp->advertising = advertising;
3933
3934 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3935
3936 val = REG_RD(bp, BNX2_EMAC_MODE);
3937
3938
3939 val &= ~BNX2_EMAC_MODE_PORT;
3940 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3941 BNX2_EMAC_MODE_ACPI_RCVD |
3942 BNX2_EMAC_MODE_MPKT;
3943 if (bp->phy_port == PORT_TP)
3944 val |= BNX2_EMAC_MODE_PORT_MII;
3945 else {
3946 val |= BNX2_EMAC_MODE_PORT_GMII;
3947 if (bp->line_speed == SPEED_2500)
3948 val |= BNX2_EMAC_MODE_25G_MODE;
3949 }
3950
3951 REG_WR(bp, BNX2_EMAC_MODE, val);
3952
3953
3954 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3955 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3956 0xffffffff);
3957 }
3958 REG_WR(bp, BNX2_EMAC_RX_MODE,
3959 BNX2_EMAC_RX_MODE_SORT_MODE);
3960
3961 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3962 BNX2_RPM_SORT_USER0_MC_EN;
3963 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3964 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3965 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3966 BNX2_RPM_SORT_USER0_ENA);
3967
3968
3969 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3970 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3971 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3972 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3973
3974 val = REG_RD(bp, BNX2_RPM_CONFIG);
3975 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3976 REG_WR(bp, BNX2_RPM_CONFIG, val);
3977
3978 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3979 }
3980 else {
3981 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3982 }
3983
3984 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3985 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3986 1, 0);
3987
3988 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3989 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3990 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3991
3992 if (bp->wol)
3993 pmcsr |= 3;
3994 }
3995 else {
3996 pmcsr |= 3;
3997 }
3998 if (bp->wol) {
3999 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
4000 }
4001 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
4002 pmcsr);
4003
4004
4005
4006
4007 udelay(50);
4008 break;
4009 }
4010 default:
4011 return -EINVAL;
4012 }
4013 return 0;
4014}
4015
4016static int
4017bnx2_acquire_nvram_lock(struct bnx2 *bp)
4018{
4019 u32 val;
4020 int j;
4021
4022
4023 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4024 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4025 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4026 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4027 break;
4028
4029 udelay(5);
4030 }
4031
4032 if (j >= NVRAM_TIMEOUT_COUNT)
4033 return -EBUSY;
4034
4035 return 0;
4036}
4037
4038static int
4039bnx2_release_nvram_lock(struct bnx2 *bp)
4040{
4041 int j;
4042 u32 val;
4043
4044
4045 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4046
4047 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4048 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4049 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4050 break;
4051
4052 udelay(5);
4053 }
4054
4055 if (j >= NVRAM_TIMEOUT_COUNT)
4056 return -EBUSY;
4057
4058 return 0;
4059}
4060
4061
4062static int
4063bnx2_enable_nvram_write(struct bnx2 *bp)
4064{
4065 u32 val;
4066
4067 val = REG_RD(bp, BNX2_MISC_CFG);
4068 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4069
4070 if (bp->flash_info->flags & BNX2_NV_WREN) {
4071 int j;
4072
4073 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4074 REG_WR(bp, BNX2_NVM_COMMAND,
4075 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4076
4077 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4078 udelay(5);
4079
4080 val = REG_RD(bp, BNX2_NVM_COMMAND);
4081 if (val & BNX2_NVM_COMMAND_DONE)
4082 break;
4083 }
4084
4085 if (j >= NVRAM_TIMEOUT_COUNT)
4086 return -EBUSY;
4087 }
4088 return 0;
4089}
4090
4091static void
4092bnx2_disable_nvram_write(struct bnx2 *bp)
4093{
4094 u32 val;
4095
4096 val = REG_RD(bp, BNX2_MISC_CFG);
4097 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4098}
4099
4100
4101static void
4102bnx2_enable_nvram_access(struct bnx2 *bp)
4103{
4104 u32 val;
4105
4106 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4107
4108 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4109 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4110}
4111
4112static void
4113bnx2_disable_nvram_access(struct bnx2 *bp)
4114{
4115 u32 val;
4116
4117 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4118
4119 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4120 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4121 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4122}
4123
4124static int
4125bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4126{
4127 u32 cmd;
4128 int j;
4129
4130 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4131
4132 return 0;
4133
4134
4135 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4136 BNX2_NVM_COMMAND_DOIT;
4137
4138
4139 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4140
4141
4142 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4143
4144
4145 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4146
4147
4148 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4149 u32 val;
4150
4151 udelay(5);
4152
4153 val = REG_RD(bp, BNX2_NVM_COMMAND);
4154 if (val & BNX2_NVM_COMMAND_DONE)
4155 break;
4156 }
4157
4158 if (j >= NVRAM_TIMEOUT_COUNT)
4159 return -EBUSY;
4160
4161 return 0;
4162}
4163
4164static int
4165bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4166{
4167 u32 cmd;
4168 int j;
4169
4170
4171 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4172
4173
4174 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4175 offset = ((offset / bp->flash_info->page_size) <<
4176 bp->flash_info->page_bits) +
4177 (offset % bp->flash_info->page_size);
4178 }
4179
4180
4181 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4182
4183
4184 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4185
4186
4187 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4188
4189
4190 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4191 u32 val;
4192
4193 udelay(5);
4194
4195 val = REG_RD(bp, BNX2_NVM_COMMAND);
4196 if (val & BNX2_NVM_COMMAND_DONE) {
4197 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4198 memcpy(ret_val, &v, 4);
4199 break;
4200 }
4201 }
4202 if (j >= NVRAM_TIMEOUT_COUNT)
4203 return -EBUSY;
4204
4205 return 0;
4206}
4207
4208
4209static int
4210bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4211{
4212 u32 cmd;
4213 __be32 val32;
4214 int j;
4215
4216
4217 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4218
4219
4220 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4221 offset = ((offset / bp->flash_info->page_size) <<
4222 bp->flash_info->page_bits) +
4223 (offset % bp->flash_info->page_size);
4224 }
4225
4226
4227 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4228
4229 memcpy(&val32, val, 4);
4230
4231
4232 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4233
4234
4235 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4236
4237
4238 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4239
4240
4241 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4242 udelay(5);
4243
4244 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4245 break;
4246 }
4247 if (j >= NVRAM_TIMEOUT_COUNT)
4248 return -EBUSY;
4249
4250 return 0;
4251}
4252
4253static int
4254bnx2_init_nvram(struct bnx2 *bp)
4255{
4256 u32 val;
4257 int j, entry_count, rc = 0;
4258 const struct flash_spec *flash;
4259
4260 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4261 bp->flash_info = &flash_5709;
4262 goto get_flash_size;
4263 }
4264
4265
4266 val = REG_RD(bp, BNX2_NVM_CFG1);
4267
4268 entry_count = ARRAY_SIZE(flash_table);
4269
4270 if (val & 0x40000000) {
4271
4272
4273 for (j = 0, flash = &flash_table[0]; j < entry_count;
4274 j++, flash++) {
4275 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4276 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4277 bp->flash_info = flash;
4278 break;
4279 }
4280 }
4281 }
4282 else {
4283 u32 mask;
4284
4285
4286 if (val & (1 << 23))
4287 mask = FLASH_BACKUP_STRAP_MASK;
4288 else
4289 mask = FLASH_STRAP_MASK;
4290
4291 for (j = 0, flash = &flash_table[0]; j < entry_count;
4292 j++, flash++) {
4293
4294 if ((val & mask) == (flash->strapping & mask)) {
4295 bp->flash_info = flash;
4296
4297
4298 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4299 return rc;
4300
4301
4302 bnx2_enable_nvram_access(bp);
4303
4304
4305 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4306 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4307 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4308 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4309
4310
4311 bnx2_disable_nvram_access(bp);
4312 bnx2_release_nvram_lock(bp);
4313
4314 break;
4315 }
4316 }
4317 }
4318
4319 if (j == entry_count) {
4320 bp->flash_info = NULL;
4321 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
4322 return -ENODEV;
4323 }
4324
4325get_flash_size:
4326 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4327 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4328 if (val)
4329 bp->flash_size = val;
4330 else
4331 bp->flash_size = bp->flash_info->total_size;
4332
4333 return rc;
4334}
4335
4336static int
4337bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4338 int buf_size)
4339{
4340 int rc = 0;
4341 u32 cmd_flags, offset32, len32, extra;
4342
4343 if (buf_size == 0)
4344 return 0;
4345
4346
4347 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4348 return rc;
4349
4350
4351 bnx2_enable_nvram_access(bp);
4352
4353 len32 = buf_size;
4354 offset32 = offset;
4355 extra = 0;
4356
4357 cmd_flags = 0;
4358
4359 if (offset32 & 3) {
4360 u8 buf[4];
4361 u32 pre_len;
4362
4363 offset32 &= ~3;
4364 pre_len = 4 - (offset & 3);
4365
4366 if (pre_len >= len32) {
4367 pre_len = len32;
4368 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4369 BNX2_NVM_COMMAND_LAST;
4370 }
4371 else {
4372 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4373 }
4374
4375 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4376
4377 if (rc)
4378 return rc;
4379
4380 memcpy(ret_buf, buf + (offset & 3), pre_len);
4381
4382 offset32 += 4;
4383 ret_buf += pre_len;
4384 len32 -= pre_len;
4385 }
4386 if (len32 & 3) {
4387 extra = 4 - (len32 & 3);
4388 len32 = (len32 + 4) & ~3;
4389 }
4390
4391 if (len32 == 4) {
4392 u8 buf[4];
4393
4394 if (cmd_flags)
4395 cmd_flags = BNX2_NVM_COMMAND_LAST;
4396 else
4397 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4398 BNX2_NVM_COMMAND_LAST;
4399
4400 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4401
4402 memcpy(ret_buf, buf, 4 - extra);
4403 }
4404 else if (len32 > 0) {
4405 u8 buf[4];
4406
4407
4408 if (cmd_flags)
4409 cmd_flags = 0;
4410 else
4411 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4412
4413 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4414
4415
4416 offset32 += 4;
4417 ret_buf += 4;
4418 len32 -= 4;
4419
4420 while (len32 > 4 && rc == 0) {
4421 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4422
4423
4424 offset32 += 4;
4425 ret_buf += 4;
4426 len32 -= 4;
4427 }
4428
4429 if (rc)
4430 return rc;
4431
4432 cmd_flags = BNX2_NVM_COMMAND_LAST;
4433 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4434
4435 memcpy(ret_buf, buf, 4 - extra);
4436 }
4437
4438
4439 bnx2_disable_nvram_access(bp);
4440
4441 bnx2_release_nvram_lock(bp);
4442
4443 return rc;
4444}
4445
4446static int
4447bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4448 int buf_size)
4449{
4450 u32 written, offset32, len32;
4451 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4452 int rc = 0;
4453 int align_start, align_end;
4454
4455 buf = data_buf;
4456 offset32 = offset;
4457 len32 = buf_size;
4458 align_start = align_end = 0;
4459
4460 if ((align_start = (offset32 & 3))) {
4461 offset32 &= ~3;
4462 len32 += align_start;
4463 if (len32 < 4)
4464 len32 = 4;
4465 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4466 return rc;
4467 }
4468
4469 if (len32 & 3) {
4470 align_end = 4 - (len32 & 3);
4471 len32 += align_end;
4472 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4473 return rc;
4474 }
4475
4476 if (align_start || align_end) {
4477 align_buf = kmalloc(len32, GFP_KERNEL);
4478 if (align_buf == NULL)
4479 return -ENOMEM;
4480 if (align_start) {
4481 memcpy(align_buf, start, 4);
4482 }
4483 if (align_end) {
4484 memcpy(align_buf + len32 - 4, end, 4);
4485 }
4486 memcpy(align_buf + align_start, data_buf, buf_size);
4487 buf = align_buf;
4488 }
4489
4490 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4491 flash_buffer = kmalloc(264, GFP_KERNEL);
4492 if (flash_buffer == NULL) {
4493 rc = -ENOMEM;
4494 goto nvram_write_end;
4495 }
4496 }
4497
4498 written = 0;
4499 while ((written < len32) && (rc == 0)) {
4500 u32 page_start, page_end, data_start, data_end;
4501 u32 addr, cmd_flags;
4502 int i;
4503
4504
4505 page_start = offset32 + written;
4506 page_start -= (page_start % bp->flash_info->page_size);
4507
4508 page_end = page_start + bp->flash_info->page_size;
4509
4510 data_start = (written == 0) ? offset32 : page_start;
4511
4512 data_end = (page_end > offset32 + len32) ?
4513 (offset32 + len32) : page_end;
4514
4515
4516 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4517 goto nvram_write_end;
4518
4519
4520 bnx2_enable_nvram_access(bp);
4521
4522 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4523 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4524 int j;
4525
4526
4527
4528 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4529 if (j == (bp->flash_info->page_size - 4)) {
4530 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4531 }
4532 rc = bnx2_nvram_read_dword(bp,
4533 page_start + j,
4534 &flash_buffer[j],
4535 cmd_flags);
4536
4537 if (rc)
4538 goto nvram_write_end;
4539
4540 cmd_flags = 0;
4541 }
4542 }
4543
4544
4545 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4546 goto nvram_write_end;
4547
4548
4549
4550 i = 0;
4551 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4552
4553 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4554 goto nvram_write_end;
4555
4556
4557 bnx2_enable_nvram_write(bp);
4558
4559 for (addr = page_start; addr < data_start;
4560 addr += 4, i += 4) {
4561
4562 rc = bnx2_nvram_write_dword(bp, addr,
4563 &flash_buffer[i], cmd_flags);
4564
4565 if (rc != 0)
4566 goto nvram_write_end;
4567
4568 cmd_flags = 0;
4569 }
4570 }
4571
4572
4573 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4574 if ((addr == page_end - 4) ||
4575 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4576 (addr == data_end - 4))) {
4577
4578 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4579 }
4580 rc = bnx2_nvram_write_dword(bp, addr, buf,
4581 cmd_flags);
4582
4583 if (rc != 0)
4584 goto nvram_write_end;
4585
4586 cmd_flags = 0;
4587 buf += 4;
4588 }
4589
4590
4591
4592 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4593 for (addr = data_end; addr < page_end;
4594 addr += 4, i += 4) {
4595
4596 if (addr == page_end-4) {
4597 cmd_flags = BNX2_NVM_COMMAND_LAST;
4598 }
4599 rc = bnx2_nvram_write_dword(bp, addr,
4600 &flash_buffer[i], cmd_flags);
4601
4602 if (rc != 0)
4603 goto nvram_write_end;
4604
4605 cmd_flags = 0;
4606 }
4607 }
4608
4609
4610 bnx2_disable_nvram_write(bp);
4611
4612
4613 bnx2_disable_nvram_access(bp);
4614 bnx2_release_nvram_lock(bp);
4615
4616
4617 written += data_end - data_start;
4618 }
4619
4620nvram_write_end:
4621 kfree(flash_buffer);
4622 kfree(align_buf);
4623 return rc;
4624}
4625
4626static void
4627bnx2_init_fw_cap(struct bnx2 *bp)
4628{
4629 u32 val, sig = 0;
4630
4631 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4632 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4633
4634 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4635 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4636
4637 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4638 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4639 return;
4640
4641 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4642 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4643 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4644 }
4645
4646 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4647 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4648 u32 link;
4649
4650 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4651
4652 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4653 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4654 bp->phy_port = PORT_FIBRE;
4655 else
4656 bp->phy_port = PORT_TP;
4657
4658 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4659 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4660 }
4661
4662 if (netif_running(bp->dev) && sig)
4663 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4664}
4665
4666static void
4667bnx2_setup_msix_tbl(struct bnx2 *bp)
4668{
4669 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4670
4671 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4672 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4673}
4674
4675static int
4676bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4677{
4678 u32 val;
4679 int i, rc = 0;
4680 u8 old_port;
4681
4682
4683
4684 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4685 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4686 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4687 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4688 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4689 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4690 udelay(5);
4691
4692
4693 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4694
4695
4696
4697 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4698 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4699
4700
4701
4702 val = REG_RD(bp, BNX2_MISC_ID);
4703
4704 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4705 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4706 REG_RD(bp, BNX2_MISC_COMMAND);
4707 udelay(5);
4708
4709 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4710 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4711
4712 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4713
4714 } else {
4715 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4716 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4717 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4718
4719
4720 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4721
4722
4723
4724
4725
4726 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4727 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4728 msleep(20);
4729
4730
4731 for (i = 0; i < 10; i++) {
4732 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4733 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4734 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4735 break;
4736 udelay(10);
4737 }
4738
4739 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4740 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4741 printk(KERN_ERR PFX "Chip reset did not complete\n");
4742 return -EBUSY;
4743 }
4744 }
4745
4746
4747 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4748 if (val != 0x01020304) {
4749 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4750 return -ENODEV;
4751 }
4752
4753
4754 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4755 if (rc)
4756 return rc;
4757
4758 spin_lock_bh(&bp->phy_lock);
4759 old_port = bp->phy_port;
4760 bnx2_init_fw_cap(bp);
4761 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4762 old_port != bp->phy_port)
4763 bnx2_set_default_remote_link(bp);
4764 spin_unlock_bh(&bp->phy_lock);
4765
4766 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4767
4768
4769 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4770
4771
4772 rc = bnx2_alloc_bad_rbuf(bp);
4773 }
4774
4775 if (bp->flags & BNX2_FLAG_USING_MSIX)
4776 bnx2_setup_msix_tbl(bp);
4777
4778 return rc;
4779}
4780
4781static int
4782bnx2_init_chip(struct bnx2 *bp)
4783{
4784 u32 val, mtu;
4785 int rc, i;
4786
4787
4788 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4789
4790 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4791 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4792#ifdef __BIG_ENDIAN
4793 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4794#endif
4795 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4796 DMA_READ_CHANS << 12 |
4797 DMA_WRITE_CHANS << 16;
4798
4799 val |= (0x2 << 20) | (1 << 11);
4800
4801 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4802 val |= (1 << 23);
4803
4804 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4805 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4806 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4807
4808 REG_WR(bp, BNX2_DMA_CONFIG, val);
4809
4810 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4811 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4812 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4813 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4814 }
4815
4816 if (bp->flags & BNX2_FLAG_PCIX) {
4817 u16 val16;
4818
4819 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4820 &val16);
4821 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4822 val16 & ~PCI_X_CMD_ERO);
4823 }
4824
4825 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4826 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4827 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4828 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4829
4830
4831
4832 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4833 rc = bnx2_init_5709_context(bp);
4834 if (rc)
4835 return rc;
4836 } else
4837 bnx2_init_context(bp);
4838
4839 if ((rc = bnx2_init_cpus(bp)) != 0)
4840 return rc;
4841
4842 bnx2_init_nvram(bp);
4843
4844 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4845
4846 val = REG_RD(bp, BNX2_MQ_CONFIG);
4847 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4848 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4849 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4850 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4851 if (CHIP_REV(bp) == CHIP_REV_Ax)
4852 val |= BNX2_MQ_CONFIG_HALT_DIS;
4853 }
4854
4855 REG_WR(bp, BNX2_MQ_CONFIG, val);
4856
4857 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4858 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4859 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4860
4861 val = (BCM_PAGE_BITS - 8) << 24;
4862 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4863
4864
4865 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4866 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4867 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4868 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4869
4870 val = bp->mac_addr[0] +
4871 (bp->mac_addr[1] << 8) +
4872 (bp->mac_addr[2] << 16) +
4873 bp->mac_addr[3] +
4874 (bp->mac_addr[4] << 8) +
4875 (bp->mac_addr[5] << 16);
4876 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4877
4878
4879 mtu = bp->dev->mtu;
4880 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4881 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4882 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4883 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4884
4885 if (mtu < 1500)
4886 mtu = 1500;
4887
4888 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4889 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4890 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4891
4892 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4893 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4894 bp->bnx2_napi[i].last_status_idx = 0;
4895
4896 bp->idle_chk_status_idx = 0xffff;
4897
4898 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4899
4900
4901 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4902
4903 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4904 (u64) bp->status_blk_mapping & 0xffffffff);
4905 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4906
4907 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4908 (u64) bp->stats_blk_mapping & 0xffffffff);
4909 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4910 (u64) bp->stats_blk_mapping >> 32);
4911
4912 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4913 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4914
4915 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4916 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4917
4918 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4919 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4920
4921 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4922
4923 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4924
4925 REG_WR(bp, BNX2_HC_COM_TICKS,
4926 (bp->com_ticks_int << 16) | bp->com_ticks);
4927
4928 REG_WR(bp, BNX2_HC_CMD_TICKS,
4929 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4930
4931 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
4932 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4933 else
4934 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4935 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);
4936
4937 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4938 val = BNX2_HC_CONFIG_COLLECT_STATS;
4939 else {
4940 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4941 BNX2_HC_CONFIG_COLLECT_STATS;
4942 }
4943
4944 if (bp->irq_nvecs > 1) {
4945 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4946 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4947
4948 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4949 }
4950
4951 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4952 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
4953
4954 REG_WR(bp, BNX2_HC_CONFIG, val);
4955
4956 for (i = 1; i < bp->irq_nvecs; i++) {
4957 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4958 BNX2_HC_SB_CONFIG_1;
4959
4960 REG_WR(bp, base,
4961 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4962 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4963 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4964
4965 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4966 (bp->tx_quick_cons_trip_int << 16) |
4967 bp->tx_quick_cons_trip);
4968
4969 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4970 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4971
4972 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4973 (bp->rx_quick_cons_trip_int << 16) |
4974 bp->rx_quick_cons_trip);
4975
4976 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4977 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4978 }
4979
4980
4981 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4982
4983 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4984
4985
4986 bnx2_set_rx_mode(bp->dev);
4987
4988 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4989 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4990 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4991 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4992 }
4993 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4994 1, 0);
4995
4996 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4997 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4998
4999 udelay(20);
5000
5001 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5002
5003 return rc;
5004}
5005
5006static void
5007bnx2_clear_ring_states(struct bnx2 *bp)
5008{
5009 struct bnx2_napi *bnapi;
5010 struct bnx2_tx_ring_info *txr;
5011 struct bnx2_rx_ring_info *rxr;
5012 int i;
5013
5014 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5015 bnapi = &bp->bnx2_napi[i];
5016 txr = &bnapi->tx_ring;
5017 rxr = &bnapi->rx_ring;
5018
5019 txr->tx_cons = 0;
5020 txr->hw_tx_cons = 0;
5021 rxr->rx_prod_bseq = 0;
5022 rxr->rx_prod = 0;
5023 rxr->rx_cons = 0;
5024 rxr->rx_pg_prod = 0;
5025 rxr->rx_pg_cons = 0;
5026 }
5027}
5028
5029static void
5030bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5031{
5032 u32 val, offset0, offset1, offset2, offset3;
5033 u32 cid_addr = GET_CID_ADDR(cid);
5034
5035 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5036 offset0 = BNX2_L2CTX_TYPE_XI;
5037 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5038 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5039 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5040 } else {
5041 offset0 = BNX2_L2CTX_TYPE;
5042 offset1 = BNX2_L2CTX_CMD_TYPE;
5043 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5044 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5045 }
5046 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5047 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5048
5049 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5050 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5051
5052 val = (u64) txr->tx_desc_mapping >> 32;
5053 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5054
5055 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5056 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5057}
5058
5059static void
5060bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5061{
5062 struct tx_bd *txbd;
5063 u32 cid = TX_CID;
5064 struct bnx2_napi *bnapi;
5065 struct bnx2_tx_ring_info *txr;
5066
5067 bnapi = &bp->bnx2_napi[ring_num];
5068 txr = &bnapi->tx_ring;
5069
5070 if (ring_num == 0)
5071 cid = TX_CID;
5072 else
5073 cid = TX_TSS_CID + ring_num - 1;
5074
5075 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5076
5077 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5078
5079 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5080 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5081
5082 txr->tx_prod = 0;
5083 txr->tx_prod_bseq = 0;
5084
5085 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5086 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5087
5088 bnx2_init_tx_context(bp, cid, txr);
5089}
5090
5091static void
5092bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5093 int num_rings)
5094{
5095 int i;
5096 struct rx_bd *rxbd;
5097
5098 for (i = 0; i < num_rings; i++) {
5099 int j;
5100
5101 rxbd = &rx_ring[i][0];
5102 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5103 rxbd->rx_bd_len = buf_size;
5104 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5105 }
5106 if (i == (num_rings - 1))
5107 j = 0;
5108 else
5109 j = i + 1;
5110 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5111 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5112 }
5113}
5114
5115static void
5116bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5117{
5118 int i;
5119 u16 prod, ring_prod;
5120 u32 cid, rx_cid_addr, val;
5121 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5122 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5123
5124 if (ring_num == 0)
5125 cid = RX_CID;
5126 else
5127 cid = RX_RSS_CID + ring_num - 1;
5128
5129 rx_cid_addr = GET_CID_ADDR(cid);
5130
5131 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5132 bp->rx_buf_use_size, bp->rx_max_ring);
5133
5134 bnx2_init_rx_context(bp, cid);
5135
5136 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5137 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5138 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5139 }
5140
5141 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5142 if (bp->rx_pg_ring_size) {
5143 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5144 rxr->rx_pg_desc_mapping,
5145 PAGE_SIZE, bp->rx_max_pg_ring);
5146 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5147 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5148 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5149 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5150
5151 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5152 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5153
5154 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5155 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5156
5157 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5158 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5159 }
5160
5161 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5162 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5163
5164 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5165 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5166
5167 ring_prod = prod = rxr->rx_pg_prod;
5168 for (i = 0; i < bp->rx_pg_ring_size; i++) {
5169 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0) {
5170 printk(KERN_WARNING PFX "%s: init'ed rx page ring %d "
5171 "with %d/%d pages only\n",
5172 bp->dev->name, ring_num, i, bp->rx_pg_ring_size);
5173 break;
5174 }
5175 prod = NEXT_RX_BD(prod);
5176 ring_prod = RX_PG_RING_IDX(prod);
5177 }
5178 rxr->rx_pg_prod = prod;
5179
5180 ring_prod = prod = rxr->rx_prod;
5181 for (i = 0; i < bp->rx_ring_size; i++) {
5182 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0) {
5183 printk(KERN_WARNING PFX "%s: init'ed rx ring %d with "
5184 "%d/%d skbs only\n",
5185 bp->dev->name, ring_num, i, bp->rx_ring_size);
5186 break;
5187 }
5188 prod = NEXT_RX_BD(prod);
5189 ring_prod = RX_RING_IDX(prod);
5190 }
5191 rxr->rx_prod = prod;
5192
5193 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5194 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5195 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5196
5197 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5198 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5199
5200 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5201}
5202
5203static void
5204bnx2_init_all_rings(struct bnx2 *bp)
5205{
5206 int i;
5207 u32 val;
5208
5209 bnx2_clear_ring_states(bp);
5210
5211 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5212 for (i = 0; i < bp->num_tx_rings; i++)
5213 bnx2_init_tx_ring(bp, i);
5214
5215 if (bp->num_tx_rings > 1)
5216 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5217 (TX_TSS_CID << 7));
5218
5219 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5220 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5221
5222 for (i = 0; i < bp->num_rx_rings; i++)
5223 bnx2_init_rx_ring(bp, i);
5224
5225 if (bp->num_rx_rings > 1) {
5226 u32 tbl_32;
5227 u8 *tbl = (u8 *) &tbl_32;
5228
5229 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5230 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5231
5232 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5233 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5234 if ((i % 4) == 3)
5235 bnx2_reg_wr_ind(bp,
5236 BNX2_RXP_SCRATCH_RSS_TBL + i,
5237 cpu_to_be32(tbl_32));
5238 }
5239
5240 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5241 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5242
5243 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5244
5245 }
5246}
5247
5248static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5249{
5250 u32 max, num_rings = 1;
5251
5252 while (ring_size > MAX_RX_DESC_CNT) {
5253 ring_size -= MAX_RX_DESC_CNT;
5254 num_rings++;
5255 }
5256
5257 max = max_size;
5258 while ((max & num_rings) == 0)
5259 max >>= 1;
5260
5261 if (num_rings != max)
5262 max <<= 1;
5263
5264 return max;
5265}
5266
5267static void
5268bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5269{
5270 u32 rx_size, rx_space, jumbo_size;
5271
5272
5273 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5274
5275 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5276 sizeof(struct skb_shared_info);
5277
5278 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5279 bp->rx_pg_ring_size = 0;
5280 bp->rx_max_pg_ring = 0;
5281 bp->rx_max_pg_ring_idx = 0;
5282 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5283 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5284
5285 jumbo_size = size * pages;
5286 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5287 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5288
5289 bp->rx_pg_ring_size = jumbo_size;
5290 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5291 MAX_RX_PG_RINGS);
5292 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5293 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5294 bp->rx_copy_thresh = 0;
5295 }
5296
5297 bp->rx_buf_use_size = rx_size;
5298
5299 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5300 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5301 bp->rx_ring_size = size;
5302 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5303 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5304}
5305
5306static void
5307bnx2_free_tx_skbs(struct bnx2 *bp)
5308{
5309 int i;
5310
5311 for (i = 0; i < bp->num_tx_rings; i++) {
5312 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5313 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5314 int j;
5315
5316 if (txr->tx_buf_ring == NULL)
5317 continue;
5318
5319 for (j = 0; j < 
