LXR linux/drivers/w1/masters/ds1wm.c

   1/*
   2 * 1-wire busmaster driver for DS1WM and ASICs with embedded DS1WMs
   3 * such as HP iPAQs (including h5xxx, h2200, and devices with ASIC3
   4 * like hx4700).
   5 *
   6 * Copyright (c) 2004-2005, Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>
   7 * Copyright (c) 2004-2007, Matt Reimer <mreimer@vpop.net>
   8 *
   9 * Use consistent with the GNU GPL is permitted,
  10 * provided that this copyright notice is
  11 * preserved in its entirety in all copies and derived works.
  12 */
  13
  14#include <linux/module.h>
  15#include <linux/interrupt.h>
  16#include <linux/irq.h>
  17#include <linux/pm.h>
  18#include <linux/platform_device.h>
  19#include <linux/err.h>
  20#include <linux/delay.h>
  21#include <linux/mfd/core.h>
  22#include <linux/mfd/ds1wm.h>
  23
  24#include <asm/io.h>
  25
  26#include "../w1.h"
  27#include "../w1_int.h"
  28
  29
  30#define DS1WM_CMD       0x00    /* R/W 4 bits command */
  31#define DS1WM_DATA      0x01    /* R/W 8 bits, transmit/receive buffer */
  32#define DS1WM_INT       0x02    /* R/W interrupt status */
  33#define DS1WM_INT_EN    0x03    /* R/W interrupt enable */
  34#define DS1WM_CLKDIV    0x04    /* R/W 5 bits of divisor and pre-scale */
  35
  36#define DS1WM_CMD_1W_RESET  (1 << 0)    /* force reset on 1-wire bus */
  37#define DS1WM_CMD_SRA       (1 << 1)    /* enable Search ROM accelerator mode */
  38#define DS1WM_CMD_DQ_OUTPUT (1 << 2)    /* write only - forces bus low */
  39#define DS1WM_CMD_DQ_INPUT  (1 << 3)    /* read only - reflects state of bus */
  40#define DS1WM_CMD_RST       (1 << 5)    /* software reset */
  41#define DS1WM_CMD_OD        (1 << 7)    /* overdrive */
  42
  43#define DS1WM_INT_PD        (1 << 0)    /* presence detect */
  44#define DS1WM_INT_PDR       (1 << 1)    /* presence detect result */
  45#define DS1WM_INT_TBE       (1 << 2)    /* tx buffer empty */
  46#define DS1WM_INT_TSRE      (1 << 3)    /* tx shift register empty */
  47#define DS1WM_INT_RBF       (1 << 4)    /* rx buffer full */
  48#define DS1WM_INT_RSRF      (1 << 5)    /* rx shift register full */
  49
  50#define DS1WM_INTEN_EPD     (1 << 0)    /* enable presence detect int */
  51#define DS1WM_INTEN_IAS     (1 << 1)    /* INTR active state */
  52#define DS1WM_INTEN_ETBE    (1 << 2)    /* enable tx buffer empty int */
  53#define DS1WM_INTEN_ETMT    (1 << 3)    /* enable tx shift register empty int */
  54#define DS1WM_INTEN_ERBF    (1 << 4)    /* enable rx buffer full int */
  55#define DS1WM_INTEN_ERSRF   (1 << 5)    /* enable rx shift register full int */
  56#define DS1WM_INTEN_DQO     (1 << 6)    /* enable direct bus driving ops */
  57
  58
  59#define DS1WM_TIMEOUT (HZ * 5)
  60
  61static struct {
  62        unsigned long freq;
  63        unsigned long divisor;
  64} freq[] = {
  65        { 4000000, 0x8 },
  66        { 5000000, 0x2 },
  67        { 6000000, 0x5 },
  68        { 7000000, 0x3 },
  69        { 8000000, 0xc },
  70        { 10000000, 0x6 },
  71        { 12000000, 0x9 },
  72        { 14000000, 0x7 },
  73        { 16000000, 0x10 },
  74        { 20000000, 0xa },
  75        { 24000000, 0xd },
  76        { 28000000, 0xb },
  77        { 32000000, 0x14 },
  78        { 40000000, 0xe },
  79        { 48000000, 0x11 },
  80        { 56000000, 0xf },
  81        { 64000000, 0x18 },
  82        { 80000000, 0x12 },
  83        { 96000000, 0x15 },
  84        { 112000000, 0x13 },
  85        { 128000000, 0x1c },
  86};
  87
  88struct ds1wm_data {
  89        void            __iomem *map;
  90        int             bus_shift; /* # of shifts to calc register offsets */
  91        struct platform_device *pdev;
  92        struct mfd_cell *cell;
  93        int             irq;
  94        int             active_high;
  95        int             slave_present;
  96        void            *reset_complete;
  97        void            *read_complete;
  98        void            *write_complete;
  99        u8              read_byte; /* last byte received */
 100};
 101
 102static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
 103                                        u8 val)
 104{
 105        __raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift));
 106}
 107
 108static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
 109{
 110        return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift));
 111}
 112
 113
 114static irqreturn_t ds1wm_isr(int isr, void *data)
 115{
 116        struct ds1wm_data *ds1wm_data = data;
 117        u8 intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
 118
 119        ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
 120
 121        if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete)
 122                complete(ds1wm_data->reset_complete);
 123
 124        if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete)
 125                complete(ds1wm_data->write_complete);
 126
 127        if (intr & DS1WM_INT_RBF) {
 128                ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
 129                                                            DS1WM_DATA);
 130                if (ds1wm_data->read_complete)
 131                        complete(ds1wm_data->read_complete);
 132        }
 133
 134        return IRQ_HANDLED;
 135}
 136
 137static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
 138{
 139        unsigned long timeleft;
 140        DECLARE_COMPLETION_ONSTACK(reset_done);
 141
 142        ds1wm_data->reset_complete = &reset_done;
 143
 144        ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
 145                (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
 146
 147        ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
 148
 149        timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT);
 150        ds1wm_data->reset_complete = NULL;
 151        if (!timeleft) {
 152                dev_err(&ds1wm_data->pdev->dev, "reset failed\n");
 153                return 1;
 154        }
 155
 156        /* Wait for the end of the reset. According to the specs, the time
 157         * from when the interrupt is asserted to the end of the reset is:
 158         *     tRSTH  - tPDH  - tPDL - tPDI
 159         *     625 us - 60 us - 240 us - 100 ns = 324.9 us
 160         *
 161         * We'll wait a bit longer just to be sure.
 162         * Was udelay(500), but if it is going to busywait the cpu that long,
 163         * might as well come back later.
 164         */
 165        msleep(1);
 166
 167        ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
 168                DS1WM_INTEN_ERBF | DS1WM_INTEN_ETMT | DS1WM_INTEN_EPD |
 169                (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
 170
 171        if (!ds1wm_data->slave_present) {
 172                dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
 173                return 1;
 174        }
 175
 176        return 0;
 177}
 178
 179static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
 180{
 181        DECLARE_COMPLETION_ONSTACK(write_done);
 182        ds1wm_data->write_complete = &write_done;
 183
 184        ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
 185
 186        wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
 187        ds1wm_data->write_complete = NULL;
 188
 189        return 0;
 190}
 191
 192static int ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
 193{
 194        DECLARE_COMPLETION_ONSTACK(read_done);
 195        ds1wm_data->read_complete = &read_done;
 196
 197        ds1wm_write(ds1wm_data, write_data);
 198        wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
 199        ds1wm_data->read_complete = NULL;
 200
 201        return ds1wm_data->read_byte;
 202}
 203
 204static int ds1wm_find_divisor(int gclk)
 205{
 206        int i;
 207
 208        for (i = 0; i < ARRAY_SIZE(freq); i++)
 209                if (gclk <= freq[i].freq)
 210                        return freq[i].divisor;
 211
 212        return 0;
 213}
 214
 215static void ds1wm_up(struct ds1wm_data *ds1wm_data)
 216{
 217        int divisor;
 218        struct ds1wm_driver_data *plat = ds1wm_data->cell->driver_data;
 219
 220        if (ds1wm_data->cell->enable)
 221                ds1wm_data->cell->enable(ds1wm_data->pdev);
 222
 223        divisor = ds1wm_find_divisor(plat->clock_rate);
 224        if (divisor == 0) {
 225                dev_err(&ds1wm_data->pdev->dev,
 226                        "no suitable divisor for %dHz clock\n",
 227                        plat->clock_rate);
 228                return;
 229        }
 230        ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor);
 231
 232        /* Let the w1 clock stabilize. */
 233        msleep(1);
 234
 235        ds1wm_reset(ds1wm_data);
 236}
 237
 238static void ds1wm_down(struct ds1wm_data *ds1wm_data)
 239{
 240        ds1wm_reset(ds1wm_data);
 241
 242        /* Disable interrupts. */
 243        ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
 244                             ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0);
 245
 246        if (ds1wm_data->cell->disable)
 247                ds1wm_data->cell->disable(ds1wm_data->pdev);
 248}
 249
 250/* --------------------------------------------------------------------- */
 251/* w1 methods */
 252
 253static u8 ds1wm_read_byte(void *data)
 254{
 255        struct ds1wm_data *ds1wm_data = data;
 256
 257        return ds1wm_read(ds1wm_data, 0xff);
 258}
 259
 260static void ds1wm_write_byte(void *data, u8 byte)
 261{
 262        struct ds1wm_data *ds1wm_data = data;
 263
 264        ds1wm_write(ds1wm_data, byte);
 265}
 266
 267static u8 ds1wm_reset_bus(void *data)
 268{
 269        struct ds1wm_data *ds1wm_data = data;
 270
 271        ds1wm_reset(ds1wm_data);
 272
 273        return 0;
 274}
 275
 276static void ds1wm_search(void *data, struct w1_master *master_dev,
 277                        u8 search_type, w1_slave_found_callback slave_found)
 278{
 279        struct ds1wm_data *ds1wm_data = data;
 280        int i;
 281        unsigned long long rom_id;
 282
 283        /* XXX We need to iterate for multiple devices per the DS1WM docs.
 284         * See http://www.maxim-ic.com/appnotes.cfm/appnote_number/120. */
 285        if (ds1wm_reset(ds1wm_data))
 286                return;
 287
 288        ds1wm_write(ds1wm_data, search_type);
 289        ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
 290
 291        for (rom_id = 0, i = 0; i < 16; i++) {
 292
 293                unsigned char resp, r, d;
 294
 295                resp = ds1wm_read(ds1wm_data, 0x00);
 296
 297                r = ((resp & 0x02) >> 1) |
 298                    ((resp & 0x08) >> 2) |
 299                    ((resp & 0x20) >> 3) |
 300                    ((resp & 0x80) >> 4);
 301
 302                d = ((resp & 0x01) >> 0) |
 303                    ((resp & 0x04) >> 1) |
 304                    ((resp & 0x10) >> 2) |
 305                    ((resp & 0x40) >> 3);
 306
 307                rom_id |= (unsigned long long) r << (i * 4);
 308
 309        }
 310        dev_dbg(&ds1wm_data->pdev->dev, "found 0x%08llX\n", rom_id);
 311
 312        ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
 313        ds1wm_reset(ds1wm_data);
 314
 315        slave_found(master_dev, rom_id);
 316}
 317
 318/* --------------------------------------------------------------------- */
 319
 320static struct w1_bus_master ds1wm_master = {
 321        .read_byte  = ds1wm_read_byte,
 322        .write_byte = ds1wm_write_byte,
 323        .reset_bus  = ds1wm_reset_bus,
 324        .search     = ds1wm_search,
 325};
 326
 327static int ds1wm_probe(struct platform_device *pdev)
 328{
 329        struct ds1wm_data *ds1wm_data;
 330        struct ds1wm_driver_data *plat;
 331        struct resource *res;
 332        struct mfd_cell *cell;
 333        int ret;
 334
 335        if (!pdev)
 336                return -ENODEV;
 337
 338        cell = pdev->dev.platform_data;
 339        if (!cell)
 340                return -ENODEV;
 341
 342        ds1wm_data = kzalloc(sizeof(*ds1wm_data), GFP_KERNEL);
 343        if (!ds1wm_data)
 344                return -ENOMEM;
 345
 346        platform_set_drvdata(pdev, ds1wm_data);
 347
 348        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 349        if (!res) {
 350                ret = -ENXIO;
 351                goto err0;
 352        }
 353        ds1wm_data->map = ioremap(res->start, resource_size(res));
 354        if (!ds1wm_data->map) {
 355                ret = -ENOMEM;
 356                goto err0;
 357        }
 358        plat = cell->driver_data;
 359
 360        /* calculate bus shift from mem resource */
 361        ds1wm_data->bus_shift = resource_size(res) >> 3;
 362
 363        ds1wm_data->pdev = pdev;
 364        ds1wm_data->cell = cell;
 365
 366        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 367        if (!res) {
 368                ret = -ENXIO;
 369                goto err1;
 370        }
 371        ds1wm_data->irq = res->start;
 372        ds1wm_data->active_high = plat->active_high;
 373
 374        if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
 375                set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
 376        if (res->flags & IORESOURCE_IRQ_LOWEDGE)
 377                set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
 378
 379        ret = request_irq(ds1wm_data->irq, ds1wm_isr, IRQF_DISABLED,
 380                          "ds1wm", ds1wm_data);
 381        if (ret)
 382                goto err1;
 383
 384        ds1wm_up(ds1wm_data);
 385
 386        ds1wm_master.data = (void *)ds1wm_data;
 387
 388        ret = w1_add_master_device(&ds1wm_master);
 389        if (ret)
 390                goto err2;
 391
 392        return 0;
 393
 394err2:
 395        ds1wm_down(ds1wm_data);
 396        free_irq(ds1wm_data->irq, ds1wm_data);
 397err1:
 398        iounmap(ds1wm_data->map);
 399err0:
 400        kfree(ds1wm_data);
 401
 402        return ret;
 403}
 404
 405#ifdef CONFIG_PM
 406static int ds1wm_suspend(struct platform_device *pdev, pm_message_t state)
 407{
 408        struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
 409
 410        ds1wm_down(ds1wm_data);
 411
 412        return 0;
 413}
 414
 415static int ds1wm_resume(struct platform_device *pdev)
 416{
 417        struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
 418
 419        ds1wm_up(ds1wm_data);
 420
 421        return 0;
 422}
 423#else
 424#define ds1wm_suspend NULL
 425#define ds1wm_resume NULL
 426#endif
 427
 428static int ds1wm_remove(struct platform_device *pdev)
 429{
 430        struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
 431
 432        w1_remove_master_device(&ds1wm_master);
 433        ds1wm_down(ds1wm_data);
 434        free_irq(ds1wm_data->irq, ds1wm_data);
 435        iounmap(ds1wm_data->map);
 436        kfree(ds1wm_data);
 437
 438        return 0;
 439}
 440
 441static struct platform_driver ds1wm_driver = {
 442        .driver   = {
 443                .name = "ds1wm",
 444        },
 445        .probe    = ds1wm_probe,
 446        .remove   = ds1wm_remove,
 447        .suspend  = ds1wm_suspend,
 448        .resume   = ds1wm_resume
 449};
 450
 451static int __init ds1wm_init(void)
 452{
 453        printk("DS1WM w1 busmaster driver - (c) 2004 Szabolcs Gyurko\n");
 454        return platform_driver_register(&ds1wm_driver);
 455}
 456
 457static void __exit ds1wm_exit(void)
 458{
 459        platform_driver_unregister(&ds1wm_driver);
 460}
 461
 462module_init(ds1wm_init);
 463module_exit(ds1wm_exit);
 464
 465MODULE_LICENSE("GPL");
 466MODULE_AUTHOR("Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>, "
 467              "Matt Reimer <mreimer@vpop.net>");
 468MODULE_DESCRIPTION("DS1WM w1 busmaster driver");
 469