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102#include <linux/version.h>
103
104#define __OLD_VIDIOC_
105
106#include "matroxfb_base.h"
107#include "matroxfb_misc.h"
108#include "matroxfb_accel.h"
109#include "matroxfb_DAC1064.h"
110#include "matroxfb_Ti3026.h"
111#include "matroxfb_maven.h"
112#include "matroxfb_crtc2.h"
113#include "matroxfb_g450.h"
114#include <linux/matroxfb.h>
115#include <linux/interrupt.h>
116#include <linux/uaccess.h>
117
118#ifdef CONFIG_PPC_PMAC
119#include <asm/machdep.h>
120unsigned char nvram_read_byte(int);
121static int default_vmode = VMODE_NVRAM;
122static int default_cmode = CMODE_NVRAM;
123#endif
124
125static void matroxfb_unregister_device(struct matrox_fb_info* minfo);
126
127
128
129
130
131
132
133
134
135static struct fb_var_screeninfo vesafb_defined = {
136 640,480,640,480,
137 0,0,
138 8,
139 0,
140 {0,0,0},
141 {0,0,0},
142 {0,0,0},
143 {0,0,0},
144 0,
145 FB_ACTIVATE_NOW,
146 -1,-1,
147 FB_ACCELF_TEXT,
148 39721L,48L,16L,33L,10L,
149 96L,2L,~0,
150 FB_VMODE_NONINTERLACED,
151 0, {0,0,0,0,0}
152};
153
154
155
156
157static void update_crtc2(struct matrox_fb_info *minfo, unsigned int pos)
158{
159 struct matroxfb_dh_fb_info *info = minfo->crtc2.info;
160
161
162 if (info && (info->fbcon.var.bits_per_pixel == minfo->fbcon.var.bits_per_pixel)
163 && (info->fbcon.var.xres_virtual == minfo->fbcon.var.xres_virtual)
164 && (info->fbcon.var.green.length == minfo->fbcon.var.green.length)
165 ) {
166 switch (minfo->fbcon.var.bits_per_pixel) {
167 case 16:
168 case 32:
169 pos = pos * 8;
170 if (info->interlaced) {
171 mga_outl(0x3C2C, pos);
172 mga_outl(0x3C28, pos + minfo->fbcon.var.xres_virtual * minfo->fbcon.var.bits_per_pixel / 8);
173 } else {
174 mga_outl(0x3C28, pos);
175 }
176 break;
177 }
178 }
179}
180
181static void matroxfb_crtc1_panpos(struct matrox_fb_info *minfo)
182{
183 if (minfo->crtc1.panpos >= 0) {
184 unsigned long flags;
185 int panpos;
186
187 matroxfb_DAC_lock_irqsave(flags);
188 panpos = minfo->crtc1.panpos;
189 if (panpos >= 0) {
190 unsigned int extvga_reg;
191
192 minfo->crtc1.panpos = -1;
193 extvga_reg = mga_inb(M_EXTVGA_INDEX);
194 mga_setr(M_EXTVGA_INDEX, 0x00, panpos);
195 if (extvga_reg != 0x00) {
196 mga_outb(M_EXTVGA_INDEX, extvga_reg);
197 }
198 }
199 matroxfb_DAC_unlock_irqrestore(flags);
200 }
201}
202
203static irqreturn_t matrox_irq(int irq, void *dev_id)
204{
205 u_int32_t status;
206 int handled = 0;
207 struct matrox_fb_info *minfo = dev_id;
208
209 status = mga_inl(M_STATUS);
210
211 if (status & 0x20) {
212 mga_outl(M_ICLEAR, 0x20);
213 minfo->crtc1.vsync.cnt++;
214 matroxfb_crtc1_panpos(minfo);
215 wake_up_interruptible(&minfo->crtc1.vsync.wait);
216 handled = 1;
217 }
218 if (status & 0x200) {
219 mga_outl(M_ICLEAR, 0x200);
220 minfo->crtc2.vsync.cnt++;
221 wake_up_interruptible(&minfo->crtc2.vsync.wait);
222 handled = 1;
223 }
224 return IRQ_RETVAL(handled);
225}
226
227int matroxfb_enable_irq(struct matrox_fb_info *minfo, int reenable)
228{
229 u_int32_t bm;
230
231 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400)
232 bm = 0x220;
233 else
234 bm = 0x020;
235
236 if (!test_and_set_bit(0, &minfo->irq_flags)) {
237 if (request_irq(minfo->pcidev->irq, matrox_irq,
238 IRQF_SHARED, "matroxfb", minfo)) {
239 clear_bit(0, &minfo->irq_flags);
240 return -EINVAL;
241 }
242
243 mga_outl(M_ICLEAR, bm);
244 mga_outl(M_IEN, mga_inl(M_IEN) | bm);
245 } else if (reenable) {
246 u_int32_t ien;
247
248 ien = mga_inl(M_IEN);
249 if ((ien & bm) != bm) {
250 printk(KERN_DEBUG "matroxfb: someone disabled IRQ [%08X]\n", ien);
251 mga_outl(M_IEN, ien | bm);
252 }
253 }
254 return 0;
255}
256
257static void matroxfb_disable_irq(struct matrox_fb_info *minfo)
258{
259 if (test_and_clear_bit(0, &minfo->irq_flags)) {
260
261 matroxfb_crtc1_panpos(minfo);
262 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400)
263 mga_outl(M_IEN, mga_inl(M_IEN) & ~0x220);
264 else
265 mga_outl(M_IEN, mga_inl(M_IEN) & ~0x20);
266 free_irq(minfo->pcidev->irq, minfo);
267 }
268}
269
270int matroxfb_wait_for_sync(struct matrox_fb_info *minfo, u_int32_t crtc)
271{
272 struct matrox_vsync *vs;
273 unsigned int cnt;
274 int ret;
275
276 switch (crtc) {
277 case 0:
278 vs = &minfo->crtc1.vsync;
279 break;
280 case 1:
281 if (minfo->devflags.accelerator != FB_ACCEL_MATROX_MGAG400) {
282 return -ENODEV;
283 }
284 vs = &minfo->crtc2.vsync;
285 break;
286 default:
287 return -ENODEV;
288 }
289 ret = matroxfb_enable_irq(minfo, 0);
290 if (ret) {
291 return ret;
292 }
293
294 cnt = vs->cnt;
295 ret = wait_event_interruptible_timeout(vs->wait, cnt != vs->cnt, HZ/10);
296 if (ret < 0) {
297 return ret;
298 }
299 if (ret == 0) {
300 matroxfb_enable_irq(minfo, 1);
301 return -ETIMEDOUT;
302 }
303 return 0;
304}
305
306
307
308static void matrox_pan_var(struct matrox_fb_info *minfo,
309 struct fb_var_screeninfo *var)
310{
311 unsigned int pos;
312 unsigned short p0, p1, p2;
313 unsigned int p3;
314 int vbl;
315 unsigned long flags;
316
317 CRITFLAGS
318
319 DBG(__func__)
320
321 if (minfo->dead)
322 return;
323
324 minfo->fbcon.var.xoffset = var->xoffset;
325 minfo->fbcon.var.yoffset = var->yoffset;
326 pos = (minfo->fbcon.var.yoffset * minfo->fbcon.var.xres_virtual + minfo->fbcon.var.xoffset) * minfo->curr.final_bppShift / 32;
327 pos += minfo->curr.ydstorg.chunks;
328 p0 = minfo->hw.CRTC[0x0D] = pos & 0xFF;
329 p1 = minfo->hw.CRTC[0x0C] = (pos & 0xFF00) >> 8;
330 p2 = minfo->hw.CRTCEXT[0] = (minfo->hw.CRTCEXT[0] & 0xB0) | ((pos >> 16) & 0x0F) | ((pos >> 14) & 0x40);
331 p3 = minfo->hw.CRTCEXT[8] = pos >> 21;
332
333
334 vbl = (var->activate & FB_ACTIVATE_VBL) && (matroxfb_enable_irq(minfo, 0) == 0);
335
336 CRITBEGIN
337
338 matroxfb_DAC_lock_irqsave(flags);
339 mga_setr(M_CRTC_INDEX, 0x0D, p0);
340 mga_setr(M_CRTC_INDEX, 0x0C, p1);
341 if (minfo->devflags.support32MB)
342 mga_setr(M_EXTVGA_INDEX, 0x08, p3);
343 if (vbl) {
344 minfo->crtc1.panpos = p2;
345 } else {
346
347 minfo->crtc1.panpos = -1;
348 mga_setr(M_EXTVGA_INDEX, 0x00, p2);
349 }
350 matroxfb_DAC_unlock_irqrestore(flags);
351
352 update_crtc2(minfo, pos);
353
354 CRITEND
355}
356
357static void matroxfb_remove(struct matrox_fb_info *minfo, int dummy)
358{
359
360
361
362
363
364
365
366
367 minfo->dead = 1;
368 if (minfo->usecount) {
369
370 return;
371 }
372 matroxfb_unregister_device(minfo);
373 unregister_framebuffer(&minfo->fbcon);
374 matroxfb_g450_shutdown(minfo);
375#ifdef CONFIG_MTRR
376 if (minfo->mtrr.vram_valid)
377 mtrr_del(minfo->mtrr.vram, minfo->video.base, minfo->video.len);
378#endif
379 mga_iounmap(minfo->mmio.vbase);
380 mga_iounmap(minfo->video.vbase);
381 release_mem_region(minfo->video.base, minfo->video.len_maximum);
382 release_mem_region(minfo->mmio.base, 16384);
383 kfree(minfo);
384}
385
386
387
388
389
390static int matroxfb_open(struct fb_info *info, int user)
391{
392 struct matrox_fb_info *minfo = info2minfo(info);
393
394 DBG_LOOP(__func__)
395
396 if (minfo->dead) {
397 return -ENXIO;
398 }
399 minfo->usecount++;
400 if (user) {
401 minfo->userusecount++;
402 }
403 return(0);
404}
405
406static int matroxfb_release(struct fb_info *info, int user)
407{
408 struct matrox_fb_info *minfo = info2minfo(info);
409
410 DBG_LOOP(__func__)
411
412 if (user) {
413 if (0 == --minfo->userusecount) {
414 matroxfb_disable_irq(minfo);
415 }
416 }
417 if (!(--minfo->usecount) && minfo->dead) {
418 matroxfb_remove(minfo, 0);
419 }
420 return(0);
421}
422
423static int matroxfb_pan_display(struct fb_var_screeninfo *var,
424 struct fb_info* info) {
425 struct matrox_fb_info *minfo = info2minfo(info);
426
427 DBG(__func__)
428
429 matrox_pan_var(minfo, var);
430 return 0;
431}
432
433static int matroxfb_get_final_bppShift(const struct matrox_fb_info *minfo,
434 int bpp)
435{
436 int bppshft2;
437
438 DBG(__func__)
439
440 bppshft2 = bpp;
441 if (!bppshft2) {
442 return 8;
443 }
444 if (isInterleave(minfo))
445 bppshft2 >>= 1;
446 if (minfo->devflags.video64bits)
447 bppshft2 >>= 1;
448 return bppshft2;
449}
450
451static int matroxfb_test_and_set_rounding(const struct matrox_fb_info *minfo,
452 int xres, int bpp)
453{
454 int over;
455 int rounding;
456
457 DBG(__func__)
458
459 switch (bpp) {
460 case 0: return xres;
461 case 4: rounding = 128;
462 break;
463 case 8: rounding = 64;
464 break;
465 case 16: rounding = 32;
466 break;
467 case 24: rounding = 64;
468 break;
469 default: rounding = 16;
470
471 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400)
472 rounding = 32;
473 break;
474 }
475 if (isInterleave(minfo)) {
476 rounding *= 2;
477 }
478 over = xres % rounding;
479 if (over)
480 xres += rounding-over;
481 return xres;
482}
483
484static int matroxfb_pitch_adjust(const struct matrox_fb_info *minfo, int xres,
485 int bpp)
486{
487 const int* width;
488 int xres_new;
489
490 DBG(__func__)
491
492 if (!bpp) return xres;
493
494 width = minfo->capable.vxres;
495
496 if (minfo->devflags.precise_width) {
497 while (*width) {
498 if ((*width >= xres) && (matroxfb_test_and_set_rounding(minfo, *width, bpp) == *width)) {
499 break;
500 }
501 width++;
502 }
503 xres_new = *width;
504 } else {
505 xres_new = matroxfb_test_and_set_rounding(minfo, xres, bpp);
506 }
507 return xres_new;
508}
509
510static int matroxfb_get_cmap_len(struct fb_var_screeninfo *var) {
511
512 DBG(__func__)
513
514 switch (var->bits_per_pixel) {
515 case 4:
516 return 16;
517 case 8:
518 return 256;
519 case 16:
520 return 16;
521
522 case 24:
523 return 16;
524
525 case 32:
526 return 16;
527
528 }
529 return 16;
530}
531
532static int matroxfb_decode_var(const struct matrox_fb_info *minfo,
533 struct fb_var_screeninfo *var, int *visual,
534 int *video_cmap_len, unsigned int* ydstorg)
535{
536 struct RGBT {
537 unsigned char bpp;
538 struct {
539 unsigned char offset,
540 length;
541 } red,
542 green,
543 blue,
544 transp;
545 signed char visual;
546 };
547 static const struct RGBT table[]= {
548 { 8,{ 0,8},{0,8},{0,8},{ 0,0},MX_VISUAL_PSEUDOCOLOR},
549 {15,{10,5},{5,5},{0,5},{15,1},MX_VISUAL_DIRECTCOLOR},
550 {16,{11,5},{5,6},{0,5},{ 0,0},MX_VISUAL_DIRECTCOLOR},
551 {24,{16,8},{8,8},{0,8},{ 0,0},MX_VISUAL_DIRECTCOLOR},
552 {32,{16,8},{8,8},{0,8},{24,8},MX_VISUAL_DIRECTCOLOR}
553 };
554 struct RGBT const *rgbt;
555 unsigned int bpp = var->bits_per_pixel;
556 unsigned int vramlen;
557 unsigned int memlen;
558
559 DBG(__func__)
560
561 switch (bpp) {
562 case 4: if (!minfo->capable.cfb4) return -EINVAL;
563 break;
564 case 8: break;
565 case 16: break;
566 case 24: break;
567 case 32: break;
568 default: return -EINVAL;
569 }
570 *ydstorg = 0;
571 vramlen = minfo->video.len_usable;
572 if (var->yres_virtual < var->yres)
573 var->yres_virtual = var->yres;
574 if (var->xres_virtual < var->xres)
575 var->xres_virtual = var->xres;
576
577 var->xres_virtual = matroxfb_pitch_adjust(minfo, var->xres_virtual, bpp);
578 memlen = var->xres_virtual * bpp * var->yres_virtual / 8;
579 if (memlen > vramlen) {
580 var->yres_virtual = vramlen * 8 / (var->xres_virtual * bpp);
581 memlen = var->xres_virtual * bpp * var->yres_virtual / 8;
582 }
583
584
585
586 if (!minfo->capable.cross4MB && (memlen > 0x400000)) {
587 if (bpp == 24) {
588
589 } else {
590 unsigned int linelen;
591 unsigned int m1 = linelen = var->xres_virtual * bpp / 8;
592 unsigned int m2 = PAGE_SIZE;
593 unsigned int max_yres;
594
595 while (m1) {
596 int t;
597
598 while (m2 >= m1) m2 -= m1;
599 t = m1;
600 m1 = m2;
601 m2 = t;
602 }
603 m2 = linelen * PAGE_SIZE / m2;
604 *ydstorg = m2 = 0x400000 % m2;
605 max_yres = (vramlen - m2) / linelen;
606 if (var->yres_virtual > max_yres)
607 var->yres_virtual = max_yres;
608 }
609 }
610
611 if (var->yres_virtual > 32767)
612 var->yres_virtual = 32767;
613
614
615 if (var->yres_virtual < var->yres)
616 var->yres = var->yres_virtual;
617 if (var->xres_virtual < var->xres)
618 var->xres = var->xres_virtual;
619 if (var->xoffset + var->xres > var->xres_virtual)
620 var->xoffset = var->xres_virtual - var->xres;
621 if (var->yoffset + var->yres > var->yres_virtual)
622 var->yoffset = var->yres_virtual - var->yres;
623
624 if (bpp == 16 && var->green.length == 5) {
625 bpp--;
626 }
627
628 for (rgbt = table; rgbt->bpp < bpp; rgbt++);
629#define SETCLR(clr)\
630 var->clr.offset = rgbt->clr.offset;\
631 var->clr.length = rgbt->clr.length
632 SETCLR(red);
633 SETCLR(green);
634 SETCLR(blue);
635 SETCLR(transp);
636#undef SETCLR
637 *visual = rgbt->visual;
638
639 if (bpp > 8)
640 dprintk("matroxfb: truecolor: "
641 "size=%d:%d:%d:%d, shift=%d:%d:%d:%d\n",
642 var->transp.length, var->red.length, var->green.length, var->blue.length,
643 var->transp.offset, var->red.offset, var->green.offset, var->blue.offset);
644
645 *video_cmap_len = matroxfb_get_cmap_len(var);
646 dprintk(KERN_INFO "requested %d*%d/%dbpp (%d*%d)\n", var->xres, var->yres, var->bits_per_pixel,
647 var->xres_virtual, var->yres_virtual);
648 return 0;
649}
650
651static int matroxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
652 unsigned blue, unsigned transp,
653 struct fb_info *fb_info)
654{
655 struct matrox_fb_info* minfo = container_of(fb_info, struct matrox_fb_info, fbcon);
656
657 DBG(__func__)
658
659
660
661
662
663
664
665
666 if (regno >= minfo->curr.cmap_len)
667 return 1;
668
669 if (minfo->fbcon.var.grayscale) {
670
671 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
672 }
673
674 red = CNVT_TOHW(red, minfo->fbcon.var.red.length);
675 green = CNVT_TOHW(green, minfo->fbcon.var.green.length);
676 blue = CNVT_TOHW(blue, minfo->fbcon.var.blue.length);
677 transp = CNVT_TOHW(transp, minfo->fbcon.var.transp.length);
678
679 switch (minfo->fbcon.var.bits_per_pixel) {
680 case 4:
681 case 8:
682 mga_outb(M_DAC_REG, regno);
683 mga_outb(M_DAC_VAL, red);
684 mga_outb(M_DAC_VAL, green);
685 mga_outb(M_DAC_VAL, blue);
686 break;
687 case 16:
688 if (regno >= 16)
689 break;
690 {
691 u_int16_t col =
692 (red << minfo->fbcon.var.red.offset) |
693 (green << minfo->fbcon.var.green.offset) |
694 (blue << minfo->fbcon.var.blue.offset) |
695 (transp << minfo->fbcon.var.transp.offset);
696 minfo->cmap[regno] = col | (col << 16);
697 }
698 break;
699 case 24:
700 case 32:
701 if (regno >= 16)
702 break;
703 minfo->cmap[regno] =
704 (red << minfo->fbcon.var.red.offset) |
705 (green << minfo->fbcon.var.green.offset) |
706 (blue << minfo->fbcon.var.blue.offset) |
707 (transp << minfo->fbcon.var.transp.offset);
708 break;
709 }
710 return 0;
711}
712
713static void matroxfb_init_fix(struct matrox_fb_info *minfo)
714{
715 struct fb_fix_screeninfo *fix = &minfo->fbcon.fix;
716 DBG(__func__)
717
718 strcpy(fix->id,"MATROX");
719
720 fix->xpanstep = 8;
721 fix->ypanstep = 1;
722 fix->ywrapstep = 0;
723 fix->mmio_start = minfo->mmio.base;
724 fix->mmio_len = minfo->mmio.len;
725 fix->accel = minfo->devflags.accelerator;
726}
727
728static void matroxfb_update_fix(struct matrox_fb_info *minfo)
729{
730 struct fb_fix_screeninfo *fix = &minfo->fbcon.fix;
731 DBG(__func__)
732
733 mutex_lock(&minfo->fbcon.mm_lock);
734 fix->smem_start = minfo->video.base + minfo->curr.ydstorg.bytes;
735 fix->smem_len = minfo->video.len_usable - minfo->curr.ydstorg.bytes;
736 mutex_unlock(&minfo->fbcon.mm_lock);
737}
738
739static int matroxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
740{
741 int err;
742 int visual;
743 int cmap_len;
744 unsigned int ydstorg;
745 struct matrox_fb_info *minfo = info2minfo(info);
746
747 if (minfo->dead) {
748 return -ENXIO;
749 }
750 if ((err = matroxfb_decode_var(minfo, var, &visual, &cmap_len, &ydstorg)) != 0)
751 return err;
752 return 0;
753}
754
755static int matroxfb_set_par(struct fb_info *info)
756{
757 int err;
758 int visual;
759 int cmap_len;
760 unsigned int ydstorg;
761 struct fb_var_screeninfo *var;
762 struct matrox_fb_info *minfo = info2minfo(info);
763
764 DBG(__func__)
765
766 if (minfo->dead) {
767 return -ENXIO;
768 }
769
770 var = &info->var;
771 if ((err = matroxfb_decode_var(minfo, var, &visual, &cmap_len, &ydstorg)) != 0)
772 return err;
773 minfo->fbcon.screen_base = vaddr_va(minfo->video.vbase) + ydstorg;
774 matroxfb_update_fix(minfo);
775 minfo->fbcon.fix.visual = visual;
776 minfo->fbcon.fix.type = FB_TYPE_PACKED_PIXELS;
777 minfo->fbcon.fix.type_aux = 0;
778 minfo->fbcon.fix.line_length = (var->xres_virtual * var->bits_per_pixel) >> 3;
779 {
780 unsigned int pos;
781
782 minfo->curr.cmap_len = cmap_len;
783 ydstorg += minfo->devflags.ydstorg;
784 minfo->curr.ydstorg.bytes = ydstorg;
785 minfo->curr.ydstorg.chunks = ydstorg >> (isInterleave(minfo) ? 3 : 2);
786 if (var->bits_per_pixel == 4)
787 minfo->curr.ydstorg.pixels = ydstorg;
788 else
789 minfo->curr.ydstorg.pixels = (ydstorg * 8) / var->bits_per_pixel;
790 minfo->curr.final_bppShift = matroxfb_get_final_bppShift(minfo, var->bits_per_pixel);
791 { struct my_timming mt;
792 struct matrox_hw_state* hw;
793 int out;
794
795 matroxfb_var2my(var, &mt);
796 mt.crtc = MATROXFB_SRC_CRTC1;
797
798 switch (var->bits_per_pixel) {
799 case 0: mt.delay = 31 + 0; break;
800 case 16: mt.delay = 21 + 8; break;
801 case 24: mt.delay = 17 + 8; break;
802 case 32: mt.delay = 16 + 8; break;
803 default: mt.delay = 31 + 8; break;
804 }
805
806 hw = &minfo->hw;
807
808 down_read(&minfo->altout.lock);
809 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
810 if (minfo->outputs[out].src == MATROXFB_SRC_CRTC1 &&
811 minfo->outputs[out].output->compute) {
812 minfo->outputs[out].output->compute(minfo->outputs[out].data, &mt);
813 }
814 }
815 up_read(&minfo->altout.lock);
816 minfo->crtc1.pixclock = mt.pixclock;
817 minfo->crtc1.mnp = mt.mnp;
818 minfo->hw_switch->init(minfo, &mt);
819 pos = (var->yoffset * var->xres_virtual + var->xoffset) * minfo->curr.final_bppShift / 32;
820 pos += minfo->curr.ydstorg.chunks;
821
822 hw->CRTC[0x0D] = pos & 0xFF;
823 hw->CRTC[0x0C] = (pos & 0xFF00) >> 8;
824 hw->CRTCEXT[0] = (hw->CRTCEXT[0] & 0xF0) | ((pos >> 16) & 0x0F) | ((pos >> 14) & 0x40);
825 hw->CRTCEXT[8] = pos >> 21;
826 minfo->hw_switch->restore(minfo);
827 update_crtc2(minfo, pos);
828 down_read(&minfo->altout.lock);
829 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
830 if (minfo->outputs[out].src == MATROXFB_SRC_CRTC1 &&
831 minfo->outputs[out].output->program) {
832 minfo->outputs[out].output->program(minfo->outputs[out].data);
833 }
834 }
835 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
836 if (minfo->outputs[out].src == MATROXFB_SRC_CRTC1 &&
837 minfo->outputs[out].output->start) {
838 minfo->outputs[out].output->start(minfo->outputs[out].data);
839 }
840 }
841 up_read(&minfo->altout.lock);
842 matrox_cfbX_init(minfo);
843 }
844 }
845 minfo->initialized = 1;
846 return 0;
847}
848
849static int matroxfb_get_vblank(struct matrox_fb_info *minfo,
850 struct fb_vblank *vblank)
851{
852 unsigned int sts1;
853
854 matroxfb_enable_irq(minfo, 0);
855 memset(vblank, 0, sizeof(*vblank));
856 vblank->flags = FB_VBLANK_HAVE_VCOUNT | FB_VBLANK_HAVE_VSYNC |
857 FB_VBLANK_HAVE_VBLANK | FB_VBLANK_HAVE_HBLANK;
858 sts1 = mga_inb(M_INSTS1);
859 vblank->vcount = mga_inl(M_VCOUNT);
860
861
862
863 if (sts1 & 1)
864 vblank->flags |= FB_VBLANK_HBLANKING;
865 if (sts1 & 8)
866 vblank->flags |= FB_VBLANK_VSYNCING;
867 if (vblank->vcount >= minfo->fbcon.var.yres)
868 vblank->flags |= FB_VBLANK_VBLANKING;
869 if (test_bit(0, &minfo->irq_flags)) {
870 vblank->flags |= FB_VBLANK_HAVE_COUNT;
871
872
873 vblank->count = minfo->crtc1.vsync.cnt;
874 }
875 return 0;
876}
877
878static struct matrox_altout panellink_output = {
879 .name = "Panellink output",
880};
881
882static int matroxfb_ioctl(struct fb_info *info,
883 unsigned int cmd, unsigned long arg)
884{
885 void __user *argp = (void __user *)arg;
886 struct matrox_fb_info *minfo = info2minfo(info);
887
888 DBG(__func__)
889
890 if (minfo->dead) {
891 return -ENXIO;
892 }
893
894 switch (cmd) {
895 case FBIOGET_VBLANK:
896 {
897 struct fb_vblank vblank;
898 int err;
899
900 err = matroxfb_get_vblank(minfo, &vblank);
901 if (err)
902 return err;
903 if (copy_to_user(argp, &vblank, sizeof(vblank)))
904 return -EFAULT;
905 return 0;
906 }
907 case FBIO_WAITFORVSYNC:
908 {
909 u_int32_t crt;
910
911 if (get_user(crt, (u_int32_t __user *)arg))
912 return -EFAULT;
913
914 return matroxfb_wait_for_sync(minfo, crt);
915 }
916 case MATROXFB_SET_OUTPUT_MODE:
917 {
918 struct matroxioc_output_mode mom;
919 struct matrox_altout *oproc;
920 int val;
921
922 if (copy_from_user(&mom, argp, sizeof(mom)))
923 return -EFAULT;
924 if (mom.output >= MATROXFB_MAX_OUTPUTS)
925 return -ENXIO;
926 down_read(&minfo->altout.lock);
927 oproc = minfo->outputs[mom.output].output;
928 if (!oproc) {
929 val = -ENXIO;
930 } else if (!oproc->verifymode) {
931 if (mom.mode == MATROXFB_OUTPUT_MODE_MONITOR) {
932 val = 0;
933 } else {
934 val = -EINVAL;
935 }
936 } else {
937 val = oproc->verifymode(minfo->outputs[mom.output].data, mom.mode);
938 }
939 if (!val) {
940 if (minfo->outputs[mom.output].mode != mom.mode) {
941 minfo->outputs[mom.output].mode = mom.mode;
942 val = 1;
943 }
944 }
945 up_read(&minfo->altout.lock);
946 if (val != 1)
947 return val;
948 switch (minfo->outputs[mom.output].src) {
949 case MATROXFB_SRC_CRTC1:
950 matroxfb_set_par(info);
951 break;
952 case MATROXFB_SRC_CRTC2:
953 {
954 struct matroxfb_dh_fb_info* crtc2;
955
956 down_read(&minfo->crtc2.lock);
957 crtc2 = minfo->crtc2.info;
958 if (crtc2)
959 crtc2->fbcon.fbops->fb_set_par(&crtc2->fbcon);
960 up_read(&minfo->crtc2.lock);
961 }
962 break;
963 }
964 return 0;
965 }
966 case MATROXFB_GET_OUTPUT_MODE:
967 {
968 struct matroxioc_output_mode mom;
969 struct matrox_altout *oproc;
970 int val;
971
972 if (copy_from_user(&mom, argp, sizeof(mom)))
973 return -EFAULT;
974 if (mom.output >= MATROXFB_MAX_OUTPUTS)
975 return -ENXIO;
976 down_read(&minfo->altout.lock);
977 oproc = minfo->outputs[mom.output].output;
978 if (!oproc) {
979 val = -ENXIO;
980 } else {
981 mom.mode = minfo->outputs[mom.output].mode;
982 val = 0;
983 }
984 up_read(&minfo->altout.lock);
985 if (val)
986 return val;
987 if (copy_to_user(argp, &mom, sizeof(mom)))
988 return -EFAULT;
989 return 0;
990 }
991 case MATROXFB_SET_OUTPUT_CONNECTION:
992 {
993 u_int32_t tmp;
994 int i;
995 int changes;
996
997 if (copy_from_user(&tmp, argp, sizeof(tmp)))
998 return -EFAULT;
999 for (i = 0; i < 32; i++) {
1000 if (tmp & (1 << i)) {
1001 if (i >= MATROXFB_MAX_OUTPUTS)
1002 return -ENXIO;
1003 if (!minfo->outputs[i].output)
1004 return -ENXIO;
1005 switch (minfo->outputs[i].src) {
1006 case MATROXFB_SRC_NONE:
1007 case MATROXFB_SRC_CRTC1:
1008 break;
1009 default:
1010 return -EBUSY;
1011 }
1012 }
1013 }
1014 if (minfo->devflags.panellink) {
1015 if (tmp & MATROXFB_OUTPUT_CONN_DFP) {
1016 if (tmp & MATROXFB_OUTPUT_CONN_SECONDARY)
1017 return -EINVAL;
1018 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1019 if (minfo->outputs[i].src == MATROXFB_SRC_CRTC2) {
1020 return -EBUSY;
1021 }
1022 }
1023 }
1024 }
1025 changes = 0;
1026 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1027 if (tmp & (1 << i)) {
1028 if (minfo->outputs[i].src != MATROXFB_SRC_CRTC1) {
1029 changes = 1;
1030 minfo->outputs[i].src = MATROXFB_SRC_CRTC1;
1031 }
1032 } else if (minfo->outputs[i].src == MATROXFB_SRC_CRTC1) {
1033 changes = 1;
1034 minfo->outputs[i].src = MATROXFB_SRC_NONE;
1035 }
1036 }
1037 if (!changes)
1038 return 0;
1039 matroxfb_set_par(info);
1040 return 0;
1041 }
1042 case MATROXFB_GET_OUTPUT_CONNECTION:
1043 {
1044 u_int32_t conn = 0;
1045 int i;
1046
1047 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1048 if (minfo->outputs[i].src == MATROXFB_SRC_CRTC1) {
1049 conn |= 1 << i;
1050 }
1051 }
1052 if (put_user(conn, (u_int32_t __user *)arg))
1053 return -EFAULT;
1054 return 0;
1055 }
1056 case MATROXFB_GET_AVAILABLE_OUTPUTS:
1057 {
1058 u_int32_t conn = 0;
1059 int i;
1060
1061 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1062 if (minfo->outputs[i].output) {
1063 switch (minfo->outputs[i].src) {
1064 case MATROXFB_SRC_NONE:
1065 case MATROXFB_SRC_CRTC1:
1066 conn |= 1 << i;
1067 break;
1068 }
1069 }
1070 }
1071 if (minfo->devflags.panellink) {
1072 if (conn & MATROXFB_OUTPUT_CONN_DFP)
1073 conn &= ~MATROXFB_OUTPUT_CONN_SECONDARY;
1074 if (conn & MATROXFB_OUTPUT_CONN_SECONDARY)
1075 conn &= ~MATROXFB_OUTPUT_CONN_DFP;
1076 }
1077 if (put_user(conn, (u_int32_t __user *)arg))
1078 return -EFAULT;
1079 return 0;
1080 }
1081 case MATROXFB_GET_ALL_OUTPUTS:
1082 {
1083 u_int32_t conn = 0;
1084 int i;
1085
1086 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1087 if (minfo->outputs[i].output) {
1088 conn |= 1 << i;
1089 }
1090 }
1091 if (put_user(conn, (u_int32_t __user *)arg))
1092 return -EFAULT;
1093 return 0;
1094 }
1095 case VIDIOC_QUERYCAP:
1096 {
1097 struct v4l2_capability r;
1098
1099 memset(&r, 0, sizeof(r));
1100 strcpy(r.driver, "matroxfb");
1101 strcpy(r.card, "Matrox");
1102 sprintf(r.bus_info, "PCI:%s", pci_name(minfo->pcidev));
1103 r.version = KERNEL_VERSION(1,0,0);
1104 r.capabilities = V4L2_CAP_VIDEO_OUTPUT;
1105 if (copy_to_user(argp, &r, sizeof(r)))
1106 return -EFAULT;
1107 return 0;
1108
1109 }
1110 case VIDIOC_QUERYCTRL:
1111 {
1112 struct v4l2_queryctrl qctrl;
1113 int err;
1114
1115 if (copy_from_user(&qctrl, argp, sizeof(qctrl)))
1116 return -EFAULT;
1117
1118 down_read(&minfo->altout.lock);
1119 if (!minfo->outputs[1].output) {
1120 err = -ENXIO;
1121 } else if (minfo->outputs[1].output->getqueryctrl) {
1122 err = minfo->outputs[1].output->getqueryctrl(minfo->outputs[1].data, &qctrl);
1123 } else {
1124 err = -EINVAL;
1125 }
1126 up_read(&minfo->altout.lock);
1127 if (err >= 0 &&
1128 copy_to_user(argp, &qctrl, sizeof(qctrl)))
1129 return -EFAULT;
1130 return err;
1131 }
1132 case VIDIOC_G_CTRL:
1133 {
1134 struct v4l2_control ctrl;
1135 int err;
1136
1137 if (copy_from_user(&ctrl, argp, sizeof(ctrl)))
1138 return -EFAULT;
1139
1140 down_read(&minfo->altout.lock);
1141 if (!minfo->outputs[1].output) {
1142 err = -ENXIO;
1143 } else if (minfo->outputs[1].output->getctrl) {
1144 err = minfo->outputs[1].output->getctrl(minfo->outputs[1].data, &ctrl);
1145 } else {
1146 err = -EINVAL;
1147 }
1148 up_read(&minfo->altout.lock);
1149 if (err >= 0 &&
1150 copy_to_user(argp, &ctrl, sizeof(ctrl)))
1151 return -EFAULT;
1152 return err;
1153 }
1154 case VIDIOC_S_CTRL_OLD:
1155 case VIDIOC_S_CTRL:
1156 {
1157 struct v4l2_control ctrl;
1158 int err;
1159
1160 if (copy_from_user(&ctrl, argp, sizeof(ctrl)))
1161 return -EFAULT;
1162
1163 down_read(&minfo->altout.lock);
1164 if (!minfo->outputs[1].output) {
1165 err = -ENXIO;
1166 } else if (minfo->outputs[1].output->setctrl) {
1167 err = minfo->outputs[1].output->setctrl(minfo->outputs[1].data, &ctrl);
1168 } else {
1169 err = -EINVAL;
1170 }
1171 up_read(&minfo->altout.lock);
1172 return err;
1173 }
1174 }
1175 return -ENOTTY;
1176}
1177
1178
1179
1180static int matroxfb_blank(int blank, struct fb_info *info)
1181{
1182 int seq;
1183 int crtc;
1184 CRITFLAGS
1185 struct matrox_fb_info *minfo = info2minfo(info);
1186
1187 DBG(__func__)
1188
1189 if (minfo->dead)
1190 return 1;
1191
1192 switch (blank) {
1193 case FB_BLANK_NORMAL: seq = 0x20; crtc = 0x00; break;
1194 case FB_BLANK_VSYNC_SUSPEND: seq = 0x20; crtc = 0x10; break;
1195 case FB_BLANK_HSYNC_SUSPEND: seq = 0x20; crtc = 0x20; break;
1196 case FB_BLANK_POWERDOWN: seq = 0x20; crtc = 0x30; break;
1197 default: seq = 0x00; crtc = 0x00; break;
1198 }
1199
1200 CRITBEGIN
1201
1202 mga_outb(M_SEQ_INDEX, 1);
1203 mga_outb(M_SEQ_DATA, (mga_inb(M_SEQ_DATA) & ~0x20) | seq);
1204 mga_outb(M_EXTVGA_INDEX, 1);
1205 mga_outb(M_EXTVGA_DATA, (mga_inb(M_EXTVGA_DATA) & ~0x30) | crtc);
1206
1207 CRITEND
1208 return 0;
1209}
1210
1211static struct fb_ops matroxfb_ops = {
1212 .owner = THIS_MODULE,
1213 .fb_open = matroxfb_open,
1214 .fb_release = matroxfb_release,
1215 .fb_check_var = matroxfb_check_var,
1216 .fb_set_par = matroxfb_set_par,
1217 .fb_setcolreg = matroxfb_setcolreg,
1218 .fb_pan_display =matroxfb_pan_display,
1219 .fb_blank = matroxfb_blank,
1220 .fb_ioctl = matroxfb_ioctl,
1221
1222
1223
1224
1225};
1226
1227#define RSDepth(X) (((X) >> 8) & 0x0F)
1228#define RS8bpp 0x1
1229#define RS15bpp 0x2
1230#define RS16bpp 0x3
1231#define RS32bpp 0x4
1232#define RS4bpp 0x5
1233#define RS24bpp 0x6
1234#define RSText 0x7
1235#define RSText8 0x8
1236
1237static struct { struct fb_bitfield red, green, blue, transp; int bits_per_pixel; } colors[] = {
1238 { { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 0, 0}, 8 },
1239 { { 10, 5, 0}, { 5, 5, 0}, { 0, 5, 0}, { 15, 1, 0}, 16 },
1240 { { 11, 5, 0}, { 5, 6, 0}, { 0, 5, 0}, { 0, 0, 0}, 16 },
1241 { { 16, 8, 0}, { 8, 8, 0}, { 0, 8, 0}, { 24, 8, 0}, 32 },
1242 { { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 0, 0}, 4 },
1243 { { 16, 8, 0}, { 8, 8, 0}, { 0, 8, 0}, { 0, 0, 0}, 24 },
1244 { { 0, 6, 0}, { 0, 6, 0}, { 0, 6, 0}, { 0, 0, 0}, 0 },
1245 { { 0, 6, 0}, { 0, 6, 0}, { 0, 6, 0}, { 0, 0, 0}, 0 },
1246};
1247
1248
1249static unsigned int mem;
1250static int option_precise_width = 1;
1251static int inv24;
1252static int cross4MB = -1;
1253static int disabled;
1254static int noaccel;
1255static int nopan;
1256static int no_pci_retry;
1257static int novga;
1258static int nobios;
1259static int noinit = 1;
1260static int inverse;
1261static int sgram;
1262#ifdef CONFIG_MTRR
1263static int mtrr = 1;
1264#endif
1265static int grayscale;
1266static int dev = -1;
1267static unsigned int vesa = ~0;
1268static int depth = -1;
1269static unsigned int xres;
1270static unsigned int yres;
1271static unsigned int upper = ~0;
1272static unsigned int lower = ~0;
1273static unsigned int vslen;
1274static unsigned int left = ~0;
1275static unsigned int right = ~0;
1276static unsigned int hslen;
1277static unsigned int pixclock;
1278static int sync = -1;
1279static unsigned int fv;
1280static unsigned int fh;
1281static unsigned int maxclk;
1282static int dfp;
1283static int dfp_type = -1;
1284static int memtype = -1;
1285static char outputs[8];
1286
1287#ifndef MODULE
1288static char videomode[64];
1289#endif
1290
1291static int matroxfb_getmemory(struct matrox_fb_info *minfo,
1292 unsigned int maxSize, unsigned int *realSize)
1293{
1294 vaddr_t vm;
1295 unsigned int offs;
1296 unsigned int offs2;
1297 unsigned char orig;
1298 unsigned char bytes[32];
1299 unsigned char* tmp;
1300
1301 DBG(__func__)
1302
1303 vm = minfo->video.vbase;
1304 maxSize &= ~0x1FFFFF;
1305
1306 if (maxSize < 0x0200000) return 0;
1307 if (maxSize > 0x2000000) maxSize = 0x2000000;
1308
1309 mga_outb(M_EXTVGA_INDEX, 0x03);
1310 orig = mga_inb(M_EXTVGA_DATA);
1311 mga_outb(M_EXTVGA_DATA, orig | 0x80);
1312
1313 tmp = bytes;
1314 for (offs = 0x100000; offs < maxSize; offs += 0x200000)
1315 *tmp++ = mga_readb(vm, offs);
1316 for (offs = 0x100000; offs < maxSize; offs += 0x200000)
1317 mga_writeb(vm, offs, 0x02);
1318 mga_outb(M_CACHEFLUSH, 0x00);
1319 for (offs = 0x100000; offs < maxSize; offs += 0x200000) {
1320 if (mga_readb(vm, offs) != 0x02)
1321 break;
1322 mga_writeb(vm, offs, mga_readb(vm, offs) - 0x02);
1323 if (mga_readb(vm, offs))
1324 break;
1325 }
1326 tmp = bytes;
1327 for (offs2 = 0x100000; offs2 < maxSize; offs2 += 0x200000)
1328 mga_writeb(vm, offs2, *tmp++);
1329
1330 mga_outb(M_EXTVGA_INDEX, 0x03);
1331 mga_outb(M_EXTVGA_DATA, orig);
1332
1333 *realSize = offs - 0x100000;
1334#ifdef CONFIG_FB_MATROX_MILLENIUM
1335 minfo->interleave = !(!isMillenium(minfo) || ((offs - 0x100000) & 0x3FFFFF));
1336#endif
1337 return 1;
1338}
1339
1340struct video_board {
1341 int maxvram;
1342 int maxdisplayable;
1343 int accelID;
1344 struct matrox_switch* lowlevel;
1345 };
1346#ifdef CONFIG_FB_MATROX_MILLENIUM
1347static struct video_board vbMillennium = {0x0800000, 0x0800000, FB_ACCEL_MATROX_MGA2064W, &matrox_millennium};
1348static struct video_board vbMillennium2 = {0x1000000, 0x0800000, FB_ACCEL_MATROX_MGA2164W, &matrox_millennium};
1349static struct video_board vbMillennium2A = {0x1000000, 0x0800000, FB_ACCEL_MATROX_MGA2164W_AGP, &matrox_millennium};
1350#endif
1351#ifdef CONFIG_FB_MATROX_MYSTIQUE
1352static struct video_board vbMystique = {0x0800000, 0x0800000, FB_ACCEL_MATROX_MGA1064SG, &matrox_mystique};
1353#endif
1354#ifdef CONFIG_FB_MATROX_G
1355static struct video_board vbG100 = {0x0800000, 0x0800000, FB_ACCEL_MATROX_MGAG100, &matrox_G100};
1356static struct video_board vbG200 = {0x1000000, 0x1000000, FB_ACCEL_MATROX_MGAG200, &matrox_G100};
1357
1358
1359static struct video_board vbG400 = {0x2000000, 0x1000000, FB_ACCEL_MATROX_MGAG400, &matrox_G100};
1360#endif
1361
1362#define DEVF_VIDEO64BIT 0x0001
1363#define DEVF_SWAPS 0x0002
1364#define DEVF_SRCORG 0x0004
1365#define DEVF_DUALHEAD 0x0008
1366#define DEVF_CROSS4MB 0x0010
1367#define DEVF_TEXT4B 0x0020
1368
1369
1370#define DEVF_SUPPORT32MB 0x0100
1371#define DEVF_ANY_VXRES 0x0200
1372#define DEVF_TEXT16B 0x0400
1373#define DEVF_CRTC2 0x0800
1374#define DEVF_MAVEN_CAPABLE 0x1000
1375#define DEVF_PANELLINK_CAPABLE 0x2000
1376#define DEVF_G450DAC 0x4000
1377
1378#define DEVF_GCORE (DEVF_VIDEO64BIT | DEVF_SWAPS | DEVF_CROSS4MB)
1379#define DEVF_G2CORE (DEVF_GCORE | DEVF_ANY_VXRES | DEVF_MAVEN_CAPABLE | DEVF_PANELLINK_CAPABLE | DEVF_SRCORG | DEVF_DUALHEAD)
1380#define DEVF_G100 (DEVF_GCORE)
1381#define DEVF_G200 (DEVF_G2CORE)
1382#define DEVF_G400 (DEVF_G2CORE | DEVF_SUPPORT32MB | DEVF_TEXT16B | DEVF_CRTC2)
1383
1384#define DEVF_G450 (DEVF_GCORE | DEVF_ANY_VXRES | DEVF_SUPPORT32MB | DEVF_TEXT16B | DEVF_CRTC2 | DEVF_G450DAC | DEVF_SRCORG | DEVF_DUALHEAD)
1385#define DEVF_G550 (DEVF_G450)
1386
1387static struct board {
1388 unsigned short vendor, device, rev, svid, sid;
1389 unsigned int flags;
1390 unsigned int maxclk;
1391 enum mga_chip chip;
1392 struct video_board* base;
1393 const char* name;
1394 } dev_list[] = {
1395#ifdef CONFIG_FB_MATROX_MILLENIUM
1396 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL, 0xFF,
1397 0, 0,
1398 DEVF_TEXT4B,
1399 230000,
1400 MGA_2064,
1401 &vbMillennium,
1402 "Millennium (PCI)"},
1403 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2, 0xFF,
1404 0, 0,
1405 DEVF_SWAPS,
1406 220000,
1407 MGA_2164,
1408 &vbMillennium2,
1409 "Millennium II (PCI)"},
1410 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2_AGP, 0xFF,
1411 0, 0,
1412 DEVF_SWAPS,
1413 250000,
1414 MGA_2164,
1415 &vbMillennium2A,
1416 "Millennium II (AGP)"},
1417#endif
1418#ifdef CONFIG_FB_MATROX_MYSTIQUE
1419 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS, 0x02,
1420 0, 0,
1421 DEVF_VIDEO64BIT | DEVF_CROSS4MB,
1422 180000,
1423 MGA_1064,
1424 &vbMystique,
1425 "Mystique (PCI)"},
1426 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS, 0xFF,
1427 0, 0,
1428 DEVF_VIDEO64BIT | DEVF_SWAPS | DEVF_CROSS4MB,
1429 220000,
1430 MGA_1164,
1431 &vbMystique,
1432 "Mystique 220 (PCI)"},
1433 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS_AGP, 0x02,
1434 0, 0,
1435 DEVF_VIDEO64BIT | DEVF_CROSS4MB,
1436 180000,
1437 MGA_1064,
1438 &vbMystique,
1439 "Mystique (AGP)"},
1440 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS_AGP, 0xFF,
1441 0, 0,
1442 DEVF_VIDEO64BIT | DEVF_SWAPS | DEVF_CROSS4MB,
1443 220000,
1444 MGA_1164,
1445 &vbMystique,
1446 "Mystique 220 (AGP)"},
1447#endif
1448#ifdef CONFIG_FB_MATROX_G
1449 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G100_MM, 0xFF,
1450 0, 0,
1451 DEVF_G100,
1452 230000,
1453 MGA_G100,
1454 &vbG100,
1455 "MGA-G100 (PCI)"},
1456 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G100_AGP, 0xFF,
1457 0, 0,
1458 DEVF_G100,
1459 230000,
1460 MGA_G100,
1461 &vbG100,
1462 "MGA-G100 (AGP)"},
1463 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200EV_PCI, 0xFF,
1464 0, 0,
1465 DEVF_G200,
1466 230000,
1467 MGA_G200,
1468 &vbG200,
1469 "MGA-G200eV (PCI)"},
1470 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI, 0xFF,
1471 0, 0,
1472 DEVF_G200,
1473 250000,
1474 MGA_G200,
1475 &vbG200,
1476 "MGA-G200 (PCI)"},
1477 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
1478 PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_GENERIC,
1479 DEVF_G200,
1480 220000,
1481 MGA_G200,
1482 &vbG200,
1483 "MGA-G200 (AGP)"},
1484 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
1485 PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP,
1486 DEVF_G200,
1487 230000,
1488 MGA_G200,
1489 &vbG200,
1490 "Mystique G200 (AGP)"},
1491 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
1492 PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_MILLENIUM_G200_AGP,
1493 DEVF_G200,
1494 250000,
1495 MGA_G200,
1496 &vbG200,
1497 "Millennium G200 (AGP)"},
1498 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
1499 PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_MARVEL_G200_AGP,
1500 DEVF_G200,
1501 230000,
1502 MGA_G200,
1503 &vbG200,
1504 "Marvel G200 (AGP)"},
1505 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
1506 PCI_SS_VENDOR_ID_SIEMENS_NIXDORF, PCI_SS_ID_SIEMENS_MGA_G200_AGP,
1507 DEVF_G200,
1508 230000,
1509 MGA_G200,
1510 &vbG200,
1511 "MGA-G200 (AGP)"},
1512 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
1513 0, 0,
1514 DEVF_G200,
1515 230000,
1516 MGA_G200,
1517 &vbG200,
1518 "G200 (AGP)"},
1519 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, 0x80,
1520 PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP,
1521 DEVF_G400,
1522 360000,
1523 MGA_G400,
1524 &vbG400,
1525 "Millennium G400 MAX (AGP)"},
1526 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, 0x80,
1527 0, 0,
1528 DEVF_G400,
1529 300000,
1530 MGA_G400,
1531 &vbG400,
1532 "G400 (AGP)"},
1533 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, 0xFF,
1534 0, 0,
1535 DEVF_G450,
1536 360000,
1537 MGA_G450,
1538 &vbG400,
1539 "G450"},
1540 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G550, 0xFF,
1541 0, 0,
1542 DEVF_G550,
1543 360000,
1544 MGA_G550,
1545 &vbG400,
1546 "G550"},
1547#endif
1548 {0, 0, 0xFF,
1549 0, 0,
1550 0,
1551 0,
1552 0,
1553 NULL,
1554 NULL}};
1555
1556#ifndef MODULE
1557static struct fb_videomode defaultmode = {
1558
1559 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
1560 0, FB_VMODE_NONINTERLACED
1561};
1562#endif
1563
1564static int hotplug = 0;
1565
1566static void setDefaultOutputs(struct matrox_fb_info *minfo)
1567{
1568 unsigned int i;
1569 const char* ptr;
1570
1571 minfo->outputs[0].default_src = MATROXFB_SRC_CRTC1;
1572 if (minfo->devflags.g450dac) {
1573 minfo->outputs[1].default_src = MATROXFB_SRC_CRTC1;
1574 minfo->outputs[2].default_src = MATROXFB_SRC_CRTC1;
1575 } else if (dfp) {
1576 minfo->outputs[2].default_src = MATROXFB_SRC_CRTC1;
1577 }
1578 ptr = outputs;
1579 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1580 char c = *ptr++;
1581
1582 if (c == 0) {
1583 break;
1584 }
1585 if (c == '0') {
1586 minfo->outputs[i].default_src = MATROXFB_SRC_NONE;
1587 } else if (c == '1') {
1588 minfo->outputs[i].default_src = MATROXFB_SRC_CRTC1;
1589 } else if (c == '2' && minfo->devflags.crtc2) {
1590 minfo->outputs[i].default_src = MATROXFB_SRC_CRTC2;
1591 } else {
1592 printk(KERN_ERR "matroxfb: Unknown outputs setting\n");
1593 break;
1594 }
1595 }
1596
1597 outputs[0] = 0;
1598}
1599
1600static int initMatrox2(struct matrox_fb_info *minfo, struct board *b)
1601{
1602 unsigned long ctrlptr_phys = 0;
1603 unsigned long video_base_phys = 0;
1604 unsigned int memsize;
1605 int err;
1606
1607 static struct pci_device_id intel_82437[] = {
1608 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437) },
1609 { },
1610 };
1611
1612 DBG(__func__)
1613
1614
1615 vesafb_defined.accel_flags = FB_ACCELF_TEXT;
1616
1617 minfo->hw_switch = b->base->lowlevel;
1618 minfo->devflags.accelerator = b->base->accelID;
1619 minfo->max_pixel_clock = b->maxclk;
1620
1621 printk(KERN_INFO "matroxfb: Matrox %s detected\n", b->name);
1622 minfo->capable.plnwt = 1;
1623 minfo->chip = b->chip;
1624 minfo->capable.srcorg = b->flags & DEVF_SRCORG;
1625 minfo->devflags.video64bits = b->flags & DEVF_VIDEO64BIT;
1626 if (b->flags & DEVF_TEXT4B) {
1627 minfo->devflags.vgastep = 4;
1628 minfo->devflags.textmode = 4;
1629 minfo->devflags.text_type_aux = FB_AUX_TEXT_MGA_STEP16;
1630 } else if (b->flags & DEVF_TEXT16B) {
1631 minfo->devflags.vgastep = 16;
1632 minfo->devflags.textmode = 1;
1633 minfo->devflags.text_type_aux = FB_AUX_TEXT_MGA_STEP16;
1634 } else {
1635 minfo->devflags.vgastep = 8;
1636 minfo->devflags.textmode = 1;
1637 minfo->devflags.text_type_aux = FB_AUX_TEXT_MGA_STEP8;
1638 }
1639 minfo->devflags.support32MB = (b->flags & DEVF_SUPPORT32MB) != 0;
1640 minfo->devflags.precise_width = !(b->flags & DEVF_ANY_VXRES);
1641 minfo->devflags.crtc2 = (b->flags & DEVF_CRTC2) != 0;
1642 minfo->devflags.maven_capable = (b->flags & DEVF_MAVEN_CAPABLE) != 0;
1643 minfo->devflags.dualhead = (b->flags & DEVF_DUALHEAD) != 0;
1644 minfo->devflags.dfp_type = dfp_type;
1645 minfo->devflags.g450dac = (b->flags & DEVF_G450DAC) != 0;
1646 minfo->devflags.textstep = minfo->devflags.vgastep * minfo->devflags.textmode;
1647 minfo->devflags.textvram = 65536 / minfo->devflags.textmode;
1648 setDefaultOutputs(minfo);
1649 if (b->flags & DEVF_PANELLINK_CAPABLE) {
1650 minfo->outputs[2].data = minfo;
1651 minfo->outputs[2].output = &panellink_output;
1652 minfo->outputs[2].src = minfo->outputs[2].default_src;
1653 minfo->outputs[2].mode = MATROXFB_OUTPUT_MODE_MONITOR;
1654 minfo->devflags.panellink = 1;
1655 }
1656
1657 if (minfo->capable.cross4MB < 0)
1658 minfo->capable.cross4MB = b->flags & DEVF_CROSS4MB;
1659 if (b->flags & DEVF_SWAPS) {
1660 ctrlptr_phys = pci_resource_start(minfo->pcidev, 1);
1661 video_base_phys = pci_resource_start(minfo->pcidev, 0);
1662 minfo->devflags.fbResource = PCI_BASE_ADDRESS_0;
1663 } else {
1664 ctrlptr_phys = pci_resource_start(minfo->pcidev, 0);
1665 video_base_phys = pci_resource_start(minfo->pcidev, 1);
1666 minfo->devflags.fbResource = PCI_BASE_ADDRESS_1;
1667 }
1668 err = -EINVAL;
1669 if (!ctrlptr_phys) {
1670 printk(KERN_ERR "matroxfb: control registers are not available, matroxfb disabled\n");
1671 goto fail;
1672 }
1673 if (!video_base_phys) {
1674 printk(KERN_ERR "matroxfb: video RAM is not available in PCI address space, matroxfb disabled\n");
1675 goto fail;
1676 }
1677 memsize = b->base->maxvram;
1678 if (!request_mem_region(ctrlptr_phys, 16384, "matroxfb MMIO")) {
1679 goto fail;
1680 }
1681 if (!request_mem_region(video_base_phys, memsize, "matroxfb FB")) {
1682 goto failCtrlMR;
1683 }
1684 minfo->video.len_maximum = memsize;
1685
1686 if (mem < 1024) mem *= 1024;
1687 if (mem < 0x00100000) mem *= 1024;
1688
1689 if (mem && (mem < memsize))
1690 memsize = mem;
1691 err = -ENOMEM;
1692 if (mga_ioremap(ctrlptr_phys, 16384, MGA_IOREMAP_MMIO, &minfo->mmio.vbase)) {
1693 printk(KERN_ERR "matroxfb: cannot ioremap(%lX, 16384), matroxfb disabled\n", ctrlptr_phys);
1694 goto failVideoMR;
1695 }
1696 minfo->mmio.base = ctrlptr_phys;
1697 minfo->mmio.len = 16384;
1698 minfo->video.base = video_base_phys;
1699 if (mga_ioremap(video_base_phys, memsize, MGA_IOREMAP_FB, &minfo->video.vbase)) {
1700 printk(KERN_ERR "matroxfb: cannot ioremap(%lX, %d), matroxfb disabled\n",
1701 video_base_phys, memsize);
1702 goto failCtrlIO;
1703 }
1704 {
1705 u_int32_t cmd;
1706 u_int32_t mga_option;
1707
1708 pci_read_config_dword(minfo->pcidev, PCI_OPTION_REG, &mga_option);
1709 pci_read_config_dword(minfo->pcidev, PCI_COMMAND, &cmd);
1710 mga_option &= 0x7FFFFFFF;
1711 mga_option |= MX_OPTION_BSWAP;
1712
1713 cmd &= ~PCI_COMMAND_VGA_PALETTE;
1714 if (pci_dev_present(intel_82437)) {
1715 if (!(mga_option & 0x20000000) && !minfo->devflags.nopciretry) {
1716 printk(KERN_WARNING "matroxfb: Disabling PCI retries due to i82437 present\n");
1717 }
1718 mga_option |= 0x20000000;
1719 minfo->devflags.nopciretry = 1;
1720 }
1721 pci_write_config_dword(minfo->pcidev, PCI_COMMAND, cmd);
1722 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mga_option);
1723 minfo->hw.MXoptionReg = mga_option;
1724
1725
1726
1727 pci_write_config_dword(minfo->pcidev, PCI_MGA_INDEX, 0x00003C00);
1728 }
1729
1730 err = -ENXIO;
1731 matroxfb_read_pins(minfo);
1732 if (minfo->hw_switch->preinit(minfo)) {
1733 goto failVideoIO;
1734 }
1735
1736 err = -ENOMEM;
1737 if (!matroxfb_getmemory(minfo, memsize, &minfo->video.len) || !minfo->video.len) {
1738 printk(KERN_ERR "matroxfb: cannot determine memory size\n");
1739 goto failVideoIO;
1740 }
1741 minfo->devflags.ydstorg = 0;
1742
1743 minfo->video.base = video_base_phys;
1744 minfo->video.len_usable = minfo->video.len;
1745 if (minfo->video.len_usable > b->base->maxdisplayable)
1746 minfo->video.len_usable = b->base->maxdisplayable;
1747#ifdef CONFIG_MTRR
1748 if (mtrr) {
1749 minfo->mtrr.vram = mtrr_add(video_base_phys, minfo->video.len, MTRR_TYPE_WRCOMB, 1);
1750 minfo->mtrr.vram_valid = 1;
1751 printk(KERN_INFO "matroxfb: MTRR's turned on\n");
1752 }
1753#endif
1754
1755 if (!minfo->devflags.novga)
1756 request_region(0x3C0, 32, "matrox");
1757 matroxfb_g450_connect(minfo);
1758 minfo->hw_switch->reset(minfo);
1759
1760 minfo->fbcon.monspecs.hfmin = 0;
1761 minfo->fbcon.monspecs.hfmax = fh;
1762 minfo->fbcon.monspecs.vfmin = 0;
1763 minfo->fbcon.monspecs.vfmax = fv;
1764 minfo->fbcon.monspecs.dpms = 0;
1765
1766
1767 vesafb_defined.red = colors[depth-1].red;
1768 vesafb_defined.green = colors[depth-1].green;
1769 vesafb_defined.blue = colors[depth-1].blue;
1770 vesafb_defined.bits_per_pixel = colors[depth-1].bits_per_pixel;
1771 vesafb_defined.grayscale = grayscale;
1772 vesafb_defined.vmode = 0;
1773 if (noaccel)
1774 vesafb_defined.accel_flags &= ~FB_ACCELF_TEXT;
1775
1776 minfo->fbops = matroxfb_ops;
1777 minfo->fbcon.fbops = &minfo->fbops;
1778 minfo->fbcon.pseudo_palette = minfo->cmap;
1779
1780 minfo->fbcon.flags = hotplug ? FBINFO_FLAG_MODULE : FBINFO_FLAG_DEFAULT;
1781 minfo->fbcon.flags |= FBINFO_PARTIAL_PAN_OK |
1782 FBINFO_HWACCEL_COPYAREA |
1783 FBINFO_HWACCEL_FILLRECT |
1784 FBINFO_HWACCEL_IMAGEBLIT |
1785 FBINFO_HWACCEL_XPAN |
1786 FBINFO_HWACCEL_YPAN;
1787 minfo->video.len_usable &= PAGE_MASK;
1788 fb_alloc_cmap(&minfo->fbcon.cmap, 256, 1);
1789
1790#ifndef MODULE
1791
1792 if (!hotplug) {
1793 fb_find_mode(&vesafb_defined, &minfo->fbcon, videomode[0] ? videomode : NULL,
1794 NULL, 0, &defaultmode, vesafb_defined.bits_per_pixel);
1795 }
1796#endif
1797
1798
1799 if (hslen)
1800 vesafb_defined.hsync_len = hslen;
1801 if (vslen)
1802 vesafb_defined.vsync_len = vslen;
1803 if (left != ~0)
1804 vesafb_defined.left_margin = left;
1805 if (right != ~0)
1806 vesafb_defined.right_margin = right;
1807 if (upper != ~0)
1808 vesafb_defined.upper_margin = upper;
1809 if (lower != ~0)
1810 vesafb_defined.lower_margin = lower;
1811 if (xres)
1812 vesafb_defined.xres = xres;
1813 if (yres)
1814 vesafb_defined.yres = yres;
1815 if (sync != -1)
1816 vesafb_defined.sync = sync;
1817 else if (vesafb_defined.sync == ~0) {
1818 vesafb_defined.sync = 0;
1819 if (yres < 400)
1820 vesafb_defined.sync |= FB_SYNC_HOR_HIGH_ACT;
1821 else if (yres < 480)
1822 vesafb_defined.sync |= FB_SYNC_VERT_HIGH_ACT;
1823 }
1824
1825
1826 {
1827 unsigned int tmp;
1828
1829 if (fv) {
1830 tmp = fv * (vesafb_defined.upper_margin + vesafb_defined.yres
1831 + vesafb_defined.lower_margin + vesafb_defined.vsync_len);
1832 if ((tmp < fh) || (fh == 0)) fh = tmp;
1833 }
1834 if (fh) {
1835 tmp = fh * (vesafb_defined.left_margin + vesafb_defined.xres
1836 + vesafb_defined.right_margin + vesafb_defined.hsync_len);
1837 if ((tmp < maxclk) || (maxclk == 0)) maxclk = tmp;
1838 }
1839 tmp = (maxclk + 499) / 500;
1840 if (tmp) {
1841 tmp = (2000000000 + tmp) / tmp;
1842 if (tmp > pixclock) pixclock = tmp;
1843 }
1844 }
1845 if (pixclock) {
1846 if (pixclock < 2000)
1847 pixclock = 4000;
1848 if (pixclock > 1000000)
1849 pixclock = 1000000;
1850 vesafb_defined.pixclock = pixclock;
1851 }
1852
1853
1854#if defined(CONFIG_PPC_PMAC)
1855#ifndef MODULE
1856 if (machine_is(powermac)) {
1857 struct fb_var_screeninfo var;
1858 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1859 default_vmode = VMODE_640_480_60;
1860#ifdef CONFIG_NVRAM
1861 if (default_cmode == CMODE_NVRAM)
1862 default_cmode = nvram_read_byte(NV_CMODE);
1863#endif
1864 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
1865 default_cmode = CMODE_8;
1866 if (!mac_vmode_to_var(default_vmode, default_cmode, &var)) {
1867 var.accel_flags = vesafb_defined.accel_flags;
1868 var.xoffset = var.yoffset = 0;
1869
1870 vesafb_defined = var;
1871 }
1872 }
1873#endif
1874#endif
1875 vesafb_defined.xres_virtual = vesafb_defined.xres;
1876 if (nopan) {
1877 vesafb_defined.yres_virtual = vesafb_defined.yres;
1878 } else {
1879 vesafb_defined.yres_virtual = 65536;
1880
1881 }
1882 matroxfb_init_fix(minfo);
1883 minfo->fbcon.screen_base = vaddr_va(minfo->video.vbase);
1884
1885 matroxfb_check_var(&vesafb_defined, &minfo->fbcon);
1886
1887
1888
1889
1890 minfo->fbcon.var = vesafb_defined;
1891 err = -EINVAL;
1892
1893 printk(KERN_INFO "matroxfb: %dx%dx%dbpp (virtual: %dx%d)\n",
1894 vesafb_defined.xres, vesafb_defined.yres, vesafb_defined.bits_per_pixel,
1895 vesafb_defined.xres_virtual, vesafb_defined.yres_virtual);
1896 printk(KERN_INFO "matroxfb: framebuffer at 0x%lX, mapped to 0x%p, size %d\n",
1897 minfo->video.base, vaddr_va(minfo->video.vbase), minfo->video.len);
1898
1899
1900
1901
1902 minfo->fbcon.device = &minfo->pcidev->dev;
1903 if (register_framebuffer(&minfo->fbcon) < 0) {
1904 goto failVideoIO;
1905 }
1906 printk("fb%d: %s frame buffer device\n",
1907 minfo->fbcon.node, minfo->fbcon.fix.id);
1908
1909
1910
1911 if (!minfo->initialized) {
1912 printk(KERN_INFO "fb%d: initializing hardware\n",
1913 minfo->fbcon.node);
1914
1915
1916 vesafb_defined.activate |= FB_ACTIVATE_FORCE;
1917 fb_set_var(&minfo->fbcon, &vesafb_defined);
1918 }
1919
1920 return 0;
1921failVideoIO:;
1922 matroxfb_g450_shutdown(minfo);
1923 mga_iounmap(minfo->video.vbase);
1924failCtrlIO:;
1925 mga_iounmap(minfo->mmio.vbase);
1926failVideoMR:;
1927 release_mem_region(video_base_phys, minfo->video.len_maximum);
1928failCtrlMR:;
1929 release_mem_region(ctrlptr_phys, 16384);
1930fail:;
1931 return err;
1932}
1933
1934static LIST_HEAD(matroxfb_list);
1935static LIST_HEAD(matroxfb_driver_list);
1936
1937#define matroxfb_l(x) list_entry(x, struct matrox_fb_info, next_fb)
1938#define matroxfb_driver_l(x) list_entry(x, struct matroxfb_driver, node)
1939int matroxfb_register_driver(struct matroxfb_driver* drv) {
1940 struct matrox_fb_info* minfo;
1941
1942 list_add(&drv->node, &matroxfb_driver_list);
1943 for (minfo = matroxfb_l(matroxfb_list.next);
1944 minfo != matroxfb_l(&matroxfb_list);
1945 minfo = matroxfb_l(minfo->next_fb.next)) {
1946 void* p;
1947
1948 if (minfo->drivers_count == MATROXFB_MAX_FB_DRIVERS)
1949 continue;
1950 p = drv->probe(minfo);
1951 if (p) {
1952 minfo->drivers_data[minfo->drivers_count] = p;
1953 minfo->drivers[minfo->drivers_count++] = drv;
1954 }
1955 }
1956 return 0;
1957}
1958
1959void matroxfb_unregister_driver(struct matroxfb_driver* drv) {
1960 struct matrox_fb_info* minfo;
1961
1962 list_del(&drv->node);
1963 for (minfo = matroxfb_l(matroxfb_list.next);
1964 minfo != matroxfb_l(&matroxfb_list);
1965 minfo = matroxfb_l(minfo->next_fb.next)) {
1966 int i;
1967
1968 for (i = 0; i < minfo->drivers_count; ) {
1969 if (minfo->drivers[i] == drv) {
1970 if (drv && drv->remove)
1971 drv->remove(minfo, minfo->drivers_data[i]);
1972 minfo->drivers[i] = minfo->drivers[--minfo->drivers_count];
1973 minfo->drivers_data[i] = minfo->drivers_data[minfo->drivers_count];
1974 } else
1975 i++;
1976 }
1977 }
1978}
1979
1980static void matroxfb_register_device(struct matrox_fb_info* minfo) {
1981 struct matroxfb_driver* drv;
1982 int i = 0;
1983 list_add(&minfo->next_fb, &matroxfb_list);
1984 for (drv = matroxfb_driver_l(matroxfb_driver_list.next);
1985 drv != matroxfb_driver_l(&matroxfb_driver_list);
1986 drv = matroxfb_driver_l(drv->node.next)) {
1987 if (drv && drv->probe) {
1988 void *p = drv->probe(minfo);
1989 if (p) {
1990 minfo->drivers_data[i] = p;
1991 minfo->drivers[i++] = drv;
1992 if (i == MATROXFB_MAX_FB_DRIVERS)
1993 break;
1994 }
1995 }
1996 }
1997 minfo->drivers_count = i;
1998}
1999
2000static void matroxfb_unregister_device(struct matrox_fb_info* minfo) {
2001 int i;
2002
2003 list_del(&minfo->next_fb);
2004 for (i = 0; i < minfo->drivers_count; i++) {
2005 struct matroxfb_driver* drv = minfo->drivers[i];
2006
2007 if (drv && drv->remove)
2008 drv->remove(minfo, minfo->drivers_data[i]);
2009 }
2010}
2011
2012static int matroxfb_probe(struct pci_dev* pdev, const struct pci_device_id* dummy) {
2013 struct board* b;
2014 u_int16_t svid;
2015 u_int16_t sid;
2016 struct matrox_fb_info* minfo;
2017 int err;
2018 u_int32_t cmd;
2019 DBG(__func__)
2020
2021 svid = pdev->subsystem_vendor;
2022 sid = pdev->subsystem_device;
2023 for (b = dev_list; b->vendor; b++) {
2024 if ((b->vendor != pdev->vendor) || (b->device != pdev->device) || (b->rev < pdev->revision)) continue;
2025 if (b->svid)
2026 if ((b->svid != svid) || (b->sid != sid)) continue;
2027 break;
2028 }
2029
2030 if (!b->vendor)
2031 return -ENODEV;
2032 if (dev > 0) {
2033
2034 dev--;
2035 return -ENODEV;
2036 }
2037 pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
2038 if (pci_enable_device(pdev)) {
2039 return -1;
2040 }
2041
2042 minfo = kmalloc(sizeof(*minfo), GFP_KERNEL);
2043 if (!minfo)
2044 return -1;
2045 memset(minfo, 0, sizeof(*minfo));
2046
2047 minfo->pcidev = pdev;
2048 minfo->dead = 0;
2049 minfo->usecount = 0;
2050 minfo->userusecount = 0;
2051
2052 pci_set_drvdata(pdev, minfo);
2053
2054 minfo->devflags.memtype = memtype;
2055 if (memtype != -1)
2056 noinit = 0;
2057 if (cmd & PCI_COMMAND_MEMORY) {
2058 minfo->devflags.novga = novga;
2059 minfo->devflags.nobios = nobios;
2060 minfo->devflags.noinit = noinit;
2061
2062 novga = 1;
2063 nobios = 1;
2064 noinit = 0;
2065 } else {
2066 minfo->devflags.novga = 1;
2067 minfo->devflags.nobios = 1;
2068 minfo->devflags.noinit = 0;
2069 }
2070
2071 minfo->devflags.nopciretry = no_pci_retry;
2072 minfo->devflags.mga_24bpp_fix = inv24;
2073 minfo->devflags.precise_width = option_precise_width;
2074 minfo->devflags.sgram = sgram;
2075 minfo->capable.cross4MB = cross4MB;
2076
2077 spin_lock_init(&minfo->lock.DAC);
2078 spin_lock_init(&minfo->lock.accel);
2079 init_rwsem(&minfo->crtc2.lock);
2080 init_rwsem(&minfo->altout.lock);
2081 mutex_init(&minfo->fbcon.mm_lock);
2082 minfo->irq_flags = 0;
2083 init_waitqueue_head(&minfo->crtc1.vsync.wait);
2084 init_waitqueue_head(&minfo->crtc2.vsync.wait);
2085 minfo->crtc1.panpos = -1;
2086
2087 err = initMatrox2(minfo, b);
2088 if (!err) {
2089 matroxfb_register_device(minfo);
2090 return 0;
2091 }
2092 kfree(minfo);
2093 return -1;
2094}
2095
2096static void pci_remove_matrox(struct pci_dev* pdev) {
2097 struct matrox_fb_info* minfo;
2098
2099 minfo = pci_get_drvdata(pdev);
2100 matroxfb_remove(minfo, 1);
2101}
2102
2103static struct pci_device_id matroxfb_devices[] = {
2104#ifdef CONFIG_FB_MATROX_MILLENIUM
2105 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL,
2106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2107 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2,
2108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2109 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2_AGP,
2110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2111#endif
2112#ifdef CONFIG_FB_MATROX_MYSTIQUE
2113 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS,
2114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2115#endif
2116#ifdef CONFIG_FB_MATROX_G
2117 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G100_MM,
2118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2119 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G100_AGP,
2120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2121 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200EV_PCI,
2122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2123 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI,
2124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2125 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP,
2126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2127 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400,
2128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2129 {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G550,
2130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2131#endif
2132 {0, 0,
2133 0, 0, 0, 0, 0}
2134};
2135
2136MODULE_DEVICE_TABLE(pci, matroxfb_devices);
2137
2138
2139static struct pci_driver matroxfb_driver = {
2140 .name = "matroxfb",
2141 .id_table = matroxfb_devices,
2142 .probe = matroxfb_probe,
2143 .remove = pci_remove_matrox,
2144};
2145
2146
2147
2148#define RSResolution(X) ((X) & 0x0F)
2149#define RS640x400 1
2150#define RS640x480 2
2151#define RS800x600 3
2152#define RS1024x768 4
2153#define RS1280x1024 5
2154#define RS1600x1200 6
2155#define RS768x576 7
2156#define RS960x720 8
2157#define RS1152x864 9
2158#define RS1408x1056 10
2159#define RS640x350 11
2160#define RS1056x344 12
2161#define RS1056x400 13
2162#define RS1056x480 14
2163#define RSNoxNo 15
2164
2165static struct { int xres, yres, left, right, upper, lower, hslen, vslen, vfreq; } timmings[] __initdata = {
2166 { 640, 400, 48, 16, 39, 8, 96, 2, 70 },
2167 { 640, 480, 48, 16, 33, 10, 96, 2, 60 },
2168 { 800, 600, 144, 24, 28, 8, 112, 6, 60 },
2169 { 1024, 768, 160, 32, 30, 4, 128, 4, 60 },
2170 { 1280, 1024, 224, 32, 32, 4, 136, 4, 60 },
2171 { 1600, 1200, 272, 48, 32, 5, 152, 5, 60 },
2172 { 768, 576, 144, 16, 28, 6, 112, 4, 60 },
2173 { 960, 720, 144, 24, 28, 8, 112, 4, 60 },
2174 { 1152, 864, 192, 32, 30, 4, 128, 4, 60 },
2175 { 1408, 1056, 256, 40, 32, 5, 144, 5, 60 },
2176 { 640, 350, 48, 16, 39, 8, 96, 2, 70 },
2177 { 1056, 344, 96, 24, 59, 44, 160, 2, 70 },
2178 { 1056, 400, 96, 24, 39, 8, 160, 2, 70 },
2179 { 1056, 480, 96, 24, 36, 12, 160, 3, 60 },
2180 { 0, 0, ~0, ~0, ~0, ~0, 0, 0, 0 }
2181};
2182
2183#define RSCreate(X,Y) ((X) | ((Y) << 8))
2184static struct { unsigned int vesa; unsigned int info; } *RSptr, vesamap[] __initdata = {
2185
2186 { ~0, RSCreate(RSNoxNo, RS8bpp ) },
2187 { 0x101, RSCreate(RS640x480, RS8bpp ) },
2188 { 0x100, RSCreate(RS640x400, RS8bpp ) },
2189 { 0x180, RSCreate(RS768x576, RS8bpp ) },
2190 { 0x103, RSCreate(RS800x600, RS8bpp ) },
2191 { 0x188, RSCreate(RS960x720, RS8bpp ) },
2192 { 0x105, RSCreate(RS1024x768, RS8bpp ) },
2193 { 0x190, RSCreate(RS1152x864, RS8bpp ) },
2194 { 0x107, RSCreate(RS1280x1024, RS8bpp ) },
2195 { 0x198, RSCreate(RS1408x1056, RS8bpp ) },
2196 { 0x11C, RSCreate(RS1600x1200, RS8bpp ) },
2197 { 0x110, RSCreate(RS640x480, RS15bpp) },
2198 { 0x181, RSCreate(RS768x576, RS15bpp) },
2199 { 0x113, RSCreate(RS800x600, RS15bpp) },
2200 { 0x189, RSCreate(RS960x720, RS15bpp) },
2201 { 0x116, RSCreate(RS1024x768, RS15bpp) },
2202 { 0x191, RSCreate(RS1152x864, RS15bpp) },
2203 { 0x119, RSCreate(RS1280x1024, RS15bpp) },
2204 { 0x199, RSCreate(RS1408x1056, RS15bpp) },
2205 { 0x11D, RSCreate(RS1600x1200, RS15bpp) },
2206 { 0x111, RSCreate(RS640x480, RS16bpp) },
2207 { 0x182, RSCreate(RS768x576, RS16bpp) },
2208 { 0x114, RSCreate(RS800x600, RS16bpp) },
2209 { 0x18A, RSCreate(RS960x720, RS16bpp) },
2210 { 0x117, RSCreate(RS1024x768, RS16bpp) },
2211 { 0x192, RSCreate(RS1152x864, RS16bpp) },
2212 { 0x11A, RSCreate(RS1280x1024, RS16bpp) },
2213 { 0x19A, RSCreate(RS1408x1056, RS16bpp) },
2214 { 0x11E, RSCreate(RS1600x1200, RS16bpp) },
2215 { 0x1B2, RSCreate(RS640x480, RS24bpp) },
2216 { 0x184, RSCreate(RS768x576, RS24bpp) },
2217 { 0x1B5, RSCreate(RS800x600, RS24bpp) },
2218 { 0x18C, RSCreate(RS960x720, RS24bpp) },
2219 { 0x1B8, RSCreate(RS1024x768, RS24bpp) },
2220 { 0x194, RSCreate(RS1152x864, RS24bpp) },
2221 { 0x1BB, RSCreate(RS1280x1024, RS24bpp) },
2222 { 0x19C, RSCreate(RS1408x1056, RS24bpp) },
2223 { 0x1BF, RSCreate(RS1600x1200, RS24bpp) },
2224 { 0x112, RSCreate(RS640x480, RS32bpp) },
2225 { 0x183, RSCreate(RS768x576, RS32bpp) },
2226 { 0x115, RSCreate(RS800x600, RS32bpp) },
2227 { 0x18B, RSCreate(RS960x720, RS32bpp) },
2228 { 0x118, RSCreate(RS1024x768, RS32bpp) },
2229 { 0x193, RSCreate(RS1152x864, RS32bpp) },
2230 { 0x11B, RSCreate(RS1280x1024, RS32bpp) },
2231 { 0x19B, RSCreate(RS1408x1056, RS32bpp) },
2232 { 0x11F, RSCreate(RS1600x1200, RS32bpp) },
2233 { 0x010, RSCreate(RS640x350, RS4bpp ) },
2234 { 0x012, RSCreate(RS640x480, RS4bpp ) },
2235 { 0x102, RSCreate(RS800x600, RS4bpp ) },
2236 { 0x104, RSCreate(RS1024x768, RS4bpp ) },
2237 { 0x106, RSCreate(RS1280x1024, RS4bpp ) },
2238 { 0, 0 }};
2239
2240static void __init matroxfb_init_params(void) {
2241
2242 if (fh < 1000)
2243 fh *= 1000;
2244
2245 if (maxclk < 1000) maxclk *= 1000;
2246 if (maxclk < 1000000) maxclk *= 1000;
2247
2248 if (vesa != ~0)
2249 vesa &= 0x1DFF;
2250
2251
2252 for (RSptr = vesamap; RSptr->vesa; RSptr++) {
2253 if (RSptr->vesa == vesa) break;
2254 }
2255 if (!RSptr->vesa) {
2256 printk(KERN_ERR "Invalid vesa mode 0x%04X\n", vesa);
2257 RSptr = vesamap;
2258 }
2259 {
2260 int res = RSResolution(RSptr->info)-1;
2261 if (left == ~0)
2262 left = timmings[res].left;
2263 if (!xres)
2264 xres = timmings[res].xres;
2265 if (right == ~0)
2266 right = timmings[res].right;
2267 if (!hslen)
2268 hslen = timmings[res].hslen;
2269 if (upper == ~0)
2270 upper = timmings[res].upper;
2271 if (!yres)
2272 yres = timmings[res].yres;
2273 if (lower == ~0)
2274 lower = timmings[res].lower;
2275 if (!vslen)
2276 vslen = timmings[res].vslen;
2277 if (!(fv||fh||maxclk||pixclock))
2278 fv = timmings[res].vfreq;
2279 if (depth == -1)
2280 depth = RSDepth(RSptr->info);
2281 }
2282}
2283
2284static int __init matrox_init(void) {
2285 int err;
2286
2287 matroxfb_init_params();
2288 err = pci_register_driver(&matroxfb_driver);
2289 dev = -1;
2290 return err;
2291}
2292
2293
2294
2295static void __exit matrox_done(void) {
2296 pci_unregister_driver(&matroxfb_driver);
2297}
2298
2299#ifndef MODULE
2300
2301
2302
2303static int __init matroxfb_setup(char *options) {
2304 char *this_opt;
2305
2306 DBG(__func__)
2307
2308 if (!options || !*options)
2309 return 0;
2310
2311 while ((this_opt = strsep(&options, ",")) != NULL) {
2312 if (!*this_opt) continue;
2313
2314 dprintk("matroxfb_setup: option %s\n", this_opt);
2315
2316 if (!strncmp(this_opt, "dev:", 4))
2317 dev = simple_strtoul(this_opt+4, NULL, 0);
2318 else if (!strncmp(this_opt, "depth:", 6)) {
2319 switch (simple_strtoul(this_opt+6, NULL, 0)) {
2320 case 0: depth = RSText; break;
2321 case 4: depth = RS4bpp; break;
2322 case 8: depth = RS8bpp; break;
2323 case 15:depth = RS15bpp; break;
2324 case 16:depth = RS16bpp; break;
2325 case 24:depth = RS24bpp; break;
2326 case 32:depth = RS32bpp; break;
2327 default:
2328 printk(KERN_ERR "matroxfb: unsupported color depth\n");
2329 }
2330 } else if (!strncmp(this_opt, "xres:", 5))
2331 xres = simple_strtoul(this_opt+5, NULL, 0);
2332 else if (!strncmp(this_opt, "yres:", 5))
2333 yres = simple_strtoul(this_opt+5, NULL, 0);
2334 else if (!strncmp(this_opt, "vslen:", 6))
2335 vslen = simple_strtoul(this_opt+6, NULL, 0);
2336 else if (!strncmp(this_opt, "hslen:", 6))
2337 hslen = simple_strtoul(this_opt+6, NULL, 0);
2338 else if (!strncmp(this_opt, "left:", 5))
2339 left = simple_strtoul(this_opt+5, NULL, 0);
2340 else if (!strncmp(this_opt, "right:", 6))
2341 right = simple_strtoul(this_opt+6, NULL, 0);
2342 else if (!strncmp(this_opt, "upper:", 6))
2343 upper = simple_strtoul(this_opt+6, NULL, 0);
2344 else if (!strncmp(this_opt, "lower:", 6))
2345 lower = simple_strtoul(this_opt+6, NULL, 0);
2346 else if (!strncmp(this_opt, "pixclock:", 9))
2347 pixclock = simple_strtoul(this_opt+9, NULL, 0);
2348 else if (!strncmp(this_opt, "sync:", 5))
2349 sync = simple_strtoul(this_opt+5, NULL, 0);
2350 else if (!strncmp(this_opt, "vesa:", 5))
2351 vesa = simple_strtoul(this_opt+5, NULL, 0);
2352 else if (!strncmp(this_opt, "maxclk:", 7))
2353 maxclk = simple_strtoul(this_opt+7, NULL, 0);
2354 else if (!strncmp(this_opt, "fh:", 3))
2355 fh = simple_strtoul(this_opt+3, NULL, 0);
2356 else if (!strncmp(this_opt, "fv:", 3))
2357 fv = simple_strtoul(this_opt+3, NULL, 0);
2358 else if (!strncmp(this_opt, "mem:", 4))
2359 mem = simple_strtoul(this_opt+4, NULL, 0);
2360 else if (!strncmp(this_opt, "mode:", 5))
2361 strlcpy(videomode, this_opt+5, sizeof(videomode));
2362 else if (!strncmp(this_opt, "outputs:", 8))
2363 strlcpy(outputs, this_opt+8, sizeof(outputs));
2364 else if (!strncmp(this_opt, "dfp:", 4)) {
2365 dfp_type = simple_strtoul(this_opt+4, NULL, 0);
2366 dfp = 1;
2367 }
2368#ifdef CONFIG_PPC_PMAC
2369 else if (!strncmp(this_opt, "vmode:", 6)) {
2370 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
2371 if (vmode > 0 && vmode <= VMODE_MAX)
2372 default_vmode = vmode;
2373 } else if (!strncmp(this_opt, "cmode:", 6)) {
2374 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
2375 switch (cmode) {
2376 case 0:
2377 case 8:
2378 default_cmode = CMODE_8;
2379 break;
2380 case 15:
2381 case 16:
2382 default_cmode = CMODE_16;
2383 break;
2384 case 24:
2385 case 32:
2386 default_cmode = CMODE_32;
2387 break;
2388 }
2389 }
2390#endif
2391 else if (!strcmp(this_opt, "disabled"))
2392 disabled = 1;
2393 else if (!strcmp(this_opt, "enabled"))
2394 disabled = 0;
2395 else if (!strcmp(this_opt, "sgram"))
2396 sgram = 1;
2397 else if (!strcmp(this_opt, "sdram"))
2398 sgram = 0;
2399 else if (!strncmp(this_opt, "memtype:", 8))
2400 memtype = simple_strtoul(this_opt+8, NULL, 0);
2401 else {
2402 int value = 1;
2403
2404 if (!strncmp(this_opt, "no", 2)) {
2405 value = 0;
2406 this_opt += 2;
2407 }
2408 if (! strcmp(this_opt, "inverse"))
2409 inverse = value;
2410 else if (!strcmp(this_opt, "accel"))
2411 noaccel = !value;
2412 else if (!strcmp(this_opt, "pan"))
2413 nopan = !value;
2414 else if (!strcmp(this_opt, "pciretry"))
2415 no_pci_retry = !value;
2416 else if (!strcmp(this_opt, "vga"))
2417 novga = !value;
2418 else if (!strcmp(this_opt, "bios"))
2419 nobios = !value;
2420 else if (!strcmp(this_opt, "init"))
2421 noinit = !value;
2422#ifdef CONFIG_MTRR
2423 else if (!strcmp(this_opt, "mtrr"))
2424 mtrr = value;
2425#endif
2426 else if (!strcmp(this_opt, "inv24"))
2427 inv24 = value;
2428 else if (!strcmp(this_opt, "cross4MB"))
2429 cross4MB = value;
2430 else if (!strcmp(this_opt, "grayscale"))
2431 grayscale = value;
2432 else if (!strcmp(this_opt, "dfp"))
2433 dfp = value;
2434 else {
2435 strlcpy(videomode, this_opt, sizeof(videomode));
2436 }
2437 }
2438 }
2439 return 0;
2440}
2441
2442static int __initdata initialized = 0;
2443
2444static int __init matroxfb_init(void)
2445{
2446 char *option = NULL;
2447 int err = 0;
2448
2449 DBG(__func__)
2450
2451 if (fb_get_options("matroxfb", &option))
2452 return -ENODEV;
2453 matroxfb_setup(option);
2454
2455 if (disabled)
2456 return -ENXIO;
2457 if (!initialized) {
2458 initialized = 1;
2459 err = matrox_init();
2460 }
2461 hotplug = 1;
2462
2463 return err;
2464}
2465
2466module_init(matroxfb_init);
2467
2468#else
2469
2470
2471
2472MODULE_AUTHOR("(c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");
2473MODULE_DESCRIPTION("Accelerated FBDev driver for Matrox Millennium/Mystique/G100/G200/G400/G450/G550");
2474MODULE_LICENSE("GPL");
2475
2476module_param(mem, int, 0);
2477MODULE_PARM_DESC(mem, "Size of available memory in MB, KB or B (2,4,8,12,16MB, default=autodetect)");
2478module_param(disabled, int, 0);
2479MODULE_PARM_DESC(disabled, "Disabled (0 or 1=disabled) (default=0)");
2480module_param(noaccel, int, 0);
2481MODULE_PARM_DESC(noaccel, "Do not use accelerating engine (0 or 1=disabled) (default=0)");
2482module_param(nopan, int, 0);
2483MODULE_PARM_DESC(nopan, "Disable pan on startup (0 or 1=disabled) (default=0)");
2484module_param(no_pci_retry, int, 0);
2485MODULE_PARM_DESC(no_pci_retry, "PCI retries enabled (0 or 1=disabled) (default=0)");
2486module_param(novga, int, 0);
2487MODULE_PARM_DESC(novga, "VGA I/O (0x3C0-0x3DF) disabled (0 or 1=disabled) (default=0)");
2488module_param(nobios, int, 0);
2489MODULE_PARM_DESC(nobios, "Disables ROM BIOS (0 or 1=disabled) (default=do not change BIOS state)");
2490module_param(noinit, int, 0);
2491MODULE_PARM_DESC(noinit, "Disables W/SG/SD-RAM and bus interface initialization (0 or 1=do not initialize) (default=0)");
2492module_param(memtype, int, 0);
2493MODULE_PARM_DESC(memtype, "Memory type for G200/G400 (see Documentation/fb/matroxfb.txt for explanation) (default=3 for G200, 0 for G400)");
2494#ifdef CONFIG_MTRR
2495module_param(mtrr, int, 0);
2496MODULE_PARM_DESC(mtrr, "This speeds up video memory accesses (0=disabled or 1) (default=1)");
2497#endif
2498module_param(sgram, int, 0);
2499MODULE_PARM_DESC(sgram, "Indicates that G100/G200/G400 has SGRAM memory (0=SDRAM, 1=SGRAM) (default=0)");
2500module_param(inv24, int, 0);
2501MODULE_PARM_DESC(inv24, "Inverts clock polarity for 24bpp and loop frequency > 100MHz (default=do not invert polarity)");
2502module_param(inverse, int, 0);
2503MODULE_PARM_DESC(inverse, "Inverse (0 or 1) (default=0)");
2504module_param(dev, int, 0);
2505MODULE_PARM_DESC(dev, "Multihead support, attach to device ID (0..N) (default=all working)");
2506module_param(vesa, int, 0);
2507MODULE_PARM_DESC(vesa, "Startup videomode (0x000-0x1FF) (default=0x101)");
2508module_param(xres, int, 0);
2509MODULE_PARM_DESC(xres, "Horizontal resolution (px), overrides xres from vesa (default=vesa)");
2510module_param(yres, int, 0);
2511MODULE_PARM_DESC(yres, "Vertical resolution (scans), overrides yres from vesa (default=vesa)");
2512module_param(upper, int, 0);
2513MODULE_PARM_DESC(upper, "Upper blank space (scans), overrides upper from vesa (default=vesa)");
2514module_param(lower, int, 0);
2515MODULE_PARM_DESC(lower, "Lower blank space (scans), overrides lower from vesa (default=vesa)");
2516module_param(vslen, int, 0);
2517MODULE_PARM_DESC(vslen, "Vertical sync length (scans), overrides lower from vesa (default=vesa)");
2518module_param(left, int, 0);
2519MODULE_PARM_DESC(left, "Left blank space (px), overrides left from vesa (default=vesa)");
2520module_param(right, int, 0);
2521MODULE_PARM_DESC(right, "Right blank space (px), overrides right from vesa (default=vesa)");
2522module_param(hslen, int, 0);
2523MODULE_PARM_DESC(hslen, "Horizontal sync length (px), overrides hslen from vesa (default=vesa)");
2524module_param(pixclock, int, 0);
2525MODULE_PARM_DESC(pixclock, "Pixelclock (ns), overrides pixclock from vesa (default=vesa)");
2526module_param(sync, int, 0);
2527MODULE_PARM_DESC(sync, "Sync polarity, overrides sync from vesa (default=vesa)");
2528module_param(depth, int, 0);
2529MODULE_PARM_DESC(depth, "Color depth (0=text,8,15,16,24,32) (default=vesa)");
2530module_param(maxclk, int, 0);
2531MODULE_PARM_DESC(maxclk, "Startup maximal clock, 0-999MHz, 1000-999999kHz, 1000000-INF Hz");
2532module_param(fh, int, 0);
2533MODULE_PARM_DESC(fh, "Startup horizontal frequency, 0-999kHz, 1000-INF Hz");
2534module_param(fv, int, 0);
2535MODULE_PARM_DESC(fv, "Startup vertical frequency, 0-INF Hz\n"
2536"You should specify \"fv:max_monitor_vsync,fh:max_monitor_hsync,maxclk:max_monitor_dotclock\"");
2537module_param(grayscale, int, 0);
2538MODULE_PARM_DESC(grayscale, "Sets display into grayscale. Works perfectly with paletized videomode (4, 8bpp), some limitations apply to 16, 24 and 32bpp videomodes (default=nograyscale)");
2539module_param(cross4MB, int, 0);
2540MODULE_PARM_DESC(cross4MB, "Specifies that 4MB boundary can be in middle of line. (default=autodetected)");
2541module_param(dfp, int, 0);
2542MODULE_PARM_DESC(dfp, "Specifies whether to use digital flat panel interface of G200/G400 (0 or 1) (default=0)");
2543module_param(dfp_type, int, 0);
2544MODULE_PARM_DESC(dfp_type, "Specifies DFP interface type (0 to 255) (default=read from hardware)");
2545module_param_string(outputs, outputs, sizeof(outputs), 0);
2546MODULE_PARM_DESC(outputs, "Specifies which CRTC is mapped to which output (string of up to three letters, consisting of 0 (disabled), 1 (CRTC1), 2 (CRTC2)) (default=111 for Gx50, 101 for G200/G400 with DFP, and 100 for all other devices)");
2547#ifdef CONFIG_PPC_PMAC
2548module_param_named(vmode, default_vmode, int, 0);
2549MODULE_PARM_DESC(vmode, "Specify the vmode mode number that should be used (640x480 default)");
2550module_param_named(cmode, default_cmode, int, 0);
2551MODULE_PARM_DESC(cmode, "Specify the video depth that should be used (8bit default)");
2552#endif
2553
2554int __init init_module(void){
2555
2556 DBG(__func__)
2557
2558 if (disabled)
2559 return -ENXIO;
2560
2561 if (depth == 0)
2562 depth = RSText;
2563 else if (depth == 4)
2564 depth = RS4bpp;
2565 else if (depth == 8)
2566 depth = RS8bpp;
2567 else if (depth == 15)
2568 depth = RS15bpp;
2569 else if (depth == 16)
2570 depth = RS16bpp;
2571 else if (depth == 24)
2572 depth = RS24bpp;
2573 else if (depth == 32)
2574 depth = RS32bpp;
2575 else if (depth != -1) {
2576 printk(KERN_ERR "matroxfb: depth %d is not supported, using default\n", depth);
2577 depth = -1;
2578 }
2579 matrox_init();
2580
2581 return 0;
2582}
2583#endif
2584
2585module_exit(matrox_done);
2586EXPORT_SYMBOL(matroxfb_register_driver);
2587EXPORT_SYMBOL(matroxfb_unregister_driver);
2588EXPORT_SYMBOL(matroxfb_wait_for_sync);
2589EXPORT_SYMBOL(matroxfb_enable_irq);
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