linux/drivers/net/pci-skeleton.c
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   1/*
   2
   3        drivers/net/pci-skeleton.c
   4
   5        Maintained by Jeff Garzik <jgarzik@pobox.com>
   6
   7        Original code came from 8139too.c, which in turns was based
   8        originally on Donald Becker's rtl8139.c driver, versions 1.11
   9        and older.  This driver was originally based on rtl8139.c
  10        version 1.07.  Header of rtl8139.c version 1.11:
  11
  12        -----<snip>-----
  13
  14                Written 1997-2000 by Donald Becker.
  15                This software may be used and distributed according to the
  16                terms of the GNU General Public License (GPL), incorporated
  17                herein by reference.  Drivers based on or derived from this
  18                code fall under the GPL and must retain the authorship,
  19                copyright and license notice.  This file is not a complete
  20                program and may only be used when the entire operating
  21                system is licensed under the GPL.
  22
  23                This driver is for boards based on the RTL8129 and RTL8139
  24                PCI ethernet chips.
  25
  26                The author may be reached as becker@scyld.com, or C/O Scyld
  27                Computing Corporation 410 Severn Ave., Suite 210 Annapolis
  28                MD 21403
  29
  30                Support and updates available at
  31                http://www.scyld.com/network/rtl8139.html
  32
  33                Twister-tuning table provided by Kinston
  34                <shangh@realtek.com.tw>.
  35
  36        -----<snip>-----
  37
  38        This software may be used and distributed according to the terms
  39        of the GNU General Public License, incorporated herein by reference.
  40
  41
  42-----------------------------------------------------------------------------
  43
  44                                Theory of Operation
  45
  46I. Board Compatibility
  47
  48This device driver is designed for the RealTek RTL8139 series, the RealTek
  49Fast Ethernet controllers for PCI and CardBus.  This chip is used on many
  50low-end boards, sometimes with its markings changed.
  51
  52
  53II. Board-specific settings
  54
  55PCI bus devices are configured by the system at boot time, so no jumpers
  56need to be set on the board.  The system BIOS will assign the
  57PCI INTA signal to a (preferably otherwise unused) system IRQ line.
  58
  59III. Driver operation
  60
  61IIIa. Rx Ring buffers
  62
  63The receive unit uses a single linear ring buffer rather than the more
  64common (and more efficient) descriptor-based architecture.  Incoming frames
  65are sequentially stored into the Rx region, and the host copies them into
  66skbuffs.
  67
  68Comment: While it is theoretically possible to process many frames in place,
  69any delay in Rx processing would cause us to drop frames.  More importantly,
  70the Linux protocol stack is not designed to operate in this manner.
  71
  72IIIb. Tx operation
  73
  74The RTL8139 uses a fixed set of four Tx descriptors in register space.
  75In a stunningly bad design choice, Tx frames must be 32 bit aligned.  Linux
  76aligns the IP header on word boundaries, and 14 byte ethernet header means
  77that almost all frames will need to be copied to an alignment buffer.
  78
  79IVb. References
  80
  81http://www.realtek.com.tw/cn/cn.html
  82http://www.scyld.com/expert/NWay.html
  83
  84IVc. Errata
  85
  86*/
  87
  88#include <linux/module.h>
  89#include <linux/kernel.h>
  90#include <linux/pci.h>
  91#include <linux/init.h>
  92#include <linux/ioport.h>
  93#include <linux/netdevice.h>
  94#include <linux/etherdevice.h>
  95#include <linux/delay.h>
  96#include <linux/ethtool.h>
  97#include <linux/mii.h>
  98#include <linux/crc32.h>
  99#include <asm/io.h>
 100
 101#define NETDRV_VERSION          "1.0.1"
 102#define MODNAME                 "netdrv"
 103#define NETDRV_DRIVER_LOAD_MSG  "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
 104#define PFX                     MODNAME ": "
 105
 106static char version[] __devinitdata =
 107KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n"
 108"  Support available from http://foo.com/bar/baz.html\n";
 109
 110/* define to 1 to enable PIO instead of MMIO */
 111#undef USE_IO_OPS
 112
 113/* define to 1 to enable copious debugging info */
 114#undef NETDRV_DEBUG
 115
 116/* define to 1 to disable lightweight runtime debugging checks */
 117#undef NETDRV_NDEBUG
 118
 119
 120#ifdef NETDRV_DEBUG
 121/* note: prints function name for you */
 122#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
 123#else
 124#  define DPRINTK(fmt, args...)
 125#endif
 126
 127#ifdef NETDRV_NDEBUG
 128#  define assert(expr) do {} while (0)
 129#else
 130#  define assert(expr) \
 131        if(!(expr)) {                                   \
 132        printk( "Assertion failed! %s,%s,%s,line=%d\n", \
 133        #expr,__FILE__,__func__,__LINE__);              \
 134        }
 135#endif
 136
 137
 138/* A few user-configurable values. */
 139/* media options */
 140static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
 141
 142/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
 143static int max_interrupt_work = 20;
 144
 145/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
 146   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */
 147static int multicast_filter_limit = 32;
 148
 149/* Size of the in-memory receive ring. */
 150#define RX_BUF_LEN_IDX  2       /* 0==8K, 1==16K, 2==32K, 3==64K */
 151#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
 152#define RX_BUF_PAD 16
 153#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
 154#define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
 155
 156/* Number of Tx descriptor registers. */
 157#define NUM_TX_DESC     4
 158
 159/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
 160#define MAX_ETH_FRAME_SIZE      1536
 161
 162/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
 163#define TX_BUF_SIZE     MAX_ETH_FRAME_SIZE
 164#define TX_BUF_TOT_LEN  (TX_BUF_SIZE * NUM_TX_DESC)
 165
 166/* PCI Tuning Parameters
 167   Threshold is bytes transferred to chip before transmission starts. */
 168#define TX_FIFO_THRESH 256      /* In bytes, rounded down to 32 byte units. */
 169
 170/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */
 171#define RX_FIFO_THRESH  6       /* Rx buffer level before first PCI xfer.  */
 172#define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
 173#define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
 174
 175
 176/* Operational parameters that usually are not changed. */
 177/* Time in jiffies before concluding the transmitter is hung. */
 178#define TX_TIMEOUT  (6*HZ)
 179
 180
 181enum {
 182        HAS_CHIP_XCVR = 0x020000,
 183        HAS_LNK_CHNG = 0x040000,
 184};
 185
 186#define NETDRV_MIN_IO_SIZE 0x80
 187#define RTL8139B_IO_SIZE 256
 188
 189#define NETDRV_CAPS     HAS_CHIP_XCVR|HAS_LNK_CHNG
 190
 191typedef enum {
 192        RTL8139 = 0,
 193        NETDRV_CB,
 194        SMC1211TX,
 195        /*MPX5030,*/
 196        DELTA8139,
 197        ADDTRON8139,
 198} board_t;
 199
 200
 201/* indexed by board_t, above */
 202static struct {
 203        const char *name;
 204} board_info[] __devinitdata = {
 205        { "RealTek RTL8139 Fast Ethernet" },
 206        { "RealTek RTL8139B PCI/CardBus" },
 207        { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
 208/*      { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
 209        { "Delta Electronics 8139 10/100BaseTX" },
 210        { "Addtron Technolgy 8139 10/100BaseTX" },
 211};
 212
 213
 214static struct pci_device_id netdrv_pci_tbl[] = {
 215        {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 216        {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
 217        {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
 218/*      {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
 219        {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
 220        {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
 221        {0,}
 222};
 223MODULE_DEVICE_TABLE (pci, netdrv_pci_tbl);
 224
 225
 226/* The rest of these values should never change. */
 227
 228/* Symbolic offsets to registers. */
 229enum NETDRV_registers {
 230        MAC0 = 0,               /* Ethernet hardware address. */
 231        MAR0 = 8,               /* Multicast filter. */
 232        TxStatus0 = 0x10,       /* Transmit status (Four 32bit registers). */
 233        TxAddr0 = 0x20,         /* Tx descriptors (also four 32bit). */
 234        RxBuf = 0x30,
 235        RxEarlyCnt = 0x34,
 236        RxEarlyStatus = 0x36,
 237        ChipCmd = 0x37,
 238        RxBufPtr = 0x38,
 239        RxBufAddr = 0x3A,
 240        IntrMask = 0x3C,
 241        IntrStatus = 0x3E,
 242        TxConfig = 0x40,
 243        ChipVersion = 0x43,
 244        RxConfig = 0x44,
 245        Timer = 0x48,           /* A general-purpose counter. */
 246        RxMissed = 0x4C,        /* 24 bits valid, write clears. */
 247        Cfg9346 = 0x50,
 248        Config0 = 0x51,
 249        Config1 = 0x52,
 250        FlashReg = 0x54,
 251        MediaStatus = 0x58,
 252        Config3 = 0x59,
 253        Config4 = 0x5A,         /* absent on RTL-8139A */
 254        HltClk = 0x5B,
 255        MultiIntr = 0x5C,
 256        TxSummary = 0x60,
 257        BasicModeCtrl = 0x62,
 258        BasicModeStatus = 0x64,
 259        NWayAdvert = 0x66,
 260        NWayLPAR = 0x68,
 261        NWayExpansion = 0x6A,
 262        /* Undocumented registers, but required for proper operation. */
 263        FIFOTMS = 0x70,         /* FIFO Control and test. */
 264        CSCR = 0x74,            /* Chip Status and Configuration Register. */
 265        PARA78 = 0x78,
 266        PARA7c = 0x7c,          /* Magic transceiver parameter register. */
 267        Config5 = 0xD8,         /* absent on RTL-8139A */
 268};
 269
 270enum ClearBitMasks {
 271        MultiIntrClear = 0xF000,
 272        ChipCmdClear = 0xE2,
 273        Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
 274};
 275
 276enum ChipCmdBits {
 277        CmdReset = 0x10,
 278        CmdRxEnb = 0x08,
 279        CmdTxEnb = 0x04,
 280        RxBufEmpty = 0x01,
 281};
 282
 283/* Interrupt register bits, using my own meaningful names. */
 284enum IntrStatusBits {
 285        PCIErr = 0x8000,
 286        PCSTimeout = 0x4000,
 287        RxFIFOOver = 0x40,
 288        RxUnderrun = 0x20,
 289        RxOverflow = 0x10,
 290        TxErr = 0x08,
 291        TxOK = 0x04,
 292        RxErr = 0x02,
 293        RxOK = 0x01,
 294};
 295enum TxStatusBits {
 296        TxHostOwns = 0x2000,
 297        TxUnderrun = 0x4000,
 298        TxStatOK = 0x8000,
 299        TxOutOfWindow = 0x20000000,
 300        TxAborted = 0x40000000,
 301        TxCarrierLost = 0x80000000,
 302};
 303enum RxStatusBits {
 304        RxMulticast = 0x8000,
 305        RxPhysical = 0x4000,
 306        RxBroadcast = 0x2000,
 307        RxBadSymbol = 0x0020,
 308        RxRunt = 0x0010,
 309        RxTooLong = 0x0008,
 310        RxCRCErr = 0x0004,
 311        RxBadAlign = 0x0002,
 312        RxStatusOK = 0x0001,
 313};
 314
 315/* Bits in RxConfig. */
 316enum rx_mode_bits {
 317        AcceptErr = 0x20,
 318        AcceptRunt = 0x10,
 319        AcceptBroadcast = 0x08,
 320        AcceptMulticast = 0x04,
 321        AcceptMyPhys = 0x02,
 322        AcceptAllPhys = 0x01,
 323};
 324
 325/* Bits in TxConfig. */
 326enum tx_config_bits {
 327        TxIFG1 = (1 << 25),     /* Interframe Gap Time */
 328        TxIFG0 = (1 << 24),     /* Enabling these bits violates IEEE 802.3 */
 329        TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
 330        TxCRC = (1 << 16),      /* DISABLE appending CRC to end of Tx packets */
 331        TxClearAbt = (1 << 0),  /* Clear abort (WO) */
 332        TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
 333
 334        TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
 335};
 336
 337/* Bits in Config1 */
 338enum Config1Bits {
 339        Cfg1_PM_Enable = 0x01,
 340        Cfg1_VPD_Enable = 0x02,
 341        Cfg1_PIO = 0x04,
 342        Cfg1_MMIO = 0x08,
 343        Cfg1_LWAKE = 0x10,
 344        Cfg1_Driver_Load = 0x20,
 345        Cfg1_LED0 = 0x40,
 346        Cfg1_LED1 = 0x80,
 347};
 348
 349enum RxConfigBits {
 350        /* Early Rx threshold, none or X/16 */
 351        RxCfgEarlyRxNone = 0,
 352        RxCfgEarlyRxShift = 24,
 353
 354        /* rx fifo threshold */
 355        RxCfgFIFOShift = 13,
 356        RxCfgFIFONone = (7 << RxCfgFIFOShift),
 357
 358        /* Max DMA burst */
 359        RxCfgDMAShift = 8,
 360        RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
 361
 362        /* rx ring buffer length */
 363        RxCfgRcv8K = 0,
 364        RxCfgRcv16K = (1 << 11),
 365        RxCfgRcv32K = (1 << 12),
 366        RxCfgRcv64K = (1 << 11) | (1 << 12),
 367
 368        /* Disable packet wrap at end of Rx buffer */
 369        RxNoWrap = (1 << 7),
 370};
 371
 372
 373/* Twister tuning parameters from RealTek.
 374   Completely undocumented, but required to tune bad links. */
 375enum CSCRBits {
 376        CSCR_LinkOKBit = 0x0400,
 377        CSCR_LinkChangeBit = 0x0800,
 378        CSCR_LinkStatusBits = 0x0f000,
 379        CSCR_LinkDownOffCmd = 0x003c0,
 380        CSCR_LinkDownCmd = 0x0f3c0,
 381};
 382
 383
 384enum Cfg9346Bits {
 385        Cfg9346_Lock = 0x00,
 386        Cfg9346_Unlock = 0xC0,
 387};
 388
 389
 390#define PARA78_default  0x78fa8388
 391#define PARA7c_default  0xcb38de43      /* param[0][3] */
 392#define PARA7c_xxx              0xcb38de43
 393static const unsigned long param[4][4] = {
 394        {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
 395        {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
 396        {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
 397        {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
 398};
 399
 400struct ring_info {
 401        struct sk_buff *skb;
 402        dma_addr_t mapping;
 403};
 404
 405
 406typedef enum {
 407        CH_8139 = 0,
 408        CH_8139_K,
 409        CH_8139A,
 410        CH_8139B,
 411        CH_8130,
 412        CH_8139C,
 413} chip_t;
 414
 415
 416/* directly indexed by chip_t, above */
 417static const struct {
 418        const char *name;
 419        u8 version; /* from RTL8139C docs */
 420        u32 RxConfigMask; /* should clear the bits supported by this chip */
 421} rtl_chip_info[] = {
 422        { "RTL-8139",
 423          0x40,
 424          0xf0fe0040, /* XXX copied from RTL8139A, verify */
 425        },
 426
 427        { "RTL-8139 rev K",
 428          0x60,
 429          0xf0fe0040,
 430        },
 431
 432        { "RTL-8139A",
 433          0x70,
 434          0xf0fe0040,
 435        },
 436
 437        { "RTL-8139B",
 438          0x78,
 439          0xf0fc0040
 440        },
 441
 442        { "RTL-8130",
 443          0x7C,
 444          0xf0fe0040, /* XXX copied from RTL8139A, verify */
 445        },
 446
 447        { "RTL-8139C",
 448          0x74,
 449          0xf0fc0040, /* XXX copied from RTL8139B, verify */
 450        },
 451
 452};
 453
 454
 455struct netdrv_private {
 456        board_t board;
 457        void *mmio_addr;
 458        int drv_flags;
 459        struct pci_dev *pci_dev;
 460        struct timer_list timer;        /* Media selection timer. */
 461        unsigned char *rx_ring;
 462        unsigned int cur_rx;    /* Index into the Rx buffer of next Rx pkt. */
 463        unsigned int tx_flag;
 464        atomic_t cur_tx;
 465        atomic_t dirty_tx;
 466        /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 467        struct ring_info tx_info[NUM_TX_DESC];
 468        unsigned char *tx_buf[NUM_TX_DESC];     /* Tx bounce buffers */
 469        unsigned char *tx_bufs; /* Tx bounce buffer region. */
 470        dma_addr_t rx_ring_dma;
 471        dma_addr_t tx_bufs_dma;
 472        char phys[4];           /* MII device addresses. */
 473        char twistie, twist_row, twist_col;     /* Twister tune state. */
 474        unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 475        unsigned int duplex_lock:1;
 476        unsigned int default_port:4;    /* Last dev->if_port value. */
 477        unsigned int media2:4;  /* Secondary monitored media port. */
 478        unsigned int medialock:1;       /* Don't sense media type. */
 479        unsigned int mediasense:1;      /* Media sensing in progress. */
 480        spinlock_t lock;
 481        chip_t chipset;
 482};
 483
 484MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
 485MODULE_DESCRIPTION ("Skeleton for a PCI Fast Ethernet driver");
 486MODULE_LICENSE("GPL");
 487module_param(multicast_filter_limit, int, 0);
 488module_param(max_interrupt_work, int, 0);
 489module_param_array(media, int, NULL, 0);
 490MODULE_PARM_DESC (multicast_filter_limit, "pci-skeleton maximum number of filtered multicast addresses");
 491MODULE_PARM_DESC (max_interrupt_work, "pci-skeleton maximum events handled per interrupt");
 492MODULE_PARM_DESC (media, "pci-skeleton: Bits 0-3: media type, bit 17: full duplex");
 493
 494static int read_eeprom (void *ioaddr, int location, int addr_len);
 495static int netdrv_open (struct net_device *dev);
 496static int mdio_read (struct net_device *dev, int phy_id, int location);
 497static void mdio_write (struct net_device *dev, int phy_id, int location,
 498                        int val);
 499static void netdrv_timer (unsigned long data);
 500static void netdrv_tx_timeout (struct net_device *dev);
 501static void netdrv_init_ring (struct net_device *dev);
 502static int netdrv_start_xmit (struct sk_buff *skb,
 503                               struct net_device *dev);
 504static irqreturn_t netdrv_interrupt (int irq, void *dev_instance);
 505static int netdrv_close (struct net_device *dev);
 506static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
 507static void netdrv_set_rx_mode (struct net_device *dev);
 508static void netdrv_hw_start (struct net_device *dev);
 509
 510
 511#ifdef USE_IO_OPS
 512
 513#define NETDRV_R8(reg)          inb (((unsigned long)ioaddr) + (reg))
 514#define NETDRV_R16(reg)         inw (((unsigned long)ioaddr) + (reg))
 515#define NETDRV_R32(reg)         ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
 516#define NETDRV_W8(reg, val8)    outb ((val8), ((unsigned long)ioaddr) + (reg))
 517#define NETDRV_W16(reg, val16)  outw ((val16), ((unsigned long)ioaddr) + (reg))
 518#define NETDRV_W32(reg, val32)  outl ((val32), ((unsigned long)ioaddr) + (reg))
 519#define NETDRV_W8_F             NETDRV_W8
 520#define NETDRV_W16_F            NETDRV_W16
 521#define NETDRV_W32_F            NETDRV_W32
 522#undef readb
 523#undef readw
 524#undef readl
 525#undef writeb
 526#undef writew
 527#undef writel
 528#define readb(addr) inb((unsigned long)(addr))
 529#define readw(addr) inw((unsigned long)(addr))
 530#define readl(addr) inl((unsigned long)(addr))
 531#define writeb(val,addr) outb((val),(unsigned long)(addr))
 532#define writew(val,addr) outw((val),(unsigned long)(addr))
 533#define writel(val,addr) outl((val),(unsigned long)(addr))
 534
 535#else
 536
 537/* write MMIO register, with flush */
 538/* Flush avoids rtl8139 bug w/ posted MMIO writes */
 539#define NETDRV_W8_F(reg, val8)  do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
 540#define NETDRV_W16_F(reg, val16)        do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
 541#define NETDRV_W32_F(reg, val32)        do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
 542
 543
 544#ifdef MMIO_FLUSH_AUDIT_COMPLETE
 545
 546/* write MMIO register */
 547#define NETDRV_W8(reg, val8)    writeb ((val8), ioaddr + (reg))
 548#define NETDRV_W16(reg, val16)  writew ((val16), ioaddr + (reg))
 549#define NETDRV_W32(reg, val32)  writel ((val32), ioaddr + (reg))
 550
 551#else
 552
 553/* write MMIO register, then flush */
 554#define NETDRV_W8               NETDRV_W8_F
 555#define NETDRV_W16              NETDRV_W16_F
 556#define NETDRV_W32              NETDRV_W32_F
 557
 558#endif /* MMIO_FLUSH_AUDIT_COMPLETE */
 559
 560/* read MMIO register */
 561#define NETDRV_R8(reg)          readb (ioaddr + (reg))
 562#define NETDRV_R16(reg)         readw (ioaddr + (reg))
 563#define NETDRV_R32(reg)         ((unsigned long) readl (ioaddr + (reg)))
 564
 565#endif /* USE_IO_OPS */
 566
 567
 568static const u16 netdrv_intr_mask =
 569        PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
 570        TxErr | TxOK | RxErr | RxOK;
 571
 572static const unsigned int netdrv_rx_config =
 573          RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
 574          (RX_FIFO_THRESH << RxCfgFIFOShift) |
 575          (RX_DMA_BURST << RxCfgDMAShift);
 576
 577
 578static int __devinit netdrv_init_board (struct pci_dev *pdev,
 579                                         struct net_device **dev_out,
 580                                         void **ioaddr_out)
 581{
 582        void *ioaddr = NULL;
 583        struct net_device *dev;
 584        struct netdrv_private *tp;
 585        int rc, i;
 586        u32 pio_start, pio_end, pio_flags, pio_len;
 587        unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
 588        u32 tmp;
 589
 590        DPRINTK ("ENTER\n");
 591
 592        assert (pdev != NULL);
 593        assert (ioaddr_out != NULL);
 594
 595        *ioaddr_out = NULL;
 596        *dev_out = NULL;
 597
 598        /* dev zeroed in alloc_etherdev */
 599        dev = alloc_etherdev (sizeof (*tp));
 600        if (dev == NULL) {
 601                dev_err(&pdev->dev, "unable to alloc new ethernet\n");
 602                DPRINTK ("EXIT, returning -ENOMEM\n");
 603                return -ENOMEM;
 604        }
 605        SET_NETDEV_DEV(dev, &pdev->dev);
 606        tp = netdev_priv(dev);
 607
 608        /* enable device (incl. PCI PM wakeup), and bus-mastering */
 609        rc = pci_enable_device (pdev);
 610        if (rc)
 611                goto err_out;
 612
 613        pio_start = pci_resource_start (pdev, 0);
 614        pio_end = pci_resource_end (pdev, 0);
 615        pio_flags = pci_resource_flags (pdev, 0);
 616        pio_len = pci_resource_len (pdev, 0);
 617
 618        mmio_start = pci_resource_start (pdev, 1);
 619        mmio_end = pci_resource_end (pdev, 1);
 620        mmio_flags = pci_resource_flags (pdev, 1);
 621        mmio_len = pci_resource_len (pdev, 1);
 622
 623        /* set this immediately, we need to know before
 624         * we talk to the chip directly */
 625        DPRINTK("PIO region size == 0x%02X\n", pio_len);
 626        DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
 627
 628        /* make sure PCI base addr 0 is PIO */
 629        if (!(pio_flags & IORESOURCE_IO)) {
 630                dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
 631                rc = -ENODEV;
 632                goto err_out;
 633        }
 634
 635        /* make sure PCI base addr 1 is MMIO */
 636        if (!(mmio_flags & IORESOURCE_MEM)) {
 637                dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
 638                rc = -ENODEV;
 639                goto err_out;
 640        }
 641
 642        /* check for weird/broken PCI region reporting */
 643        if ((pio_len < NETDRV_MIN_IO_SIZE) ||
 644            (mmio_len < NETDRV_MIN_IO_SIZE)) {
 645                dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
 646                rc = -ENODEV;
 647                goto err_out;
 648        }
 649
 650        rc = pci_request_regions (pdev, MODNAME);
 651        if (rc)
 652                goto err_out;
 653
 654        pci_set_master (pdev);
 655
 656#ifdef USE_IO_OPS
 657        ioaddr = (void *) pio_start;
 658#else
 659        /* ioremap MMIO region */
 660        ioaddr = ioremap (mmio_start, mmio_len);
 661        if (ioaddr == NULL) {
 662                dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
 663                rc = -EIO;
 664                goto err_out_free_res;
 665        }
 666#endif /* USE_IO_OPS */
 667
 668        /* Soft reset the chip. */
 669        NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
 670
 671        /* Check that the chip has finished the reset. */
 672        for (i = 1000; i > 0; i--)
 673                if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
 674                        break;
 675                else
 676                        udelay (10);
 677
 678        /* Bring the chip out of low-power mode. */
 679        /* <insert device-specific code here> */
 680
 681#ifndef USE_IO_OPS
 682        /* sanity checks -- ensure PIO and MMIO registers agree */
 683        assert (inb (pio_start+Config0) == readb (ioaddr+Config0));
 684        assert (inb (pio_start+Config1) == readb (ioaddr+Config1));
 685        assert (inb (pio_start+TxConfig) == readb (ioaddr+TxConfig));
 686        assert (inb (pio_start+RxConfig) == readb (ioaddr+RxConfig));
 687#endif /* !USE_IO_OPS */
 688
 689        /* identify chip attached to board */
 690        tmp = NETDRV_R8 (ChipVersion);
 691        for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--)
 692                if (tmp == rtl_chip_info[i].version) {
 693                        tp->chipset = i;
 694                        goto match;
 695                }
 696
 697        /* if unknown chip, assume array element #0, original RTL-8139 in this case */
 698        dev_printk (KERN_DEBUG, &pdev->dev,
 699                "unknown chip version, assuming RTL-8139\n");
 700        dev_printk (KERN_DEBUG, &pdev->dev, "TxConfig = 0x%lx\n",
 701                NETDRV_R32 (TxConfig));
 702        tp->chipset = 0;
 703
 704match:
 705        DPRINTK ("chipset id (%d) == index %d, '%s'\n",
 706                tmp,
 707                tp->chipset,
 708                rtl_chip_info[tp->chipset].name);
 709
 710        rc = register_netdev (dev);
 711        if (rc)
 712                goto err_out_unmap;
 713
 714        DPRINTK ("EXIT, returning 0\n");
 715        *ioaddr_out = ioaddr;
 716        *dev_out = dev;
 717        return 0;
 718
 719err_out_unmap:
 720#ifndef USE_IO_OPS
 721        iounmap(ioaddr);
 722err_out_free_res:
 723#endif
 724        pci_release_regions (pdev);
 725err_out:
 726        free_netdev (dev);
 727        DPRINTK ("EXIT, returning %d\n", rc);
 728        return rc;
 729}
 730
 731static const struct net_device_ops netdrv_netdev_ops = {
 732        .ndo_open               = netdrv_open,
 733        .ndo_stop               = netdrv_close,
 734        .ndo_start_xmit         = netdrv_start_xmit,
 735        .ndo_set_multicast_list = netdrv_set_rx_mode,
 736        .ndo_do_ioctl           = netdrv_ioctl,
 737        .ndo_tx_timeout         = netdrv_tx_timeout,
 738        .ndo_change_mtu         = eth_change_mtu,
 739        .ndo_validate_addr      = eth_validate_addr,
 740        .ndo_set_mac_address    = eth_mac_addr,
 741};
 742
 743static int __devinit netdrv_init_one (struct pci_dev *pdev,
 744                                       const struct pci_device_id *ent)
 745{
 746        struct net_device *dev = NULL;
 747        struct netdrv_private *tp;
 748        int i, addr_len, option;
 749        void *ioaddr = NULL;
 750        static int board_idx = -1;
 751
 752/* when built into the kernel, we only print version if device is found */
 753#ifndef MODULE
 754        static int printed_version;
 755        if (!printed_version++)
 756                printk(version);
 757#endif
 758
 759        DPRINTK ("ENTER\n");
 760
 761        assert (pdev != NULL);
 762        assert (ent != NULL);
 763
 764        board_idx++;
 765
 766        i = netdrv_init_board (pdev, &dev, &ioaddr);
 767        if (i < 0) {
 768                DPRINTK ("EXIT, returning %d\n", i);
 769                return i;
 770        }
 771
 772        tp = netdev_priv(dev);
 773
 774        assert (ioaddr != NULL);
 775        assert (dev != NULL);
 776        assert (tp != NULL);
 777
 778        addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
 779        for (i = 0; i < 3; i++)
 780                ((u16 *) (dev->dev_addr))[i] =
 781                    le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
 782
 783        dev->netdev_ops = &netdrv_netdev_ops;
 784        dev->watchdog_timeo = TX_TIMEOUT;
 785
 786        dev->irq = pdev->irq;
 787        dev->base_addr = (unsigned long) ioaddr;
 788
 789        /* netdev_priv()/tp zeroed and aligned in alloc_etherdev */
 790        tp = netdev_priv(dev);
 791
 792        /* note: tp->chipset set in netdrv_init_board */
 793        tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 794                        PCI_COMMAND_MASTER | NETDRV_CAPS;
 795        tp->pci_dev = pdev;
 796        tp->board = ent->driver_data;
 797        tp->mmio_addr = ioaddr;
 798        spin_lock_init(&tp->lock);
 799
 800        pci_set_drvdata(pdev, dev);
 801
 802        tp->phys[0] = 32;
 803
 804        printk (KERN_INFO "%s: %s at 0x%lx, %pM IRQ %d\n",
 805                dev->name,
 806                board_info[ent->driver_data].name,
 807                dev->base_addr,
 808                dev->dev_addr,
 809                dev->irq);
 810
 811        printk (KERN_DEBUG "%s:  Identified 8139 chip type '%s'\n",
 812                dev->name, rtl_chip_info[tp->chipset].name);
 813
 814        /* Put the chip into low-power mode. */
 815        NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
 816
 817        /* The lower four bits are the media type. */
 818        option = (board_idx > 7) ? 0 : media[board_idx];
 819        if (option > 0) {
 820                tp->full_duplex = (option & 0x200) ? 1 : 0;
 821                tp->default_port = option & 15;
 822                if (tp->default_port)
 823                        tp->medialock = 1;
 824        }
 825
 826        if (tp->full_duplex) {
 827                printk (KERN_INFO
 828                        "%s: Media type forced to Full Duplex.\n",
 829                        dev->name);
 830                mdio_write (dev, tp->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
 831                tp->duplex_lock = 1;
 832        }
 833
 834        DPRINTK ("EXIT - returning 0\n");
 835        return 0;
 836}
 837
 838
 839static void __devexit netdrv_remove_one (struct pci_dev *pdev)
 840{
 841        struct net_device *dev = pci_get_drvdata (pdev);
 842        struct netdrv_private *np;
 843
 844        DPRINTK ("ENTER\n");
 845
 846        assert (dev != NULL);
 847
 848        np = netdev_priv(dev);
 849        assert (np != NULL);
 850
 851        unregister_netdev (dev);
 852
 853#ifndef USE_IO_OPS
 854        iounmap (np->mmio_addr);
 855#endif /* !USE_IO_OPS */
 856
 857        pci_release_regions (pdev);
 858
 859        free_netdev (dev);
 860
 861        pci_set_drvdata (pdev, NULL);
 862
 863        pci_disable_device (pdev);
 864
 865        DPRINTK ("EXIT\n");
 866}
 867
 868
 869/* Serial EEPROM section. */
 870
 871/*  EEPROM_Ctrl bits. */
 872#define EE_SHIFT_CLK    0x04    /* EEPROM shift clock. */
 873#define EE_CS                   0x08    /* EEPROM chip select. */
 874#define EE_DATA_WRITE   0x02    /* EEPROM chip data in. */
 875#define EE_WRITE_0              0x00
 876#define EE_WRITE_1              0x02
 877#define EE_DATA_READ    0x01    /* EEPROM chip data out. */
 878#define EE_ENB                  (0x80 | EE_CS)
 879
 880/* Delay between EEPROM clock transitions.
 881   No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
 882 */
 883
 884#define eeprom_delay()  readl(ee_addr)
 885
 886/* The EEPROM commands include the alway-set leading bit. */
 887#define EE_WRITE_CMD    (5)
 888#define EE_READ_CMD             (6)
 889#define EE_ERASE_CMD    (7)
 890
 891static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
 892{
 893        int i;
 894        unsigned retval = 0;
 895        void *ee_addr = ioaddr + Cfg9346;
 896        int read_cmd = location | (EE_READ_CMD << addr_len);
 897
 898        DPRINTK ("ENTER\n");
 899
 900        writeb (EE_ENB & ~EE_CS, ee_addr);
 901        writeb (EE_ENB, ee_addr);
 902        eeprom_delay ();
 903
 904        /* Shift the read command bits out. */
 905        for (i = 4 + addr_len; i >= 0; i--) {
 906                int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 907                writeb (EE_ENB | dataval, ee_addr);
 908                eeprom_delay ();
 909                writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
 910                eeprom_delay ();
 911        }
 912        writeb (EE_ENB, ee_addr);
 913        eeprom_delay ();
 914
 915        for (i = 16; i > 0; i--) {
 916                writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
 917                eeprom_delay ();
 918                retval =
 919                    (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
 920                                     0);
 921                writeb (EE_ENB, ee_addr);
 922                eeprom_delay ();
 923        }
 924
 925        /* Terminate the EEPROM access. */
 926        writeb (~EE_CS, ee_addr);
 927        eeprom_delay ();
 928
 929        DPRINTK ("EXIT - returning %d\n", retval);
 930        return retval;
 931}
 932
 933/* MII serial management: mostly bogus for now. */
 934/* Read and write the MII management registers using software-generated
 935   serial MDIO protocol.
 936   The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
 937   met by back-to-back PCI I/O cycles, but we insert a delay to avoid
 938   "overclocking" issues. */
 939#define MDIO_DIR                0x80
 940#define MDIO_DATA_OUT   0x04
 941#define MDIO_DATA_IN    0x02
 942#define MDIO_CLK                0x01
 943#define MDIO_WRITE0 (MDIO_DIR)
 944#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
 945
 946#define mdio_delay()    readb(mdio_addr)
 947
 948
 949static char mii_2_8139_map[8] = {
 950        BasicModeCtrl,
 951        BasicModeStatus,
 952        0,
 953        0,
 954        NWayAdvert,
 955        NWayLPAR,
 956        NWayExpansion,
 957        0
 958};
 959
 960
 961/* Syncronize the MII management interface by shifting 32 one bits out. */
 962static void mdio_sync (void *mdio_addr)
 963{
 964        int i;
 965
 966        DPRINTK ("ENTER\n");
 967
 968        for (i = 32; i >= 0; i--) {
 969                writeb (MDIO_WRITE1, mdio_addr);
 970                mdio_delay ();
 971                writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
 972                mdio_delay ();
 973        }
 974
 975        DPRINTK ("EXIT\n");
 976}
 977
 978
 979static int mdio_read (struct net_device *dev, int phy_id, int location)
 980{
 981        struct netdrv_private *tp = netdev_priv(dev);
 982        void *mdio_addr = tp->mmio_addr + Config4;
 983        int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
 984        int retval = 0;
 985        int i;
 986
 987        DPRINTK ("ENTER\n");
 988
 989        if (phy_id > 31) {      /* Really a 8139.  Use internal registers. */
 990                DPRINTK ("EXIT after directly using 8139 internal regs\n");
 991                return location < 8 && mii_2_8139_map[location] ?
 992                    readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
 993        }
 994        mdio_sync (mdio_addr);
 995        /* Shift the read command bits out. */
 996        for (i = 15; i >= 0; i--) {
 997                int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
 998
 999                writeb (MDIO_DIR | dataval, mdio_addr);
1000                mdio_delay ();

1001                writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1002                mdio_delay ();
1003        }
1004
1005        /* Read the two transition, 16 data, and wire-idle bits. */
1006        for (i = 19; i > 0; i--) {
1007                writeb (0, mdio_addr);
1008                mdio_delay ();
1009                retval =
1010                    (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1
1011                                     : 0);
1012                writeb (MDIO_CLK, mdio_addr);
1013                mdio_delay ();
1014        }
1015
1016        DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1017        return (retval >> 1) & 0xffff;
1018}
1019
1020
1021static void mdio_write (struct net_device *dev, int phy_id, int location,
1022                        int value)
1023{
1024        struct netdrv_private *tp = netdev_priv(dev);
1025        void *mdio_addr = tp->mmio_addr + Config4;
1026        int mii_cmd =
1027            (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1028        int i;
1029
1030        DPRINTK ("ENTER\n");
1031
1032        if (phy_id > 31) {      /* Really a 8139.  Use internal registers. */
1033                if (location < 8 && mii_2_8139_map[location]) {
1034                        writew (value,
1035                                tp->mmio_addr + mii_2_8139_map[location]);
1036                        readw (tp->mmio_addr + mii_2_8139_map[location]);
1037                }
1038                DPRINTK ("EXIT after directly using 8139 internal regs\n");
1039                return;
1040        }
1041        mdio_sync (mdio_addr);
1042
1043        /* Shift the command bits out. */
1044        for (i = 31; i >= 0; i--) {
1045                int dataval =
1046                    (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1047                writeb (dataval, mdio_addr);
1048                mdio_delay ();
1049                writeb (dataval | MDIO_CLK, mdio_addr);
1050                mdio_delay ();
1051        }
1052
1053        /* Clear out extra bits. */
1054        for (i = 2; i > 0; i--) {
1055                writeb (0, mdio_addr);
1056                mdio_delay ();
1057                writeb (MDIO_CLK, mdio_addr);
1058                mdio_delay ();
1059        }
1060
1061        DPRINTK ("EXIT\n");
1062}
1063
1064
1065static int netdrv_open (struct net_device *dev)
1066{
1067        struct netdrv_private *tp = netdev_priv(dev);
1068        int retval;
1069#ifdef NETDRV_DEBUG
1070        void *ioaddr = tp->mmio_addr;
1071#endif
1072
1073        DPRINTK ("ENTER\n");
1074
1075        retval = request_irq (dev->irq, netdrv_interrupt, IRQF_SHARED, dev->name, dev);
1076        if (retval) {
1077                DPRINTK ("EXIT, returning %d\n", retval);
1078                return retval;
1079        }
1080
1081        tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1082                                           &tp->tx_bufs_dma);
1083        tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1084                                           &tp->rx_ring_dma);
1085        if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1086                free_irq(dev->irq, dev);
1087
1088                if (tp->tx_bufs)
1089                        pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1090                                            tp->tx_bufs, tp->tx_bufs_dma);
1091                if (tp->rx_ring)
1092                        pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1093                                            tp->rx_ring, tp->rx_ring_dma);
1094
1095                DPRINTK ("EXIT, returning -ENOMEM\n");
1096                return -ENOMEM;
1097
1098        }
1099
1100        tp->full_duplex = tp->duplex_lock;
1101        tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1102
1103        netdrv_init_ring (dev);
1104        netdrv_hw_start (dev);
1105
1106        DPRINTK ("%s: netdrv_open() ioaddr %#lx IRQ %d"
1107                        " GP Pins %2.2x %s-duplex.\n",
1108                        dev->name, pci_resource_start (tp->pci_dev, 1),
1109                        dev->irq, NETDRV_R8 (MediaStatus),
1110                        tp->full_duplex ? "full" : "half");
1111
1112        /* Set the timer to switch to check for link beat and perhaps switch
1113           to an alternate media type. */
1114        init_timer (&tp->timer);
1115        tp->timer.expires = jiffies + 3 * HZ;
1116        tp->timer.data = (unsigned long) dev;
1117        tp->timer.function = &netdrv_timer;
1118        add_timer (&tp->timer);
1119
1120        DPRINTK ("EXIT, returning 0\n");
1121        return 0;
1122}
1123
1124
1125/* Start the hardware at open or resume. */
1126static void netdrv_hw_start (struct net_device *dev)
1127{
1128        struct netdrv_private *tp = netdev_priv(dev);
1129        void *ioaddr = tp->mmio_addr;
1130        u32 i;
1131
1132        DPRINTK ("ENTER\n");
1133
1134        /* Soft reset the chip. */
1135        NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
1136        udelay (100);
1137
1138        /* Check that the chip has finished the reset. */
1139        for (i = 1000; i > 0; i--)
1140                if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
1141                        break;
1142
1143        /* Restore our idea of the MAC address. */
1144        NETDRV_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1145        NETDRV_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1146
1147        /* Must enable Tx/Rx before setting transfer thresholds! */
1148        NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1149                           CmdRxEnb | CmdTxEnb);
1150
1151        i = netdrv_rx_config |
1152            (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1153        NETDRV_W32_F (RxConfig, i);
1154
1155        /* Check this value: the documentation for IFG contradicts ifself. */
1156        NETDRV_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1157
1158        /* unlock Config[01234] and BMCR register writes */
1159        NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
1160        udelay (10);
1161
1162        tp->cur_rx = 0;
1163
1164        /* Lock Config[01234] and BMCR register writes */
1165        NETDRV_W8_F (Cfg9346, Cfg9346_Lock);
1166        udelay (10);
1167
1168        /* init Rx ring buffer DMA address */
1169        NETDRV_W32_F (RxBuf, tp->rx_ring_dma);
1170
1171        /* init Tx buffer DMA addresses */
1172        for (i = 0; i < NUM_TX_DESC; i++)
1173                NETDRV_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1174
1175        NETDRV_W32_F (RxMissed, 0);
1176
1177        netdrv_set_rx_mode (dev);
1178
1179        /* no early-rx interrupts */
1180        NETDRV_W16 (MultiIntr, NETDRV_R16 (MultiIntr) & MultiIntrClear);
1181
1182        /* make sure RxTx has started */
1183        NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1184                           CmdRxEnb | CmdTxEnb);
1185
1186        /* Enable all known interrupts by setting the interrupt mask. */
1187        NETDRV_W16_F (IntrMask, netdrv_intr_mask);
1188
1189        netif_start_queue (dev);
1190
1191        DPRINTK ("EXIT\n");
1192}
1193
1194
1195/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1196static void netdrv_init_ring (struct net_device *dev)
1197{
1198        struct netdrv_private *tp = netdev_priv(dev);
1199        int i;
1200
1201        DPRINTK ("ENTER\n");
1202
1203        tp->cur_rx = 0;
1204        atomic_set (&tp->cur_tx, 0);
1205        atomic_set (&tp->dirty_tx, 0);
1206
1207        for (i = 0; i < NUM_TX_DESC; i++) {
1208                tp->tx_info[i].skb = NULL;
1209                tp->tx_info[i].mapping = 0;
1210                tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1211        }
1212
1213        DPRINTK ("EXIT\n");
1214}
1215
1216
1217static void netdrv_timer (unsigned long data)
1218{
1219        struct net_device *dev = (struct net_device *) data;
1220        struct netdrv_private *tp = netdev_priv(dev);
1221        void *ioaddr = tp->mmio_addr;
1222        int next_tick = 60 * HZ;
1223        int mii_lpa;
1224
1225        mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1226
1227        if (!tp->duplex_lock && mii_lpa != 0xffff) {
1228                int duplex = (mii_lpa & LPA_100FULL)
1229                    || (mii_lpa & 0x01C0) == 0x0040;
1230                if (tp->full_duplex != duplex) {
1231                        tp->full_duplex = duplex;
1232                        printk (KERN_INFO
1233                                "%s: Setting %s-duplex based on MII #%d link"
1234                                " partner ability of %4.4x.\n", dev->name,
1235                                tp->full_duplex ? "full" : "half",
1236                                tp->phys[0], mii_lpa);
1237                        NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1238                        NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1239                        NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1240                }
1241        }
1242
1243        DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1244                 dev->name, NETDRV_R16 (NWayLPAR));
1245        DPRINTK ("%s:  Other registers are IntMask %4.4x IntStatus %4.4x"
1246                 " RxStatus %4.4x.\n", dev->name,
1247                 NETDRV_R16 (IntrMask),
1248                 NETDRV_R16 (IntrStatus),
1249                 NETDRV_R32 (RxEarlyStatus));
1250        DPRINTK ("%s:  Chip config %2.2x %2.2x.\n",
1251                 dev->name, NETDRV_R8 (Config0),
1252                 NETDRV_R8 (Config1));
1253
1254        tp->timer.expires = jiffies + next_tick;
1255        add_timer (&tp->timer);
1256}
1257
1258
1259static void netdrv_tx_clear (struct net_device *dev)
1260{
1261        int i;
1262        struct netdrv_private *tp = netdev_priv(dev);
1263
1264        atomic_set (&tp->cur_tx, 0);
1265        atomic_set (&tp->dirty_tx, 0);
1266
1267        /* Dump the unsent Tx packets. */
1268        for (i = 0; i < NUM_TX_DESC; i++) {
1269                struct ring_info *rp = &tp->tx_info[i];
1270                if (rp->mapping != 0) {
1271                        pci_unmap_single (tp->pci_dev, rp->mapping,
1272                                          rp->skb->len, PCI_DMA_TODEVICE);
1273                        rp->mapping = 0;
1274                }
1275                if (rp->skb) {
1276                        dev_kfree_skb (rp->skb);
1277                        rp->skb = NULL;
1278                        dev->stats.tx_dropped++;
1279                }
1280        }
1281}
1282
1283
1284static void netdrv_tx_timeout (struct net_device *dev)
1285{
1286        struct netdrv_private *tp = netdev_priv(dev);
1287        void *ioaddr = tp->mmio_addr;
1288        int i;
1289        u8 tmp8;
1290        unsigned long flags;
1291
1292        DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1293                 "media %2.2x.\n", dev->name,
1294                 NETDRV_R8 (ChipCmd),
1295                 NETDRV_R16 (IntrStatus),
1296                 NETDRV_R8 (MediaStatus));
1297
1298        /* disable Tx ASAP, if not already */
1299        tmp8 = NETDRV_R8 (ChipCmd);
1300        if (tmp8 & CmdTxEnb)
1301                NETDRV_W8 (ChipCmd, tmp8 & ~CmdTxEnb);
1302
1303        /* Disable interrupts by clearing the interrupt mask. */
1304        NETDRV_W16 (IntrMask, 0x0000);
1305
1306        /* Emit info to figure out what went wrong. */
1307        printk (KERN_DEBUG "%s: Tx queue start entry %d  dirty entry %d.\n",
1308                dev->name, atomic_read (&tp->cur_tx),
1309                atomic_read (&tp->dirty_tx));
1310        for (i = 0; i < NUM_TX_DESC; i++)
1311                printk (KERN_DEBUG "%s:  Tx descriptor %d is %8.8lx.%s\n",
1312                        dev->name, i, NETDRV_R32 (TxStatus0 + (i * 4)),
1313                        i == atomic_read (&tp->dirty_tx) % NUM_TX_DESC ?
1314                                " (queue head)" : "");
1315
1316        /* Stop a shared interrupt from scavenging while we are. */
1317        spin_lock_irqsave (&tp->lock, flags);
1318
1319        netdrv_tx_clear (dev);
1320
1321        spin_unlock_irqrestore (&tp->lock, flags);
1322
1323        /* ...and finally, reset everything */
1324        netdrv_hw_start (dev);
1325
1326        netif_wake_queue (dev);
1327}
1328
1329
1330
1331static int netdrv_start_xmit (struct sk_buff *skb, struct net_device *dev)
1332{
1333        struct netdrv_private *tp = netdev_priv(dev);
1334        void *ioaddr = tp->mmio_addr;
1335        int entry;
1336
1337        /* Calculate the next Tx descriptor entry. */
1338        entry = atomic_read (&tp->cur_tx) % NUM_TX_DESC;
1339
1340        assert (tp->tx_info[entry].skb == NULL);
1341        assert (tp->tx_info[entry].mapping == 0);
1342
1343        tp->tx_info[entry].skb = skb;
1344        /* tp->tx_info[entry].mapping = 0; */
1345        skb_copy_from_linear_data(skb, tp->tx_buf[entry], skb->len);
1346
1347        /* Note: the chip doesn't have auto-pad! */
1348        NETDRV_W32 (TxStatus0 + (entry * sizeof(u32)),
1349                 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1350
1351        dev->trans_start = jiffies;
1352        atomic_inc (&tp->cur_tx);
1353        if ((atomic_read (&tp->cur_tx) - atomic_read (&tp->dirty_tx)) >= NUM_TX_DESC)
1354                netif_stop_queue (dev);
1355
1356        DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1357                 dev->name, skb->data, skb->len, entry);
1358
1359        return NETDEV_TX_OK;
1360}
1361
1362
1363static void netdrv_tx_interrupt (struct net_device *dev,
1364                                  struct netdrv_private *tp,
1365                                  void *ioaddr)
1366{
1367        int cur_tx, dirty_tx, tx_left;
1368
1369        assert (dev != NULL);
1370        assert (tp != NULL);
1371        assert (ioaddr != NULL);
1372
1373        dirty_tx = atomic_read (&tp->dirty_tx);
1374
1375        cur_tx = atomic_read (&tp->cur_tx);
1376        tx_left = cur_tx - dirty_tx;
1377        while (tx_left > 0) {
1378                int entry = dirty_tx % NUM_TX_DESC;
1379                int txstatus;
1380
1381                txstatus = NETDRV_R32 (TxStatus0 + (entry * sizeof (u32)));
1382
1383                if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1384                        break;  /* It still hasn't been Txed */
1385
1386                /* Note: TxCarrierLost is always asserted at 100mbps. */
1387                if (txstatus & (TxOutOfWindow | TxAborted)) {
1388                        /* There was an major error, log it. */
1389                        DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1390                                 dev->name, txstatus);
1391                        dev->stats.tx_errors++;
1392                        if (txstatus & TxAborted) {
1393                                dev->stats.tx_aborted_errors++;
1394                                NETDRV_W32 (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1395                        }
1396                        if (txstatus & TxCarrierLost)
1397                                dev->stats.tx_carrier_errors++;
1398                        if (txstatus & TxOutOfWindow)
1399                                dev->stats.tx_window_errors++;
1400                } else {
1401                        if (txstatus & TxUnderrun) {
1402                                /* Add 64 to the Tx FIFO threshold. */
1403                                if (tp->tx_flag < 0x00300000)
1404                                        tp->tx_flag += 0x00020000;
1405                                dev->stats.tx_fifo_errors++;
1406                        }
1407                        dev->stats.collisions += (txstatus >> 24) & 15;
1408                        dev->stats.tx_bytes += txstatus & 0x7ff;
1409                        dev->stats.tx_packets++;
1410                }
1411
1412                /* Free the original skb. */
1413                if (tp->tx_info[entry].mapping != 0) {
1414                        pci_unmap_single(tp->pci_dev,
1415                                         tp->tx_info[entry].mapping,
1416                                         tp->tx_info[entry].skb->len,
1417                                         PCI_DMA_TODEVICE);
1418                        tp->tx_info[entry].mapping = 0;
1419                }
1420                dev_kfree_skb_irq (tp->tx_info[entry].skb);
1421                tp->tx_info[entry].skb = NULL;
1422                dirty_tx++;
1423                if (dirty_tx < 0) { /* handle signed int overflow */
1424                        atomic_sub (cur_tx, &tp->cur_tx); /* XXX racy? */
1425                        dirty_tx = cur_tx - tx_left + 1;
1426                }
1427                if (netif_queue_stopped (dev))
1428                        netif_wake_queue (dev);
1429
1430                cur_tx = atomic_read (&tp->cur_tx);
1431                tx_left = cur_tx - dirty_tx;
1432
1433        }
1434
1435#ifndef NETDRV_NDEBUG
1436        if (atomic_read (&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1437                printk (KERN_ERR
1438                  "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
1439                     dev->name, dirty_tx, atomic_read (&tp->cur_tx));
1440                dirty_tx += NUM_TX_DESC;
1441        }
1442#endif /* NETDRV_NDEBUG */
1443
1444        atomic_set (&tp->dirty_tx, dirty_tx);
1445}
1446
1447
1448/* TODO: clean this up!  Rx reset need not be this intensive */
1449static void netdrv_rx_err (u32 rx_status, struct net_device *dev,
1450                            struct netdrv_private *tp, void *ioaddr)
1451{
1452        u8 tmp8;
1453        int tmp_work = 1000;
1454
1455        DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1456                 dev->name, rx_status);
1457        if (rx_status & RxTooLong) {
1458                DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1459                         dev->name, rx_status);
1460                /* A.C.: The chip hangs here. */
1461        }
1462        dev->stats.rx_errors++;
1463        if (rx_status & (RxBadSymbol | RxBadAlign))
1464                dev->stats.rx_frame_errors++;
1465        if (rx_status & (RxRunt | RxTooLong))
1466                dev->stats.rx_length_errors++;
1467        if (rx_status & RxCRCErr)
1468                dev->stats.rx_crc_errors++;
1469        /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1470        tp->cur_rx = 0;
1471
1472        /* disable receive */
1473        tmp8 = NETDRV_R8 (ChipCmd) & ChipCmdClear;
1474        NETDRV_W8_F (ChipCmd, tmp8 | CmdTxEnb);
1475
1476        /* A.C.: Reset the multicast list. */
1477        netdrv_set_rx_mode (dev);
1478
1479        /* XXX potentially temporary hack to
1480         * restart hung receiver */
1481        while (--tmp_work > 0) {
1482                tmp8 = NETDRV_R8 (ChipCmd);
1483                if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1484                        break;
1485                NETDRV_W8_F (ChipCmd,
1486                          (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1487        }
1488
1489        /* G.S.: Re-enable receiver */
1490        /* XXX temporary hack to work around receiver hang */
1491        netdrv_set_rx_mode (dev);
1492
1493        if (tmp_work <= 0)
1494                printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1495}
1496
1497
1498/* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1499   field alignments and semantics. */
1500static void netdrv_rx_interrupt (struct net_device *dev,
1501                                  struct netdrv_private *tp, void *ioaddr)
1502{
1503        unsigned char *rx_ring;
1504        u16 cur_rx;
1505
1506        assert (dev != NULL);
1507        assert (tp != NULL);
1508        assert (ioaddr != NULL);
1509
1510        rx_ring = tp->rx_ring;
1511        cur_rx = tp->cur_rx;
1512
1513        DPRINTK ("%s: In netdrv_rx(), current %4.4x BufAddr %4.4x,"
1514                 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1515                 NETDRV_R16 (RxBufAddr),
1516                 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1517
1518        while ((NETDRV_R8 (ChipCmd) & RxBufEmpty) == 0) {
1519                int ring_offset = cur_rx % RX_BUF_LEN;
1520                u32 rx_status;
1521                unsigned int rx_size;
1522                unsigned int pkt_size;
1523                struct sk_buff *skb;
1524
1525                /* read size+status of next frame from DMA ring buffer */
1526                rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1527                rx_size = rx_status >> 16;
1528                pkt_size = rx_size - 4;
1529
1530                DPRINTK ("%s:  netdrv_rx() status %4.4x, size %4.4x,"
1531                         " cur %4.4x.\n", dev->name, rx_status,
1532                         rx_size, cur_rx);
1533#if defined(NETDRV_DEBUG) && (NETDRV_DEBUG > 2)
1534                {
1535                        int i;
1536                        DPRINTK ("%s: Frame contents ", dev->name);
1537                        for (i = 0; i < 70; i++)
1538                                printk (" %2.2x",
1539                                        rx_ring[ring_offset + i]);
1540                        printk (".\n");
1541                }
1542#endif
1543
1544                /* If Rx err or invalid rx_size/rx_status received
1545                 * (which happens if we get lost in the ring),
1546                 * Rx process gets reset, so we abort any further
1547                 * Rx processing.
1548                 */
1549                if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1550                    (!(rx_status & RxStatusOK))) {
1551                        netdrv_rx_err (rx_status, dev, tp, ioaddr);
1552                        return;
1553                }
1554
1555                /* Malloc up new buffer, compatible with net-2e. */
1556                /* Omit the four octet CRC from the length. */
1557
1558                /* TODO: consider allocating skb's outside of
1559                 * interrupt context, both to speed interrupt processing,
1560                 * and also to reduce the chances of having to
1561                 * drop packets here under memory pressure.
1562                 */
1563
1564                skb = dev_alloc_skb (pkt_size + 2);
1565                if (skb) {
1566                        skb_reserve (skb, 2);   /* 16 byte align the IP fields. */
1567
1568                        skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
1569                        skb_put (skb, pkt_size);
1570
1571                        skb->protocol = eth_type_trans (skb, dev);
1572                        netif_rx (skb);
1573                        dev->stats.rx_bytes += pkt_size;
1574                        dev->stats.rx_packets++;
1575                } else {
1576                        printk (KERN_WARNING
1577                                "%s: Memory squeeze, dropping packet.\n",
1578                                dev->name);
1579                        dev->stats.rx_dropped++;
1580                }
1581
1582                cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1583                NETDRV_W16_F (RxBufPtr, cur_rx - 16);
1584        }
1585
1586        DPRINTK ("%s: Done netdrv_rx(), current %4.4x BufAddr %4.4x,"
1587                 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1588                 NETDRV_R16 (RxBufAddr),
1589                 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1590
1591        tp->cur_rx = cur_rx;
1592}
1593
1594
1595static void netdrv_weird_interrupt (struct net_device *dev,
1596                                     struct netdrv_private *tp,
1597                                     void *ioaddr,
1598                                     int status, int link_changed)
1599{
1600        printk (KERN_DEBUG "%s: Abnormal interrupt, status %8.8x.\n",
1601                dev->name, status);
1602
1603        assert (dev != NULL);
1604        assert (tp != NULL);
1605        assert (ioaddr != NULL);
1606
1607        /* Update the error count. */
1608        dev->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1609        NETDRV_W32 (RxMissed, 0);
1610
1611        if ((status & RxUnderrun) && link_changed &&
1612            (tp->drv_flags & HAS_LNK_CHNG)) {
1613                /* Really link-change on new chips. */
1614                int lpar = NETDRV_R16 (NWayLPAR);
1615                int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
1616                                || tp->duplex_lock;
1617                if (tp->full_duplex != duplex) {
1618                        tp->full_duplex = duplex;
1619                        NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1620                        NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1621                        NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1622                }
1623                status &= ~RxUnderrun;
1624        }
1625
1626        /* XXX along with netdrv_rx_err, are we double-counting errors? */
1627        if (status &
1628            (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1629                dev->stats.rx_errors++;
1630
1631        if (status & (PCSTimeout))
1632                dev->stats.rx_length_errors++;
1633        if (status & (RxUnderrun | RxFIFOOver))
1634                dev->stats.rx_fifo_errors++;
1635        if (status & RxOverflow) {
1636                dev->stats.rx_over_errors++;
1637                tp->cur_rx = NETDRV_R16 (RxBufAddr) % RX_BUF_LEN;
1638                NETDRV_W16_F (RxBufPtr, tp->cur_rx - 16);
1639        }
1640        if (status & PCIErr) {
1641                u16 pci_cmd_status;
1642                pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1643
1644                printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
1645                        dev->name, pci_cmd_status);
1646        }
1647}
1648
1649
1650/* The interrupt handler does all of the Rx thread work and cleans up
1651   after the Tx thread. */
1652static irqreturn_t netdrv_interrupt (int irq, void *dev_instance)
1653{
1654        struct net_device *dev = (struct net_device *) dev_instance;
1655        struct netdrv_private *tp = netdev_priv(dev);
1656        int boguscnt = max_interrupt_work;
1657        void *ioaddr = tp->mmio_addr;
1658        int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1659        int handled = 0;
1660
1661        spin_lock (&tp->lock);
1662
1663        do {
1664                status = NETDRV_R16 (IntrStatus);
1665
1666                /* h/w no longer present (hotplug?) or major error, bail */
1667                if (status == 0xFFFF)
1668                        break;
1669
1670                handled = 1;
1671                /* Acknowledge all of the current interrupt sources ASAP */
1672                NETDRV_W16_F (IntrStatus, status);
1673
1674                DPRINTK ("%s: interrupt  status=%#4.4x new intstat=%#4.4x.\n",
1675                                dev->name, status,
1676                                NETDRV_R16 (IntrStatus));
1677
1678                if ((status &
1679                     (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1680                      RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1681                        break;
1682
1683                /* Check uncommon events with one test. */
1684                if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1685                              RxFIFOOver | TxErr | RxErr))
1686                        netdrv_weird_interrupt (dev, tp, ioaddr,
1687                                                 status, link_changed);
1688
1689                if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver))     /* Rx interrupt */
1690                        netdrv_rx_interrupt (dev, tp, ioaddr);
1691
1692                if (status & (TxOK | TxErr))
1693                        netdrv_tx_interrupt (dev, tp, ioaddr);
1694
1695                boguscnt--;
1696        } while (boguscnt > 0);
1697
1698        if (boguscnt <= 0) {
1699                printk (KERN_WARNING
1700                        "%s: Too much work at interrupt, "
1701                        "IntrStatus=0x%4.4x.\n", dev->name,
1702                        status);
1703
1704                /* Clear all interrupt sources. */
1705                NETDRV_W16 (IntrStatus, 0xffff);
1706        }
1707
1708        spin_unlock (&tp->lock);
1709
1710        DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
1711                 dev->name, NETDRV_R16 (IntrStatus));
1712        return IRQ_RETVAL(handled);
1713}
1714
1715
1716static int netdrv_close (struct net_device *dev)
1717{
1718        struct netdrv_private *tp = netdev_priv(dev);
1719        void *ioaddr = tp->mmio_addr;
1720        unsigned long flags;
1721
1722        DPRINTK ("ENTER\n");
1723
1724        netif_stop_queue (dev);
1725
1726        DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
1727                        dev->name, NETDRV_R16 (IntrStatus));
1728
1729        del_timer_sync (&tp->timer);
1730
1731        spin_lock_irqsave (&tp->lock, flags);
1732
1733        /* Stop the chip's Tx and Rx DMA processes. */
1734        NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1735
1736        /* Disable interrupts by clearing the interrupt mask. */
1737        NETDRV_W16 (IntrMask, 0x0000);
1738
1739        /* Update the error counts. */
1740        dev->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1741        NETDRV_W32 (RxMissed, 0);
1742
1743        spin_unlock_irqrestore (&tp->lock, flags);
1744
1745        free_irq (dev->irq, dev);
1746
1747        netdrv_tx_clear (dev);
1748
1749        pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1750                            tp->rx_ring, tp->rx_ring_dma);
1751        pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1752                            tp->tx_bufs, tp->tx_bufs_dma);
1753        tp->rx_ring = NULL;
1754        tp->tx_bufs = NULL;
1755
1756        /* Green! Put the chip in low-power mode. */
1757        NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1758        NETDRV_W8 (Config1, 0x03);
1759        NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1760
1761        DPRINTK ("EXIT\n");
1762        return 0;
1763}
1764
1765
1766static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1767{
1768        struct netdrv_private *tp = netdev_priv(dev);
1769        struct mii_ioctl_data *data = if_mii(rq);
1770        unsigned long flags;
1771        int rc = 0;
1772
1773        DPRINTK ("ENTER\n");
1774
1775        switch (cmd) {
1776        case SIOCGMIIPHY:               /* Get address of MII PHY in use. */
1777                data->phy_id = tp->phys[0] & 0x3f;
1778                /* Fall Through */
1779
1780        case SIOCGMIIREG:               /* Read MII PHY register. */
1781                spin_lock_irqsave (&tp->lock, flags);
1782                data->val_out = mdio_read (dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1783                spin_unlock_irqrestore (&tp->lock, flags);
1784                break;
1785
1786        case SIOCSMIIREG:               /* Write MII PHY register. */
1787                spin_lock_irqsave (&tp->lock, flags);
1788                mdio_write (dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1789                spin_unlock_irqrestore (&tp->lock, flags);
1790                break;
1791
1792        default:
1793                rc = -EOPNOTSUPP;
1794                break;
1795        }
1796
1797        DPRINTK ("EXIT, returning %d\n", rc);
1798        return rc;
1799}
1800
1801/* Set or clear the multicast filter for this adaptor.
1802   This routine is not state sensitive and need not be SMP locked. */
1803
1804static void netdrv_set_rx_mode (struct net_device *dev)
1805{
1806        struct netdrv_private *tp = netdev_priv(dev);
1807        void *ioaddr = tp->mmio_addr;
1808        u32 mc_filter[2];       /* Multicast hash filter */
1809        int i, rx_mode;
1810        u32 tmp;
1811
1812        DPRINTK ("ENTER\n");
1813
1814        DPRINTK ("%s:   netdrv_set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1815                        dev->name, dev->flags, NETDRV_R32 (RxConfig));
1816
1817        /* Note: do not reorder, GCC is clever about common statements. */
1818        if (dev->flags & IFF_PROMISC) {
1819                rx_mode =
1820                    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1821                    AcceptAllPhys;
1822                mc_filter[1] = mc_filter[0] = 0xffffffff;
1823        } else if ((dev->mc_count > multicast_filter_limit)
1824                   || (dev->flags & IFF_ALLMULTI)) {
1825                /* Too many to filter perfectly -- accept all multicasts. */
1826                rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1827                mc_filter[1] = mc_filter[0] = 0xffffffff;
1828        } else {
1829                struct dev_mc_list *mclist;
1830                rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1831                mc_filter[1] = mc_filter[0] = 0;
1832                for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1833                     i++, mclist = mclist->next) {
1834                        int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1835
1836                        mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1837                }
1838        }
1839
1840        /* if called from irq handler, lock already acquired */
1841        if (!in_irq ())
1842                spin_lock_irq (&tp->lock);
1843
1844        /* We can safely update without stopping the chip. */
1845        tmp = netdrv_rx_config | rx_mode |
1846                (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1847        NETDRV_W32_F (RxConfig, tmp);
1848        NETDRV_W32_F (MAR0 + 0, mc_filter[0]);
1849        NETDRV_W32_F (MAR0 + 4, mc_filter[1]);
1850
1851        if (!in_irq ())
1852                spin_unlock_irq (&tp->lock);
1853
1854        DPRINTK ("EXIT\n");
1855}
1856
1857
1858#ifdef CONFIG_PM
1859
1860static int netdrv_suspend (struct pci_dev *pdev, pm_message_t state)
1861{
1862        struct net_device *dev = pci_get_drvdata (pdev);
1863        struct netdrv_private *tp = netdev_priv(dev);
1864        void *ioaddr = tp->mmio_addr;
1865        unsigned long flags;
1866
1867        if (!netif_running(dev))
1868                return 0;
1869        netif_device_detach (dev);
1870
1871        spin_lock_irqsave (&tp->lock, flags);
1872
1873        /* Disable interrupts, stop Tx and Rx. */
1874        NETDRV_W16 (IntrMask, 0x0000);
1875        NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1876
1877        /* Update the error counts. */
1878        dev->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1879        NETDRV_W32 (RxMissed, 0);
1880
1881        spin_unlock_irqrestore (&tp->lock, flags);
1882
1883        pci_save_state (pdev);
1884        pci_set_power_state (pdev, PCI_D3hot);
1885
1886        return 0;
1887}
1888
1889
1890static int netdrv_resume (struct pci_dev *pdev)
1891{
1892        struct net_device *dev = pci_get_drvdata (pdev);
1893        /*struct netdrv_private *tp = netdev_priv(dev);*/
1894
1895        if (!netif_running(dev))
1896                return 0;
1897        pci_set_power_state (pdev, PCI_D0);
1898        pci_restore_state (pdev);
1899        netif_device_attach (dev);
1900        netdrv_hw_start (dev);
1901
1902        return 0;
1903}
1904
1905#endif /* CONFIG_PM */
1906
1907
1908static struct pci_driver netdrv_pci_driver = {
1909        .name           = MODNAME,
1910        .id_table       = netdrv_pci_tbl,
1911        .probe          = netdrv_init_one,
1912        .remove         = __devexit_p(netdrv_remove_one),
1913#ifdef CONFIG_PM
1914        .suspend        = netdrv_suspend,
1915        .resume         = netdrv_resume,
1916#endif /* CONFIG_PM */
1917};
1918
1919
1920static int __init netdrv_init_module (void)
1921{
1922/* when a module, this is printed whether or not devices are found in probe */
1923#ifdef MODULE
1924        printk(version);
1925#endif
1926        return pci_register_driver(&netdrv_pci_driver);
1927}
1928
1929
1930static void __exit netdrv_cleanup_module (void)
1931{
1932        pci_unregister_driver (&netdrv_pci_driver);
1933}
1934
1935
1936module_init(netdrv_init_module);
1937module_exit(netdrv_cleanup_module);
1938
The original LXR software by the LXR community, this experimental version by lxr@linux.no.
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