linux/drivers/media/video/pvrusb2/pvrusb2-hdw.c
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   1/*
   2 *
   3 *
   4 *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5 *
   6 *  This program is free software; you can redistribute it and/or modify
   7 *  it under the terms of the GNU General Public License as published by
   8 *  the Free Software Foundation; either version 2 of the License
   9 *
  10 *  This program is distributed in the hope that it will be useful,
  11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 *  GNU General Public License for more details.
  14 *
  15 *  You should have received a copy of the GNU General Public License
  16 *  along with this program; if not, write to the Free Software
  17 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18 *
  19 */
  20
  21#include <linux/errno.h>
  22#include <linux/string.h>
  23#include <linux/slab.h>
  24#include <linux/firmware.h>
  25#include <linux/videodev2.h>
  26#include <media/v4l2-common.h>
  27#include <media/tuner.h>
  28#include "pvrusb2.h"
  29#include "pvrusb2-std.h"
  30#include "pvrusb2-util.h"
  31#include "pvrusb2-hdw.h"
  32#include "pvrusb2-i2c-core.h"
  33#include "pvrusb2-eeprom.h"
  34#include "pvrusb2-hdw-internal.h"
  35#include "pvrusb2-encoder.h"
  36#include "pvrusb2-debug.h"
  37#include "pvrusb2-fx2-cmd.h"
  38#include "pvrusb2-wm8775.h"
  39#include "pvrusb2-video-v4l.h"
  40#include "pvrusb2-cx2584x-v4l.h"
  41#include "pvrusb2-cs53l32a.h"
  42#include "pvrusb2-audio.h"
  43
  44#define TV_MIN_FREQ     55250000L
  45#define TV_MAX_FREQ    850000000L
  46
  47/* This defines a minimum interval that the decoder must remain quiet
  48   before we are allowed to start it running. */
  49#define TIME_MSEC_DECODER_WAIT 50
  50
  51/* This defines a minimum interval that the encoder must remain quiet
  52   before we are allowed to configure it.  I had this originally set to
  53   50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  54   things work better when it's set to 100msec. */
  55#define TIME_MSEC_ENCODER_WAIT 100
  56
  57/* This defines the minimum interval that the encoder must successfully run
  58   before we consider that the encoder has run at least once since its
  59   firmware has been loaded.  This measurement is in important for cases
  60   where we can't do something until we know that the encoder has been run
  61   at least once. */
  62#define TIME_MSEC_ENCODER_OK 250
  63
  64static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  65static DEFINE_MUTEX(pvr2_unit_mtx);
  66
  67static int ctlchg;
  68static int procreload;
  69static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  70static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  71static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  72static int init_pause_msec;
  73
  74module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  75MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  76module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  77MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  78module_param(procreload, int, S_IRUGO|S_IWUSR);
  79MODULE_PARM_DESC(procreload,
  80                 "Attempt init failure recovery with firmware reload");
  81module_param_array(tuner,    int, NULL, 0444);
  82MODULE_PARM_DESC(tuner,"specify installed tuner type");
  83module_param_array(video_std,    int, NULL, 0444);
  84MODULE_PARM_DESC(video_std,"specify initial video standard");
  85module_param_array(tolerance,    int, NULL, 0444);
  86MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  87
  88/* US Broadcast channel 3 (61.25 MHz), to help with testing */
  89static int default_tv_freq    = 61250000L;
  90/* 104.3 MHz, a usable FM station for my area */
  91static int default_radio_freq = 104300000L;
  92
  93module_param_named(tv_freq, default_tv_freq, int, 0444);
  94MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  95module_param_named(radio_freq, default_radio_freq, int, 0444);
  96MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  97
  98#define PVR2_CTL_WRITE_ENDPOINT  0x01
  99#define PVR2_CTL_READ_ENDPOINT   0x81
 100
 101#define PVR2_GPIO_IN 0x9008
 102#define PVR2_GPIO_OUT 0x900c
 103#define PVR2_GPIO_DIR 0x9020
 104
 105#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 106
 107#define PVR2_FIRMWARE_ENDPOINT   0x02
 108
 109/* size of a firmware chunk */
 110#define FIRMWARE_CHUNK_SIZE 0x2000
 111
 112typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 113                                        struct v4l2_subdev *);
 114
 115static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 116        [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 117        [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 118        [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 119        [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 120        [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
 121};
 122
 123static const char *module_names[] = {
 124        [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 125        [PVR2_CLIENT_ID_CX25840] = "cx25840",
 126        [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 127        [PVR2_CLIENT_ID_TUNER] = "tuner",
 128        [PVR2_CLIENT_ID_DEMOD] = "tuner",
 129        [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 130        [PVR2_CLIENT_ID_WM8775] = "wm8775",
 131};
 132
 133
 134static const unsigned char *module_i2c_addresses[] = {
 135        [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 136        [PVR2_CLIENT_ID_DEMOD] = "\x43",
 137        [PVR2_CLIENT_ID_MSP3400] = "\x40",
 138        [PVR2_CLIENT_ID_SAA7115] = "\x21",
 139        [PVR2_CLIENT_ID_WM8775] = "\x1b",
 140        [PVR2_CLIENT_ID_CX25840] = "\x44",
 141        [PVR2_CLIENT_ID_CS53L32A] = "\x11",
 142};
 143
 144
 145static const char *ir_scheme_names[] = {
 146        [PVR2_IR_SCHEME_NONE] = "none",
 147        [PVR2_IR_SCHEME_29XXX] = "29xxx",
 148        [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
 149        [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
 150        [PVR2_IR_SCHEME_ZILOG] = "Zilog",
 151};
 152
 153
 154/* Define the list of additional controls we'll dynamically construct based
 155   on query of the cx2341x module. */
 156struct pvr2_mpeg_ids {
 157        const char *strid;
 158        int id;
 159};
 160static const struct pvr2_mpeg_ids mpeg_ids[] = {
 161        {
 162                .strid = "audio_layer",
 163                .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 164        },{
 165                .strid = "audio_bitrate",
 166                .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 167        },{
 168                /* Already using audio_mode elsewhere :-( */
 169                .strid = "mpeg_audio_mode",
 170                .id = V4L2_CID_MPEG_AUDIO_MODE,
 171        },{
 172                .strid = "mpeg_audio_mode_extension",
 173                .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 174        },{
 175                .strid = "audio_emphasis",
 176                .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 177        },{
 178                .strid = "audio_crc",
 179                .id = V4L2_CID_MPEG_AUDIO_CRC,
 180        },{
 181                .strid = "video_aspect",
 182                .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 183        },{
 184                .strid = "video_b_frames",
 185                .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 186        },{
 187                .strid = "video_gop_size",
 188                .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 189        },{
 190                .strid = "video_gop_closure",
 191                .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 192        },{
 193                .strid = "video_bitrate_mode",
 194                .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 195        },{
 196                .strid = "video_bitrate",
 197                .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 198        },{
 199                .strid = "video_bitrate_peak",
 200                .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 201        },{
 202                .strid = "video_temporal_decimation",
 203                .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 204        },{
 205                .strid = "stream_type",
 206                .id = V4L2_CID_MPEG_STREAM_TYPE,
 207        },{
 208                .strid = "video_spatial_filter_mode",
 209                .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 210        },{
 211                .strid = "video_spatial_filter",
 212                .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 213        },{
 214                .strid = "video_luma_spatial_filter_type",
 215                .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 216        },{
 217                .strid = "video_chroma_spatial_filter_type",
 218                .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 219        },{
 220                .strid = "video_temporal_filter_mode",
 221                .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 222        },{
 223                .strid = "video_temporal_filter",
 224                .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 225        },{
 226                .strid = "video_median_filter_type",
 227                .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 228        },{
 229                .strid = "video_luma_median_filter_top",
 230                .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 231        },{
 232                .strid = "video_luma_median_filter_bottom",
 233                .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 234        },{
 235                .strid = "video_chroma_median_filter_top",
 236                .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 237        },{
 238                .strid = "video_chroma_median_filter_bottom",
 239                .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 240        }
 241};
 242#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 243
 244
 245static const char *control_values_srate[] = {
 246        [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 247        [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 248        [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 249};
 250
 251
 252
 253static const char *control_values_input[] = {
 254        [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 255        [PVR2_CVAL_INPUT_DTV]       = "dtv",
 256        [PVR2_CVAL_INPUT_RADIO]     = "radio",
 257        [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 258        [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 259};
 260
 261
 262static const char *control_values_audiomode[] = {
 263        [V4L2_TUNER_MODE_MONO]   = "Mono",
 264        [V4L2_TUNER_MODE_STEREO] = "Stereo",
 265        [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 266        [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 267        [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 268};
 269
 270
 271static const char *control_values_hsm[] = {
 272        [PVR2_CVAL_HSM_FAIL] = "Fail",
 273        [PVR2_CVAL_HSM_HIGH] = "High",
 274        [PVR2_CVAL_HSM_FULL] = "Full",
 275};
 276
 277
 278static const char *pvr2_state_names[] = {
 279        [PVR2_STATE_NONE] =    "none",
 280        [PVR2_STATE_DEAD] =    "dead",
 281        [PVR2_STATE_COLD] =    "cold",
 282        [PVR2_STATE_WARM] =    "warm",
 283        [PVR2_STATE_ERROR] =   "error",
 284        [PVR2_STATE_READY] =   "ready",
 285        [PVR2_STATE_RUN] =     "run",
 286};
 287
 288
 289struct pvr2_fx2cmd_descdef {
 290        unsigned char id;
 291        unsigned char *desc;
 292};
 293
 294static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 295        {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 296        {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 297        {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 298        {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 299        {FX2CMD_REG_WRITE, "write encoder register"},
 300        {FX2CMD_REG_READ, "read encoder register"},
 301        {FX2CMD_MEMSEL, "encoder memsel"},
 302        {FX2CMD_I2C_WRITE, "i2c write"},
 303        {FX2CMD_I2C_READ, "i2c read"},
 304        {FX2CMD_GET_USB_SPEED, "get USB speed"},
 305        {FX2CMD_STREAMING_ON, "stream on"},
 306        {FX2CMD_STREAMING_OFF, "stream off"},
 307        {FX2CMD_FWPOST1, "fwpost1"},
 308        {FX2CMD_POWER_OFF, "power off"},
 309        {FX2CMD_POWER_ON, "power on"},
 310        {FX2CMD_DEEP_RESET, "deep reset"},
 311        {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 312        {FX2CMD_GET_IR_CODE, "get IR code"},
 313        {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 314        {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 315        {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 316        {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 317        {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 318        {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 319        {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 320};
 321
 322
 323static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 324static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 325static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 326static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 327static void pvr2_hdw_worker_poll(struct work_struct *work);
 328static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 329static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 330static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 331static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 332static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 333static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 334static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 335static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 336static void pvr2_hdw_quiescent_timeout(unsigned long);
 337static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 338static void pvr2_hdw_encoder_run_timeout(unsigned long);
 339static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 340static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 341                                unsigned int timeout,int probe_fl,
 342                                void *write_data,unsigned int write_len,
 343                                void *read_data,unsigned int read_len);
 344static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 345
 346
 347static void trace_stbit(const char *name,int val)
 348{
 349        pvr2_trace(PVR2_TRACE_STBITS,
 350                   "State bit %s <-- %s",
 351                   name,(val ? "true" : "false"));
 352}
 353
 354static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 355{
 356        struct pvr2_hdw *hdw = cptr->hdw;
 357        if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 358                *vp = hdw->freqTable[hdw->freqProgSlot-1];
 359        } else {
 360                *vp = 0;
 361        }
 362        return 0;
 363}
 364
 365static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 366{
 367        struct pvr2_hdw *hdw = cptr->hdw;
 368        unsigned int slotId = hdw->freqProgSlot;
 369        if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 370                hdw->freqTable[slotId-1] = v;
 371                /* Handle side effects correctly - if we're tuned to this
 372                   slot, then forgot the slot id relation since the stored
 373                   frequency has been changed. */
 374                if (hdw->freqSelector) {
 375                        if (hdw->freqSlotRadio == slotId) {
 376                                hdw->freqSlotRadio = 0;
 377                        }
 378                } else {
 379                        if (hdw->freqSlotTelevision == slotId) {
 380                                hdw->freqSlotTelevision = 0;
 381                        }
 382                }
 383        }
 384        return 0;
 385}
 386
 387static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 388{
 389        *vp = cptr->hdw->freqProgSlot;
 390        return 0;
 391}
 392
 393static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 394{
 395        struct pvr2_hdw *hdw = cptr->hdw;
 396        if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 397                hdw->freqProgSlot = v;
 398        }
 399        return 0;
 400}
 401
 402static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 403{
 404        struct pvr2_hdw *hdw = cptr->hdw;
 405        *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 406        return 0;
 407}
 408
 409static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 410{
 411        unsigned freq = 0;
 412        struct pvr2_hdw *hdw = cptr->hdw;
 413        if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 414        if (slotId > 0) {
 415                freq = hdw->freqTable[slotId-1];
 416                if (!freq) return 0;
 417                pvr2_hdw_set_cur_freq(hdw,freq);
 418        }
 419        if (hdw->freqSelector) {
 420                hdw->freqSlotRadio = slotId;
 421        } else {
 422                hdw->freqSlotTelevision = slotId;
 423        }
 424        return 0;
 425}
 426
 427static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 428{
 429        *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 430        return 0;
 431}
 432
 433static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 434{
 435        return cptr->hdw->freqDirty != 0;
 436}
 437
 438static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 439{
 440        cptr->hdw->freqDirty = 0;
 441}
 442
 443static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 444{
 445        pvr2_hdw_set_cur_freq(cptr->hdw,v);
 446        return 0;
 447}
 448
 449static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 450{
 451        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 452        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 453        if (stat != 0) {
 454                return stat;
 455        }
 456        *left = cap->bounds.left;
 457        return 0;
 458}
 459
 460static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 461{
 462        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 463        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 464        if (stat != 0) {
 465                return stat;
 466        }
 467        *left = cap->bounds.left;
 468        if (cap->bounds.width > cptr->hdw->cropw_val) {
 469                *left += cap->bounds.width - cptr->hdw->cropw_val;
 470        }
 471        return 0;
 472}
 473
 474static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 475{
 476        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 477        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 478        if (stat != 0) {
 479                return stat;
 480        }
 481        *top = cap->bounds.top;
 482        return 0;
 483}
 484
 485static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 486{
 487        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 488        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 489        if (stat != 0) {
 490                return stat;
 491        }
 492        *top = cap->bounds.top;
 493        if (cap->bounds.height > cptr->hdw->croph_val) {
 494                *top += cap->bounds.height - cptr->hdw->croph_val;
 495        }
 496        return 0;
 497}
 498
 499static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 500{
 501        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 502        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 503        if (stat != 0) {
 504                return stat;
 505        }
 506        *val = 0;
 507        if (cap->bounds.width > cptr->hdw->cropl_val) {
 508                *val = cap->bounds.width - cptr->hdw->cropl_val;
 509        }
 510        return 0;
 511}
 512
 513static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 514{
 515        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 516        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 517        if (stat != 0) {
 518                return stat;
 519        }
 520        *val = 0;
 521        if (cap->bounds.height > cptr->hdw->cropt_val) {
 522                *val = cap->bounds.height - cptr->hdw->cropt_val;
 523        }
 524        return 0;
 525}
 526
 527static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 528{
 529        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 530        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 531        if (stat != 0) {
 532                return stat;
 533        }
 534        *val = cap->bounds.left;
 535        return 0;
 536}
 537
 538static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 539{
 540        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 541        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 542        if (stat != 0) {
 543                return stat;
 544        }
 545        *val = cap->bounds.top;
 546        return 0;
 547}
 548
 549static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 550{
 551        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 552        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 553        if (stat != 0) {
 554                return stat;
 555        }
 556        *val = cap->bounds.width;
 557        return 0;
 558}
 559
 560static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 561{
 562        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 563        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 564        if (stat != 0) {
 565                return stat;
 566        }
 567        *val = cap->bounds.height;
 568        return 0;
 569}
 570
 571static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 572{
 573        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 574        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 575        if (stat != 0) {
 576                return stat;
 577        }
 578        *val = cap->defrect.left;
 579        return 0;
 580}
 581
 582static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 583{
 584        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 585        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 586        if (stat != 0) {
 587                return stat;
 588        }
 589        *val = cap->defrect.top;
 590        return 0;
 591}
 592
 593static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 594{
 595        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 596        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 597        if (stat != 0) {
 598                return stat;
 599        }
 600        *val = cap->defrect.width;
 601        return 0;
 602}
 603
 604static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 605{
 606        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 607        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 608        if (stat != 0) {
 609                return stat;
 610        }
 611        *val = cap->defrect.height;
 612        return 0;
 613}
 614
 615static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 616{
 617        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 618        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 619        if (stat != 0) {
 620                return stat;
 621        }
 622        *val = cap->pixelaspect.numerator;
 623        return 0;
 624}
 625
 626static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 627{
 628        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 629        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 630        if (stat != 0) {
 631                return stat;
 632        }
 633        *val = cap->pixelaspect.denominator;
 634        return 0;
 635}
 636
 637static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 638{
 639        /* Actual maximum depends on the video standard in effect. */
 640        if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 641                *vp = 480;
 642        } else {
 643                *vp = 576;
 644        }
 645        return 0;
 646}
 647
 648static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 649{
 650        /* Actual minimum depends on device digitizer type. */
 651        if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 652                *vp = 75;
 653        } else {
 654                *vp = 17;
 655        }
 656        return 0;
 657}
 658
 659static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 660{
 661        *vp = cptr->hdw->input_val;
 662        return 0;
 663}
 664
 665static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 666{
 667        return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 668}
 669
 670static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 671{
 672        return pvr2_hdw_set_input(cptr->hdw,v);
 673}
 674
 675static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 676{
 677        return cptr->hdw->input_dirty != 0;
 678}
 679
 680static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 681{
 682        cptr->hdw->input_dirty = 0;
 683}
 684
 685
 686static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 687{
 688        unsigned long fv;
 689        struct pvr2_hdw *hdw = cptr->hdw;
 690        if (hdw->tuner_signal_stale) {
 691                pvr2_hdw_status_poll(hdw);
 692        }
 693        fv = hdw->tuner_signal_info.rangehigh;
 694        if (!fv) {
 695                /* Safety fallback */
 696                *vp = TV_MAX_FREQ;
 697                return 0;
 698        }
 699        if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 700                fv = (fv * 125) / 2;
 701        } else {
 702                fv = fv * 62500;
 703        }
 704        *vp = fv;
 705        return 0;
 706}
 707
 708static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 709{
 710        unsigned long fv;
 711        struct pvr2_hdw *hdw = cptr->hdw;
 712        if (hdw->tuner_signal_stale) {
 713                pvr2_hdw_status_poll(hdw);
 714        }
 715        fv = hdw->tuner_signal_info.rangelow;
 716        if (!fv) {
 717                /* Safety fallback */
 718                *vp = TV_MIN_FREQ;
 719                return 0;
 720        }
 721        if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 722                fv = (fv * 125) / 2;
 723        } else {
 724                fv = fv * 62500;
 725        }
 726        *vp = fv;
 727        return 0;
 728}
 729
 730static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 731{
 732        return cptr->hdw->enc_stale != 0;
 733}
 734
 735static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 736{
 737        cptr->hdw->enc_stale = 0;
 738        cptr->hdw->enc_unsafe_stale = 0;
 739}
 740
 741static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 742{
 743        int ret;
 744        struct v4l2_ext_controls cs;
 745        struct v4l2_ext_control c1;
 746        memset(&cs,0,sizeof(cs));
 747        memset(&c1,0,sizeof(c1));
 748        cs.controls = &c1;
 749        cs.count = 1;
 750        c1.id = cptr->info->v4l_id;
 751        ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 752                                VIDIOC_G_EXT_CTRLS);
 753        if (ret) return ret;
 754        *vp = c1.value;
 755        return 0;
 756}
 757
 758static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 759{
 760        int ret;
 761        struct pvr2_hdw *hdw = cptr->hdw;
 762        struct v4l2_ext_controls cs;
 763        struct v4l2_ext_control c1;
 764        memset(&cs,0,sizeof(cs));
 765        memset(&c1,0,sizeof(c1));
 766        cs.controls = &c1;
 767        cs.count = 1;
 768        c1.id = cptr->info->v4l_id;
 769        c1.value = v;
 770        ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 771                                hdw->state_encoder_run, &cs,
 772                                VIDIOC_S_EXT_CTRLS);
 773        if (ret == -EBUSY) {
 774                /* Oops.  cx2341x is telling us it's not safe to change
 775                   this control while we're capturing.  Make a note of this
 776                   fact so that the pipeline will be stopped the next time
 777                   controls are committed.  Then go on ahead and store this
 778                   change anyway. */
 779                ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 780                                        0, &cs,
 781                                        VIDIOC_S_EXT_CTRLS);
 782                if (!ret) hdw->enc_unsafe_stale = !0;
 783        }
 784        if (ret) return ret;
 785        hdw->enc_stale = !0;
 786        return 0;
 787}
 788
 789static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 790{
 791        struct v4l2_queryctrl qctrl;
 792        struct pvr2_ctl_info *info;
 793        qctrl.id = cptr->info->v4l_id;
 794        cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 795        /* Strip out the const so we can adjust a function pointer.  It's
 796           OK to do this here because we know this is a dynamically created
 797           control, so the underlying storage for the info pointer is (a)
 798           private to us, and (b) not in read-only storage.  Either we do
 799           this or we significantly complicate the underlying control
 800           implementation. */
 801        info = (struct pvr2_ctl_info *)(cptr->info);
 802        if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 803                if (info->set_value) {
 804                        info->set_value = NULL;
 805                }
 806        } else {
 807                if (!(info->set_value)) {
 808                        info->set_value = ctrl_cx2341x_set;
 809                }
 810        }
 811        return qctrl.flags;
 812}
 813
 814static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 815{
 816        *vp = cptr->hdw->state_pipeline_req;
 817        return 0;
 818}
 819
 820static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 821{
 822        *vp = cptr->hdw->master_state;
 823        return 0;
 824}
 825
 826static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 827{
 828        int result = pvr2_hdw_is_hsm(cptr->hdw);
 829        *vp = PVR2_CVAL_HSM_FULL;
 830        if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 831        if (result) *vp = PVR2_CVAL_HSM_HIGH;
 832        return 0;
 833}
 834
 835static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 836{
 837        *vp = cptr->hdw->std_mask_avail;
 838        return 0;
 839}
 840
 841static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 842{
 843        struct pvr2_hdw *hdw = cptr->hdw;
 844        v4l2_std_id ns;
 845        ns = hdw->std_mask_avail;
 846        ns = (ns & ~m) | (v & m);
 847        if (ns == hdw->std_mask_avail) return 0;
 848        hdw->std_mask_avail = ns;
 849        pvr2_hdw_internal_set_std_avail(hdw);
 850        pvr2_hdw_internal_find_stdenum(hdw);
 851        return 0;
 852}
 853
 854static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 855                               char *bufPtr,unsigned int bufSize,
 856                               unsigned int *len)
 857{
 858        *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 859        return 0;
 860}
 861
 862static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 863                               const char *bufPtr,unsigned int bufSize,
 864                               int *mskp,int *valp)
 865{
 866        int ret;
 867        v4l2_std_id id;
 868        ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 869        if (ret < 0) return ret;
 870        if (mskp) *mskp = id;
 871        if (valp) *valp = id;
 872        return 0;
 873}
 874
 875static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 876{
 877        *vp = cptr->hdw->std_mask_cur;
 878        return 0;
 879}
 880
 881static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 882{
 883        struct pvr2_hdw *hdw = cptr->hdw;
 884        v4l2_std_id ns;
 885        ns = hdw->std_mask_cur;
 886        ns = (ns & ~m) | (v & m);
 887        if (ns == hdw->std_mask_cur) return 0;
 888        hdw->std_mask_cur = ns;
 889        hdw->std_dirty = !0;
 890        pvr2_hdw_internal_find_stdenum(hdw);
 891        return 0;
 892}
 893
 894static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 895{
 896        return cptr->hdw->std_dirty != 0;
 897}
 898
 899static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 900{
 901        cptr->hdw->std_dirty = 0;
 902}
 903
 904static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 905{
 906        struct pvr2_hdw *hdw = cptr->hdw;
 907        pvr2_hdw_status_poll(hdw);
 908        *vp = hdw->tuner_signal_info.signal;
 909        return 0;
 910}
 911
 912static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 913{
 914        int val = 0;
 915        unsigned int subchan;
 916        struct pvr2_hdw *hdw = cptr->hdw;
 917        pvr2_hdw_status_poll(hdw);
 918        subchan = hdw->tuner_signal_info.rxsubchans;
 919        if (subchan & V4L2_TUNER_SUB_MONO) {
 920                val |= (1 << V4L2_TUNER_MODE_MONO);
 921        }
 922        if (subchan & V4L2_TUNER_SUB_STEREO) {
 923                val |= (1 << V4L2_TUNER_MODE_STEREO);
 924        }
 925        if (subchan & V4L2_TUNER_SUB_LANG1) {
 926                val |= (1 << V4L2_TUNER_MODE_LANG1);
 927        }
 928        if (subchan & V4L2_TUNER_SUB_LANG2) {
 929                val |= (1 << V4L2_TUNER_MODE_LANG2);
 930        }
 931        *vp = val;
 932        return 0;
 933}
 934
 935
 936static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 937{
 938        struct pvr2_hdw *hdw = cptr->hdw;
 939        if (v < 0) return -EINVAL;
 940        if (v > hdw->std_enum_cnt) return -EINVAL;
 941        hdw->std_enum_cur = v;
 942        if (!v) return 0;
 943        v--;
 944        if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 945        hdw->std_mask_cur = hdw->std_defs[v].id;
 946        hdw->std_dirty = !0;
 947        return 0;
 948}
 949
 950
 951static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 952{
 953        *vp = cptr->hdw->std_enum_cur;
 954        return 0;
 955}
 956
 957
 958static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 959{
 960        return cptr->hdw->std_dirty != 0;
 961}
 962
 963
 964static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 965{
 966        cptr->hdw->std_dirty = 0;
 967}
 968
 969
 970#define DEFINT(vmin,vmax) \
 971        .type = pvr2_ctl_int, \
 972        .def.type_int.min_value = vmin, \
 973        .def.type_int.max_value = vmax
 974
 975#define DEFENUM(tab) \
 976        .type = pvr2_ctl_enum, \
 977        .def.type_enum.count = ARRAY_SIZE(tab), \
 978        .def.type_enum.value_names = tab
 979
 980#define DEFBOOL \
 981        .type = pvr2_ctl_bool
 982
 983#define DEFMASK(msk,tab) \
 984        .type = pvr2_ctl_bitmask, \
 985        .def.type_bitmask.valid_bits = msk, \
 986        .def.type_bitmask.bit_names = tab
 987
 988#define DEFREF(vname) \
 989        .set_value = ctrl_set_##vname, \
 990        .get_value = ctrl_get_##vname, \
 991        .is_dirty = ctrl_isdirty_##vname, \
 992        .clear_dirty = ctrl_cleardirty_##vname
 993
 994
 995#define VCREATE_FUNCS(vname) \
 996static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 997{*vp = cptr->hdw->vname##_val; return 0;} \
 998static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 999{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1000static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1001{return cptr->hdw->vname##_dirty != 0;} \
1002static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1003{cptr->hdw->vname##_dirty = 0;}
1004
1005VCREATE_FUNCS(brightness)
1006VCREATE_FUNCS(contrast)
1007VCREATE_FUNCS(saturation)
1008VCREATE_FUNCS(hue)
1009VCREATE_FUNCS(volume)
1010VCREATE_FUNCS(balance)
1011VCREATE_FUNCS(bass)
1012VCREATE_FUNCS(treble)
1013VCREATE_FUNCS(mute)
1014VCREATE_FUNCS(cropl)
1015VCREATE_FUNCS(cropt)
1016VCREATE_FUNCS(cropw)
1017VCREATE_FUNCS(croph)
1018VCREATE_FUNCS(audiomode)
1019VCREATE_FUNCS(res_hor)
1020VCREATE_FUNCS(res_ver)
1021VCREATE_FUNCS(srate)
1022
1023/* Table definition of all controls which can be manipulated */
1024static const struct pvr2_ctl_info control_defs[] = {
1025        {
1026                .v4l_id = V4L2_CID_BRIGHTNESS,
1027                .desc = "Brightness",
1028                .name = "brightness",
1029                .default_value = 128,
1030                DEFREF(brightness),
1031                DEFINT(0,255),
1032        },{
1033                .v4l_id = V4L2_CID_CONTRAST,
1034                .desc = "Contrast",
1035                .name = "contrast",
1036                .default_value = 68,
1037                DEFREF(contrast),
1038                DEFINT(0,127),
1039        },{
1040                .v4l_id = V4L2_CID_SATURATION,
1041                .desc = "Saturation",
1042                .name = "saturation",
1043                .default_value = 64,
1044                DEFREF(saturation),
1045                DEFINT(0,127),
1046        },{
1047                .v4l_id = V4L2_CID_HUE,
1048                .desc = "Hue",
1049                .name = "hue",
1050                .default_value = 0,
1051                DEFREF(hue),
1052                DEFINT(-128,127),
1053        },{
1054                .v4l_id = V4L2_CID_AUDIO_VOLUME,
1055                .desc = "Volume",
1056                .name = "volume",
1057                .default_value = 62000,
1058                DEFREF(volume),
1059                DEFINT(0,65535),
1060        },{
1061                .v4l_id = V4L2_CID_AUDIO_BALANCE,
1062                .desc = "Balance",
1063                .name = "balance",
1064                .default_value = 0,
1065                DEFREF(balance),
1066                DEFINT(-32768,32767),
1067        },{
1068                .v4l_id = V4L2_CID_AUDIO_BASS,
1069                .desc = "Bass",
1070                .name = "bass",
1071                .default_value = 0,
1072                DEFREF(bass),
1073                DEFINT(-32768,32767),
1074        },{
1075                .v4l_id = V4L2_CID_AUDIO_TREBLE,
1076                .desc = "Treble",
1077                .name = "treble",
1078                .default_value = 0,
1079                DEFREF(treble),
1080                DEFINT(-32768,32767),
1081        },{
1082                .v4l_id = V4L2_CID_AUDIO_MUTE,
1083                .desc = "Mute",
1084                .name = "mute",
1085                .default_value = 0,
1086                DEFREF(mute),
1087                DEFBOOL,
1088        }, {
1089                .desc = "Capture crop left margin",
1090                .name = "crop_left",
1091                .internal_id = PVR2_CID_CROPL,
1092                .default_value = 0,
1093                DEFREF(cropl),
1094                DEFINT(-129, 340),
1095                .get_min_value = ctrl_cropl_min_get,
1096                .get_max_value = ctrl_cropl_max_get,
1097                .get_def_value = ctrl_get_cropcapdl,
1098        }, {
1099                .desc = "Capture crop top margin",
1100                .name = "crop_top",
1101                .internal_id = PVR2_CID_CROPT,
1102                .default_value = 0,
1103                DEFREF(cropt),
1104                DEFINT(-35, 544),
1105                .get_min_value = ctrl_cropt_min_get,
1106                .get_max_value = ctrl_cropt_max_get,
1107                .get_def_value = ctrl_get_cropcapdt,
1108        }, {
1109                .desc = "Capture crop width",
1110                .name = "crop_width",
1111                .internal_id = PVR2_CID_CROPW,
1112                .default_value = 720,
1113                DEFREF(cropw),
1114                .get_max_value = ctrl_cropw_max_get,
1115                .get_def_value = ctrl_get_cropcapdw,
1116        }, {
1117                .desc = "Capture crop height",
1118                .name = "crop_height",
1119                .internal_id = PVR2_CID_CROPH,
1120                .default_value = 480,
1121                DEFREF(croph),
1122                .get_max_value = ctrl_croph_max_get,
1123                .get_def_value = ctrl_get_cropcapdh,
1124        }, {
1125                .desc = "Capture capability pixel aspect numerator",
1126                .name = "cropcap_pixel_numerator",
1127                .internal_id = PVR2_CID_CROPCAPPAN,
1128                .get_value = ctrl_get_cropcappan,
1129        }, {
1130                .desc = "Capture capability pixel aspect denominator",
1131                .name = "cropcap_pixel_denominator",
1132                .internal_id = PVR2_CID_CROPCAPPAD,
1133                .get_value = ctrl_get_cropcappad,
1134        }, {
1135                .desc = "Capture capability bounds top",
1136                .name = "cropcap_bounds_top",
1137                .internal_id = PVR2_CID_CROPCAPBT,
1138                .get_value = ctrl_get_cropcapbt,
1139        }, {
1140                .desc = "Capture capability bounds left",
1141                .name = "cropcap_bounds_left",
1142                .internal_id = PVR2_CID_CROPCAPBL,
1143                .get_value = ctrl_get_cropcapbl,
1144        }, {
1145                .desc = "Capture capability bounds width",
1146                .name = "cropcap_bounds_width",
1147                .internal_id = PVR2_CID_CROPCAPBW,
1148                .get_value = ctrl_get_cropcapbw,
1149        }, {
1150                .desc = "Capture capability bounds height",
1151                .name = "cropcap_bounds_height",
1152                .internal_id = PVR2_CID_CROPCAPBH,
1153                .get_value = ctrl_get_cropcapbh,
1154        },{
1155                .desc = "Video Source",
1156                .name = "input",
1157                .internal_id = PVR2_CID_INPUT,
1158                .default_value = PVR2_CVAL_INPUT_TV,
1159                .check_value = ctrl_check_input,
1160                DEFREF(input),
1161                DEFENUM(control_values_input),
1162        },{
1163                .desc = "Audio Mode",
1164                .name = "audio_mode",
1165                .internal_id = PVR2_CID_AUDIOMODE,
1166                .default_value = V4L2_TUNER_MODE_STEREO,
1167                DEFREF(audiomode),
1168                DEFENUM(control_values_audiomode),
1169        },{
1170                .desc = "Horizontal capture resolution",
1171                .name = "resolution_hor",
1172                .internal_id = PVR2_CID_HRES,
1173                .default_value = 720,
1174                DEFREF(res_hor),
1175                DEFINT(19,720),
1176        },{
1177                .desc = "Vertical capture resolution",
1178                .name = "resolution_ver",
1179                .internal_id = PVR2_CID_VRES,
1180                .default_value = 480,
1181                DEFREF(res_ver),
1182                DEFINT(17,576),
1183                /* Hook in check for video standard and adjust maximum
1184                   depending on the standard. */
1185                .get_max_value = ctrl_vres_max_get,
1186                .get_min_value = ctrl_vres_min_get,
1187        },{
1188                .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1189                .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1190                .desc = "Audio Sampling Frequency",
1191                .name = "srate",
1192                DEFREF(srate),
1193                DEFENUM(control_values_srate),
1194        },{
1195                .desc = "Tuner Frequency (Hz)",
1196                .name = "frequency",
1197                .internal_id = PVR2_CID_FREQUENCY,
1198                .default_value = 0,
1199                .set_value = ctrl_freq_set,
1200                .get_value = ctrl_freq_get,
1201                .is_dirty = ctrl_freq_is_dirty,
1202                .clear_dirty = ctrl_freq_clear_dirty,
1203                DEFINT(0,0),
1204                /* Hook in check for input value (tv/radio) and adjust
1205                   max/min values accordingly */
1206                .get_max_value = ctrl_freq_max_get,
1207                .get_min_value = ctrl_freq_min_get,
1208        },{
1209                .desc = "Channel",
1210                .name = "channel",
1211                .set_value = ctrl_channel_set,
1212                .get_value = ctrl_channel_get,
1213                DEFINT(0,FREQTABLE_SIZE),
1214        },{
1215                .desc = "Channel Program Frequency",
1216                .name = "freq_table_value",
1217                .set_value = ctrl_channelfreq_set,
1218                .get_value = ctrl_channelfreq_get,
1219                DEFINT(0,0),
1220                /* Hook in check for input value (tv/radio) and adjust
1221                   max/min values accordingly */
1222                .get_max_value = ctrl_freq_max_get,
1223                .get_min_value = ctrl_freq_min_get,
1224        },{
1225                .desc = "Channel Program ID",
1226                .name = "freq_table_channel",
1227                .set_value = ctrl_channelprog_set,
1228                .get_value = ctrl_channelprog_get,
1229                DEFINT(0,FREQTABLE_SIZE),
1230        },{
1231                .desc = "Streaming Enabled",
1232                .name = "streaming_enabled",
1233                .get_value = ctrl_streamingenabled_get,
1234                DEFBOOL,
1235        },{
1236                .desc = "USB Speed",
1237                .name = "usb_speed",
1238                .get_value = ctrl_hsm_get,
1239                DEFENUM(control_values_hsm),
1240        },{
1241                .desc = "Master State",
1242                .name = "master_state",
1243                .get_value = ctrl_masterstate_get,
1244                DEFENUM(pvr2_state_names),
1245        },{
1246                .desc = "Signal Present",
1247                .name = "signal_present",
1248                .get_value = ctrl_signal_get,
1249                DEFINT(0,65535),
1250        },{
1251                .desc = "Audio Modes Present",
1252                .name = "audio_modes_present",
1253                .get_value = ctrl_audio_modes_present_get,
1254                /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1255                   v4l.  Nothing outside of this module cares about this,
1256                   but I reuse it in order to also reuse the
1257                   control_values_audiomode string table. */
1258                DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1259                         (1 << V4L2_TUNER_MODE_STEREO)|
1260                         (1 << V4L2_TUNER_MODE_LANG1)|
1261                         (1 << V4L2_TUNER_MODE_LANG2)),
1262                        control_values_audiomode),
1263        },{
1264                .desc = "Video Standards Available Mask",
1265                .name = "video_standard_mask_available",
1266                .internal_id = PVR2_CID_STDAVAIL,
1267                .skip_init = !0,
1268                .get_value = ctrl_stdavail_get,
1269                .set_value = ctrl_stdavail_set,
1270                .val_to_sym = ctrl_std_val_to_sym,
1271                .sym_to_val = ctrl_std_sym_to_val,
1272                .type = pvr2_ctl_bitmask,
1273        },{
1274                .desc = "Video Standards In Use Mask",
1275                .name = "video_standard_mask_active",
1276                .internal_id = PVR2_CID_STDCUR,
1277                .skip_init = !0,
1278                .get_value = ctrl_stdcur_get,
1279                .set_value = ctrl_stdcur_set,
1280                .is_dirty = ctrl_stdcur_is_dirty,
1281                .clear_dirty = ctrl_stdcur_clear_dirty,
1282                .val_to_sym = ctrl_std_val_to_sym,
1283                .sym_to_val = ctrl_std_sym_to_val,
1284                .type = pvr2_ctl_bitmask,
1285        },{
1286                .desc = "Video Standard Name",
1287                .name = "video_standard",
1288                .internal_id = PVR2_CID_STDENUM,
1289                .skip_init = !0,
1290                .get_value = ctrl_stdenumcur_get,
1291                .set_value = ctrl_stdenumcur_set,
1292                .is_dirty = ctrl_stdenumcur_is_dirty,
1293                .clear_dirty = ctrl_stdenumcur_clear_dirty,
1294                .type = pvr2_ctl_enum,
1295        }
1296};
1297
1298#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1299
1300
1301const char *pvr2_config_get_name(enum pvr2_config cfg)
1302{
1303        switch (cfg) {
1304        case pvr2_config_empty: return "empty";
1305        case pvr2_config_mpeg: return "mpeg";
1306        case pvr2_config_vbi: return "vbi";
1307        case pvr2_config_pcm: return "pcm";
1308        case pvr2_config_rawvideo: return "raw video";
1309        }
1310        return "<unknown>";
1311}
1312
1313
1314struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1315{
1316        return hdw->usb_dev;
1317}
1318
1319
1320unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1321{
1322        return hdw->serial_number;
1323}
1324
1325
1326const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1327{
1328        return hdw->bus_info;
1329}
1330
1331
1332const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1333{
1334        return hdw->identifier;
1335}
1336
1337
1338unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1339{
1340        return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1341}
1342
1343/* Set the currently tuned frequency and account for all possible
1344   driver-core side effects of this action. */
1345static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1346{
1347        if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1348                if (hdw->freqSelector) {
1349                        /* Swing over to radio frequency selection */
1350                        hdw->freqSelector = 0;
1351                        hdw->freqDirty = !0;
1352                }
1353                if (hdw->freqValRadio != val) {
1354                        hdw->freqValRadio = val;
1355                        hdw->freqSlotRadio = 0;
1356                        hdw->freqDirty = !0;
1357                }
1358        } else {
1359                if (!(hdw->freqSelector)) {
1360                        /* Swing over to television frequency selection */
1361                        hdw->freqSelector = 1;
1362                        hdw->freqDirty = !0;
1363                }
1364                if (hdw->freqValTelevision != val) {
1365                        hdw->freqValTelevision = val;
1366                        hdw->freqSlotTelevision = 0;
1367                        hdw->freqDirty = !0;
1368                }
1369        }
1370}
1371
1372int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1373{
1374        return hdw->unit_number;
1375}
1376
1377
1378/* Attempt to locate one of the given set of files.  Messages are logged
1379   appropriate to what has been found.  The return value will be 0 or
1380   greater on success (it will be the index of the file name found) and
1381   fw_entry will be filled in.  Otherwise a negative error is returned on
1382   failure.  If the return value is -ENOENT then no viable firmware file
1383   could be located. */
1384static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1385                                const struct firmware **fw_entry,
1386                                const char *fwtypename,
1387                                unsigned int fwcount,
1388                                const char *fwnames[])
1389{
1390        unsigned int idx;
1391        int ret = -EINVAL;
1392        for (idx = 0; idx < fwcount; idx++) {
1393                ret = request_firmware(fw_entry,
1394                                       fwnames[idx],
1395                                       &hdw->usb_dev->dev);
1396                if (!ret) {
1397                        trace_firmware("Located %s firmware: %s;"
1398                                       " uploading...",
1399                                       fwtypename,
1400                                       fwnames[idx]);
1401                        return idx;
1402                }
1403                if (ret == -ENOENT) continue;
1404                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1405                           "request_firmware fatal error with code=%d",ret);
1406                return ret;
1407        }
1408        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1409                   "***WARNING***"
1410                   " Device %s firmware"
1411                   " seems to be missing.",
1412                   fwtypename);
1413        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1414                   "Did you install the pvrusb2 firmware files"
1415                   " in their proper location?");
1416        if (fwcount == 1) {
1417                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1418                           "request_firmware unable to locate %s file %s",
1419                           fwtypename,fwnames[0]);
1420        } else {
1421                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1422                           "request_firmware unable to locate"
1423                           " one of the following %s files:",
1424                           fwtypename);
1425                for (idx = 0; idx < fwcount; idx++) {
1426                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1427                                   "request_firmware: Failed to find %s",
1428                                   fwnames[idx]);
1429                }
1430        }
1431        return ret;
1432}
1433
1434
1435/*
1436 * pvr2_upload_firmware1().
1437 *
1438 * Send the 8051 firmware to the device.  After the upload, arrange for
1439 * device to re-enumerate.
1440 *
1441 * NOTE : the pointer to the firmware data given by request_firmware()
1442 * is not suitable for an usb transaction.
1443 *
1444 */
1445static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1446{
1447        const struct firmware *fw_entry = NULL;
1448        void  *fw_ptr;
1449        unsigned int pipe;
1450        int ret;
1451        u16 address;
1452
1453        if (!hdw->hdw_desc->fx2_firmware.cnt) {
1454                hdw->fw1_state = FW1_STATE_OK;
1455                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1456                           "Connected device type defines"
1457                           " no firmware to upload; ignoring firmware");
1458                return -ENOTTY;
1459        }
1460
1461        hdw->fw1_state = FW1_STATE_FAILED; // default result
1462
1463        trace_firmware("pvr2_upload_firmware1");
1464
1465        ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1466                                   hdw->hdw_desc->fx2_firmware.cnt,
1467                                   hdw->hdw_desc->fx2_firmware.lst);
1468        if (ret < 0) {
1469                if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1470                return ret;
1471        }
1472
1473        usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1474
1475        pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1476
1477        if (fw_entry->size != 0x2000){
1478                pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1479                release_firmware(fw_entry);
1480                return -ENOMEM;
1481        }
1482
1483        fw_ptr = kmalloc(0x800, GFP_KERNEL);
1484        if (fw_ptr == NULL){
1485                release_firmware(fw_entry);
1486                return -ENOMEM;
1487        }
1488
1489        /* We have to hold the CPU during firmware upload. */
1490        pvr2_hdw_cpureset_assert(hdw,1);
1491
1492        /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1493           chunk. */
1494
1495        ret = 0;
1496        for(address = 0; address < fw_entry->size; address += 0x800) {
1497                memcpy(fw_ptr, fw_entry->data + address, 0x800);
1498                ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1499                                       0, fw_ptr, 0x800, HZ);
1500        }
1501
1502        trace_firmware("Upload done, releasing device's CPU");
1503
1504        /* Now release the CPU.  It will disconnect and reconnect later. */
1505        pvr2_hdw_cpureset_assert(hdw,0);
1506
1507        kfree(fw_ptr);
1508        release_firmware(fw_entry);
1509
1510        trace_firmware("Upload done (%d bytes sent)",ret);
1511
1512        /* We should have written 8192 bytes */
1513        if (ret == 8192) {
1514                hdw->fw1_state = FW1_STATE_RELOAD;
1515                return 0;
1516        }
1517
1518        return -EIO;
1519}
1520
1521
1522/*
1523 * pvr2_upload_firmware2()
1524 *
1525 * This uploads encoder firmware on endpoint 2.
1526 *
1527 */
1528
1529int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1530{
1531        const struct firmware *fw_entry = NULL;
1532        void  *fw_ptr;
1533        unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1534        int actual_length;
1535        int ret = 0;
1536        int fwidx;
1537        static const char *fw_files[] = {
1538                CX2341X_FIRM_ENC_FILENAME,
1539        };
1540
1541        if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1542                return 0;
1543        }
1544
1545        trace_firmware("pvr2_upload_firmware2");
1546
1547        ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1548                                   ARRAY_SIZE(fw_files), fw_files);
1549        if (ret < 0) return ret;
1550        fwidx = ret;
1551        ret = 0;
1552        /* Since we're about to completely reinitialize the encoder,
1553           invalidate our cached copy of its configuration state.  Next
1554           time we configure the encoder, then we'll fully configure it. */
1555        hdw->enc_cur_valid = 0;
1556
1557        /* Encoder is about to be reset so note that as far as we're
1558           concerned now, the encoder has never been run. */
1559        del_timer_sync(&hdw->encoder_run_timer);
1560        if (hdw->state_encoder_runok) {
1561                hdw->state_encoder_runok = 0;
1562                trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1563        }
1564
1565        /* First prepare firmware loading */
1566        ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1567        ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1568        ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1569        ret |= pvr2_hdw_cmd_deep_reset(hdw);
1570        ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1571        ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1572        ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1573        ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1574        ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1575        ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1576        ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1577        ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1578        ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1579        ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1580        ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1581        ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1582        ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1583        ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1584
1585        if (ret) {
1586                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1587                           "firmware2 upload prep failed, ret=%d",ret);
1588                release_firmware(fw_entry);
1589                goto done;
1590        }
1591
1592        /* Now send firmware */
1593
1594        fw_len = fw_entry->size;
1595
1596        if (fw_len % sizeof(u32)) {
1597                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1598                           "size of %s firmware"
1599                           " must be a multiple of %zu bytes",
1600                           fw_files[fwidx],sizeof(u32));
1601                release_firmware(fw_entry);
1602                ret = -EINVAL;
1603                goto done;
1604        }
1605
1606        fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1607        if (fw_ptr == NULL){
1608                release_firmware(fw_entry);
1609                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1610                           "failed to allocate memory for firmware2 upload");
1611                ret = -ENOMEM;
1612                goto done;
1613        }
1614
1615        pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1616
1617        fw_done = 0;
1618        for (fw_done = 0; fw_done < fw_len;) {
1619                bcnt = fw_len - fw_done;
1620                if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1621                memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1622                /* Usbsnoop log shows that we must swap bytes... */
1623                /* Some background info: The data being swapped here is a
1624                   firmware image destined for the mpeg encoder chip that
1625                   lives at the other end of a USB endpoint.  The encoder
1626                   chip always talks in 32 bit chunks and its storage is
1627                   organized into 32 bit words.  However from the file
1628                   system to the encoder chip everything is purely a byte
1629                   stream.  The firmware file's contents are always 32 bit
1630                   swapped from what the encoder expects.  Thus the need
1631                   always exists to swap the bytes regardless of the endian
1632                   type of the host processor and therefore swab32() makes
1633                   the most sense. */
1634                for (icnt = 0; icnt < bcnt/4 ; icnt++)
1635                        ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1636
1637                ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1638                                    &actual_length, HZ);
1639                ret |= (actual_length != bcnt);
1640                if (ret) break;
1641                fw_done += bcnt;
1642        }
1643
1644        trace_firmware("upload of %s : %i / %i ",
1645                       fw_files[fwidx],fw_done,fw_len);
1646
1647        kfree(fw_ptr);
1648        release_firmware(fw_entry);
1649
1650        if (ret) {
1651                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1652                           "firmware2 upload transfer failure");
1653                goto done;
1654        }
1655
1656        /* Finish upload */
1657
1658        ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1659        ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1660        ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1661
1662        if (ret) {
1663                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1664                           "firmware2 upload post-proc failure");
1665        }
1666
1667 done:
1668        if (hdw->hdw_desc->signal_routing_scheme ==
1669            PVR2_ROUTING_SCHEME_GOTVIEW) {
1670                /* Ensure that GPIO 11 is set to output for GOTVIEW
1671                   hardware. */
1672                pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1673        }
1674        return ret;
1675}
1676
1677
1678static const char *pvr2_get_state_name(unsigned int st)
1679{
1680        if (st < ARRAY_SIZE(pvr2_state_names)) {
1681                return pvr2_state_names[st];
1682        }
1683        return "???";
1684}
1685
1686static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1687{
1688        /* Even though we really only care about the video decoder chip at
1689           this point, we'll broadcast stream on/off to all sub-devices
1690           anyway, just in case somebody else wants to hear the
1691           command... */
1692        pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1693                   (enablefl ? "on" : "off"));
1694        v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1695        if (hdw->decoder_client_id) {
1696                /* We get here if the encoder has been noticed.  Otherwise
1697                   we'll issue a warning to the user (which should
1698                   normally never happen). */
1699                return 0;
1700        }
1701        if (!hdw->flag_decoder_missed) {
1702                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1703                           "WARNING: No decoder present");
1704                hdw->flag_decoder_missed = !0;
1705                trace_stbit("flag_decoder_missed",
1706                            hdw->flag_decoder_missed);
1707        }
1708        return -EIO;
1709}
1710
1711
1712int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1713{
1714        return hdw->master_state;
1715}
1716
1717
1718static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1719{
1720        if (!hdw->flag_tripped) return 0;
1721        hdw->flag_tripped = 0;
1722        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1723                   "Clearing driver error statuss");
1724        return !0;
1725}
1726
1727
1728int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1729{
1730        int fl;
1731        LOCK_TAKE(hdw->big_lock); do {
1732                fl = pvr2_hdw_untrip_unlocked(hdw);
1733        } while (0); LOCK_GIVE(hdw->big_lock);
1734        if (fl) pvr2_hdw_state_sched(hdw);
1735        return 0;
1736}
1737
1738
1739
1740
1741int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1742{
1743        return hdw->state_pipeline_req != 0;
1744}
1745
1746
1747int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1748{
1749        int ret,st;
1750        LOCK_TAKE(hdw->big_lock); do {
1751                pvr2_hdw_untrip_unlocked(hdw);
1752                if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1753                        hdw->state_pipeline_req = enable_flag != 0;
1754                        pvr2_trace(PVR2_TRACE_START_STOP,
1755                                   "/*--TRACE_STREAM--*/ %s",
1756                                   enable_flag ? "enable" : "disable");
1757                }
1758                pvr2_hdw_state_sched(hdw);
1759        } while (0); LOCK_GIVE(hdw->big_lock);
1760        if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1761        if (enable_flag) {
1762                while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1763                        if (st != PVR2_STATE_READY) return -EIO;
1764                        if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1765                }
1766        }
1767        return 0;
1768}
1769
1770
1771int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1772{
1773        int fl;
1774        LOCK_TAKE(hdw->big_lock);
1775        if ((fl = (hdw->desired_stream_type != config)) != 0) {
1776                hdw->desired_stream_type = config;
1777                hdw->state_pipeline_config = 0;
1778                trace_stbit("state_pipeline_config",
1779                            hdw->state_pipeline_config);
1780                pvr2_hdw_state_sched(hdw);
1781        }
1782        LOCK_GIVE(hdw->big_lock);
1783        if (fl) return 0;
1784        return pvr2_hdw_wait(hdw,0);
1785}
1786
1787
1788static int get_default_tuner_type(struct pvr2_hdw *hdw)
1789{
1790        int unit_number = hdw->unit_number;
1791        int tp = -1;
1792        if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1793                tp = tuner[unit_number];
1794        }
1795        if (tp < 0) return -EINVAL;
1796        hdw->tuner_type = tp;
1797        hdw->tuner_updated = !0;
1798        return 0;
1799}
1800
1801
1802static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1803{
1804        int unit_number = hdw->unit_number;
1805        int tp = 0;
1806        if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1807                tp = video_std[unit_number];
1808                if (tp) return tp;
1809        }
1810        return 0;
1811}
1812
1813
1814static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1815{
1816        int unit_number = hdw->unit_number;
1817        int tp = 0;
1818        if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1819                tp = tolerance[unit_number];
1820        }
1821        return tp;
1822}
1823
1824
1825static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1826{
1827        /* Try a harmless request to fetch the eeprom's address over
1828           endpoint 1.  See what happens.  Only the full FX2 image can
1829           respond to this.  If this probe fails then likely the FX2
1830           firmware needs be loaded. */
1831        int result;
1832        LOCK_TAKE(hdw->ctl_lock); do {
1833                hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1834                result = pvr2_send_request_ex(hdw,HZ*1,!0,
1835                                           hdw->cmd_buffer,1,
1836                                           hdw->cmd_buffer,1);
1837                if (result < 0) break;
1838        } while(0); LOCK_GIVE(hdw->ctl_lock);
1839        if (result) {
1840                pvr2_trace(PVR2_TRACE_INIT,
1841                           "Probe of device endpoint 1 result status %d",
1842                           result);
1843        } else {
1844                pvr2_trace(PVR2_TRACE_INIT,
1845                           "Probe of device endpoint 1 succeeded");
1846        }
1847        return result == 0;
1848}
1849
1850struct pvr2_std_hack {
1851        v4l2_std_id pat;  /* Pattern to match */
1852        v4l2_std_id msk;  /* Which bits we care about */
1853        v4l2_std_id std;  /* What additional standards or default to set */
1854};
1855
1856/* This data structure labels specific combinations of standards from
1857   tveeprom that we'll try to recognize.  If we recognize one, then assume
1858   a specified default standard to use.  This is here because tveeprom only
1859   tells us about available standards not the intended default standard (if
1860   any) for the device in question.  We guess the default based on what has
1861   been reported as available.  Note that this is only for guessing a
1862   default - which can always be overridden explicitly - and if the user
1863   has otherwise named a default then that default will always be used in
1864   place of this table. */
1865static const struct pvr2_std_hack std_eeprom_maps[] = {
1866        {       /* PAL(B/G) */
1867                .pat = V4L2_STD_B|V4L2_STD_GH,
1868                .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1869        },
1870        {       /* NTSC(M) */
1871                .pat = V4L2_STD_MN,
1872                .std = V4L2_STD_NTSC_M,
1873        },
1874        {       /* PAL(I) */
1875                .pat = V4L2_STD_PAL_I,
1876                .std = V4L2_STD_PAL_I,
1877        },
1878        {       /* SECAM(L/L') */
1879                .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1880                .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1881        },
1882        {       /* PAL(D/D1/K) */
1883                .pat = V4L2_STD_DK,
1884                .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1885        },
1886};
1887
1888static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1889{
1890        char buf[40];
1891        unsigned int bcnt;
1892        v4l2_std_id std1,std2,std3;
1893
1894        std1 = get_default_standard(hdw);
1895        std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1896
1897        bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1898        pvr2_trace(PVR2_TRACE_STD,
1899                   "Supported video standard(s) reported available"
1900                   " in hardware: %.*s",
1901                   bcnt,buf);
1902
1903        hdw->std_mask_avail = hdw->std_mask_eeprom;
1904
1905        std2 = (std1|std3) & ~hdw->std_mask_avail;
1906        if (std2) {
1907                bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1908                pvr2_trace(PVR2_TRACE_STD,
1909                           "Expanding supported video standards"
1910                           " to include: %.*s",
1911                           bcnt,buf);
1912                hdw->std_mask_avail |= std2;
1913        }
1914
1915        pvr2_hdw_internal_set_std_avail(hdw);
1916
1917        if (std1) {
1918                bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1919                pvr2_trace(PVR2_TRACE_STD,
1920                           "Initial video standard forced to %.*s",
1921                           bcnt,buf);
1922                hdw->std_mask_cur = std1;
1923                hdw->std_dirty = !0;
1924                pvr2_hdw_internal_find_stdenum(hdw);
1925                return;
1926        }
1927        if (std3) {
1928                bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1929                pvr2_trace(PVR2_TRACE_STD,
1930                           "Initial video standard"
1931                           " (determined by device type): %.*s",bcnt,buf);
1932                hdw->std_mask_cur = std3;
1933                hdw->std_dirty = !0;
1934                pvr2_hdw_internal_find_stdenum(hdw);
1935                return;
1936        }
1937
1938        {
1939                unsigned int idx;
1940                for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1941                        if (std_eeprom_maps[idx].msk ?
1942                            ((std_eeprom_maps[idx].pat ^
1943                             hdw->std_mask_eeprom) &
1944                             std_eeprom_maps[idx].msk) :
1945                            (std_eeprom_maps[idx].pat !=
1946                             hdw->std_mask_eeprom)) continue;
1947                        bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1948                                                  std_eeprom_maps[idx].std);
1949                        pvr2_trace(PVR2_TRACE_STD,
1950                                   "Initial video standard guessed as %.*s",
1951                                   bcnt,buf);
1952                        hdw->std_mask_cur = std_eeprom_maps[idx].std;
1953                        hdw->std_dirty = !0;
1954                        pvr2_hdw_internal_find_stdenum(hdw);
1955                        return;
1956                }
1957        }
1958
1959        if (hdw->std_enum_cnt > 1) {
1960                // Autoselect the first listed standard
1961                hdw->std_enum_cur = 1;
1962                hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1963                hdw->std_dirty = !0;
1964                pvr2_trace(PVR2_TRACE_STD,
1965                           "Initial video standard auto-selected to %s",
1966                           hdw->std_defs[hdw->std_enum_cur-1].name);
1967                return;
1968        }
1969
1970        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1971                   "Unable to select a viable initial video standard");
1972}
1973
1974
1975static unsigned int pvr2_copy_i2c_addr_list(
1976        unsigned short *dst, const unsigned char *src,
1977        unsigned int dst_max)
1978{
1979        unsigned int cnt = 0;
1980        if (!src) return 0;
1981        while (src[cnt] && (cnt + 1) < dst_max) {
1982                dst[cnt] = src[cnt];
1983                cnt++;
1984        }
1985        dst[cnt] = I2C_CLIENT_END;
1986        return cnt;
1987}
1988
1989
1990static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1991{
1992        /*
1993          Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
1994          for cx25840 causes that module to correctly set up its video
1995          scaling.  This is really a problem in the cx25840 module itself,
1996          but we work around it here.  The problem has not been seen in
1997          ivtv because there VBI is supported and set up.  We don't do VBI
1998          here (at least not yet) and thus we never attempted to even set
1999          it up.
2000        */
2001        struct v4l2_format fmt;
2002        if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2003                /* We're not using a cx25840 so don't enable the hack */
2004                return;
2005        }
2006
2007        pvr2_trace(PVR2_TRACE_INIT,
2008                   "Module ID %u:"
2009                   " Executing cx25840 VBI hack",
2010                   hdw->decoder_client_id);
2011        memset(&fmt, 0, sizeof(fmt));
2012        fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2013        v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
2014                             video, s_fmt, &fmt);
2015}
2016
2017
2018static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2019                                const struct pvr2_device_client_desc *cd)
2020{
2021        const char *fname;
2022        unsigned char mid;
2023        struct v4l2_subdev *sd;
2024        unsigned int i2ccnt;
2025        const unsigned char *p;
2026        /* Arbitrary count - max # i2c addresses we will probe */
2027        unsigned short i2caddr[25];
2028
2029        mid = cd->module_id;
2030        fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2031        if (!fname) {
2032                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2033                           "Module ID %u for device %s has no name",
2034                           mid,
2035                           hdw->hdw_desc->description);
2036                return -EINVAL;
2037        }
2038        pvr2_trace(PVR2_TRACE_INIT,
2039                   "Module ID %u (%s) for device %s being loaded...",
2040                   mid, fname,
2041                   hdw->hdw_desc->description);
2042
2043        i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2044                                         ARRAY_SIZE(i2caddr));
2045        if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2046                         module_i2c_addresses[mid] : NULL) != NULL)) {
2047                /* Second chance: Try default i2c address list */
2048                i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2049                                                 ARRAY_SIZE(i2caddr));
2050                if (i2ccnt) {
2051                        pvr2_trace(PVR2_TRACE_INIT,
2052                                   "Module ID %u:"
2053                                   " Using default i2c address list",
2054                                   mid);
2055                }
2056        }
2057
2058        if (!i2ccnt) {
2059                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2060                           "Module ID %u (%s) for device %s:"
2061                           " No i2c addresses",
2062                           mid, fname, hdw->hdw_desc->description);
2063                return -EINVAL;
2064        }
2065
2066        /* Note how the 2nd and 3rd arguments are the same for
2067         * v4l2_i2c_new_subdev().  Why?
2068         * Well the 2nd argument is the module name to load, while the 3rd
2069         * argument is documented in the framework as being the "chipid" -
2070         * and every other place where I can find examples of this, the
2071         * "chipid" appears to just be the module name again.  So here we
2072         * just do the same thing. */
2073        if (i2ccnt == 1) {
2074                pvr2_trace(PVR2_TRACE_INIT,
2075                           "Module ID %u:"
2076                           " Setting up with specified i2c address 0x%x",
2077                           mid, i2caddr[0]);
2078                sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2079                                         fname, fname,
2080                                         i2caddr[0], NULL);
2081        } else {
2082                pvr2_trace(PVR2_TRACE_INIT,
2083                           "Module ID %u:"
2084                           " Setting up with address probe list",
2085                           mid);
2086                sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2087                                                fname, fname,
2088                                                0, i2caddr);
2089        }
2090
2091        if (!sd) {
2092                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2093                           "Module ID %u (%s) for device %s failed to load",
2094                           mid, fname, hdw->hdw_desc->description);
2095                return -EIO;
2096        }
2097
2098        /* Tag this sub-device instance with the module ID we know about.
2099           In other places we'll use that tag to determine if the instance
2100           requires special handling. */
2101        sd->grp_id = mid;
2102
2103        pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2104
2105
2106        /* client-specific setup... */
2107        switch (mid) {
2108        case PVR2_CLIENT_ID_CX25840:
2109        case PVR2_CLIENT_ID_SAA7115:
2110                hdw->decoder_client_id = mid;
2111                break;
2112        default: break;
2113        }
2114
2115        return 0;
2116}
2117
2118
2119static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2120{
2121        unsigned int idx;
2122        const struct pvr2_string_table *cm;
2123        const struct pvr2_device_client_table *ct;
2124        int okFl = !0;
2125
2126        cm = &hdw->hdw_desc->client_modules;
2127        for (idx = 0; idx < cm->cnt; idx++) {
2128                request_module(cm->lst[idx]);
2129        }
2130
2131        ct = &hdw->hdw_desc->client_table;
2132        for (idx = 0; idx < ct->cnt; idx++) {
2133                if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2134        }
2135        if (!okFl) pvr2_hdw_render_useless(hdw);
2136}
2137
2138
2139static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2140{
2141        int ret;
2142        unsigned int idx;
2143        struct pvr2_ctrl *cptr;
2144        int reloadFl = 0;
2145        if (hdw->hdw_desc->fx2_firmware.cnt) {
2146                if (!reloadFl) {
2147                        reloadFl =
2148                                (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2149                                 == 0);
2150                        if (reloadFl) {
2151                                pvr2_trace(PVR2_TRACE_INIT,
2152                                           "USB endpoint config looks strange"
2153                                           "; possibly firmware needs to be"
2154                                           " loaded");
2155                        }
2156                }
2157                if (!reloadFl) {
2158                        reloadFl = !pvr2_hdw_check_firmware(hdw);
2159                        if (reloadFl) {
2160                                pvr2_trace(PVR2_TRACE_INIT,
2161                                           "Check for FX2 firmware failed"
2162                                           "; possibly firmware needs to be"
2163                                           " loaded");
2164                        }
2165                }
2166                if (reloadFl) {
2167                        if (pvr2_upload_firmware1(hdw) != 0) {
2168                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2169                                           "Failure uploading firmware1");
2170                        }
2171                        return;
2172                }
2173        }
2174        hdw->fw1_state = FW1_STATE_OK;
2175
2176        if (!pvr2_hdw_dev_ok(hdw)) return;
2177
2178        hdw->force_dirty = !0;
2179
2180        if (!hdw->hdw_desc->flag_no_powerup) {
2181                pvr2_hdw_cmd_powerup(hdw);
2182                if (!pvr2_hdw_dev_ok(hdw)) return;
2183        }
2184
2185        /* Take the IR chip out of reset, if appropriate */
2186        if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2187                pvr2_issue_simple_cmd(hdw,
2188                                      FX2CMD_HCW_ZILOG_RESET |
2189                                      (1 << 8) |
2190                                      ((0) << 16));
2191        }
2192
2193        // This step MUST happen after the earlier powerup step.
2194        pvr2_i2c_core_init(hdw);
2195        if (!pvr2_hdw_dev_ok(hdw)) return;
2196
2197        pvr2_hdw_load_modules(hdw);
2198        if (!pvr2_hdw_dev_ok(hdw)) return;
2199
2200        v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2201
2202        for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2203                cptr = hdw->controls + idx;
2204                if (cptr->info->skip_init) continue;
2205                if (!cptr->info->set_value) continue;
2206                cptr->info->set_value(cptr,~0,cptr->info->default_value);
2207        }
2208
2209        pvr2_hdw_cx25840_vbi_hack(hdw);
2210
2211        /* Set up special default values for the television and radio
2212           frequencies here.  It's not really important what these defaults
2213           are, but I set them to something usable in the Chicago area just
2214           to make driver testing a little easier. */
2215
2216        hdw->freqValTelevision = default_tv_freq;
2217        hdw->freqValRadio = default_radio_freq;
2218
2219        // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2220        // thread-safe against the normal pvr2_send_request() mechanism.
2221        // (We should make it thread safe).
2222
2223        if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2224                ret = pvr2_hdw_get_eeprom_addr(hdw);
2225                if (!pvr2_hdw_dev_ok(hdw)) return;
2226                if (ret < 0) {
2227                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2228                                   "Unable to determine location of eeprom,"
2229                                   " skipping");
2230                } else {
2231                        hdw->eeprom_addr = ret;
2232                        pvr2_eeprom_analyze(hdw);
2233                        if (!pvr2_hdw_dev_ok(hdw)) return;
2234                }
2235        } else {
2236                hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2237                hdw->tuner_updated = !0;
2238                hdw->std_mask_eeprom = V4L2_STD_ALL;
2239        }
2240
2241        if (hdw->serial_number) {
2242                idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2243                                "sn-%lu", hdw->serial_number);
2244        } else if (hdw->unit_number >= 0) {
2245                idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2246                                "unit-%c",
2247                                hdw->unit_number + 'a');
2248        } else {
2249                idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2250                                "unit-??");
2251        }
2252        hdw->identifier[idx] = 0;
2253
2254        pvr2_hdw_setup_std(hdw);
2255
2256        if (!get_default_tuner_type(hdw)) {
2257                pvr2_trace(PVR2_TRACE_INIT,
2258                           "pvr2_hdw_setup: Tuner type overridden to %d",
2259                           hdw->tuner_type);
2260        }
2261
2262
2263        if (!pvr2_hdw_dev_ok(hdw)) return;
2264
2265        if (hdw->hdw_desc->signal_routing_scheme ==
2266            PVR2_ROUTING_SCHEME_GOTVIEW) {
2267                /* Ensure that GPIO 11 is set to output for GOTVIEW
2268                   hardware. */
2269                pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2270        }
2271
2272        pvr2_hdw_commit_setup(hdw);
2273
2274        hdw->vid_stream = pvr2_stream_create();
2275        if (!pvr2_hdw_dev_ok(hdw)) return;
2276        pvr2_trace(PVR2_TRACE_INIT,
2277                   "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2278        if (hdw->vid_stream) {
2279                idx = get_default_error_tolerance(hdw);
2280                if (idx) {
2281                        pvr2_trace(PVR2_TRACE_INIT,
2282                                   "pvr2_hdw_setup: video stream %p"
2283                                   " setting tolerance %u",
2284                                   hdw->vid_stream,idx);
2285                }
2286                pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2287                                  PVR2_VID_ENDPOINT,idx);
2288        }
2289
2290        if (!pvr2_hdw_dev_ok(hdw)) return;
2291
2292        hdw->flag_init_ok = !0;
2293
2294        pvr2_hdw_state_sched(hdw);
2295}
2296
2297
2298/* Set up the structure and attempt to put the device into a usable state.
2299   This can be a time-consuming operation, which is why it is not done
2300   internally as part of the create() step. */
2301static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2302{
2303        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2304        do {
2305                pvr2_hdw_setup_low(hdw);
2306                pvr2_trace(PVR2_TRACE_INIT,
2307                           "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2308                           hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2309                if (pvr2_hdw_dev_ok(hdw)) {
2310                        if (hdw->flag_init_ok) {
2311                                pvr2_trace(
2312                                        PVR2_TRACE_INFO,
2313                                        "Device initialization"
2314                                        " completed successfully.");
2315                                break;
2316                        }
2317                        if (hdw->fw1_state == FW1_STATE_RELOAD) {
2318                                pvr2_trace(
2319                                        PVR2_TRACE_INFO,
2320                                        "Device microcontroller firmware"
2321                                        " (re)loaded; it should now reset"
2322                                        " and reconnect.");
2323                                break;
2324                        }
2325                        pvr2_trace(
2326                                PVR2_TRACE_ERROR_LEGS,
2327                                "Device initialization was not successful.");
2328                        if (hdw->fw1_state == FW1_STATE_MISSING) {
2329                                pvr2_trace(
2330                                        PVR2_TRACE_ERROR_LEGS,
2331                                        "Giving up since device"
2332                                        " microcontroller firmware"
2333                                        " appears to be missing.");
2334                                break;
2335                        }
2336                }
2337                if (procreload) {
2338                        pvr2_trace(
2339                                PVR2_TRACE_ERROR_LEGS,
2340                                "Attempting pvrusb2 recovery by reloading"
2341                                " primary firmware.");
2342                        pvr2_trace(
2343                                PVR2_TRACE_ERROR_LEGS,
2344                                "If this works, device should disconnect"
2345                                " and reconnect in a sane state.");
2346                        hdw->fw1_state = FW1_STATE_UNKNOWN;
2347                        pvr2_upload_firmware1(hdw);
2348                } else {
2349                        pvr2_trace(
2350                                PVR2_TRACE_ERROR_LEGS,
2351                                "***WARNING*** pvrusb2 device hardware"
2352                                " appears to be jammed"
2353                                " and I can't clear it.");
2354                        pvr2_trace(
2355                                PVR2_TRACE_ERROR_LEGS,
2356                                "You might need to power cycle"
2357                                " the pvrusb2 device"
2358                                " in order to recover.");
2359                }
2360        } while (0);
2361        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2362}
2363
2364
2365/* Perform second stage initialization.  Set callback pointer first so that
2366   we can avoid a possible initialization race (if the kernel thread runs
2367   before the callback has been set). */
2368int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2369                        void (*callback_func)(void *),
2370                        void *callback_data)
2371{
2372        LOCK_TAKE(hdw->big_lock); do {
2373                if (hdw->flag_disconnected) {
2374                        /* Handle a race here: If we're already
2375                           disconnected by this point, then give up.  If we
2376                           get past this then we'll remain connected for
2377                           the duration of initialization since the entire
2378                           initialization sequence is now protected by the
2379                           big_lock. */
2380                        break;
2381                }
2382                hdw->state_data = callback_data;
2383                hdw->state_func = callback_func;
2384                pvr2_hdw_setup(hdw);
2385        } while (0); LOCK_GIVE(hdw->big_lock);
2386        return hdw->flag_init_ok;
2387}
2388
2389
2390/* Create, set up, and return a structure for interacting with the
2391   underlying hardware.  */
2392struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2393                                 const struct usb_device_id *devid)
2394{
2395        unsigned int idx,cnt1,cnt2,m;
2396        struct pvr2_hdw *hdw = NULL;
2397        int valid_std_mask;
2398        struct pvr2_ctrl *cptr;
2399        struct usb_device *usb_dev;
2400        const struct pvr2_device_desc *hdw_desc;
2401        __u8 ifnum;
2402        struct v4l2_queryctrl qctrl;
2403        struct pvr2_ctl_info *ciptr;
2404
2405        usb_dev = interface_to_usbdev(intf);
2406
2407        hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2408
2409        if (hdw_desc == NULL) {
2410                pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2411                           " No device description pointer,"
2412                           " unable to continue.");
2413                pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2414                           " please contact Mike Isely <isely@pobox.com>"
2415                           " to get it included in the driver\n");
2416                goto fail;
2417        }
2418
2419        hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2420        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2421                   hdw,hdw_desc->description);
2422        if (!hdw) goto fail;
2423
2424        init_timer(&hdw->quiescent_timer);
2425        hdw->quiescent_timer.data = (unsigned long)hdw;
2426        hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2427
2428        init_timer(&hdw->encoder_wait_timer);
2429        hdw->encoder_wait_timer.data = (unsigned long)hdw;
2430        hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2431
2432        init_timer(&hdw->encoder_run_timer);
2433        hdw->encoder_run_timer.data = (unsigned long)hdw;
2434        hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2435
2436        hdw->master_state = PVR2_STATE_DEAD;
2437
2438        init_waitqueue_head(&hdw->state_wait_data);
2439
2440        hdw->tuner_signal_stale = !0;
2441        cx2341x_fill_defaults(&hdw->enc_ctl_state);
2442
2443        /* Calculate which inputs are OK */
2444        m = 0;
2445        if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2446        if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2447                m |= 1 << PVR2_CVAL_INPUT_DTV;
2448        }
2449        if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2450        if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2451        if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2452        hdw->input_avail_mask = m;
2453        hdw->input_allowed_mask = hdw->input_avail_mask;
2454
2455        /* If not a hybrid device, pathway_state never changes.  So
2456           initialize it here to what it should forever be. */
2457        if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2458                hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2459        } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2460                hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2461        }
2462
2463        hdw->control_cnt = CTRLDEF_COUNT;
2464        hdw->control_cnt += MPEGDEF_COUNT;
2465        hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2466                                GFP_KERNEL);
2467        if (!hdw->controls) goto fail;
2468        hdw->hdw_desc = hdw_desc;
2469        hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2470        for (idx = 0; idx < hdw->control_cnt; idx++) {
2471                cptr = hdw->controls + idx;
2472                cptr->hdw = hdw;
2473        }
2474        for (idx = 0; idx < 32; idx++) {
2475                hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2476        }
2477        for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2478                cptr = hdw->controls + idx;
2479                cptr->info = control_defs+idx;
2480        }
2481
2482        /* Ensure that default input choice is a valid one. */
2483        m = hdw->input_avail_mask;
2484        if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2485                if (!((1 << idx) & m)) continue;
2486                hdw->input_val = idx;
2487                break;
2488        }
2489
2490        /* Define and configure additional controls from cx2341x module. */
2491        hdw->mpeg_ctrl_info = kzalloc(
2492                sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2493        if (!hdw->mpeg_ctrl_info) goto fail;
2494        for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2495                cptr = hdw->controls + idx + CTRLDEF_COUNT;
2496                ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2497                ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2498                ciptr->name = mpeg_ids[idx].strid;
2499                ciptr->v4l_id = mpeg_ids[idx].id;
2500                ciptr->skip_init = !0;
2501                ciptr->get_value = ctrl_cx2341x_get;
2502                ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2503                ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2504                if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2505                qctrl.id = ciptr->v4l_id;
2506                cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2507                if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2508                        ciptr->set_value = ctrl_cx2341x_set;
2509                }
2510                strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2511                        PVR2_CTLD_INFO_DESC_SIZE);
2512                hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2513                ciptr->default_value = qctrl.default_value;
2514                switch (qctrl.type) {
2515                default:
2516                case V4L2_CTRL_TYPE_INTEGER:
2517                        ciptr->type = pvr2_ctl_int;
2518                        ciptr->def.type_int.min_value = qctrl.minimum;
2519                        ciptr->def.type_int.max_value = qctrl.maximum;
2520                        break;
2521                case V4L2_CTRL_TYPE_BOOLEAN:
2522                        ciptr->type = pvr2_ctl_bool;
2523                        break;
2524                case V4L2_CTRL_TYPE_MENU:
2525                        ciptr->type = pvr2_ctl_enum;
2526                        ciptr->def.type_enum.value_names =
2527                                cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2528                                                                ciptr->v4l_id);
2529                        for (cnt1 = 0;
2530                             ciptr->def.type_enum.value_names[cnt1] != NULL;
2531                             cnt1++) { }
2532                        ciptr->def.type_enum.count = cnt1;
2533                        break;
2534                }
2535                cptr->info = ciptr;
2536        }
2537
2538        // Initialize video standard enum dynamic control
2539        cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2540        if (cptr) {
2541                memcpy(&hdw->std_info_enum,cptr->info,
2542                       sizeof(hdw->std_info_enum));
2543                cptr->info = &hdw->std_info_enum;
2544
2545        }
2546        // Initialize control data regarding video standard masks
2547        valid_std_mask = pvr2_std_get_usable();
2548        for (idx = 0; idx < 32; idx++) {
2549                if (!(valid_std_mask & (1 << idx))) continue;
2550                cnt1 = pvr2_std_id_to_str(
2551                        hdw->std_mask_names[idx],
2552                        sizeof(hdw->std_mask_names[idx])-1,
2553                        1 << idx);
2554                hdw->std_mask_names[idx][cnt1] = 0;
2555        }
2556        cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2557        if (cptr) {
2558                memcpy(&hdw->std_info_avail,cptr->info,
2559                       sizeof(hdw->std_info_avail));
2560                cptr->info = &hdw->std_info_avail;
2561                hdw->std_info_avail.def.type_bitmask.bit_names =
2562                        hdw->std_mask_ptrs;
2563                hdw->std_info_avail.def.type_bitmask.valid_bits =
2564                        valid_std_mask;
2565        }
2566        cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2567        if (cptr) {
2568                memcpy(&hdw->std_info_cur,cptr->info,
2569                       sizeof(hdw->std_info_cur));
2570                cptr->info = &hdw->std_info_cur;
2571                hdw->std_info_cur.def.type_bitmask.bit_names =
2572                        hdw->std_mask_ptrs;
2573                hdw->std_info_avail.def.type_bitmask.valid_bits =
2574                        valid_std_mask;
2575        }
2576
2577        hdw->cropcap_stale = !0;
2578        hdw->eeprom_addr = -1;
2579        hdw->unit_number = -1;
2580        hdw->v4l_minor_number_video = -1;
2581        hdw->v4l_minor_number_vbi = -1;
2582        hdw->v4l_minor_number_radio = -1;
2583        hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2584        if (!hdw->ctl_write_buffer) goto fail;
2585        hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2586        if (!hdw->ctl_read_buffer) goto fail;
2587        hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2588        if (!hdw->ctl_write_urb) goto fail;
2589        hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2590        if (!hdw->ctl_read_urb) goto fail;
2591
2592        if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2593                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2594                           "Error registering with v4l core, giving up");
2595                goto fail;
2596        }
2597        mutex_lock(&pvr2_unit_mtx); do {
2598                for (idx = 0; idx < PVR_NUM; idx++) {
2599                        if (unit_pointers[idx]) continue;
2600                        hdw->unit_number = idx;
2601                        unit_pointers[idx] = hdw;
2602                        break;
2603                }
2604        } while (0); mutex_unlock(&pvr2_unit_mtx);
2605
2606        cnt1 = 0;
2607        cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2608        cnt1 += cnt2;
2609        if (hdw->unit_number >= 0) {
2610                cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2611                                 ('a' + hdw->unit_number));
2612                cnt1 += cnt2;
2613        }
2614        if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2615        hdw->name[cnt1] = 0;
2616
2617        hdw->workqueue = create_singlethread_workqueue(hdw->name);
2618        INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2619
2620        pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2621                   hdw->unit_number,hdw->name);
2622
2623        hdw->tuner_type = -1;
2624        hdw->flag_ok = !0;
2625
2626        hdw->usb_intf = intf;
2627        hdw->usb_dev = usb_dev;
2628
2629        usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2630
2631        ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2632        usb_set_interface(hdw->usb_dev,ifnum,0);
2633
2634        mutex_init(&hdw->ctl_lock_mutex);
2635        mutex_init(&hdw->big_lock_mutex);
2636
2637        return hdw;
2638 fail:
2639        if (hdw) {
2640                del_timer_sync(&hdw->quiescent_timer);
2641                del_timer_sync(&hdw->encoder_run_timer);
2642                del_timer_sync(&hdw->encoder_wait_timer);
2643                if (hdw->workqueue) {
2644                        flush_workqueue(hdw->workqueue);
2645                        destroy_workqueue(hdw->workqueue);
2646                        hdw->workqueue = NULL;
2647                }
2648                usb_free_urb(hdw->ctl_read_urb);
2649                usb_free_urb(hdw->ctl_write_urb);
2650                kfree(hdw->ctl_read_buffer);
2651                kfree(hdw->ctl_write_buffer);
2652                kfree(hdw->controls);
2653                kfree(hdw->mpeg_ctrl_info);
2654                kfree(hdw->std_defs);
2655                kfree(hdw->std_enum_names);
2656                kfree(hdw);
2657        }
2658        return NULL;
2659}
2660
2661
2662/* Remove _all_ associations between this driver and the underlying USB
2663   layer. */
2664static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2665{
2666        if (hdw->flag_disconnected) return;
2667        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2668        if (hdw->ctl_read_urb) {
2669                usb_kill_urb(hdw->ctl_read_urb);
2670                usb_free_urb(hdw->ctl_read_urb);
2671                hdw->ctl_read_urb = NULL;
2672        }
2673        if (hdw->ctl_write_urb) {
2674                usb_kill_urb(hdw->ctl_write_urb);
2675                usb_free_urb(hdw->ctl_write_urb);
2676                hdw->ctl_write_urb = NULL;
2677        }
2678        if (hdw->ctl_read_buffer) {
2679                kfree(hdw->ctl_read_buffer);
2680                hdw->ctl_read_buffer = NULL;
2681        }
2682        if (hdw->ctl_write_buffer) {
2683                kfree(hdw->ctl_write_buffer);
2684                hdw->ctl_write_buffer = NULL;
2685        }
2686        hdw->flag_disconnected = !0;
2687        /* If we don't do this, then there will be a dangling struct device
2688           reference to our disappearing device persisting inside the V4L
2689           core... */
2690        v4l2_device_disconnect(&hdw->v4l2_dev);
2691        hdw->usb_dev = NULL;
2692        hdw->usb_intf = NULL;
2693        pvr2_hdw_render_useless(hdw);
2694}
2695
2696
2697/* Destroy hardware interaction structure */
2698void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2699{
2700        if (!hdw) return;
2701        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2702        if (hdw->workqueue) {
2703                flush_workqueue(hdw->workqueue);
2704                destroy_workqueue(hdw->workqueue);
2705                hdw->workqueue = NULL;
2706        }
2707        del_timer_sync(&hdw->quiescent_timer);
2708        del_timer_sync(&hdw->encoder_run_timer);
2709        del_timer_sync(&hdw->encoder_wait_timer);
2710        if (hdw->fw_buffer) {
2711                kfree(hdw->fw_buffer);
2712                hdw->fw_buffer = NULL;
2713        }
2714        if (hdw->vid_stream) {
2715                pvr2_stream_destroy(hdw->vid_stream);
2716                hdw->vid_stream = NULL;
2717        }
2718        pvr2_i2c_core_done(hdw);
2719        v4l2_device_unregister(&hdw->v4l2_dev);
2720        pvr2_hdw_remove_usb_stuff(hdw);
2721        mutex_lock(&pvr2_unit_mtx); do {
2722                if ((hdw->unit_number >= 0) &&
2723                    (hdw->unit_number < PVR_NUM) &&
2724                    (unit_pointers[hdw->unit_number] == hdw)) {
2725                        unit_pointers[hdw->unit_number] = NULL;
2726                }
2727        } while (0); mutex_unlock(&pvr2_unit_mtx);
2728        kfree(hdw->controls);
2729        kfree(hdw->mpeg_ctrl_info);
2730        kfree(hdw->std_defs);
2731        kfree(hdw->std_enum_names);
2732        kfree(hdw);
2733}
2734
2735
2736int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2737{
2738        return (hdw && hdw->flag_ok);
2739}
2740
2741
2742/* Called when hardware has been unplugged */
2743void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2744{
2745        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2746        LOCK_TAKE(hdw->big_lock);
2747        LOCK_TAKE(hdw->ctl_lock);
2748        pvr2_hdw_remove_usb_stuff(hdw);
2749        LOCK_GIVE(hdw->ctl_lock);
2750        LOCK_GIVE(hdw->big_lock);
2751}
2752
2753
2754// Attempt to autoselect an appropriate value for std_enum_cur given
2755// whatever is currently in std_mask_cur
2756static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2757{
2758        unsigned int idx;
2759        for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2760                if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2761                        hdw->std_enum_cur = idx;
2762                        return;
2763                }
2764        }
2765        hdw->std_enum_cur = 0;
2766}
2767
2768
2769// Calculate correct set of enumerated standards based on currently known
2770// set of available standards bits.
2771static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2772{
2773        struct v4l2_standard *newstd;
2774        unsigned int std_cnt;
2775        unsigned int idx;
2776
2777        newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2778
2779        if (hdw->std_defs) {
2780                kfree(hdw->std_defs);
2781                hdw->std_defs = NULL;
2782        }
2783        hdw->std_enum_cnt = 0;
2784        if (hdw->std_enum_names) {
2785                kfree(hdw->std_enum_names);
2786                hdw->std_enum_names = NULL;
2787        }
2788
2789        if (!std_cnt) {
2790                pvr2_trace(
2791                        PVR2_TRACE_ERROR_LEGS,
2792                        "WARNING: Failed to identify any viable standards");
2793        }
2794        hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2795        hdw->std_enum_names[0] = "none";
2796        for (idx = 0; idx < std_cnt; idx++) {
2797                hdw->std_enum_names[idx+1] =
2798                        newstd[idx].name;
2799        }
2800        // Set up the dynamic control for this standard
2801        hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2802        hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2803        hdw->std_defs = newstd;
2804        hdw->std_enum_cnt = std_cnt+1;
2805        hdw->std_enum_cur = 0;
2806        hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2807}
2808
2809
2810int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2811                               struct v4l2_standard *std,
2812                               unsigned int idx)
2813{
2814        int ret = -EINVAL;
2815        if (!idx) return ret;
2816        LOCK_TAKE(hdw->big_lock); do {
2817                if (idx >= hdw->std_enum_cnt) break;
2818                idx--;
2819                memcpy(std,hdw->std_defs+idx,sizeof(*std));
2820                ret = 0;
2821        } while (0); LOCK_GIVE(hdw->big_lock);
2822        return ret;
2823}
2824
2825
2826/* Get the number of defined controls */
2827unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2828{
2829        return hdw->control_cnt;
2830}
2831
2832
2833/* Retrieve a control handle given its index (0..count-1) */
2834struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2835                                             unsigned int idx)
2836{
2837        if (idx >= hdw->control_cnt) return NULL;
2838        return hdw->controls + idx;
2839}
2840
2841
2842/* Retrieve a control handle given its index (0..count-1) */
2843struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2844                                          unsigned int ctl_id)
2845{
2846        struct pvr2_ctrl *cptr;
2847        unsigned int idx;
2848        int i;
2849
2850        /* This could be made a lot more efficient, but for now... */
2851        for (idx = 0; idx < hdw->control_cnt; idx++) {
2852                cptr = hdw->controls + idx;
2853                i = cptr->info->internal_id;
2854                if (i && (i == ctl_id)) return cptr;
2855        }
2856        return NULL;
2857}
2858
2859
2860/* Given a V4L ID, retrieve the control structure associated with it. */
2861struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2862{
2863        struct pvr2_ctrl *cptr;
2864        unsigned int idx;
2865        int i;
2866
2867        /* This could be made a lot more efficient, but for now... */
2868        for (idx = 0; idx < hdw->control_cnt; idx++) {
2869                cptr = hdw->controls + idx;
2870                i = cptr->info->v4l_id;
2871                if (i && (i == ctl_id)) return cptr;
2872        }
2873        return NULL;
2874}
2875
2876
2877/* Given a V4L ID for its immediate predecessor, retrieve the control
2878   structure associated with it. */
2879struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2880                                            unsigned int ctl_id)
2881{
2882        struct pvr2_ctrl *cptr,*cp2;
2883        unsigned int idx;
2884        int i;
2885
2886        /* This could be made a lot more efficient, but for now... */
2887        cp2 = NULL;
2888        for (idx = 0; idx < hdw->control_cnt; idx++) {
2889                cptr = hdw->controls + idx;
2890                i = cptr->info->v4l_id;
2891                if (!i) continue;
2892                if (i <= ctl_id) continue;
2893                if (cp2 && (cp2->info->v4l_id < i)) continue;
2894                cp2 = cptr;
2895        }
2896        return cp2;
2897        return NULL;
2898}
2899
2900
2901static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2902{
2903        switch (tp) {
2904        case pvr2_ctl_int: return "integer";
2905        case pvr2_ctl_enum: return "enum";
2906        case pvr2_ctl_bool: return "boolean";
2907        case pvr2_ctl_bitmask: return "bitmask";
2908        }
2909        return "";
2910}
2911
2912
2913static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2914                                    const char *name, int val)
2915{
2916        struct v4l2_control ctrl;
2917        pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2918        memset(&ctrl, 0, sizeof(ctrl));
2919        ctrl.id = id;
2920        ctrl.value = val;
2921        v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2922}
2923
2924#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2925        if ((hdw)->lab##_dirty || (hdw)->force_dirty) {         \
2926                pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2927        }
2928
2929/* Execute whatever commands are required to update the state of all the
2930   sub-devices so that they match our current control values. */
2931static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2932{
2933        struct v4l2_subdev *sd;
2934        unsigned int id;
2935        pvr2_subdev_update_func fp;
2936
2937        pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2938
2939        if (hdw->tuner_updated || hdw->force_dirty) {
2940                struct tuner_setup setup;
2941                pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2942                           hdw->tuner_type);
2943                if (((int)(hdw->tuner_type)) >= 0) {
2944                        memset(&setup, 0, sizeof(setup));
2945                        setup.addr = ADDR_UNSET;
2946                        setup.type = hdw->tuner_type;
2947                        setup.mode_mask = T_RADIO | T_ANALOG_TV;
2948                        v4l2_device_call_all(&hdw->v4l2_dev, 0,
2949                                             tuner, s_type_addr, &setup);
2950                }
2951        }
2952
2953        if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2954                pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2955                if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2956                        v4l2_device_call_all(&hdw->v4l2_dev, 0,
2957                                             tuner, s_radio);
2958                } else {
2959                        v4l2_std_id vs;
2960                        vs = hdw->std_mask_cur;
2961                        v4l2_device_call_all(&hdw->v4l2_dev, 0,
2962                                             core, s_std, vs);
2963                        pvr2_hdw_cx25840_vbi_hack(hdw);
2964                }
2965                hdw->tuner_signal_stale = !0;
2966                hdw->cropcap_stale = !0;
2967        }
2968
2969        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2970        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2971        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2972        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2973        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2974        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2975        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2976        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2977        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2978
2979        if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2980                struct v4l2_tuner vt;
2981                memset(&vt, 0, sizeof(vt));
2982                vt.audmode = hdw->audiomode_val;
2983                v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2984        }
2985
2986        if (hdw->freqDirty || hdw->force_dirty) {
2987                unsigned long fv;
2988                struct v4l2_frequency freq;
2989                fv = pvr2_hdw_get_cur_freq(hdw);
2990                pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2991                if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2992                memset(&freq, 0, sizeof(freq));
2993                if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2994                        /* ((fv * 1000) / 62500) */
2995                        freq.frequency = (fv * 2) / 125;
2996                } else {
2997                        freq.frequency = fv / 62500;
2998                }
2999                /* tuner-core currently doesn't seem to care about this, but
3000                   let's set it anyway for completeness. */
3001                if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3002                        freq.type = V4L2_TUNER_RADIO;
3003                } else {
3004                        freq.type = V4L2_TUNER_ANALOG_TV;
3005                }
3006                freq.tuner = 0;
3007                v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3008                                     s_frequency, &freq);
3009        }
3010
3011        if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
3012                struct v4l2_format fmt;
3013                memset(&fmt, 0, sizeof(fmt));
3014                fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
3015                fmt.fmt.pix.width = hdw->res_hor_val;
3016                fmt.fmt.pix.height = hdw->res_ver_val;
3017                pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
3018                           fmt.fmt.pix.width, fmt.fmt.pix.height);
3019                v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3020        }
3021
3022        if (hdw->srate_dirty || hdw->force_dirty) {
3023                u32 val;
3024                pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3025                           hdw->srate_val);
3026                switch (hdw->srate_val) {
3027                default:
3028                case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3029                        val = 48000;
3030                        break;
3031                case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3032                        val = 44100;
3033                        break;
3034                case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3035                        val = 32000;
3036                        break;
3037                }
3038                v4l2_device_call_all(&hdw->v4l2_dev, 0,
3039                                     audio, s_clock_freq, val);
3040        }
3041
3042        /* Unable to set crop parameters; there is apparently no equivalent
3043           for VIDIOC_S_CROP */
3044
3045        v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3046                id = sd->grp_id;
3047                if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3048                fp = pvr2_module_update_functions[id];
3049                if (!fp) continue;
3050                (*fp)(hdw, sd);
3051        }
3052
3053        if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
3054                pvr2_hdw_status_poll(hdw);
3055        }
3056}
3057
3058
3059/* Figure out if we need to commit control changes.  If so, mark internal
3060   state flags to indicate this fact and return true.  Otherwise do nothing
3061   else and return false. */
3062static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3063{
3064        unsigned int idx;
3065        struct pvr2_ctrl *cptr;
3066        int value;
3067        int commit_flag = hdw->force_dirty;
3068        char buf[100];
3069        unsigned int bcnt,ccnt;
3070
3071        for (idx = 0; idx < hdw->control_cnt; idx++) {
3072                cptr = hdw->controls + idx;
3073                if (!cptr->info->is_dirty) continue;
3074                if (!cptr->info->is_dirty(cptr)) continue;
3075                commit_flag = !0;
3076
3077                if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3078                bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3079                                 cptr->info->name);
3080                value = 0;
3081                cptr->info->get_value(cptr,&value);
3082                pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3083                                                buf+bcnt,
3084                                                sizeof(buf)-bcnt,&ccnt);
3085                bcnt += ccnt;
3086                bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3087                                  get_ctrl_typename(cptr->info->type));
3088                pvr2_trace(PVR2_TRACE_CTL,
3089                           "/*--TRACE_COMMIT--*/ %.*s",
3090                           bcnt,buf);
3091        }
3092
3093        if (!commit_flag) {
3094                /* Nothing has changed */
3095                return 0;
3096        }
3097
3098        hdw->state_pipeline_config = 0;
3099        trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3100        pvr2_hdw_state_sched(hdw);
3101
3102        return !0;
3103}
3104
3105
3106/* Perform all operations needed to commit all control changes.  This must
3107   be performed in synchronization with the pipeline state and is thus
3108   expected to be called as part of the driver's worker thread.  Return
3109   true if commit successful, otherwise return false to indicate that
3110   commit isn't possible at this time. */
3111static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3112{
3113        unsigned int idx;
3114        struct pvr2_ctrl *cptr;
3115        int disruptive_change;
3116
3117        /* Handle some required side effects when the video standard is
3118           changed.... */
3119        if (hdw->std_dirty) {
3120                int nvres;
3121                int gop_size;
3122                if (hdw->std_mask_cur & V4L2_STD_525_60) {
3123                        nvres = 480;
3124                        gop_size = 15;
3125                } else {
3126                        nvres = 576;
3127                        gop_size = 12;
3128                }
3129                /* Rewrite the vertical resolution to be appropriate to the
3130                   video standard that has been selected. */
3131                if (nvres != hdw->res_ver_val) {
3132                        hdw->res_ver_val = nvres;
3133                        hdw->res_ver_dirty = !0;
3134                }
3135                /* Rewrite the GOP size to be appropriate to the video
3136                   standard that has been selected. */
3137                if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3138                        struct v4l2_ext_controls cs;
3139                        struct v4l2_ext_control c1;
3140                        memset(&cs, 0, sizeof(cs));
3141                        memset(&c1, 0, sizeof(c1));
3142                        cs.controls = &c1;
3143                        cs.count = 1;
3144                        c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3145                        c1.value = gop_size;
3146                        cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3147                                          VIDIOC_S_EXT_CTRLS);
3148                }
3149        }
3150
3151        if (hdw->input_dirty && hdw->state_pathway_ok &&
3152            (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3153              PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3154             hdw->pathway_state)) {
3155                /* Change of mode being asked for... */
3156                hdw->state_pathway_ok = 0;
3157                trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3158        }
3159        if (!hdw->state_pathway_ok) {
3160                /* Can't commit anything until pathway is ok. */
3161                return 0;
3162        }
3163        /* The broadcast decoder can only scale down, so if
3164         * res_*_dirty && crop window < output format ==> enlarge crop.
3165         *
3166         * The mpeg encoder receives fields of res_hor_val dots and
3167         * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3168         */
3169        if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3170                hdw->cropw_val = hdw->res_hor_val;
3171                hdw->cropw_dirty = !0;
3172        } else if (hdw->cropw_dirty) {
3173                hdw->res_hor_dirty = !0;           /* must rescale */
3174                hdw->res_hor_val = min(720, hdw->cropw_val);
3175        }
3176        if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3177                hdw->croph_val = hdw->res_ver_val;
3178                hdw->croph_dirty = !0;
3179        } else if (hdw->croph_dirty) {
3180                int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3181                hdw->res_ver_dirty = !0;
3182                hdw->res_ver_val = min(nvres, hdw->croph_val);
3183        }
3184
3185        /* If any of the below has changed, then we can't do the update
3186           while the pipeline is running.  Pipeline must be paused first
3187           and decoder -> encoder connection be made quiescent before we
3188           can proceed. */
3189        disruptive_change =
3190                (hdw->std_dirty ||
3191                 hdw->enc_unsafe_stale ||
3192                 hdw->srate_dirty ||
3193                 hdw->res_ver_dirty ||
3194                 hdw->res_hor_dirty ||
3195                 hdw->cropw_dirty ||
3196                 hdw->croph_dirty ||
3197                 hdw->input_dirty ||
3198                 (hdw->active_stream_type != hdw->desired_stream_type));
3199        if (disruptive_change && !hdw->state_pipeline_idle) {
3200                /* Pipeline is not idle; we can't proceed.  Arrange to
3201                   cause pipeline to stop so that we can try this again
3202                   later.... */
3203                hdw->state_pipeline_pause = !0;
3204                return 0;
3205        }
3206
3207        if (hdw->srate_dirty) {
3208                /* Write new sample rate into control structure since
3209                 * the master copy is stale.  We must track srate
3210                 * separate from the mpeg control structure because
3211                 * other logic also uses this value. */
3212                struct v4l2_ext_controls cs;
3213                struct v4l2_ext_control c1;
3214                memset(&cs,0,sizeof(cs));
3215                memset(&c1,0,sizeof(c1));
3216                cs.controls = &c1;
3217                cs.count = 1;
3218                c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3219                c1.value = hdw->srate_val;
3220                cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3221        }
3222
3223        if (hdw->active_stream_type != hdw->desired_stream_type) {
3224                /* Handle any side effects of stream config here */
3225                hdw->active_stream_type = hdw->desired_stream_type;
3226        }
3227
3228        if (hdw->hdw_desc->signal_routing_scheme ==
3229            PVR2_ROUTING_SCHEME_GOTVIEW) {
3230                u32 b;
3231                /* Handle GOTVIEW audio switching */
3232                pvr2_hdw_gpio_get_out(hdw,&b);
3233                if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3234                        /* Set GPIO 11 */
3235                        pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3236                } else {
3237                        /* Clear GPIO 11 */
3238                        pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3239                }
3240        }
3241
3242        /* Check and update state for all sub-devices. */
3243        pvr2_subdev_update(hdw);
3244
3245        hdw->tuner_updated = 0;
3246        hdw->force_dirty = 0;
3247        for (idx = 0; idx < hdw->control_cnt; idx++) {
3248                cptr = hdw->controls + idx;
3249                if (!cptr->info->clear_dirty) continue;
3250                cptr->info->clear_dirty(cptr);
3251        }
3252
3253        if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3254            hdw->state_encoder_run) {
3255                /* If encoder isn't running or it can't be touched, then
3256                   this will get worked out later when we start the
3257                   encoder. */
3258                if (pvr2_encoder_adjust(hdw) < 0) return !0;
3259        }
3260
3261        hdw->state_pipeline_config = !0;
3262        /* Hardware state may have changed in a way to cause the cropping
3263           capabilities to have changed.  So mark it stale, which will
3264           cause a later re-fetch. */
3265        trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3266        return !0;
3267}
3268
3269
3270int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3271{
3272        int fl;
3273        LOCK_TAKE(hdw->big_lock);
3274        fl = pvr2_hdw_commit_setup(hdw);
3275        LOCK_GIVE(hdw->big_lock);
3276        if (!fl) return 0;
3277        return pvr2_hdw_wait(hdw,0);
3278}
3279
3280
3281static void pvr2_hdw_worker_poll(struct work_struct *work)
3282{
3283        int fl = 0;
3284        struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3285        LOCK_TAKE(hdw->big_lock); do {
3286                fl = pvr2_hdw_state_eval(hdw);
3287        } while (0); LOCK_GIVE(hdw->big_lock);
3288        if (fl && hdw->state_func) {
3289                hdw->state_func(hdw->state_data);
3290        }
3291}
3292
3293
3294static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3295{
3296        return wait_event_interruptible(
3297                hdw->state_wait_data,
3298                (hdw->state_stale == 0) &&
3299                (!state || (hdw->master_state != state)));
3300}
3301
3302
3303/* Return name for this driver instance */
3304const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3305{
3306        return hdw->name;
3307}
3308
3309
3310const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3311{
3312        return hdw->hdw_desc->description;
3313}
3314
3315
3316const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3317{
3318        return hdw->hdw_desc->shortname;
3319}
3320
3321
3322int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3323{
3324        int result;
3325        LOCK_TAKE(hdw->ctl_lock); do {
3326                hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3327                result = pvr2_send_request(hdw,
3328                                           hdw->cmd_buffer,1,
3329                                           hdw->cmd_buffer,1);
3330                if (result < 0) break;
3331                result = (hdw->cmd_buffer[0] != 0);
3332        } while(0); LOCK_GIVE(hdw->ctl_lock);
3333        return result;
3334}
3335
3336
3337/* Execute poll of tuner status */
3338void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3339{
3340        LOCK_TAKE(hdw->big_lock); do {
3341                pvr2_hdw_status_poll(hdw);
3342        } while (0); LOCK_GIVE(hdw->big_lock);
3343}
3344
3345
3346static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3347{
3348        if (!hdw->cropcap_stale) {
3349                return 0;
3350        }
3351        pvr2_hdw_status_poll(hdw);
3352        if (hdw->cropcap_stale) {
3353                return -EIO;
3354        }
3355        return 0;
3356}
3357
3358
3359/* Return information about cropping capabilities */
3360int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3361{
3362        int stat = 0;
3363        LOCK_TAKE(hdw->big_lock);
3364        stat = pvr2_hdw_check_cropcap(hdw);
3365        if (!stat) {
3366                memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3367        }
3368        LOCK_GIVE(hdw->big_lock);
3369        return stat;
3370}
3371
3372
3373/* Return information about the tuner */
3374int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3375{
3376        LOCK_TAKE(hdw->big_lock); do {
3377                if (hdw->tuner_signal_stale) {
3378                        pvr2_hdw_status_poll(hdw);
3379                }
3380                memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3381        } while (0); LOCK_GIVE(hdw->big_lock);
3382        return 0;
3383}
3384
3385
3386/* Get handle to video output stream */
3387struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3388{
3389        return hp->vid_stream;
3390}
3391
3392
3393void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3394{
3395        int nr = pvr2_hdw_get_unit_number(hdw);
3396        LOCK_TAKE(hdw->big_lock); do {
3397                printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3398                v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3399                pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3400                cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3401                pvr2_hdw_state_log_state(hdw);
3402                printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3403        } while (0); LOCK_GIVE(hdw->big_lock);
3404}
3405
3406
3407/* Grab EEPROM contents, needed for direct method. */
3408#define EEPROM_SIZE 8192
3409#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3410static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3411{
3412        struct i2c_msg msg[2];
3413        u8 *eeprom;
3414        u8 iadd[2];
3415        u8 addr;
3416        u16 eepromSize;
3417        unsigned int offs;
3418        int ret;
3419        int mode16 = 0;
3420        unsigned pcnt,tcnt;
3421        eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3422        if (!eeprom) {
3423                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3424                           "Failed to allocate memory"
3425                           " required to read eeprom");
3426                return NULL;
3427        }
3428
3429        trace_eeprom("Value for eeprom addr from controller was 0x%x",
3430                     hdw->eeprom_addr);
3431        addr = hdw->eeprom_addr;
3432        /* Seems that if the high bit is set, then the *real* eeprom
3433           address is shifted right now bit position (noticed this in
3434           newer PVR USB2 hardware) */
3435        if (addr & 0x80) addr >>= 1;
3436
3437        /* FX2 documentation states that a 16bit-addressed eeprom is
3438           expected if the I2C address is an odd number (yeah, this is
3439           strange but it's what they do) */
3440        mode16 = (addr & 1);
3441        eepromSize = (mode16 ? EEPROM_SIZE : 256);
3442        trace_eeprom("Examining %d byte eeprom at location 0x%x"
3443                     " using %d bit addressing",eepromSize,addr,
3444                     mode16 ? 16 : 8);
3445
3446        msg[0].addr = addr;
3447        msg[0].flags = 0;
3448        msg[0].len = mode16 ? 2 : 1;
3449        msg[0].buf = iadd;
3450        msg[1].addr = addr;
3451        msg[1].flags = I2C_M_RD;
3452
3453        /* We have to do the actual eeprom data fetch ourselves, because
3454           (1) we're only fetching part of the eeprom, and (2) if we were
3455           getting the whole thing our I2C driver can't grab it in one
3456           pass - which is what tveeprom is otherwise going to attempt */
3457        memset(eeprom,0,EEPROM_SIZE);
3458        for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3459                pcnt = 16;
3460                if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3461                offs = tcnt + (eepromSize - EEPROM_SIZE);
3462                if (mode16) {
3463                        iadd[0] = offs >> 8;
3464                        iadd[1] = offs;
3465                } else {
3466                        iadd[0] = offs;
3467                }
3468                msg[1].len = pcnt;
3469                msg[1].buf = eeprom+tcnt;
3470                if ((ret = i2c_transfer(&hdw->i2c_adap,
3471                                        msg,ARRAY_SIZE(msg))) != 2) {
3472                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3473                                   "eeprom fetch set offs err=%d",ret);
3474                        kfree(eeprom);
3475                        return NULL;
3476                }
3477        }
3478        return eeprom;
3479}
3480
3481
3482void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3483                                int prom_flag,
3484                                int enable_flag)
3485{
3486        int ret;
3487        u16 address;
3488        unsigned int pipe;
3489        LOCK_TAKE(hdw->big_lock); do {
3490                if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3491
3492                if (!enable_flag) {
3493                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3494                                   "Cleaning up after CPU firmware fetch");
3495                        kfree(hdw->fw_buffer);
3496                        hdw->fw_buffer = NULL;
3497                        hdw->fw_size = 0;
3498                        if (hdw->fw_cpu_flag) {
3499                                /* Now release the CPU.  It will disconnect
3500                                   and reconnect later. */
3501                                pvr2_hdw_cpureset_assert(hdw,0);
3502                        }
3503                        break;
3504                }
3505
3506                hdw->fw_cpu_flag = (prom_flag == 0);
3507                if (hdw->fw_cpu_flag) {
3508                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3509                                   "Preparing to suck out CPU firmware");
3510                        hdw->fw_size = 0x2000;
3511                        hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3512                        if (!hdw->fw_buffer) {
3513                                hdw->fw_size = 0;
3514                                break;
3515                        }
3516
3517                        /* We have to hold the CPU during firmware upload. */
3518                        pvr2_hdw_cpureset_assert(hdw,1);
3519
3520                        /* download the firmware from address 0000-1fff in 2048
3521                           (=0x800) bytes chunk. */
3522
3523                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3524                                   "Grabbing CPU firmware");
3525                        pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3526                        for(address = 0; address < hdw->fw_size;
3527                            address += 0x800) {
3528                                ret = usb_control_msg(hdw->usb_dev,pipe,
3529                                                      0xa0,0xc0,
3530                                                      address,0,
3531                                                      hdw->fw_buffer+address,
3532                                                      0x800,HZ);
3533                                if (ret < 0) break;
3534                        }
3535
3536                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3537                                   "Done grabbing CPU firmware");
3538                } else {
3539                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3540                                   "Sucking down EEPROM contents");
3541                        hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3542                        if (!hdw->fw_buffer) {
3543                                pvr2_trace(PVR2_TRACE_FIRMWARE,
3544                                           "EEPROM content suck failed.");
3545                                break;
3546                        }
3547                        hdw->fw_size = EEPROM_SIZE;
3548                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3549                                   "Done sucking down EEPROM contents");
3550                }
3551
3552        } while (0); LOCK_GIVE(hdw->big_lock);
3553}
3554
3555
3556/* Return true if we're in a mode for retrieval CPU firmware */
3557int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3558{
3559        return hdw->fw_buffer != NULL;
3560}
3561
3562
3563int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3564                       char *buf,unsigned int cnt)
3565{
3566        int ret = -EINVAL;
3567        LOCK_TAKE(hdw->big_lock); do {
3568                if (!buf) break;
3569                if (!cnt) break;
3570
3571                if (!hdw->fw_buffer) {
3572                        ret = -EIO;
3573                        break;
3574                }
3575
3576                if (offs >= hdw->fw_size) {
3577                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3578                                   "Read firmware data offs=%d EOF",
3579                                   offs);
3580                        ret = 0;
3581                        break;
3582                }
3583
3584                if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3585
3586                memcpy(buf,hdw->fw_buffer+offs,cnt);
3587
3588                pvr2_trace(PVR2_TRACE_FIRMWARE,
3589                           "Read firmware data offs=%d cnt=%d",
3590                           offs,cnt);
3591                ret = cnt;
3592        } while (0); LOCK_GIVE(hdw->big_lock);
3593
3594        return ret;
3595}
3596
3597
3598int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3599                                  enum pvr2_v4l_type index)
3600{
3601        switch (index) {
3602        case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3603        case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3604        case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3605        default: return -1;
3606        }
3607}
3608
3609
3610/* Store a v4l minor device number */
3611void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3612                                     enum pvr2_v4l_type index,int v)
3613{
3614        switch (index) {
3615        case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3616        case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3617        case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3618        default: break;
3619        }
3620}
3621
3622
3623static void pvr2_ctl_write_complete(struct urb *urb)
3624{
3625        struct pvr2_hdw *hdw = urb->context;
3626        hdw->ctl_write_pend_flag = 0;
3627        if (hdw->ctl_read_pend_flag) return;
3628        complete(&hdw->ctl_done);
3629}
3630
3631
3632static void pvr2_ctl_read_complete(struct urb *urb)
3633{
3634        struct pvr2_hdw *hdw = urb->context;
3635        hdw->ctl_read_pend_flag = 0;
3636        if (hdw->ctl_write_pend_flag) return;
3637        complete(&hdw->ctl_done);
3638}
3639
3640
3641static void pvr2_ctl_timeout(unsigned long data)
3642{
3643        struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3644        if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3645                hdw->ctl_timeout_flag = !0;
3646                if (hdw->ctl_write_pend_flag)
3647                        usb_unlink_urb(hdw->ctl_write_urb);
3648                if (hdw->ctl_read_pend_flag)
3649                        usb_unlink_urb(hdw->ctl_read_urb);
3650        }
3651}
3652
3653
3654/* Issue a command and get a response from the device.  This extended
3655   version includes a probe flag (which if set means that device errors
3656   should not be logged or treated as fatal) and a timeout in jiffies.
3657   This can be used to non-lethally probe the health of endpoint 1. */
3658static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3659                                unsigned int timeout,int probe_fl,
3660                                void *write_data,unsigned int write_len,
3661                                void *read_data,unsigned int read_len)
3662{
3663        unsigned int idx;
3664        int status = 0;
3665        struct timer_list timer;
3666        if (!hdw->ctl_lock_held) {
3667                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3668                           "Attempted to execute control transfer"
3669                           " without lock!!");
3670                return -EDEADLK;
3671        }
3672        if (!hdw->flag_ok && !probe_fl) {
3673                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3674                           "Attempted to execute control transfer"
3675                           " when device not ok");
3676                return -EIO;
3677        }
3678        if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3679                if (!probe_fl) {
3680                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3681                                   "Attempted to execute control transfer"
3682                                   " when USB is disconnected");
3683                }
3684                return -ENOTTY;
3685        }
3686
3687        /* Ensure that we have sane parameters */
3688        if (!write_data) write_len = 0;
3689        if (!read_data) read_len = 0;
3690        if (write_len > PVR2_CTL_BUFFSIZE) {
3691                pvr2_trace(
3692                        PVR2_TRACE_ERROR_LEGS,
3693                        "Attempted to execute %d byte"
3694                        " control-write transfer (limit=%d)",
3695                        write_len,PVR2_CTL_BUFFSIZE);
3696                return -EINVAL;
3697        }
3698        if (read_len > PVR2_CTL_BUFFSIZE) {
3699                pvr2_trace(
3700                        PVR2_TRACE_ERROR_LEGS,
3701                        "Attempted to execute %d byte"
3702                        " control-read transfer (limit=%d)",
3703                        write_len,PVR2_CTL_BUFFSIZE);
3704                return -EINVAL;
3705        }
3706        if ((!write_len) && (!read_len)) {
3707                pvr2_trace(
3708                        PVR2_TRACE_ERROR_LEGS,
3709                        "Attempted to execute null control transfer?");
3710                return -EINVAL;
3711        }
3712
3713
3714        hdw->cmd_debug_state = 1;
3715        if (write_len) {
3716                hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3717        } else {
3718                hdw->cmd_debug_code = 0;
3719        }
3720        hdw->cmd_debug_write_len = write_len;
3721        hdw->cmd_debug_read_len = read_len;
3722
3723        /* Initialize common stuff */
3724        init_completion(&hdw->ctl_done);
3725        hdw->ctl_timeout_flag = 0;
3726        hdw->ctl_write_pend_flag = 0;
3727        hdw->ctl_read_pend_flag = 0;
3728        init_timer(&timer);
3729        timer.expires = jiffies + timeout;
3730        timer.data = (unsigned long)hdw;
3731        timer.function = pvr2_ctl_timeout;
3732
3733        if (write_len) {
3734                hdw->cmd_debug_state = 2;
3735                /* Transfer write data to internal buffer */
3736                for (idx = 0; idx < write_len; idx++) {
3737                        hdw->ctl_write_buffer[idx] =
3738                                ((unsigned char *)write_data)[idx];
3739                }
3740                /* Initiate a write request */
3741                usb_fill_bulk_urb(hdw->ctl_write_urb,
3742                                  hdw->usb_dev,
3743                                  usb_sndbulkpipe(hdw->usb_dev,
3744                                                  PVR2_CTL_WRITE_ENDPOINT),
3745                                  hdw->ctl_write_buffer,
3746                                  write_len,
3747                                  pvr2_ctl_write_complete,
3748                                  hdw);
3749                hdw->ctl_write_urb->actual_length = 0;
3750                hdw->ctl_write_pend_flag = !0;
3751                status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3752                if (status < 0) {
3753                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3754                                   "Failed to submit write-control"
3755                                   " URB status=%d",status);
3756                        hdw->ctl_write_pend_flag = 0;
3757                        goto done;
3758                }
3759        }
3760
3761        if (read_len) {
3762                hdw->cmd_debug_state = 3;
3763                memset(hdw->ctl_read_buffer,0x43,read_len);
3764                /* Initiate a read request */
3765                usb_fill_bulk_urb(hdw->ctl_read_urb,
3766                                  hdw->usb_dev,
3767                                  usb_rcvbulkpipe(hdw->usb_dev,
3768                                                  PVR2_CTL_READ_ENDPOINT),
3769                                  hdw->ctl_read_buffer,
3770                                  read_len,
3771                                  pvr2_ctl_read_complete,
3772                                  hdw);
3773                hdw->ctl_read_urb->actual_length = 0;
3774                hdw->ctl_read_pend_flag = !0;
3775                status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3776                if (status < 0) {
3777                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3778                                   "Failed to submit read-control"
3779                                   " URB status=%d",status);
3780                        hdw->ctl_read_pend_flag = 0;
3781                        goto done;
3782                }
3783        }
3784
3785        /* Start timer */
3786        add_timer(&timer);
3787
3788        /* Now wait for all I/O to complete */
3789        hdw->cmd_debug_state = 4;
3790        while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3791                wait_for_completion(&hdw->ctl_done);
3792        }
3793        hdw->cmd_debug_state = 5;
3794
3795        /* Stop timer */
3796        del_timer_sync(&timer);
3797
3798        hdw->cmd_debug_state = 6;
3799        status = 0;
3800
3801        if (hdw->ctl_timeout_flag) {
3802                status = -ETIMEDOUT;
3803                if (!probe_fl) {
3804                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3805                                   "Timed out control-write");
3806                }
3807                goto done;
3808        }
3809
3810        if (write_len) {
3811                /* Validate results of write request */
3812                if ((hdw->ctl_write_urb->status != 0) &&
3813                    (hdw->ctl_write_urb->status != -ENOENT) &&
3814                    (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3815                    (hdw->ctl_write_urb->status != -ECONNRESET)) {
3816                        /* USB subsystem is reporting some kind of failure
3817                           on the write */
3818                        status = hdw->ctl_write_urb->status;
3819                        if (!probe_fl) {
3820                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3821                                           "control-write URB failure,"
3822                                           " status=%d",
3823                                           status);
3824                        }
3825                        goto done;
3826                }
3827                if (hdw->ctl_write_urb->actual_length < write_len) {
3828                        /* Failed to write enough data */
3829                        status = -EIO;
3830                        if (!probe_fl) {
3831                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3832                                           "control-write URB short,"
3833                                           " expected=%d got=%d",
3834                                           write_len,
3835                                           hdw->ctl_write_urb->actual_length);
3836                        }
3837                        goto done;
3838                }
3839        }
3840        if (read_len) {
3841                /* Validate results of read request */
3842                if ((hdw->ctl_read_urb->status != 0) &&
3843                    (hdw->ctl_read_urb->status != -ENOENT) &&
3844                    (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3845                    (hdw->ctl_read_urb->status != -ECONNRESET)) {
3846                        /* USB subsystem is reporting some kind of failure
3847                           on the read */
3848                        status = hdw->ctl_read_urb->status;
3849                        if (!probe_fl) {
3850                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3851                                           "control-read URB failure,"
3852                                           " status=%d",
3853                                           status);
3854                        }
3855                        goto done;
3856                }
3857                if (hdw->ctl_read_urb->actual_length < read_len) {
3858                        /* Failed to read enough data */
3859                        status = -EIO;
3860                        if (!probe_fl) {
3861                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3862                                           "control-read URB short,"
3863                                           " expected=%d got=%d",
3864                                           read_len,
3865                                           hdw->ctl_read_urb->actual_length);
3866                        }
3867                        goto done;
3868                }
3869                /* Transfer retrieved data out from internal buffer */
3870                for (idx = 0; idx < read_len; idx++) {
3871                        ((unsigned char *)read_data)[idx] =
3872                                hdw->ctl_read_buffer[idx];
3873                }
3874        }
3875
3876 done:
3877
3878        hdw->cmd_debug_state = 0;
3879        if ((status < 0) && (!probe_fl)) {
3880                pvr2_hdw_render_useless(hdw);
3881        }
3882        return status;
3883}
3884
3885
3886int pvr2_send_request(struct pvr2_hdw *hdw,
3887                      void *write_data,unsigned int write_len,
3888                      void *read_data,unsigned int read_len)
3889{
3890        return pvr2_send_request_ex(hdw,HZ*4,0,
3891                                    write_data,write_len,
3892                                    read_data,read_len);
3893}
3894
3895
3896static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3897{
3898        int ret;
3899        unsigned int cnt = 1;
3900        unsigned int args = 0;
3901        LOCK_TAKE(hdw->ctl_lock);
3902        hdw->cmd_buffer[0] = cmdcode & 0xffu;
3903        args = (cmdcode >> 8) & 0xffu;
3904        args = (args > 2) ? 2 : args;
3905        if (args) {
3906                cnt += args;
3907                hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3908                if (args > 1) {
3909                        hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3910                }
3911        }
3912        if (pvrusb2_debug & PVR2_TRACE_INIT) {
3913                unsigned int idx;
3914                unsigned int ccnt,bcnt;
3915                char tbuf[50];
3916                cmdcode &= 0xffu;
3917                bcnt = 0;
3918                ccnt = scnprintf(tbuf+bcnt,
3919                                 sizeof(tbuf)-bcnt,
3920                                 "Sending FX2 command 0x%x",cmdcode);
3921                bcnt += ccnt;
3922                for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3923                        if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3924                                ccnt = scnprintf(tbuf+bcnt,
3925                                                 sizeof(tbuf)-bcnt,
3926                                                 " \"%s\"",
3927                                                 pvr2_fx2cmd_desc[idx].desc);
3928                                bcnt += ccnt;
3929                                break;
3930                        }
3931                }
3932                if (args) {
3933                        ccnt = scnprintf(tbuf+bcnt,
3934                                         sizeof(tbuf)-bcnt,
3935                                         " (%u",hdw->cmd_buffer[1]);
3936                        bcnt += ccnt;
3937                        if (args > 1) {
3938                                ccnt = scnprintf(tbuf+bcnt,
3939                                                 sizeof(tbuf)-bcnt,
3940                                                 ",%u",hdw->cmd_buffer[2]);
3941                                bcnt += ccnt;
3942                        }
3943                        ccnt = scnprintf(tbuf+bcnt,
3944                                         sizeof(tbuf)-bcnt,
3945                                         ")");
3946                        bcnt += ccnt;
3947                }
3948                pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3949        }
3950        ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3951        LOCK_GIVE(hdw->ctl_lock);
3952        return ret;
3953}
3954
3955
3956int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3957{
3958        int ret;
3959
3960        LOCK_TAKE(hdw->ctl_lock);
3961
3962        hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3963        PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3964        hdw->cmd_buffer[5] = 0;
3965        hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3966        hdw->cmd_buffer[7] = reg & 0xff;
3967
3968
3969        ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3970
3971        LOCK_GIVE(hdw->ctl_lock);
3972
3973        return ret;
3974}
3975
3976
3977static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3978{
3979        int ret = 0;
3980
3981        LOCK_TAKE(hdw->ctl_lock);
3982
3983        hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3984        hdw->cmd_buffer[1] = 0;
3985        hdw->cmd_buffer[2] = 0;
3986        hdw->cmd_buffer[3] = 0;
3987        hdw->cmd_buffer[4] = 0;
3988        hdw->cmd_buffer[5] = 0;
3989        hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3990        hdw->cmd_buffer[7] = reg & 0xff;
3991
3992        ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3993        *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3994
3995        LOCK_GIVE(hdw->ctl_lock);
3996
3997        return ret;
3998}
3999
4000
4001void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
4002{
4003        if (!hdw->flag_ok) return;
4004        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4005                   "Device being rendered inoperable");
4006        if (hdw->vid_stream) {
4007                pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
4008        }
4009        hdw->flag_ok = 0;
4010        trace_stbit("flag_ok",hdw->flag_ok);
4011        pvr2_hdw_state_sched(hdw);
4012}
4013
4014
4015void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4016{
4017        int ret;
4018        pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
4019        ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
4020        if (ret == 0) {
4021                ret = usb_reset_device(hdw->usb_dev);
4022                usb_unlock_device(hdw->usb_dev);
4023        } else {
4024                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4025                           "Failed to lock USB device ret=%d",ret);
4026        }
4027        if (init_pause_msec) {
4028                pvr2_trace(PVR2_TRACE_INFO,
4029                           "Waiting %u msec for hardware to settle",
4030                           init_pause_msec);
4031                msleep(init_pause_msec);
4032        }
4033
4034}
4035
4036
4037void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4038{
4039        char da[1];
4040        unsigned int pipe;
4041        int ret;
4042
4043        if (!hdw->usb_dev) return;
4044
4045        pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4046
4047        da[0] = val ? 0x01 : 0x00;
4048
4049        /* Write the CPUCS register on the 8051.  The lsb of the register
4050           is the reset bit; a 1 asserts reset while a 0 clears it. */
4051        pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4052        ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4053        if (ret < 0) {
4054                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4055                           "cpureset_assert(%d) error=%d",val,ret);
4056                pvr2_hdw_render_useless(hdw);
4057        }
4058}
4059
4060
4061int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4062{
4063        return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4064}
4065
4066
4067int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4068{
4069        return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4070}
4071
4072
4073int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4074{
4075        return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4076}
4077
4078
4079int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4080{
4081        pvr2_trace(PVR2_TRACE_INIT,
4082                   "Requesting decoder reset");
4083        if (hdw->decoder_client_id) {
4084                v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4085                                     core, reset, 0);
4086                pvr2_hdw_cx25840_vbi_hack(hdw);
4087                return 0;
4088        }
4089        pvr2_trace(PVR2_TRACE_INIT,
4090                   "Unable to reset decoder: nothing attached");
4091        return -ENOTTY;
4092}
4093
4094
4095static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4096{
4097        hdw->flag_ok = !0;
4098        return pvr2_issue_simple_cmd(hdw,
4099                                     FX2CMD_HCW_DEMOD_RESETIN |
4100                                     (1 << 8) |
4101                                     ((onoff ? 1 : 0) << 16));
4102}
4103
4104
4105static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4106{
4107        hdw->flag_ok = !0;
4108        return pvr2_issue_simple_cmd(hdw,(onoff ?
4109                                          FX2CMD_ONAIR_DTV_POWER_ON :
4110                                          FX2CMD_ONAIR_DTV_POWER_OFF));
4111}
4112
4113
4114static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4115                                                int onoff)
4116{
4117        return pvr2_issue_simple_cmd(hdw,(onoff ?
4118                                          FX2CMD_ONAIR_DTV_STREAMING_ON :
4119                                          FX2CMD_ONAIR_DTV_STREAMING_OFF));
4120}
4121
4122
4123static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4124{
4125        int cmode;
4126        /* Compare digital/analog desired setting with current setting.  If
4127           they don't match, fix it... */
4128        cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4129        if (cmode == hdw->pathway_state) {
4130                /* They match; nothing to do */
4131                return;
4132        }
4133
4134        switch (hdw->hdw_desc->digital_control_scheme) {
4135        case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4136                pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4137                if (cmode == PVR2_PATHWAY_ANALOG) {
4138                        /* If moving to analog mode, also force the decoder
4139                           to reset.  If no decoder is attached, then it's
4140                           ok to ignore this because if/when the decoder
4141                           attaches, it will reset itself at that time. */
4142                        pvr2_hdw_cmd_decoder_reset(hdw);
4143                }
4144                break;
4145        case PVR2_DIGITAL_SCHEME_ONAIR:
4146                /* Supposedly we should always have the power on whether in
4147                   digital or analog mode.  But for now do what appears to
4148                   work... */
4149                pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4150                break;
4151        default: break;
4152        }
4153
4154        pvr2_hdw_untrip_unlocked(hdw);
4155        hdw->pathway_state = cmode;
4156}
4157
4158
4159static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4160{
4161        /* change some GPIO data
4162         *
4163         * note: bit d7 of dir appears to control the LED,
4164         * so we shut it off here.
4165         *
4166         */
4167        if (onoff) {
4168                pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4169        } else {
4170                pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4171        }
4172        pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4173}
4174
4175
4176typedef void (*led_method_func)(struct pvr2_hdw *,int);
4177
4178static led_method_func led_methods[] = {
4179        [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4180};
4181
4182
4183/* Toggle LED */
4184static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4185{
4186        unsigned int scheme_id;
4187        led_method_func fp;
4188
4189        if ((!onoff) == (!hdw->led_on)) return;
4190
4191        hdw->led_on = onoff != 0;
4192
4193        scheme_id = hdw->hdw_desc->led_scheme;
4194        if (scheme_id < ARRAY_SIZE(led_methods)) {
4195                fp = led_methods[scheme_id];
4196        } else {
4197                fp = NULL;
4198        }
4199
4200        if (fp) (*fp)(hdw,onoff);
4201}
4202
4203
4204/* Stop / start video stream transport */
4205static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4206{
4207        int ret;
4208
4209        /* If we're in analog mode, then just issue the usual analog
4210           command. */
4211        if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4212                return pvr2_issue_simple_cmd(hdw,
4213                                             (runFl ?
4214                                              FX2CMD_STREAMING_ON :
4215                                              FX2CMD_STREAMING_OFF));
4216                /*Note: Not reached */
4217        }
4218
4219        if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4220                /* Whoops, we don't know what mode we're in... */
4221                return -EINVAL;
4222        }
4223
4224        /* To get here we have to be in digital mode.  The mechanism here
4225           is unfortunately different for different vendors.  So we switch
4226           on the device's digital scheme attribute in order to figure out
4227           what to do. */
4228        switch (hdw->hdw_desc->digital_control_scheme) {
4229        case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4230                return pvr2_issue_simple_cmd(hdw,
4231                                             (runFl ?
4232                                              FX2CMD_HCW_DTV_STREAMING_ON :
4233                                              FX2CMD_HCW_DTV_STREAMING_OFF));
4234        case PVR2_DIGITAL_SCHEME_ONAIR:
4235                ret = pvr2_issue_simple_cmd(hdw,
4236                                            (runFl ?
4237                                             FX2CMD_STREAMING_ON :
4238                                             FX2CMD_STREAMING_OFF));
4239                if (ret) return ret;
4240                return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4241        default:
4242                return -EINVAL;
4243        }
4244}
4245
4246
4247/* Evaluate whether or not state_pathway_ok can change */
4248static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4249{
4250        if (hdw->state_pathway_ok) {
4251                /* Nothing to do if pathway is already ok */
4252                return 0;
4253        }
4254        if (!hdw->state_pipeline_idle) {
4255                /* Not allowed to change anything if pipeline is not idle */
4256                return 0;
4257        }
4258        pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4259        hdw->state_pathway_ok = !0;
4260        trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4261        return !0;
4262}
4263
4264
4265/* Evaluate whether or not state_encoder_ok can change */
4266static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4267{
4268        if (hdw->state_encoder_ok) return 0;
4269        if (hdw->flag_tripped) return 0;
4270        if (hdw->state_encoder_run) return 0;
4271        if (hdw->state_encoder_config) return 0;
4272        if (hdw->state_decoder_run) return 0;
4273        if (hdw->state_usbstream_run) return 0;
4274        if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4275                if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4276        } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4277                return 0;
4278        }
4279
4280        if (pvr2_upload_firmware2(hdw) < 0) {
4281                hdw->flag_tripped = !0;
4282                trace_stbit("flag_tripped",hdw->flag_tripped);
4283                return !0;
4284        }
4285        hdw->state_encoder_ok = !0;
4286        trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4287        return !0;
4288}
4289
4290
4291/* Evaluate whether or not state_encoder_config can change */
4292static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4293{
4294        if (hdw->state_encoder_config) {
4295                if (hdw->state_encoder_ok) {
4296                        if (hdw->state_pipeline_req &&
4297                            !hdw->state_pipeline_pause) return 0;
4298                }
4299                hdw->state_encoder_config = 0;
4300                hdw->state_encoder_waitok = 0;
4301                trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4302                /* paranoia - solve race if timer just completed */
4303                del_timer_sync(&hdw->encoder_wait_timer);
4304        } else {
4305                if (!hdw->state_pathway_ok ||
4306                    (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4307                    !hdw->state_encoder_ok ||
4308                    !hdw->state_pipeline_idle ||
4309                    hdw->state_pipeline_pause ||
4310                    !hdw->state_pipeline_req ||
4311                    !hdw->state_pipeline_config) {
4312                        /* We must reset the enforced wait interval if
4313                           anything has happened that might have disturbed
4314                           the encoder.  This should be a rare case. */
4315                        if (timer_pending(&hdw->encoder_wait_timer)) {
4316                                del_timer_sync(&hdw->encoder_wait_timer);
4317                        }
4318                        if (hdw->state_encoder_waitok) {
4319                                /* Must clear the state - therefore we did
4320                                   something to a state bit and must also
4321                                   return true. */
4322                                hdw->state_encoder_waitok = 0;
4323                                trace_stbit("state_encoder_waitok",
4324                                            hdw->state_encoder_waitok);
4325                                return !0;
4326                        }
4327                        return 0;
4328                }
4329                if (!hdw->state_encoder_waitok) {
4330                        if (!timer_pending(&hdw->encoder_wait_timer)) {
4331                                /* waitok flag wasn't set and timer isn't
4332                                   running.  Check flag once more to avoid
4333                                   a race then start the timer.  This is
4334                                   the point when we measure out a minimal
4335                                   quiet interval before doing something to
4336                                   the encoder. */
4337                                if (!hdw->state_encoder_waitok) {
4338                                        hdw->encoder_wait_timer.expires =
4339                                                jiffies +
4340                                                (HZ * TIME_MSEC_ENCODER_WAIT
4341                                                 / 1000);
4342                                        add_timer(&hdw->encoder_wait_timer);
4343                                }
4344                        }
4345                        /* We can't continue until we know we have been
4346                           quiet for the interval measured by this
4347                           timer. */
4348                        return 0;
4349                }
4350                pvr2_encoder_configure(hdw);
4351                if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4352        }
4353        trace_stbit("state_encoder_config",hdw->state_encoder_config);
4354        return !0;
4355}
4356
4357
4358/* Return true if the encoder should not be running. */
4359static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4360{
4361        if (!hdw->state_encoder_ok) {
4362                /* Encoder isn't healthy at the moment, so stop it. */
4363                return !0;
4364        }
4365        if (!hdw->state_pathway_ok) {
4366                /* Mode is not understood at the moment (i.e. it wants to
4367                   change), so encoder must be stopped. */
4368                return !0;
4369        }
4370
4371        switch (hdw->pathway_state) {
4372        case PVR2_PATHWAY_ANALOG:
4373                if (!hdw->state_decoder_run) {
4374                        /* We're in analog mode and the decoder is not
4375                           running; thus the encoder should be stopped as
4376                           well. */
4377                        return !0;
4378                }
4379                break;
4380        case PVR2_PATHWAY_DIGITAL:
4381                if (hdw->state_encoder_runok) {
4382                        /* This is a funny case.  We're in digital mode so
4383                           really the encoder should be stopped.  However
4384                           if it really is running, only kill it after
4385                           runok has been set.  This gives a chance for the
4386                           onair quirk to function (encoder must run
4387                           briefly first, at least once, before onair
4388                           digital streaming can work). */
4389                        return !0;
4390                }
4391                break;
4392        default:
4393                /* Unknown mode; so encoder should be stopped. */
4394                return !0;
4395        }
4396
4397        /* If we get here, we haven't found a reason to stop the
4398           encoder. */
4399        return 0;
4400}
4401
4402
4403/* Return true if the encoder should be running. */
4404static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4405{
4406        if (!hdw->state_encoder_ok) {
4407                /* Don't run the encoder if it isn't healthy... */
4408                return 0;
4409        }
4410        if (!hdw->state_pathway_ok) {
4411                /* Don't run the encoder if we don't (yet) know what mode
4412                   we need to be in... */
4413                return 0;
4414        }
4415
4416        switch (hdw->pathway_state) {
4417        case PVR2_PATHWAY_ANALOG:
4418                if (hdw->state_decoder_run) {
4419                        /* In analog mode, if the decoder is running, then
4420                           run the encoder. */
4421                        return !0;
4422                }
4423                break;
4424        case PVR2_PATHWAY_DIGITAL:
4425                if ((hdw->hdw_desc->digital_control_scheme ==
4426                     PVR2_DIGITAL_SCHEME_ONAIR) &&
4427                    !hdw->state_encoder_runok) {
4428                        /* This is a quirk.  OnAir hardware won't stream
4429                           digital until the encoder has been run at least
4430                           once, for a minimal period of time (empiricially
4431                           measured to be 1/4 second).  So if we're on
4432                           OnAir hardware and the encoder has never been
4433                           run at all, then start the encoder.  Normal
4434                           state machine logic in the driver will
4435                           automatically handle the remaining bits. */
4436                        return !0;
4437                }
4438                break;
4439        default:
4440                /* For completeness (unknown mode; encoder won't run ever) */
4441                break;
4442        }
4443        /* If we get here, then we haven't found any reason to run the
4444           encoder, so don't run it. */
4445        return 0;
4446}
4447
4448
4449/* Evaluate whether or not state_encoder_run can change */
4450static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4451{
4452        if (hdw->state_encoder_run) {
4453                if (!state_check_disable_encoder_run(hdw)) return 0;
4454                if (hdw->state_encoder_ok) {
4455                        del_timer_sync(&hdw->encoder_run_timer);
4456                        if (pvr2_encoder_stop(hdw) < 0) return !0;
4457                }
4458                hdw->state_encoder_run = 0;
4459        } else {
4460                if (!state_check_enable_encoder_run(hdw)) return 0;
4461                if (pvr2_encoder_start(hdw) < 0) return !0;
4462                hdw->state_encoder_run = !0;
4463                if (!hdw->state_encoder_runok) {
4464                        hdw->encoder_run_timer.expires =
4465                                jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4466                        add_timer(&hdw->encoder_run_timer);
4467                }
4468        }
4469        trace_stbit("state_encoder_run",hdw->state_encoder_run);
4470        return !0;
4471}
4472
4473
4474/* Timeout function for quiescent timer. */
4475static void pvr2_hdw_quiescent_timeout(unsigned long data)
4476{
4477        struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4478        hdw->state_decoder_quiescent = !0;
4479        trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4480        hdw->state_stale = !0;
4481        queue_work(hdw->workqueue,&hdw->workpoll);
4482}
4483
4484
4485/* Timeout function for encoder wait timer. */
4486static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4487{
4488        struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4489        hdw->state_encoder_waitok = !0;
4490        trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4491        hdw->state_stale = !0;
4492        queue_work(hdw->workqueue,&hdw->workpoll);
4493}
4494
4495
4496/* Timeout function for encoder run timer. */
4497static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4498{
4499        struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4500        if (!hdw->state_encoder_runok) {
4501                hdw->state_encoder_runok = !0;
4502                trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4503                hdw->state_stale = !0;
4504                queue_work(hdw->workqueue,&hdw->workpoll);
4505        }
4506}
4507
4508
4509/* Evaluate whether or not state_decoder_run can change */
4510static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4511{
4512        if (hdw->state_decoder_run) {
4513                if (hdw->state_encoder_ok) {
4514                        if (hdw->state_pipeline_req &&
4515                            !hdw->state_pipeline_pause &&
4516                            hdw->state_pathway_ok) return 0;
4517                }
4518                if (!hdw->flag_decoder_missed) {
4519                        pvr2_decoder_enable(hdw,0);
4520                }
4521                hdw->state_decoder_quiescent = 0;
4522                hdw->state_decoder_run = 0;
4523                /* paranoia - solve race if timer just completed */
4524                del_timer_sync(&hdw->quiescent_timer);
4525        } else {
4526                if (!hdw->state_decoder_quiescent) {
4527                        if (!timer_pending(&hdw->quiescent_timer)) {
4528                                /* We don't do something about the
4529                                   quiescent timer until right here because
4530                                   we also want to catch cases where the
4531                                   decoder was already not running (like
4532                                   after initialization) as opposed to
4533                                   knowing that we had just stopped it.
4534                                   The second flag check is here to cover a
4535                                   race - the timer could have run and set
4536                                   this flag just after the previous check
4537                                   but before we did the pending check. */
4538                                if (!hdw->state_decoder_quiescent) {
4539                                        hdw->quiescent_timer.expires =
4540                                                jiffies +
4541                                                (HZ * TIME_MSEC_DECODER_WAIT
4542                                                 / 1000);
4543                                        add_timer(&hdw->quiescent_timer);
4544                                }
4545                        }
4546                        /* Don't allow decoder to start again until it has
4547                           been quiesced first.  This little detail should
4548                           hopefully further stabilize the encoder. */
4549                        return 0;
4550                }
4551                if (!hdw->state_pathway_ok ||
4552                    (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4553                    !hdw->state_pipeline_req ||
4554                    hdw->state_pipeline_pause ||
4555                    !hdw->state_pipeline_config ||
4556                    !hdw->state_encoder_config ||
4557                    !hdw->state_encoder_ok) return 0;
4558                del_timer_sync(&hdw->quiescent_timer);
4559                if (hdw->flag_decoder_missed) return 0;
4560                if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4561                hdw->state_decoder_quiescent = 0;
4562                hdw->state_decoder_run = !0;
4563        }
4564        trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4565        trace_stbit("state_decoder_run",hdw->state_decoder_run);
4566        return !0;
4567}
4568
4569
4570/* Evaluate whether or not state_usbstream_run can change */
4571static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4572{
4573        if (hdw->state_usbstream_run) {
4574                int fl = !0;
4575                if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4576                        fl = (hdw->state_encoder_ok &&
4577                              hdw->state_encoder_run);
4578                } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4579                           (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4580                        fl = hdw->state_encoder_ok;
4581                }
4582                if (fl &&
4583                    hdw->state_pipeline_req &&
4584                    !hdw->state_pipeline_pause &&
4585                    hdw->state_pathway_ok) {
4586                        return 0;
4587                }
4588                pvr2_hdw_cmd_usbstream(hdw,0);
4589                hdw->state_usbstream_run = 0;
4590        } else {
4591                if (!hdw->state_pipeline_req ||
4592                    hdw->state_pipeline_pause ||
4593                    !hdw->state_pathway_ok) return 0;
4594                if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4595                        if (!hdw->state_encoder_ok ||
4596                            !hdw->state_encoder_run) return 0;
4597                } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4598                           (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4599                        if (!hdw->state_encoder_ok) return 0;
4600                        if (hdw->state_encoder_run) return 0;
4601                        if (hdw->hdw_desc->digital_control_scheme ==
4602                            PVR2_DIGITAL_SCHEME_ONAIR) {
4603                                /* OnAir digital receivers won't stream
4604                                   unless the analog encoder has run first.
4605                                   Why?  I have no idea.  But don't even
4606                                   try until we know the analog side is
4607                                   known to have run. */
4608                                if (!hdw->state_encoder_runok) return 0;
4609                        }
4610                }
4611                if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4612                hdw->state_usbstream_run = !0;
4613        }
4614        trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4615        return !0;
4616}
4617
4618
4619/* Attempt to configure pipeline, if needed */
4620static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4621{
4622        if (hdw->state_pipeline_config ||
4623            hdw->state_pipeline_pause) return 0;
4624        pvr2_hdw_commit_execute(hdw);
4625        return !0;
4626}
4627
4628
4629/* Update pipeline idle and pipeline pause tracking states based on other
4630   inputs.  This must be called whenever the other relevant inputs have
4631   changed. */
4632static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4633{
4634        unsigned int st;
4635        int updatedFl = 0;
4636        /* Update pipeline state */
4637        st = !(hdw->state_encoder_run ||
4638               hdw->state_decoder_run ||
4639               hdw->state_usbstream_run ||
4640               (!hdw->state_decoder_quiescent));
4641        if (!st != !hdw->state_pipeline_idle) {
4642                hdw->state_pipeline_idle = st;
4643                updatedFl = !0;
4644        }
4645        if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4646                hdw->state_pipeline_pause = 0;
4647                updatedFl = !0;
4648        }
4649        return updatedFl;
4650}
4651
4652
4653typedef int (*state_eval_func)(struct pvr2_hdw *);
4654
4655/* Set of functions to be run to evaluate various states in the driver. */
4656static const state_eval_func eval_funcs[] = {
4657        state_eval_pathway_ok,
4658        state_eval_pipeline_config,
4659        state_eval_encoder_ok,
4660        state_eval_encoder_config,
4661        state_eval_decoder_run,
4662        state_eval_encoder_run,
4663        state_eval_usbstream_run,
4664};
4665
4666
4667/* Process various states and return true if we did anything interesting. */
4668static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4669{
4670        unsigned int i;
4671        int state_updated = 0;
4672        int check_flag;
4673
4674        if (!hdw->state_stale) return 0;
4675        if ((hdw->fw1_state != FW1_STATE_OK) ||
4676            !hdw->flag_ok) {
4677                hdw->state_stale = 0;
4678                return !0;
4679        }
4680        /* This loop is the heart of the entire driver.  It keeps trying to
4681           evaluate various bits of driver state until nothing changes for
4682           one full iteration.  Each "bit of state" tracks some global
4683           aspect of the driver, e.g. whether decoder should run, if
4684           pipeline is configured, usb streaming is on, etc.  We separately
4685           evaluate each of those questions based on other driver state to
4686           arrive at the correct running configuration. */
4687        do {
4688                check_flag = 0;
4689                state_update_pipeline_state(hdw);
4690                /* Iterate over each bit of state */
4691                for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4692                        if ((*eval_funcs[i])(hdw)) {
4693                                check_flag = !0;
4694                                state_updated = !0;
4695                                state_update_pipeline_state(hdw);
4696                        }
4697                }
4698        } while (check_flag && hdw->flag_ok);
4699        hdw->state_stale = 0;
4700        trace_stbit("state_stale",hdw->state_stale);
4701        return state_updated;
4702}
4703
4704
4705static unsigned int print_input_mask(unsigned int msk,
4706                                     char *buf,unsigned int acnt)
4707{
4708        unsigned int idx,ccnt;
4709        unsigned int tcnt = 0;
4710        for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4711                if (!((1 << idx) & msk)) continue;
4712                ccnt = scnprintf(buf+tcnt,
4713                                 acnt-tcnt,
4714                                 "%s%s",
4715                                 (tcnt ? ", " : ""),
4716                                 control_values_input[idx]);
4717                tcnt += ccnt;
4718        }
4719        return tcnt;
4720}
4721
4722
4723static const char *pvr2_pathway_state_name(int id)
4724{
4725        switch (id) {
4726        case PVR2_PATHWAY_ANALOG: return "analog";
4727        case PVR2_PATHWAY_DIGITAL: return "digital";
4728        default: return "unknown";
4729        }
4730}
4731
4732
4733static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4734                                             char *buf,unsigned int acnt)
4735{
4736        switch (which) {
4737        case 0:
4738                return scnprintf(
4739                        buf,acnt,
4740                        "driver:%s%s%s%s%s <mode=%s>",
4741                        (hdw->flag_ok ? " <ok>" : " <fail>"),
4742                        (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4743                        (hdw->flag_disconnected ? " <disconnected>" :
4744                         " <connected>"),
4745                        (hdw->flag_tripped ? " <tripped>" : ""),
4746                        (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4747                        pvr2_pathway_state_name(hdw->pathway_state));
4748
4749        case 1:
4750                return scnprintf(
4751                        buf,acnt,
4752                        "pipeline:%s%s%s%s",
4753                        (hdw->state_pipeline_idle ? " <idle>" : ""),
4754                        (hdw->state_pipeline_config ?
4755                         " <configok>" : " <stale>"),
4756                        (hdw->state_pipeline_req ? " <req>" : ""),
4757                        (hdw->state_pipeline_pause ? " <pause>" : ""));
4758        case 2:
4759                return scnprintf(
4760                        buf,acnt,
4761                        "worker:%s%s%s%s%s%s%s",
4762                        (hdw->state_decoder_run ?
4763                         " <decode:run>" :
4764                         (hdw->state_decoder_quiescent ?
4765                          "" : " <decode:stop>")),
4766                        (hdw->state_decoder_quiescent ?
4767                         " <decode:quiescent>" : ""),
4768                        (hdw->state_encoder_ok ?
4769                         "" : " <encode:init>"),
4770                        (hdw->state_encoder_run ?
4771                         (hdw->state_encoder_runok ?
4772                          " <encode:run>" :
4773                          " <encode:firstrun>") :
4774                         (hdw->state_encoder_runok ?
4775                          " <encode:stop>" :
4776                          " <encode:virgin>")),
4777                        (hdw->state_encoder_config ?
4778                         " <encode:configok>" :
4779                         (hdw->state_encoder_waitok ?
4780                          "" : " <encode:waitok>")),
4781                        (hdw->state_usbstream_run ?
4782                         " <usb:run>" : " <usb:stop>"),
4783                        (hdw->state_pathway_ok ?
4784                         " <pathway:ok>" : ""));
4785        case 3:
4786                return scnprintf(
4787                        buf,acnt,
4788                        "state: %s",
4789                        pvr2_get_state_name(hdw->master_state));
4790        case 4: {
4791                unsigned int tcnt = 0;
4792                unsigned int ccnt;
4793
4794                ccnt = scnprintf(buf,
4795                                 acnt,
4796                                 "Hardware supported inputs: ");
4797                tcnt += ccnt;
4798                tcnt += print_input_mask(hdw->input_avail_mask,
4799                                         buf+tcnt,
4800                                         acnt-tcnt);
4801                if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4802                        ccnt = scnprintf(buf+tcnt,
4803                                         acnt-tcnt,
4804                                         "; allowed inputs: ");
4805                        tcnt += ccnt;
4806                        tcnt += print_input_mask(hdw->input_allowed_mask,
4807                                                 buf+tcnt,
4808                                                 acnt-tcnt);
4809                }
4810                return tcnt;
4811        }
4812        case 5: {
4813                struct pvr2_stream_stats stats;
4814                if (!hdw->vid_stream) break;
4815                pvr2_stream_get_stats(hdw->vid_stream,
4816                                      &stats,
4817                                      0);
4818                return scnprintf(
4819                        buf,acnt,
4820                        "Bytes streamed=%u"
4821                        " URBs: queued=%u idle=%u ready=%u"
4822                        " processed=%u failed=%u",
4823                        stats.bytes_processed,
4824                        stats.buffers_in_queue,
4825                        stats.buffers_in_idle,
4826                        stats.buffers_in_ready,
4827                        stats.buffers_processed,
4828                        stats.buffers_failed);
4829        }
4830        case 6: {
4831                unsigned int id = hdw->ir_scheme_active;
4832                return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4833                                 (id >= ARRAY_SIZE(ir_scheme_names) ?
4834                                  "?" : ir_scheme_names[id]));
4835        }
4836        default: break;
4837        }
4838        return 0;
4839}
4840
4841
4842/* Generate report containing info about attached sub-devices and attached
4843   i2c clients, including an indication of which attached i2c clients are
4844   actually sub-devices. */
4845static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4846                                            char *buf, unsigned int acnt)
4847{
4848        struct v4l2_subdev *sd;
4849        unsigned int tcnt = 0;
4850        unsigned int ccnt;
4851        struct i2c_client *client;
4852        const char *p;
4853        unsigned int id;
4854
4855        ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4856        tcnt += ccnt;
4857        v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4858                id = sd->grp_id;
4859                p = NULL;
4860                if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4861                if (p) {
4862                        ccnt = scnprintf(buf + tcnt, acnt - tcnt, "  %s:", p);
4863                        tcnt += ccnt;
4864                } else {
4865                        ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4866                                         "  (unknown id=%u):", id);
4867                        tcnt += ccnt;
4868                }
4869                client = v4l2_get_subdevdata(sd);
4870                if (client) {
4871                        ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4872                                         " %s @ %02x\n", client->name,
4873                                         client->addr);
4874                        tcnt += ccnt;
4875                } else {
4876                        ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4877                                         " no i2c client\n");
4878                        tcnt += ccnt;
4879                }
4880        }
4881        return tcnt;
4882}
4883
4884
4885unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4886                                   char *buf,unsigned int acnt)
4887{
4888        unsigned int bcnt,ccnt,idx;
4889        bcnt = 0;
4890        LOCK_TAKE(hdw->big_lock);
4891        for (idx = 0; ; idx++) {
4892                ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4893                if (!ccnt) break;
4894                bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4895                if (!acnt) break;
4896                buf[0] = '\n'; ccnt = 1;
4897                bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4898        }
4899        ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4900        bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4901        LOCK_GIVE(hdw->big_lock);
4902        return bcnt;
4903}
4904
4905
4906static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4907{
4908        char buf[256];
4909        unsigned int idx, ccnt;
4910        unsigned int lcnt, ucnt;
4911
4912        for (idx = 0; ; idx++) {
4913                ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4914                if (!ccnt) break;
4915                printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4916        }
4917        ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4918        ucnt = 0;
4919        while (ucnt < ccnt) {
4920                lcnt = 0;
4921                while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4922                        lcnt++;
4923                }
4924                printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4925                ucnt += lcnt + 1;
4926        }
4927}
4928
4929
4930/* Evaluate and update the driver's current state, taking various actions
4931   as appropriate for the update. */
4932static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4933{
4934        unsigned int st;
4935        int state_updated = 0;
4936        int callback_flag = 0;
4937        int analog_mode;
4938
4939        pvr2_trace(PVR2_TRACE_STBITS,
4940                   "Drive state check START");
4941        if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4942                pvr2_hdw_state_log_state(hdw);
4943        }
4944
4945        /* Process all state and get back over disposition */
4946        state_updated = pvr2_hdw_state_update(hdw);
4947
4948        analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4949
4950        /* Update master state based upon all other states. */
4951        if (!hdw->flag_ok) {
4952                st = PVR2_STATE_DEAD;
4953        } else if (hdw->fw1_state != FW1_STATE_OK) {
4954                st = PVR2_STATE_COLD;
4955        } else if ((analog_mode ||
4956                    hdw->hdw_desc->flag_digital_requires_cx23416) &&
4957                   !hdw->state_encoder_ok) {
4958                st = PVR2_STATE_WARM;
4959        } else if (hdw->flag_tripped ||
4960                   (analog_mode && hdw->flag_decoder_missed)) {
4961                st = PVR2_STATE_ERROR;
4962        } else if (hdw->state_usbstream_run &&
4963                   (!analog_mode ||
4964                    (hdw->state_encoder_run && hdw->state_decoder_run))) {
4965                st = PVR2_STATE_RUN;
4966        } else {
4967                st = PVR2_STATE_READY;
4968        }
4969        if (hdw->master_state != st) {
4970                pvr2_trace(PVR2_TRACE_STATE,
4971                           "Device state change from %s to %s",
4972                           pvr2_get_state_name(hdw->master_state),
4973                           pvr2_get_state_name(st));
4974                pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4975                hdw->master_state = st;
4976                state_updated = !0;
4977                callback_flag = !0;
4978        }
4979        if (state_updated) {
4980                /* Trigger anyone waiting on any state changes here. */
4981                wake_up(&hdw->state_wait_data);
4982        }
4983
4984        if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4985                pvr2_hdw_state_log_state(hdw);
4986        }
4987        pvr2_trace(PVR2_TRACE_STBITS,
4988                   "Drive state check DONE callback=%d",callback_flag);
4989
4990        return callback_flag;
4991}
4992
4993
4994/* Cause kernel thread to check / update driver state */
4995static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4996{
4997        if (hdw->state_stale) return;
4998        hdw->state_stale = !0;
4999        trace_stbit("state_stale",hdw->state_stale);
5000        queue_work(hdw->workqueue,&hdw->workpoll);
5001}
5002
5003
5004int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5005{
5006        return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5007}
5008
5009
5010int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5011{
5012        return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5013}
5014
5015
5016int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5017{
5018        return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5019}
5020
5021
5022int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5023{
5024        u32 cval,nval;
5025        int ret;
5026        if (~msk) {
5027                ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5028                if (ret) return ret;
5029                nval = (cval & ~msk) | (val & msk);
5030                pvr2_trace(PVR2_TRACE_GPIO,
5031                           "GPIO direction changing 0x%x:0x%x"
5032                           " from 0x%x to 0x%x",
5033                           msk,val,cval,nval);
5034        } else {
5035                nval = val;
5036                pvr2_trace(PVR2_TRACE_GPIO,
5037                           "GPIO direction changing to 0x%x",nval);
5038        }
5039        return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5040}
5041
5042
5043int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5044{
5045        u32 cval,nval;
5046        int ret;
5047        if (~msk) {
5048                ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5049                if (ret) return ret;
5050                nval = (cval & ~msk) | (val & msk);
5051                pvr2_trace(PVR2_TRACE_GPIO,
5052                           "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5053                           msk,val,cval,nval);
5054        } else {
5055                nval = val;
5056                pvr2_trace(PVR2_TRACE_GPIO,
5057                           "GPIO output changing to 0x%x",nval);
5058        }
5059        return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5060}
5061
5062
5063void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5064{
5065        struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5066        memset(vtp, 0, sizeof(*vtp));
5067        hdw->tuner_signal_stale = 0;
5068        /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5069           using v4l2-subdev - therefore we can't support that AT ALL right
5070           now.  (Of course, no sub-drivers seem to implement it either.
5071           But now it's a a chicken and egg problem...) */
5072        v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5073                             &hdw->tuner_signal_info);
5074        pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5075                   " type=%u strength=%u audio=0x%x cap=0x%x"
5076                   " low=%u hi=%u",
5077                   vtp->type,
5078                   vtp->signal, vtp->rxsubchans, vtp->capability,
5079                   vtp->rangelow, vtp->rangehigh);
5080
5081        /* We have to do this to avoid getting into constant polling if
5082           there's nobody to answer a poll of cropcap info. */
5083        hdw->cropcap_stale = 0;
5084}
5085
5086
5087unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5088{
5089        return hdw->input_avail_mask;
5090}
5091
5092
5093unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5094{
5095        return hdw->input_allowed_mask;
5096}
5097
5098
5099static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5100{
5101        if (hdw->input_val != v) {
5102                hdw->input_val = v;
5103                hdw->input_dirty = !0;
5104        }
5105
5106        /* Handle side effects - if we switch to a mode that needs the RF
5107           tuner, then select the right frequency choice as well and mark
5108           it dirty. */
5109        if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5110                hdw->freqSelector = 0;
5111                hdw->freqDirty = !0;
5112        } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5113                   (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5114                hdw->freqSelector = 1;
5115                hdw->freqDirty = !0;
5116        }
5117        return 0;
5118}
5119
5120
5121int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5122                               unsigned int change_mask,
5123                               unsigned int change_val)
5124{
5125        int ret = 0;
5126        unsigned int nv,m,idx;
5127        LOCK_TAKE(hdw->big_lock);
5128        do {
5129                nv = hdw->input_allowed_mask & ~change_mask;
5130                nv |= (change_val & change_mask);
5131                nv &= hdw->input_avail_mask;
5132                if (!nv) {
5133                        /* No legal modes left; return error instead. */
5134                        ret = -EPERM;
5135                        break;
5136                }
5137                hdw->input_allowed_mask = nv;
5138                if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5139                        /* Current mode is still in the allowed mask, so
5140                           we're done. */
5141                        break;
5142                }
5143                /* Select and switch to a mode that is still in the allowed
5144                   mask */
5145                if (!hdw->input_allowed_mask) {
5146                        /* Nothing legal; give up */
5147                        break;
5148                }
5149                m = hdw->input_allowed_mask;
5150                for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5151                        if (!((1 << idx) & m)) continue;
5152                        pvr2_hdw_set_input(hdw,idx);
5153                        break;
5154                }
5155        } while (0);
5156        LOCK_GIVE(hdw->big_lock);
5157        return ret;
5158}
5159
5160
5161/* Find I2C address of eeprom */
5162static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5163{
5164        int result;
5165        LOCK_TAKE(hdw->ctl_lock); do {
5166                hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5167                result = pvr2_send_request(hdw,
5168                                           hdw->cmd_buffer,1,
5169                                           hdw->cmd_buffer,1);
5170                if (result < 0) break;
5171                result = hdw->cmd_buffer[0];
5172        } while(0); LOCK_GIVE(hdw->ctl_lock);
5173        return result;
5174}
5175
5176
5177int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5178                             struct v4l2_dbg_match *match, u64 reg_id,
5179                             int setFl, u64 *val_ptr)
5180{
5181#ifdef CONFIG_VIDEO_ADV_DEBUG
5182        struct v4l2_dbg_register req;
5183        int stat = 0;
5184        int okFl = 0;
5185
5186        if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5187
5188        req.match = *match;
5189        req.reg = reg_id;
5190        if (setFl) req.val = *val_ptr;
5191        /* It would be nice to know if a sub-device answered the request */
5192        v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5193        if (!setFl) *val_ptr = req.val;
5194        if (okFl) {
5195                return stat;
5196        }
5197        return -EINVAL;
5198#else
5199        return -ENOSYS;
5200#endif
5201}
5202
5203
5204/*
5205  Stuff for Emacs to see, in order to encourage consistent editing style:
5206  *** Local Variables: ***
5207  *** mode: c ***
5208  *** fill-column: 75 ***
5209  *** tab-width: 8 ***
5210  *** c-basic-offset: 8 ***
5211  *** End: ***
5212  */
5213
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