LXR linux/drivers/ide/serverworks.c

   1/*
   2 * Copyright (C) 1998-2000 Michel Aubry
   3 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
   4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   5 * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
   6 * Portions copyright (c) 2001 Sun Microsystems
   7 *
   8 *
   9 * RCC/ServerWorks IDE driver for Linux
  10 *
  11 *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  12 *         supports UDMA mode 2 (33 MB/s)
  13 *
  14 *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  15 *         all revisions support UDMA mode 4 (66 MB/s)
  16 *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  17 *
  18 *         *** The CSB5 does not provide ANY register ***
  19 *         *** to detect 80-conductor cable presence. ***
  20 *
  21 *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  22 *
  23 *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
  24 *   controller same as the CSB6. Single channel ATA100 only.
  25 *
  26 * Documentation:
  27 *      Available under NDA only. Errata info very hard to get.
  28 *
  29 */
  30
  31#include <linux/types.h>
  32#include <linux/module.h>
  33#include <linux/kernel.h>
  34#include <linux/pci.h>
  35#include <linux/ide.h>
  36#include <linux/init.h>
  37
  38#include <asm/io.h>
  39
  40#define DRV_NAME "serverworks"
  41
  42#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  43#define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  44
  45/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  46 * can overrun their FIFOs when used with the CSB5 */
  47static const char *svwks_bad_ata100[] = {
  48        "ST320011A",
  49        "ST340016A",
  50        "ST360021A",
  51        "ST380021A",
  52        NULL
  53};
  54
  55static struct pci_dev *isa_dev;
  56
  57static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  58{
  59        char *m = (char *)&drive->id[ATA_ID_PROD];
  60
  61        while (*list)
  62                if (!strcmp(*list++, m))
  63                        return 1;
  64        return 0;
  65}
  66
  67static u8 svwks_udma_filter(ide_drive_t *drive)
  68{
  69        struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  70        u8 mask = 0;
  71
  72        if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
  73                return 0x1f;
  74        if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  75                u32 reg = 0;
  76                if (isa_dev)
  77                        pci_read_config_dword(isa_dev, 0x64, &reg);
  78                        
  79                /*
  80                 *      Don't enable UDMA on disk devices for the moment
  81                 */
  82                if(drive->media == ide_disk)
  83                        return 0;
  84                /* Check the OSB4 DMA33 enable bit */
  85                return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
  86        } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
  87                return 0x07;
  88        } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
  89                u8 btr = 0, mode;
  90                pci_read_config_byte(dev, 0x5A, &btr);
  91                mode = btr & 0x3;
  92
  93                /* If someone decides to do UDMA133 on CSB5 the same
  94                   issue will bite so be inclusive */
  95                if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
  96                        mode = 2;
  97
  98                switch(mode) {
  99                case 3:  mask = 0x3f; break;
 100                case 2:  mask = 0x1f; break;
 101                case 1:  mask = 0x07; break;
 102                default: mask = 0x00; break;
 103                }
 104        }
 105        if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 106             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 107            (!(PCI_FUNC(dev->devfn) & 1)))
 108                mask = 0x1f;
 109
 110        return mask;
 111}
 112
 113static u8 svwks_csb_check (struct pci_dev *dev)
 114{
 115        switch (dev->device) {
 116                case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 117                case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 118                case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 119                case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 120                        return 1;
 121                default:
 122                        break;
 123        }
 124        return 0;
 125}
 126
 127static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio)
 128{
 129        static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 130        static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
 131
 132        struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
 133
 134        pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
 135
 136        if (svwks_csb_check(dev)) {
 137                u16 csb_pio = 0;
 138
 139                pci_read_config_word(dev, 0x4a, &csb_pio);
 140
 141                csb_pio &= ~(0x0f << (4 * drive->dn));
 142                csb_pio |= (pio << (4 * drive->dn));
 143
 144                pci_write_config_word(dev, 0x4a, csb_pio);
 145        }
 146}
 147
 148static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed)
 149{
 150        static const u8 udma_modes[]            = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
 151        static const u8 dma_modes[]             = { 0x77, 0x21, 0x20 };
 152        static const u8 drive_pci2[]            = { 0x45, 0x44, 0x47, 0x46 };
 153
 154        ide_hwif_t *hwif        = drive->hwif;
 155        struct pci_dev *dev     = to_pci_dev(hwif->dev);
 156        u8 unit                 = drive->dn & 1;
 157
 158        u8 ultra_enable  = 0, ultra_timing = 0, dma_timing = 0;
 159
 160        pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
 161        pci_read_config_byte(dev, 0x54, &ultra_enable);
 162
 163        ultra_timing    &= ~(0x0F << (4*unit));
 164        ultra_enable    &= ~(0x01 << drive->dn);
 165
 166        if (speed >= XFER_UDMA_0) {
 167                dma_timing   |= dma_modes[2];
 168                ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
 169                ultra_enable |= (0x01 << drive->dn);
 170        } else if (speed >= XFER_MW_DMA_0)
 171                dma_timing   |= dma_modes[speed - XFER_MW_DMA_0];
 172
 173        pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
 174        pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
 175        pci_write_config_byte(dev, 0x54, ultra_enable);
 176}
 177
 178static int init_chipset_svwks(struct pci_dev *dev)
 179{
 180        unsigned int reg;
 181        u8 btr;
 182
 183        /* force Master Latency Timer value to 64 PCICLKs */
 184        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
 185
 186        /* OSB4 : South Bridge and IDE */
 187        if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 188                isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 189                          PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 190                if (isa_dev) {
 191                        pci_read_config_dword(isa_dev, 0x64, &reg);
 192                        reg &= ~0x00002000; /* disable 600ns interrupt mask */
 193                        if(!(reg & 0x00004000))
 194                                printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS "
 195                                        "enabled.\n", pci_name(dev));
 196                        reg |=  0x00004000; /* enable UDMA/33 support */
 197                        pci_write_config_dword(isa_dev, 0x64, reg);
 198                }
 199        }
 200
 201        /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 202        else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 203                 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 204                 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 205
 206                /* Third Channel Test */
 207                if (!(PCI_FUNC(dev->devfn) & 1)) {
 208                        struct pci_dev * findev = NULL;
 209                        u32 reg4c = 0;
 210                        findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 211                                PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 212                        if (findev) {
 213                                pci_read_config_dword(findev, 0x4C, &reg4c);
 214                                reg4c &= ~0x000007FF;
 215                                reg4c |=  0x00000040;
 216                                reg4c |=  0x00000020;
 217                                pci_write_config_dword(findev, 0x4C, reg4c);
 218                                pci_dev_put(findev);
 219                        }
 220                        outb_p(0x06, 0x0c00);
 221                        dev->irq = inb_p(0x0c01);
 222                } else {
 223                        struct pci_dev * findev = NULL;
 224                        u8 reg41 = 0;
 225
 226                        findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 227                                        PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 228                        if (findev) {
 229                                pci_read_config_byte(findev, 0x41, &reg41);
 230                                reg41 &= ~0x40;
 231                                pci_write_config_byte(findev, 0x41, reg41);
 232                                pci_dev_put(findev);
 233                        }
 234                        /*
 235                         * This is a device pin issue on CSB6.
 236                         * Since there will be a future raid mode,
 237                         * early versions of the chipset require the
 238                         * interrupt pin to be set, and it is a compatibility
 239                         * mode issue.
 240                         */
 241                        if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 242                                dev->irq = 0;
 243                }
 244//              pci_read_config_dword(dev, 0x40, &pioreg)
 245//              pci_write_config_dword(dev, 0x40, 0x99999999);
 246//              pci_read_config_dword(dev, 0x44, &dmareg);
 247//              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
 248                /* setup the UDMA Control register
 249                 *
 250                 * 1. clear bit 6 to enable DMA
 251                 * 2. enable DMA modes with bits 0-1
 252                 *      00 : legacy
 253                 *      01 : udma2
 254                 *      10 : udma2/udma4
 255                 *      11 : udma2/udma4/udma5
 256                 */
 257                pci_read_config_byte(dev, 0x5A, &btr);
 258                btr &= ~0x40;
 259                if (!(PCI_FUNC(dev->devfn) & 1))
 260                        btr |= 0x2;
 261                else
 262                        btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 263                pci_write_config_byte(dev, 0x5A, btr);
 264        }
 265        /* Setup HT1000 SouthBridge Controller - Single Channel Only */
 266        else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
 267                pci_read_config_byte(dev, 0x5A, &btr);
 268                btr &= ~0x40;
 269                btr |= 0x3;
 270                pci_write_config_byte(dev, 0x5A, btr);
 271        }
 272
 273        return 0;
 274}
 275
 276static u8 ata66_svwks_svwks(ide_hwif_t *hwif)
 277{
 278        return ATA_CBL_PATA80;
 279}
 280
 281/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 282 * of the subsystem device ID indicate presence of an 80-pin cable.
 283 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 284 * Bit 15 set   = secondary IDE channel has 80-pin cable.
 285 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 286 * Bit 14 set   = primary IDE channel has 80-pin cable.
 287 */
 288static u8 ata66_svwks_dell(ide_hwif_t *hwif)
 289{
 290        struct pci_dev *dev = to_pci_dev(hwif->dev);
 291
 292        if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
 293            dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 294            (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
 295             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
 296                return ((1 << (hwif->channel + 14)) &
 297                        dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 298        return ATA_CBL_PATA40;
 299}
 300
 301/* Sun Cobalt Alpine hardware avoids the 80-pin cable
 302 * detect issue by attaching the drives directly to the board.
 303 * This check follows the Dell precedent (how scary is that?!)
 304 *
 305 * WARNING: this only works on Alpine hardware!
 306 */
 307static u8 ata66_svwks_cobalt(ide_hwif_t *hwif)
 308{
 309        struct pci_dev *dev = to_pci_dev(hwif->dev);
 310
 311        if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
 312            dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 313            dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
 314                return ((1 << (hwif->channel + 14)) &
 315                        dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 316        return ATA_CBL_PATA40;
 317}
 318
 319static u8 svwks_cable_detect(ide_hwif_t *hwif)
 320{
 321        struct pci_dev *dev = to_pci_dev(hwif->dev);
 322
 323        /* Server Works */
 324        if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
 325                return ata66_svwks_svwks (hwif);
 326        
 327        /* Dell PowerEdge */
 328        if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
 329                return ata66_svwks_dell (hwif);
 330
 331        /* Cobalt Alpine */
 332        if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
 333                return ata66_svwks_cobalt (hwif);
 334
 335        /* Per Specified Design by OEM, and ASIC Architect */
 336        if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 337            (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
 338                return ATA_CBL_PATA80;
 339
 340        return ATA_CBL_PATA40;
 341}
 342
 343static const struct ide_port_ops osb4_port_ops = {
 344        .set_pio_mode           = svwks_set_pio_mode,
 345        .set_dma_mode           = svwks_set_dma_mode,
 346        .udma_filter            = svwks_udma_filter,
 347};
 348
 349static const struct ide_port_ops svwks_port_ops = {
 350        .set_pio_mode           = svwks_set_pio_mode,
 351        .set_dma_mode           = svwks_set_dma_mode,
 352        .udma_filter            = svwks_udma_filter,
 353        .cable_detect           = svwks_cable_detect,
 354};
 355
 356static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
 357        {       /* 0: OSB4 */
 358                .name           = DRV_NAME,
 359                .init_chipset   = init_chipset_svwks,
 360                .port_ops       = &osb4_port_ops,
 361                .pio_mask       = ATA_PIO4,
 362                .mwdma_mask     = ATA_MWDMA2,
 363                .udma_mask      = 0x00, /* UDMA is problematic on OSB4 */
 364        },
 365        {       /* 1: CSB5 */
 366                .name           = DRV_NAME,
 367                .init_chipset   = init_chipset_svwks,
 368                .port_ops       = &svwks_port_ops,
 369                .pio_mask       = ATA_PIO4,
 370                .mwdma_mask     = ATA_MWDMA2,
 371                .udma_mask      = ATA_UDMA5,
 372        },
 373        {       /* 2: CSB6 */
 374                .name           = DRV_NAME,
 375                .init_chipset   = init_chipset_svwks,
 376                .port_ops       = &svwks_port_ops,
 377                .pio_mask       = ATA_PIO4,
 378                .mwdma_mask     = ATA_MWDMA2,
 379                .udma_mask      = ATA_UDMA5,
 380        },
 381        {       /* 3: CSB6-2 */
 382                .name           = DRV_NAME,
 383                .init_chipset   = init_chipset_svwks,
 384                .port_ops       = &svwks_port_ops,
 385                .host_flags     = IDE_HFLAG_SINGLE,
 386                .pio_mask       = ATA_PIO4,
 387                .mwdma_mask     = ATA_MWDMA2,
 388                .udma_mask      = ATA_UDMA5,
 389        },
 390        {       /* 4: HT1000 */
 391                .name           = DRV_NAME,
 392                .init_chipset   = init_chipset_svwks,
 393                .port_ops       = &svwks_port_ops,
 394                .host_flags     = IDE_HFLAG_SINGLE,
 395                .pio_mask       = ATA_PIO4,
 396                .mwdma_mask     = ATA_MWDMA2,
 397                .udma_mask      = ATA_UDMA5,
 398        }
 399};
 400
 401/**
 402 *      svwks_init_one  -       called when a OSB/CSB is found
 403 *      @dev: the svwks device
 404 *      @id: the matching pci id
 405 *
 406 *      Called when the PCI registration layer (or the IDE initialization)
 407 *      finds a device matching our IDE device tables.
 408 */
 409 
 410static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 411{
 412        struct ide_port_info d;
 413        u8 idx = id->driver_data;
 414
 415        d = serverworks_chipsets[idx];
 416
 417        if (idx == 1)
 418                d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
 419        else if (idx == 2 || idx == 3) {
 420                if ((PCI_FUNC(dev->devfn) & 1) == 0) {
 421                        if (pci_resource_start(dev, 0) != 0x01f1)
 422                                d.host_flags |= IDE_HFLAG_NON_BOOTABLE;
 423                        d.host_flags |= IDE_HFLAG_SINGLE;
 424                } else
 425                        d.host_flags &= ~IDE_HFLAG_SINGLE;
 426        }
 427
 428        return ide_pci_init_one(dev, &d, NULL);
 429}
 430
 431static const struct pci_device_id svwks_pci_tbl[] = {
 432        { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE),   0 },
 433        { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE),   1 },
 434        { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE),   2 },
 435        { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2),  3 },
 436        { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
 437        { 0, },
 438};
 439MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
 440
 441static struct pci_driver svwks_pci_driver = {
 442        .name           = "Serverworks_IDE",
 443        .id_table       = svwks_pci_tbl,
 444        .probe          = svwks_init_one,
 445        .remove         = ide_pci_remove,
 446        .suspend        = ide_pci_suspend,
 447        .resume         = ide_pci_resume,
 448};
 449
 450static int __init svwks_ide_init(void)
 451{
 452        return ide_pci_register_driver(&svwks_pci_driver);
 453}
 454
 455static void __exit svwks_ide_exit(void)
 456{
 457        pci_unregister_driver(&svwks_pci_driver);
 458}
 459
 460module_init(svwks_ide_init);
 461module_exit(svwks_ide_exit);
 462
 463MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
 464MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
 465MODULE_LICENSE("GPL");
 466