LXR linux/arch/powerpc/platforms/83xx/mpc836x

   1/*
   2 * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
   3 *
   4 * Author: Li Yang <LeoLi@freescale.com>
   5 *         Yin Olivia <Hong-hua.Yin@freescale.com>
   6 *
   7 * Description:
   8 * MPC8360E MDS board specific routines.
   9 *
  10 * Changelog:
  11 * Jun 21, 2006 Initial version
  12 *
  13 * This program is free software; you can redistribute it and/or modify it
  14 * under  the terms of  the GNU General  Public License as published by the
  15 * Free Software Foundation;  either version 2 of the  License, or (at your
  16 * option) any later version.
  17 */
  18
  19#include <linux/stddef.h>
  20#include <linux/kernel.h>
  21#include <linux/compiler.h>
  22#include <linux/init.h>
  23#include <linux/errno.h>
  24#include <linux/reboot.h>
  25#include <linux/pci.h>
  26#include <linux/kdev_t.h>
  27#include <linux/major.h>
  28#include <linux/console.h>
  29#include <linux/delay.h>
  30#include <linux/seq_file.h>
  31#include <linux/root_dev.h>
  32#include <linux/initrd.h>
  33#include <linux/of_platform.h>
  34#include <linux/of_device.h>
  35
  36#include <asm/system.h>
  37#include <asm/atomic.h>
  38#include <asm/time.h>
  39#include <asm/io.h>
  40#include <asm/machdep.h>
  41#include <asm/ipic.h>
  42#include <asm/irq.h>
  43#include <asm/prom.h>
  44#include <asm/udbg.h>
  45#include <sysdev/fsl_soc.h>
  46#include <sysdev/fsl_pci.h>
  47#include <sysdev/simple_gpio.h>
  48#include <asm/qe.h>
  49#include <asm/qe_ic.h>
  50
  51#include "mpc83xx.h"
  52
  53#undef DEBUG
  54#ifdef DEBUG
  55#define DBG(fmt...) udbg_printf(fmt)
  56#else
  57#define DBG(fmt...)
  58#endif
  59
  60/* ************************************************************************
  61 *
  62 * Setup the architecture
  63 *
  64 */
  65static void __init mpc836x_mds_setup_arch(void)
  66{
  67        struct device_node *np;
  68        u8 __iomem *bcsr_regs = NULL;
  69
  70        if (ppc_md.progress)
  71                ppc_md.progress("mpc836x_mds_setup_arch()", 0);
  72
  73        /* Map BCSR area */
  74        np = of_find_node_by_name(NULL, "bcsr");
  75        if (np) {
  76                struct resource res;
  77
  78                of_address_to_resource(np, 0, &res);
  79                bcsr_regs = ioremap(res.start, res.end - res.start +1);
  80                of_node_put(np);
  81        }
  82
  83#ifdef CONFIG_PCI
  84        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
  85                mpc83xx_add_bridge(np);
  86#endif
  87
  88#ifdef CONFIG_QUICC_ENGINE
  89        qe_reset();
  90
  91        if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
  92                par_io_init(np);
  93                of_node_put(np);
  94
  95                for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
  96                        par_io_of_config(np);
  97#ifdef CONFIG_QE_USB
  98                /* Must fixup Par IO before QE GPIO chips are registered. */
  99                par_io_config_pin(1,  2, 1, 0, 3, 0); /* USBOE  */
 100                par_io_config_pin(1,  3, 1, 0, 3, 0); /* USBTP  */
 101                par_io_config_pin(1,  8, 1, 0, 1, 0); /* USBTN  */
 102                par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
 103                par_io_config_pin(1,  9, 2, 1, 3, 0); /* USBRP  */
 104                par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN  */
 105                par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21  */
 106#endif /* CONFIG_QE_USB */
 107        }
 108
 109        if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
 110                        != NULL){
 111                uint svid;
 112
 113                /* Reset the Ethernet PHY */
 114#define BCSR9_GETHRST 0x20
 115                clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
 116                udelay(1000);
 117                setbits8(&bcsr_regs[9], BCSR9_GETHRST);
 118
 119                /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
 120                svid = mfspr(SPRN_SVR);
 121                if (svid == 0x80480021) {
 122                        void __iomem *immap;
 123
 124                        immap = ioremap(get_immrbase() + 0x14a8, 8);
 125
 126                        /*
 127                         * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
 128                         * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
 129                         */
 130                        setbits32(immap, 0x0c003000);
 131
 132                        /*
 133                         * IMMR + 0x14AC[20:27] = 10101010
 134                         * (data delay for both UCC's)
 135                         */
 136                        clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
 137
 138                        iounmap(immap);
 139                }
 140
 141                iounmap(bcsr_regs);
 142                of_node_put(np);
 143        }
 144#endif                          /* CONFIG_QUICC_ENGINE */
 145}
 146
 147static struct of_device_id mpc836x_ids[] = {
 148        { .type = "soc", },
 149        { .compatible = "soc", },
 150        { .compatible = "simple-bus", },
 151        { .type = "qe", },
 152        { .compatible = "fsl,qe", },
 153        {},
 154};
 155
 156static int __init mpc836x_declare_of_platform_devices(void)
 157{
 158        /* Publish the QE devices */
 159        of_platform_bus_probe(NULL, mpc836x_ids, NULL);
 160
 161        return 0;
 162}
 163machine_device_initcall(mpc836x_mds, mpc836x_declare_of_platform_devices);
 164
 165#ifdef CONFIG_QE_USB
 166static int __init mpc836x_usb_cfg(void)
 167{
 168        u8 __iomem *bcsr;
 169        struct device_node *np;
 170        const char *mode;
 171        int ret = 0;
 172
 173        np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr");
 174        if (!np)
 175                return -ENODEV;
 176
 177        bcsr = of_iomap(np, 0);
 178        of_node_put(np);
 179        if (!bcsr)
 180                return -ENOMEM;
 181
 182        np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb");
 183        if (!np) {
 184                ret = -ENODEV;
 185                goto err;
 186        }
 187
 188#define BCSR8_TSEC1M_MASK       (0x3 << 6)
 189#define BCSR8_TSEC1M_RGMII      (0x0 << 6)
 190#define BCSR8_TSEC2M_MASK       (0x3 << 4)
 191#define BCSR8_TSEC2M_RGMII      (0x0 << 4)
 192        /*
 193         * Default is GMII (2), but we should set it to RGMII (0) if we use
 194         * USB (Eth PHY is in RGMII mode anyway).
 195         */
 196        clrsetbits_8(&bcsr[8], BCSR8_TSEC1M_MASK | BCSR8_TSEC2M_MASK,
 197                               BCSR8_TSEC1M_RGMII | BCSR8_TSEC2M_RGMII);
 198
 199#define BCSR13_USBMASK  0x0f
 200#define BCSR13_nUSBEN   0x08 /* 1 - Disable, 0 - Enable                 */
 201#define BCSR13_USBSPEED 0x04 /* 1 - Full, 0 - Low                       */
 202#define BCSR13_USBMODE  0x02 /* 1 - Host, 0 - Function                  */
 203#define BCSR13_nUSBVCC  0x01 /* 1 - gets VBUS, 0 - supplies VBUS        */
 204
 205        clrsetbits_8(&bcsr[13], BCSR13_USBMASK, BCSR13_USBSPEED);
 206
 207        mode = of_get_property(np, "mode", NULL);
 208        if (mode && !strcmp(mode, "peripheral")) {
 209                setbits8(&bcsr[13], BCSR13_nUSBVCC);
 210                qe_usb_clock_set(QE_CLK21, 48000000);
 211        } else {
 212                setbits8(&bcsr[13], BCSR13_USBMODE);
 213                /*
 214                 * The BCSR GPIOs are used to control power and
 215                 * speed of the USB transceiver. This is needed for
 216                 * the USB Host only.
 217                 */
 218                simple_gpiochip_init("fsl,mpc8360mds-bcsr-gpio");
 219        }
 220
 221        of_node_put(np);
 222err:
 223        iounmap(bcsr);
 224        return ret;
 225}
 226machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
 227#endif /* CONFIG_QE_USB */
 228
 229static void __init mpc836x_mds_init_IRQ(void)
 230{
 231        struct device_node *np;
 232
 233        np = of_find_node_by_type(NULL, "ipic");
 234        if (!np)
 235                return;
 236
 237        ipic_init(np, 0);
 238
 239        /* Initialize the default interrupt mapping priorities,
 240         * in case the boot rom changed something on us.
 241         */
 242        ipic_set_default_priority();
 243        of_node_put(np);
 244
 245#ifdef CONFIG_QUICC_ENGINE
 246        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
 247        if (!np) {
 248                np = of_find_node_by_type(NULL, "qeic");
 249                if (!np)
 250                        return;
 251        }
 252        qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
 253        of_node_put(np);
 254#endif                          /* CONFIG_QUICC_ENGINE */
 255}
 256
 257/*
 258 * Called very early, MMU is off, device-tree isn't unflattened
 259 */
 260static int __init mpc836x_mds_probe(void)
 261{
 262        unsigned long root = of_get_flat_dt_root();
 263
 264        return of_flat_dt_is_compatible(root, "MPC836xMDS");
 265}
 266
 267define_machine(mpc836x_mds) {
 268        .name           = "MPC836x MDS",
 269        .probe          = mpc836x_mds_probe,
 270        .setup_arch     = mpc836x_mds_setup_arch,
 271        .init_IRQ       = mpc836x_mds_init_IRQ,
 272        .get_irq        = ipic_get_irq,
 273        .restart        = mpc83xx_restart,
 274        .time_init      = mpc83xx_time_init,
 275        .calibrate_decr = generic_calibrate_decr,
 276        .progress       = udbg_progress,
 277};
 278