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13#include <linux/init.h>
14#include <linux/oprofile.h>
15#include <linux/interrupt.h>
16
17#include <loongson.h>
18#include "op_impl.h"
19
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24
25#define LOONGSON2_CPU_TYPE "mips/loongson2"
26
27#define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5)
28#define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9)
29
30#define LOONGSON2_PERFCNT_EXL (1UL << 0)
31#define LOONGSON2_PERFCNT_KERNEL (1UL << 1)
32#define LOONGSON2_PERFCNT_SUPERVISOR (1UL << 2)
33#define LOONGSON2_PERFCNT_USER (1UL << 3)
34#define LOONGSON2_PERFCNT_INT_EN (1UL << 4)
35#define LOONGSON2_PERFCNT_OVERFLOW (1ULL << 31)
36
37
38#define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
39#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
40#define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
41#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)
42
43static struct loongson2_register_config {
44 unsigned int ctrl;
45 unsigned long long reset_counter1;
46 unsigned long long reset_counter2;
47 int cnt1_enabled, cnt2_enabled;
48} reg;
49
50DEFINE_SPINLOCK(sample_lock);
51
52static char *oprofid = "LoongsonPerf";
53static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);
54
55
56static void loongson2_reg_setup(struct op_counter_config *cfg)
57{
58 unsigned int ctrl = 0;
59
60 reg.reset_counter1 = 0;
61 reg.reset_counter2 = 0;
62
63
64 if (cfg[0].enabled) {
65 ctrl |= LOONGSON2_COUNTER1_EVENT(cfg[0].event);
66 reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
67 }
68
69 if (cfg[1].enabled) {
70 ctrl |= LOONGSON2_COUNTER2_EVENT(cfg[1].event);
71 reg.reset_counter2 = (0x80000000ULL - cfg[1].count);
72 }
73
74 if (cfg[0].enabled || cfg[1].enabled) {
75 ctrl |= LOONGSON2_PERFCNT_EXL | LOONGSON2_PERFCNT_INT_EN;
76 if (cfg[0].kernel || cfg[1].kernel)
77 ctrl |= LOONGSON2_PERFCNT_KERNEL;
78 if (cfg[0].user || cfg[1].user)
79 ctrl |= LOONGSON2_PERFCNT_USER;
80 }
81
82 reg.ctrl = ctrl;
83
84 reg.cnt1_enabled = cfg[0].enabled;
85 reg.cnt2_enabled = cfg[1].enabled;
86
87}
88
89
90
91static void loongson2_cpu_setup(void *args)
92{
93 uint64_t perfcount;
94
95 perfcount = (reg.reset_counter2 << 32) | reg.reset_counter1;
96 write_c0_perfcnt(perfcount);
97}
98
99static void loongson2_cpu_start(void *args)
100{
101
102 if (reg.cnt1_enabled || reg.cnt2_enabled)
103 write_c0_perfctrl(reg.ctrl);
104}
105
106static void loongson2_cpu_stop(void *args)
107{
108
109 write_c0_perfctrl(0);
110 memset(®, 0, sizeof(reg));
111}
112
113static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
114{
115 uint64_t counter, counter1, counter2;
116 struct pt_regs *regs = get_irq_regs();
117 int enabled;
118 unsigned long flags;
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127
128 enabled = reg.cnt1_enabled | reg.cnt2_enabled;
129 if (!enabled)
130 return IRQ_NONE;
131
132 counter = read_c0_perfcnt();
133 counter1 = counter & 0xffffffff;
134 counter2 = counter >> 32;
135
136 spin_lock_irqsave(&sample_lock, flags);
137
138 if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
139 if (reg.cnt1_enabled)
140 oprofile_add_sample(regs, 0);
141 counter1 = reg.reset_counter1;
142 }
143 if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) {
144 if (reg.cnt2_enabled)
145 oprofile_add_sample(regs, 1);
146 counter2 = reg.reset_counter2;
147 }
148
149 spin_unlock_irqrestore(&sample_lock, flags);
150
151 write_c0_perfcnt((counter2 << 32) | counter1);
152
153 return IRQ_HANDLED;
154}
155
156static int __init loongson2_init(void)
157{
158 return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler,
159 IRQF_SHARED, "Perfcounter", oprofid);
160}
161
162static void loongson2_exit(void)
163{
164 write_c0_perfctrl(0);
165 free_irq(LOONGSON2_PERFCNT_IRQ, oprofid);
166}
167
168struct op_mips_model op_model_loongson2_ops = {
169 .reg_setup = loongson2_reg_setup,
170 .cpu_setup = loongson2_cpu_setup,
171 .init = loongson2_init,
172 .exit = loongson2_exit,
173 .cpu_start = loongson2_cpu_start,
174 .cpu_stop = loongson2_cpu_stop,
175 .cpu_type = LOONGSON2_CPU_TYPE,
176 .num_counters = 2
177};
178