1#ifndef _IOP13XX_TIME_H_ 2#define _IOP13XX_TIME_H_ 3#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0 4 5#define IOP_TMR_EN 0x02 6#define IOP_TMR_RELOAD 0x04 7#define IOP_TMR_PRIVILEGED 0x08 8#define IOP_TMR_RATIO_1_1 0x00 9 10#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19) 11#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19) 12#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19) 13#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19) 14#define IOP13XX_CORE_FREQ_MASK (7 << 16) 15#define IOP13XX_CORE_FREQ_600 (0 << 16) 16#define IOP13XX_CORE_FREQ_667 (1 << 16) 17#define IOP13XX_CORE_FREQ_800 (2 << 16) 18#define IOP13XX_CORE_FREQ_933 (3 << 16) 19#define IOP13XX_CORE_FREQ_1000 (4 << 16) 20#define IOP13XX_CORE_FREQ_1200 (5 << 16) 21 22void iop_init_time(unsigned long tickrate); 23unsigned long iop_gettimeoffset(void); 24 25static inline unsigned long iop13xx_core_freq(void) 26{ 27 unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ); 28 freq &= IOP13XX_CORE_FREQ_MASK; 29 switch (freq) { 30 case IOP13XX_CORE_FREQ_600: 31 return 600000000; 32 case IOP13XX_CORE_FREQ_667: 33 return 667000000; 34 case IOP13XX_CORE_FREQ_800: 35 return 800000000; 36 case IOP13XX_CORE_FREQ_933: 37 return 933000000; 38 case IOP13XX_CORE_FREQ_1000: 39 return 1000000000; 40 case IOP13XX_CORE_FREQ_1200: 41 return 1200000000; 42 default: 43 printk("%s: warning unknown frequency, defaulting to 800Mhz\n", 44 __func__); 45 } 46 47 return 800000000; 48} 49 50static inline unsigned long iop13xx_xsi_bus_ratio(void) 51{ 52 unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ); 53 ratio &= IOP13XX_XSI_FREQ_RATIO_MASK; 54 switch (ratio) { 55 case IOP13XX_XSI_FREQ_RATIO_2: 56 return 2; 57 case IOP13XX_XSI_FREQ_RATIO_3: 58 return 3; 59 case IOP13XX_XSI_FREQ_RATIO_4: 60 return 4; 61 default: 62 printk("%s: warning unknown ratio, defaulting to 2\n", 63 __func__); 64 } 65 66 return 2; 67} 68 69static inline void write_tmr0(u32 val) 70{ 71 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); 72} 73 74static inline void write_tmr1(u32 val) 75{ 76 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val)); 77} 78 79static inline u32 read_tcr0(void) 80{ 81 u32 val; 82 asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val)); 83 return val; 84} 85 86static inline u32 read_tcr1(void) 87{ 88 u32 val; 89 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val)); 90 return val; 91} 92 93static inline void write_trr0(u32 val) 94{ 95 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val)); 96} 97 98static inline void write_trr1(u32 val) 99{ 100 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val)); 101} 102 103static inline void write_tisr(u32 val) 104{ 105 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val)); 106} 107#endif 108

