1/* 2 * linux/arch/arm/plat-omap/sram-fn.S 3 * 4 * Functions that need to be run in internal SRAM 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#include <linux/linkage.h> 12#include <asm/assembler.h> 13#include <mach/io.h> 14#include <mach/hardware.h> 15 16 .text 17 18/* 19 * Reprograms ULPD and CKCTL. 20 */ 21ENTRY(omap1_sram_reprogram_clock) 22 stmfd sp!, {r0 - r12, lr} @ save registers on stack 23 24 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000 25 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000 26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00 27 28 mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000 29 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000 30 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00 31 32 tst r0, #1 << 4 @ want lock mode? 33 beq newck @ nope 34 bic r0, r0, #1 << 4 @ else clear lock bit 35 strh r0, [r2] @ set dpll into bypass mode 36 orr r0, r0, #1 << 4 @ set lock bit again 37 38newck: 39 strh r1, [r3] @ write new ckctl value 40 strh r0, [r2] @ write new dpll value 41 42 mov r4, #0x0700 @ let the clocks settle 43 orr r4, r4, #0x00ff 44delay: sub r4, r4, #1 45 cmp r4, #0 46 bne delay 47 48lock: ldrh r4, [r2], #0 @ read back dpll value 49 tst r0, #1 << 4 @ want lock mode? 50 beq out @ nope 51 tst r4, #1 << 0 @ dpll rate locked? 52 beq lock @ try again 53 54out: 55 ldmfd sp!, {r0 - r12, pc} @ restore regs and return 56ENTRY(omap1_sram_reprogram_clock_sz) 57 .word . - omap1_sram_reprogram_clock 58