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173#include <linux/module.h>
174#include <linux/init.h>
175#include <linux/ioport.h>
176#include <linux/eisa.h>
177#include <linux/pci.h>
178#include <linux/dma-mapping.h>
179#include <linux/netdevice.h>
180#include <linux/etherdevice.h>
181#include <linux/delay.h>
182#include <linux/spinlock.h>
183#include <linux/workqueue.h>
184#include <linux/mii.h>
185
186#include "tlan.h"
187
188typedef u32 (TLanIntVectorFunc)( struct net_device *, u16 );
189
190
191
192static struct net_device *TLan_Eisa_Devices;
193
194static int TLanDevicesInstalled;
195
196
197static int aui[MAX_TLAN_BOARDS];
198static int duplex[MAX_TLAN_BOARDS];
199static int speed[MAX_TLAN_BOARDS];
200static int boards_found;
201module_param_array(aui, int, NULL, 0);
202module_param_array(duplex, int, NULL, 0);
203module_param_array(speed, int, NULL, 0);
204MODULE_PARM_DESC(aui, "ThunderLAN use AUI port(s) (0-1)");
205MODULE_PARM_DESC(duplex, "ThunderLAN duplex setting(s) (0-default, 1-half, 2-full)");
206MODULE_PARM_DESC(speed, "ThunderLAN port speen setting(s) (0,10,100)");
207
208MODULE_AUTHOR("Maintainer: Samuel Chessman <chessman@tux.org>");
209MODULE_DESCRIPTION("Driver for TI ThunderLAN based ethernet PCI adapters");
210MODULE_LICENSE("GPL");
211
212
213
214#undef MONITOR
215
216
217static int debug;
218module_param(debug, int, 0);
219MODULE_PARM_DESC(debug, "ThunderLAN debug mask");
220
221static const char TLanSignature[] = "TLAN";
222static const char tlan_banner[] = "ThunderLAN driver v1.15a\n";
223static int tlan_have_pci;
224static int tlan_have_eisa;
225
226static const char *media[] = {
227 "10BaseT-HD ", "10BaseT-FD ","100baseTx-HD ",
228 "100baseTx-FD", "100baseT4", NULL
229};
230
231static struct board {
232 const char *deviceLabel;
233 u32 flags;
234 u16 addrOfs;
235} board_info[] = {
236 { "Compaq Netelligent 10 T PCI UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
237 { "Compaq Netelligent 10/100 TX PCI UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
238 { "Compaq Integrated NetFlex-3/P", TLAN_ADAPTER_NONE, 0x83 },
239 { "Compaq NetFlex-3/P",
240 TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83 },
241 { "Compaq NetFlex-3/P", TLAN_ADAPTER_NONE, 0x83 },
242 { "Compaq Netelligent Integrated 10/100 TX UTP",
243 TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
244 { "Compaq Netelligent Dual 10/100 TX PCI UTP", TLAN_ADAPTER_NONE, 0x83 },
245 { "Compaq Netelligent 10/100 TX Embedded UTP", TLAN_ADAPTER_NONE, 0x83 },
246 { "Olicom OC-2183/2185", TLAN_ADAPTER_USE_INTERN_10, 0x83 },
247 { "Olicom OC-2325", TLAN_ADAPTER_UNMANAGED_PHY, 0xF8 },
248 { "Olicom OC-2326", TLAN_ADAPTER_USE_INTERN_10, 0xF8 },
249 { "Compaq Netelligent 10/100 TX UTP", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
250 { "Compaq Netelligent 10 T/2 PCI UTP/Coax", TLAN_ADAPTER_NONE, 0x83 },
251 { "Compaq NetFlex-3/E",
252 TLAN_ADAPTER_ACTIVITY_LED |
253 TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83 },
254 { "Compaq NetFlex-3/E", TLAN_ADAPTER_ACTIVITY_LED, 0x83 },
255};
256
257static struct pci_device_id tlan_pci_tbl[] = {
258 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL10,
259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
260 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL100,
261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
262 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETFLEX3I,
263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
264 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_THUNDER,
265 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
266 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETFLEX3B,
267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
268 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL100PI,
269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
270 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL100D,
271 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
272 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_NETEL100I,
273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7 },
274 { PCI_VENDOR_ID_OLICOM, PCI_DEVICE_ID_OLICOM_OC2183,
275 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
276 { PCI_VENDOR_ID_OLICOM, PCI_DEVICE_ID_OLICOM_OC2325,
277 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9 },
278 { PCI_VENDOR_ID_OLICOM, PCI_DEVICE_ID_OLICOM_OC2326,
279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10 },
280 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100,
281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11 },
282 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_NETELLIGENT_10_T2,
283 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12 },
284 { 0,}
285};
286MODULE_DEVICE_TABLE(pci, tlan_pci_tbl);
287
288static void TLan_EisaProbe( void );
289static void TLan_Eisa_Cleanup( void );
290static int TLan_Init( struct net_device * );
291static int TLan_Open( struct net_device *dev );
292static int TLan_StartTx( struct sk_buff *, struct net_device *);
293static irqreturn_t TLan_HandleInterrupt( int, void *);
294static int TLan_Close( struct net_device *);
295static struct net_device_stats *TLan_GetStats( struct net_device *);
296static void TLan_SetMulticastList( struct net_device *);
297static int TLan_ioctl( struct net_device *dev, struct ifreq *rq, int cmd);
298static int TLan_probe1( struct pci_dev *pdev, long ioaddr,
299 int irq, int rev, const struct pci_device_id *ent);
300static void TLan_tx_timeout( struct net_device *dev);
301static void TLan_tx_timeout_work(struct work_struct *work);
302static int tlan_init_one( struct pci_dev *pdev, const struct pci_device_id *ent);
303
304static u32 TLan_HandleTxEOF( struct net_device *, u16 );
305static u32 TLan_HandleStatOverflow( struct net_device *, u16 );
306static u32 TLan_HandleRxEOF( struct net_device *, u16 );
307static u32 TLan_HandleDummy( struct net_device *, u16 );
308static u32 TLan_HandleTxEOC( struct net_device *, u16 );
309static u32 TLan_HandleStatusCheck( struct net_device *, u16 );
310static u32 TLan_HandleRxEOC( struct net_device *, u16 );
311
312static void TLan_Timer( unsigned long );
313
314static void TLan_ResetLists( struct net_device * );
315static void TLan_FreeLists( struct net_device * );
316static void TLan_PrintDio( u16 );
317static void TLan_PrintList( TLanList *, char *, int );
318static void TLan_ReadAndClearStats( struct net_device *, int );
319static void TLan_ResetAdapter( struct net_device * );
320static void TLan_FinishReset( struct net_device * );
321static void TLan_SetMac( struct net_device *, int areg, char *mac );
322
323static void TLan_PhyPrint( struct net_device * );
324static void TLan_PhyDetect( struct net_device * );
325static void TLan_PhyPowerDown( struct net_device * );
326static void TLan_PhyPowerUp( struct net_device * );
327static void TLan_PhyReset( struct net_device * );
328static void TLan_PhyStartLink( struct net_device * );
329static void TLan_PhyFinishAutoNeg( struct net_device * );
330#ifdef MONITOR
331static void TLan_PhyMonitor( struct net_device * );
332#endif
333
334
335
336
337
338
339
340
341static int TLan_MiiReadReg( struct net_device *, u16, u16, u16 * );
342static void TLan_MiiSendData( u16, u32, unsigned );
343static void TLan_MiiSync( u16 );
344static void TLan_MiiWriteReg( struct net_device *, u16, u16, u16 );
345
346static void TLan_EeSendStart( u16 );
347static int TLan_EeSendByte( u16, u8, int );
348static void TLan_EeReceiveByte( u16, u8 *, int );
349static int TLan_EeReadByte( struct net_device *, u8, u8 * );
350
351
352static inline void
353TLan_StoreSKB( struct tlan_list_tag *tag, struct sk_buff *skb)
354{
355 unsigned long addr = (unsigned long)skb;
356 tag->buffer[9].address = addr;
357 tag->buffer[8].address = upper_32_bits(addr);
358}
359
360static inline struct sk_buff *
361TLan_GetSKB( const struct tlan_list_tag *tag)
362{
363 unsigned long addr;
364
365 addr = tag->buffer[9].address;
366 addr |= (tag->buffer[8].address << 16) << 16;
367 return (struct sk_buff *) addr;
368}
369
370
371static TLanIntVectorFunc *TLanIntVector[TLAN_INT_NUMBER_OF_INTS] = {
372 NULL,
373 TLan_HandleTxEOF,
374 TLan_HandleStatOverflow,
375 TLan_HandleRxEOF,
376 TLan_HandleDummy,
377 TLan_HandleTxEOC,
378 TLan_HandleStatusCheck,
379 TLan_HandleRxEOC
380};
381
382static inline void
383TLan_SetTimer( struct net_device *dev, u32 ticks, u32 type )
384{
385 TLanPrivateInfo *priv = netdev_priv(dev);
386 unsigned long flags = 0;
387
388 if (!in_irq())
389 spin_lock_irqsave(&priv->lock, flags);
390 if ( priv->timer.function != NULL &&
391 priv->timerType != TLAN_TIMER_ACTIVITY ) {
392 if (!in_irq())
393 spin_unlock_irqrestore(&priv->lock, flags);
394 return;
395 }
396 priv->timer.function = &TLan_Timer;
397 if (!in_irq())
398 spin_unlock_irqrestore(&priv->lock, flags);
399
400 priv->timer.data = (unsigned long) dev;
401 priv->timerSetAt = jiffies;
402 priv->timerType = type;
403 mod_timer(&priv->timer, jiffies + ticks);
404
405}
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438static void __devexit tlan_remove_one( struct pci_dev *pdev)
439{
440 struct net_device *dev = pci_get_drvdata( pdev );
441 TLanPrivateInfo *priv = netdev_priv(dev);
442
443 unregister_netdev( dev );
444
445 if ( priv->dmaStorage ) {
446 pci_free_consistent(priv->pciDev,
447 priv->dmaSize, priv->dmaStorage,
448 priv->dmaStorageDMA );
449 }
450
451#ifdef CONFIG_PCI
452 pci_release_regions(pdev);
453#endif
454
455 free_netdev( dev );
456
457 pci_set_drvdata( pdev, NULL );
458}
459
460static struct pci_driver tlan_driver = {
461 .name = "tlan",
462 .id_table = tlan_pci_tbl,
463 .probe = tlan_init_one,
464 .remove = __devexit_p(tlan_remove_one),
465};
466
467static int __init tlan_probe(void)
468{
469 int rc = -ENODEV;
470
471 printk(KERN_INFO "%s", tlan_banner);
472
473 TLAN_DBG(TLAN_DEBUG_PROBE, "Starting PCI Probe....\n");
474
475
476
477 rc = pci_register_driver(&tlan_driver);
478
479 if (rc != 0) {
480 printk(KERN_ERR "TLAN: Could not register pci driver.\n");
481 goto err_out_pci_free;
482 }
483
484 TLAN_DBG(TLAN_DEBUG_PROBE, "Starting EISA Probe....\n");
485 TLan_EisaProbe();
486
487 printk(KERN_INFO "TLAN: %d device%s installed, PCI: %d EISA: %d\n",
488 TLanDevicesInstalled, TLanDevicesInstalled == 1 ? "" : "s",
489 tlan_have_pci, tlan_have_eisa);
490
491 if (TLanDevicesInstalled == 0) {
492 rc = -ENODEV;
493 goto err_out_pci_unreg;
494 }
495 return 0;
496
497err_out_pci_unreg:
498 pci_unregister_driver(&tlan_driver);
499err_out_pci_free:
500 return rc;
501}
502
503
504static int __devinit tlan_init_one( struct pci_dev *pdev,
505 const struct pci_device_id *ent)
506{
507 return TLan_probe1( pdev, -1, -1, 0, ent);
508}
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530static int __devinit TLan_probe1(struct pci_dev *pdev,
531 long ioaddr, int irq, int rev,
532 const struct pci_device_id *ent )
533{
534
535 struct net_device *dev;
536 TLanPrivateInfo *priv;
537 u16 device_id;
538 int reg, rc = -ENODEV;
539
540#ifdef CONFIG_PCI
541 if (pdev) {
542 rc = pci_enable_device(pdev);
543 if (rc)
544 return rc;
545
546 rc = pci_request_regions(pdev, TLanSignature);
547 if (rc) {
548 printk(KERN_ERR "TLAN: Could not reserve IO regions\n");
549 goto err_out;
550 }
551 }
552#endif
553
554 dev = alloc_etherdev(sizeof(TLanPrivateInfo));
555 if (dev == NULL) {
556 printk(KERN_ERR "TLAN: Could not allocate memory for device.\n");
557 rc = -ENOMEM;
558 goto err_out_regions;
559 }
560 SET_NETDEV_DEV(dev, &pdev->dev);
561
562 priv = netdev_priv(dev);
563
564 priv->pciDev = pdev;
565 priv->dev = dev;
566
567
568 if (pdev) {
569 u32 pci_io_base = 0;
570
571 priv->adapter = &board_info[ent->driver_data];
572
573 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
574 if (rc) {
575 printk(KERN_ERR "TLAN: No suitable PCI mapping available.\n");
576 goto err_out_free_dev;
577 }
578
579 for ( reg= 0; reg <= 5; reg ++ ) {
580 if (pci_resource_flags(pdev, reg) & IORESOURCE_IO) {
581 pci_io_base = pci_resource_start(pdev, reg);
582 TLAN_DBG( TLAN_DEBUG_GNRL, "IO mapping is available at %x.\n",
583 pci_io_base);
584 break;
585 }
586 }
587 if (!pci_io_base) {
588 printk(KERN_ERR "TLAN: No IO mappings available\n");
589 rc = -EIO;
590 goto err_out_free_dev;
591 }
592
593 dev->base_addr = pci_io_base;
594 dev->irq = pdev->irq;
595 priv->adapterRev = pdev->revision;
596 pci_set_master(pdev);
597 pci_set_drvdata(pdev, dev);
598
599 } else {
600
601
602 device_id = inw(ioaddr + EISA_ID2);
603 priv->is_eisa = 1;
604 if (device_id == 0x20F1) {
605 priv->adapter = &board_info[13];
606 priv->adapterRev = 23;
607 } else {
608 priv->adapter = &board_info[14];
609 priv->adapterRev = 10;
610 }
611 dev->base_addr = ioaddr;
612 dev->irq = irq;
613 }
614
615
616 if (dev->mem_start) {
617 priv->aui = dev->mem_start & 0x01;
618 priv->duplex = ((dev->mem_start & 0x06) == 0x06) ? 0
619 : (dev->mem_start & 0x06) >> 1;
620 priv->speed = ((dev->mem_start & 0x18) == 0x18) ? 0
621 : (dev->mem_start & 0x18) >> 3;
622
623 if (priv->speed == 0x1) {
624 priv->speed = TLAN_SPEED_10;
625 } else if (priv->speed == 0x2) {
626 priv->speed = TLAN_SPEED_100;
627 }
628 debug = priv->debug = dev->mem_end;
629 } else {
630 priv->aui = aui[boards_found];
631 priv->speed = speed[boards_found];
632 priv->duplex = duplex[boards_found];
633 priv->debug = debug;
634 }
635
636
637
638 INIT_WORK(&priv->tlan_tqueue, TLan_tx_timeout_work);
639
640 spin_lock_init(&priv->lock);
641
642 rc = TLan_Init(dev);
643 if (rc) {
644 printk(KERN_ERR "TLAN: Could not set up device.\n");
645 goto err_out_free_dev;
646 }
647
648 rc = register_netdev(dev);
649 if (rc) {
650 printk(KERN_ERR "TLAN: Could not register device.\n");
651 goto err_out_uninit;
652 }
653
654
655 TLanDevicesInstalled++;
656 boards_found++;
657
658
659 if (pdev)
660 tlan_have_pci++;
661 else {
662 priv->nextDevice = TLan_Eisa_Devices;
663 TLan_Eisa_Devices = dev;
664 tlan_have_eisa++;
665 }
666
667 printk(KERN_INFO "TLAN: %s irq=%2d, io=%04x, %s, Rev. %d\n",
668 dev->name,
669 (int) dev->irq,
670 (int) dev->base_addr,
671 priv->adapter->deviceLabel,
672 priv->adapterRev);
673 return 0;
674
675err_out_uninit:
676 pci_free_consistent(priv->pciDev, priv->dmaSize, priv->dmaStorage,
677 priv->dmaStorageDMA );
678err_out_free_dev:
679 free_netdev(dev);
680err_out_regions:
681#ifdef CONFIG_PCI
682 if (pdev)
683 pci_release_regions(pdev);
684#endif
685err_out:
686 if (pdev)
687 pci_disable_device(pdev);
688 return rc;
689}
690
691
692static void TLan_Eisa_Cleanup(void)
693{
694 struct net_device *dev;
695 TLanPrivateInfo *priv;
696
697 while( tlan_have_eisa ) {
698 dev = TLan_Eisa_Devices;
699 priv = netdev_priv(dev);
700 if (priv->dmaStorage) {
701 pci_free_consistent(priv->pciDev, priv->dmaSize,
702 priv->dmaStorage, priv->dmaStorageDMA );
703 }
704 release_region( dev->base_addr, 0x10);
705 unregister_netdev( dev );
706 TLan_Eisa_Devices = priv->nextDevice;
707 free_netdev( dev );
708 tlan_have_eisa--;
709 }
710}
711
712
713static void __exit tlan_exit(void)
714{
715 pci_unregister_driver(&tlan_driver);
716
717 if (tlan_have_eisa)
718 TLan_Eisa_Cleanup();
719
720}
721
722
723
724module_init(tlan_probe);
725module_exit(tlan_exit);
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741
742static void __init TLan_EisaProbe (void)
743{
744 long ioaddr;
745 int rc = -ENODEV;
746 int irq;
747 u16 device_id;
748
749 if (!EISA_bus) {
750 TLAN_DBG(TLAN_DEBUG_PROBE, "No EISA bus present\n");
751 return;
752 }
753
754
755 for (ioaddr = 0x1000; ioaddr < 0x9000; ioaddr += 0x1000) {
756
757 TLAN_DBG(TLAN_DEBUG_PROBE,"EISA_ID 0x%4x: 0x%4x\n",
758 (int) ioaddr + 0xC80, inw(ioaddr + EISA_ID));
759 TLAN_DBG(TLAN_DEBUG_PROBE,"EISA_ID 0x%4x: 0x%4x\n",
760 (int) ioaddr + 0xC82, inw(ioaddr + EISA_ID2));
761
762
763 TLAN_DBG(TLAN_DEBUG_PROBE, "Probing for EISA adapter at IO: 0x%4x : ",
764 (int) ioaddr);
765 if (request_region(ioaddr, 0x10, TLanSignature) == NULL)
766 goto out;
767
768 if (inw(ioaddr + EISA_ID) != 0x110E) {
769 release_region(ioaddr, 0x10);
770 goto out;
771 }
772
773 device_id = inw(ioaddr + EISA_ID2);
774 if (device_id != 0x20F1 && device_id != 0x40F1) {
775 release_region (ioaddr, 0x10);
776 goto out;
777 }
778
779 if (inb(ioaddr + EISA_CR) != 0x1) {
780 release_region (ioaddr, 0x10);
781 goto out2;
782 }
783
784 if (debug == 0x10)
785 printk("Found one\n");
786
787
788
789 switch (inb(ioaddr + 0xCC0)) {
790 case(0x10):
791 irq=5;
792 break;
793 case(0x20):
794 irq=9;
795 break;
796 case(0x40):
797 irq=10;
798 break;
799 case(0x80):
800 irq=11;
801 break;
802 default:
803 goto out;
804 }
805
806
807
808 rc = TLan_probe1( NULL, ioaddr, irq,
809 12, NULL);
810 continue;
811
812 out:
813 if (debug == 0x10)
814 printk("None found\n");
815 continue;
816
817 out2: if (debug == 0x10)
818 printk("Card found but it is not enabled, skipping\n");
819 continue;
820
821 }
822
823}
824
825#ifdef CONFIG_NET_POLL_CONTROLLER
826static void TLan_Poll(struct net_device *dev)
827{
828 disable_irq(dev->irq);
829 TLan_HandleInterrupt(dev->irq, dev);
830 enable_irq(dev->irq);
831}
832#endif
833
834static const struct net_device_ops TLan_netdev_ops = {
835 .ndo_open = TLan_Open,
836 .ndo_stop = TLan_Close,
837 .ndo_start_xmit = TLan_StartTx,
838 .ndo_tx_timeout = TLan_tx_timeout,
839 .ndo_get_stats = TLan_GetStats,
840 .ndo_set_multicast_list = TLan_SetMulticastList,
841 .ndo_do_ioctl = TLan_ioctl,
842 .ndo_change_mtu = eth_change_mtu,
843 .ndo_set_mac_address = eth_mac_addr,
844 .ndo_validate_addr = eth_validate_addr,
845#ifdef CONFIG_NET_POLL_CONTROLLER
846 .ndo_poll_controller = TLan_Poll,
847#endif
848};
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862
863
864
865
866
867
868
869static int TLan_Init( struct net_device *dev )
870{
871 int dma_size;
872 int err;
873 int i;
874 TLanPrivateInfo *priv;
875
876 priv = netdev_priv(dev);
877
878 dma_size = ( TLAN_NUM_RX_LISTS + TLAN_NUM_TX_LISTS )
879 * ( sizeof(TLanList) );
880 priv->dmaStorage = pci_alloc_consistent(priv->pciDev,
881 dma_size, &priv->dmaStorageDMA);
882 priv->dmaSize = dma_size;
883
884 if ( priv->dmaStorage == NULL ) {
885 printk(KERN_ERR "TLAN: Could not allocate lists and buffers for %s.\n",
886 dev->name );
887 return -ENOMEM;
888 }
889 memset( priv->dmaStorage, 0, dma_size );
890 priv->rxList = (TLanList *) ALIGN((unsigned long)priv->dmaStorage, 8);
891 priv->rxListDMA = ALIGN(priv->dmaStorageDMA, 8);
892 priv->txList = priv->rxList + TLAN_NUM_RX_LISTS;
893 priv->txListDMA = priv->rxListDMA + sizeof(TLanList) * TLAN_NUM_RX_LISTS;
894
895 err = 0;
896 for ( i = 0; i < 6 ; i++ )
897 err |= TLan_EeReadByte( dev,
898 (u8) priv->adapter->addrOfs + i,
899 (u8 *) &dev->dev_addr[i] );
900 if ( err ) {
901 printk(KERN_ERR "TLAN: %s: Error reading MAC from eeprom: %d\n",
902 dev->name,
903 err );
904 }
905 dev->addr_len = 6;
906
907 netif_carrier_off(dev);
908
909
910 dev->netdev_ops = &TLan_netdev_ops;
911 dev->watchdog_timeo = TX_TIMEOUT;
912
913 return 0;
914
915}
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937static int TLan_Open( struct net_device *dev )
938{
939 TLanPrivateInfo *priv = netdev_priv(dev);
940 int err;
941
942 priv->tlanRev = TLan_DioRead8( dev->base_addr, TLAN_DEF_REVISION );
943 err = request_irq( dev->irq, TLan_HandleInterrupt, IRQF_SHARED,
944 dev->name, dev );
945
946 if ( err ) {
947 pr_err("TLAN: Cannot open %s because IRQ %d is already in use.\n",
948 dev->name, dev->irq );
949 return err;
950 }
951
952 init_timer(&priv->timer);
953 netif_start_queue(dev);
954
955
956
957
958 TLan_ResetLists( dev );
959 TLan_ReadAndClearStats( dev, TLAN_IGNORE );
960 TLan_ResetAdapter( dev );
961
962 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Opened. TLAN Chip Rev: %x\n",
963 dev->name, priv->tlanRev );
964
965 return 0;
966
967}
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986static int TLan_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
987{
988 TLanPrivateInfo *priv = netdev_priv(dev);
989 struct mii_ioctl_data *data = if_mii(rq);
990 u32 phy = priv->phy[priv->phyNum];
991
992 if (!priv->phyOnline)
993 return -EAGAIN;
994
995 switch(cmd) {
996 case SIOCGMIIPHY:
997 data->phy_id = phy;
998
999
1000 case SIOCGMIIREG:
1001 TLan_MiiReadReg(dev, data->phy_id & 0x1f,
1002 data->reg_num & 0x1f, &data->val_out);
1003 return 0;
1004
1005
1006 case SIOCSMIIREG:
1007 if (!capable(CAP_NET_ADMIN))
1008 return -EPERM;
1009 TLan_MiiWriteReg(dev, data->phy_id & 0x1f,
1010 data->reg_num & 0x1f, data->val_in);
1011 return 0;
1012 default:
1013 return -EOPNOTSUPP;
1014 }
1015}
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029static void TLan_tx_timeout(struct net_device *dev)
1030{
1031
1032 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Transmit timed out.\n", dev->name);
1033
1034
1035 TLan_FreeLists( dev );
1036 TLan_ResetLists( dev );
1037 TLan_ReadAndClearStats( dev, TLAN_IGNORE );
1038 TLan_ResetAdapter( dev );
1039 dev->trans_start = jiffies;
1040 netif_wake_queue( dev );
1041
1042}
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055static void TLan_tx_timeout_work(struct work_struct *work)
1056{
1057 TLanPrivateInfo *priv =
1058 container_of(work, TLanPrivateInfo, tlan_tqueue);
1059
1060 TLan_tx_timeout(priv->dev);
1061}
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086static int TLan_StartTx( struct sk_buff *skb, struct net_device *dev )
1087{
1088 TLanPrivateInfo *priv = netdev_priv(dev);
1089 dma_addr_t tail_list_phys;
1090 TLanList *tail_list;
1091 unsigned long flags;
1092 unsigned int txlen;
1093
1094 if ( ! priv->phyOnline ) {
1095 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s PHY is not ready\n",
1096 dev->name );
1097 dev_kfree_skb_any(skb);
1098 return 0;
1099 }
1100
1101 if (skb_padto(skb, TLAN_MIN_FRAME_SIZE))
1102 return 0;
1103 txlen = max(skb->len, (unsigned int)TLAN_MIN_FRAME_SIZE);
1104
1105 tail_list = priv->txList + priv->txTail;
1106 tail_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txTail;
1107
1108 if ( tail_list->cStat != TLAN_CSTAT_UNUSED ) {
1109 TLAN_DBG( TLAN_DEBUG_TX,
1110 "TRANSMIT: %s is busy (Head=%d Tail=%d)\n",
1111 dev->name, priv->txHead, priv->txTail );
1112 netif_stop_queue(dev);
1113 priv->txBusyCount++;
1114 return NETDEV_TX_BUSY;
1115 }
1116
1117 tail_list->forward = 0;
1118
1119 tail_list->buffer[0].address = pci_map_single(priv->pciDev,
1120 skb->data, txlen,
1121 PCI_DMA_TODEVICE);
1122 TLan_StoreSKB(tail_list, skb);
1123
1124 tail_list->frameSize = (u16) txlen;
1125 tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) txlen;
1126 tail_list->buffer[1].count = 0;
1127 tail_list->buffer[1].address = 0;
1128
1129 spin_lock_irqsave(&priv->lock, flags);
1130 tail_list->cStat = TLAN_CSTAT_READY;
1131 if ( ! priv->txInProgress ) {
1132 priv->txInProgress = 1;
1133 TLAN_DBG( TLAN_DEBUG_TX,
1134 "TRANSMIT: Starting TX on buffer %d\n", priv->txTail );
1135 outl( tail_list_phys, dev->base_addr + TLAN_CH_PARM );
1136 outl( TLAN_HC_GO, dev->base_addr + TLAN_HOST_CMD );
1137 } else {
1138 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Adding buffer %d to TX channel\n",
1139 priv->txTail );
1140 if ( priv->txTail == 0 ) {
1141 ( priv->txList + ( TLAN_NUM_TX_LISTS - 1 ) )->forward
1142 = tail_list_phys;
1143 } else {
1144 ( priv->txList + ( priv->txTail - 1 ) )->forward
1145 = tail_list_phys;
1146 }
1147 }
1148 spin_unlock_irqrestore(&priv->lock, flags);
1149
1150 CIRC_INC( priv->txTail, TLAN_NUM_TX_LISTS );
1151
1152 dev->trans_start = jiffies;
1153 return 0;
1154
1155}
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180static irqreturn_t TLan_HandleInterrupt(int irq, void *dev_id)
1181{
1182 struct net_device *dev = dev_id;
1183 TLanPrivateInfo *priv = netdev_priv(dev);
1184 u16 host_int;
1185 u16 type;
1186
1187 spin_lock(&priv->lock);
1188
1189 host_int = inw( dev->base_addr + TLAN_HOST_INT );
1190 type = ( host_int & TLAN_HI_IT_MASK ) >> 2;
1191 if ( type ) {
1192 u32 ack;
1193 u32 host_cmd;
1194
1195 outw( host_int, dev->base_addr + TLAN_HOST_INT );
1196 ack = TLanIntVector[type]( dev, host_int );
1197
1198 if ( ack ) {
1199 host_cmd = TLAN_HC_ACK | ack | ( type << 18 );
1200 outl( host_cmd, dev->base_addr + TLAN_HOST_CMD );
1201 }
1202 }
1203
1204 spin_unlock(&priv->lock);
1205
1206 return IRQ_RETVAL(type);
1207}
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227static int TLan_Close(struct net_device *dev)
1228{
1229 TLanPrivateInfo *priv = netdev_priv(dev);
1230
1231 netif_stop_queue(dev);
1232 priv->neg_be_verbose = 0;
1233
1234 TLan_ReadAndClearStats( dev, TLAN_RECORD );
1235 outl( TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD );
1236 if ( priv->timer.function != NULL ) {
1237 del_timer_sync( &priv->timer );
1238 priv->timer.function = NULL;
1239 }
1240
1241 free_irq( dev->irq, dev );
1242 TLan_FreeLists( dev );
1243 TLAN_DBG( TLAN_DEBUG_GNRL, "Device %s closed.\n", dev->name );
1244
1245 return 0;
1246
1247}
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267static struct net_device_stats *TLan_GetStats( struct net_device *dev )
1268{
1269 TLanPrivateInfo *priv = netdev_priv(dev);
1270 int i;
1271
1272
1273 TLan_ReadAndClearStats( dev, TLAN_RECORD );
1274
1275 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: %s EOC count = %d\n", dev->name,
1276 priv->rxEocCount );
1277 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: %s Busy count = %d\n", dev->name,
1278 priv->txBusyCount );
1279 if ( debug & TLAN_DEBUG_GNRL ) {
1280 TLan_PrintDio( dev->base_addr );
1281 TLan_PhyPrint( dev );
1282 }
1283 if ( debug & TLAN_DEBUG_LIST ) {
1284 for ( i = 0; i < TLAN_NUM_RX_LISTS; i++ )
1285 TLan_PrintList( priv->rxList + i, "RX", i );
1286 for ( i = 0; i < TLAN_NUM_TX_LISTS; i++ )
1287 TLan_PrintList( priv->txList + i, "TX", i );
1288 }
1289
1290 return &dev->stats;
1291
1292}
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317static void TLan_SetMulticastList( struct net_device *dev )
1318{
1319 struct dev_mc_list *dmi = dev->mc_list;
1320 u32 hash1 = 0;
1321 u32 hash2 = 0;
1322 int i;
1323 u32 offset;
1324 u8 tmp;
1325
1326 if ( dev->flags & IFF_PROMISC ) {
1327 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD );
1328 TLan_DioWrite8( dev->base_addr,
1329 TLAN_NET_CMD, tmp | TLAN_NET_CMD_CAF );
1330 } else {
1331 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD );
1332 TLan_DioWrite8( dev->base_addr,
1333 TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF );
1334 if ( dev->flags & IFF_ALLMULTI ) {
1335 for ( i = 0; i < 3; i++ )
1336 TLan_SetMac( dev, i + 1, NULL );
1337 TLan_DioWrite32( dev->base_addr, TLAN_HASH_1, 0xFFFFFFFF );
1338 TLan_DioWrite32( dev->base_addr, TLAN_HASH_2, 0xFFFFFFFF );
1339 } else {
1340 for ( i = 0; i < dev->mc_count; i++ ) {
1341 if ( i < 3 ) {
1342 TLan_SetMac( dev, i + 1,
1343 (char *) &dmi->dmi_addr );
1344 } else {
1345 offset = TLan_HashFunc( (u8 *) &dmi->dmi_addr );
1346 if ( offset < 32 )
1347 hash1 |= ( 1 << offset );
1348 else
1349 hash2 |= ( 1 << ( offset - 32 ) );
1350 }
1351 dmi = dmi->next;
1352 }
1353 for ( ; i < 3; i++ )
1354 TLan_SetMac( dev, i + 1, NULL );
1355 TLan_DioWrite32( dev->base_addr, TLAN_HASH_1, hash1 );
1356 TLan_DioWrite32( dev->base_addr, TLAN_HASH_2, hash2 );
1357 }
1358 }
1359
1360}
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
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1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401static u32 TLan_HandleTxEOF( struct net_device *dev, u16 host_int )
1402{
1403 TLanPrivateInfo *priv = netdev_priv(dev);
1404 int eoc = 0;
1405 TLanList *head_list;
1406 dma_addr_t head_list_phys;
1407 u32 ack = 0;
1408 u16 tmpCStat;
1409
1410 TLAN_DBG( TLAN_DEBUG_TX, "TRANSMIT: Handling TX EOF (Head=%d Tail=%d)\n",
1411 priv->txHead, priv->txTail );
1412 head_list = priv->txList + priv->txHead;
1413
1414 while (((tmpCStat = head_list->cStat ) & TLAN_CSTAT_FRM_CMP) && (ack < 255)) {
1415 struct sk_buff *skb = TLan_GetSKB(head_list);
1416
1417 ack++;
1418 pci_unmap_single(priv->pciDev, head_list->buffer[0].address,
1419 max(skb->len,
1420 (unsigned int)TLAN_MIN_FRAME_SIZE),
1421 PCI_DMA_TODEVICE);
1422 dev_kfree_skb_any(skb);
1423 head_list->buffer[8].address = 0;
1424 head_list->buffer[9].address = 0;
1425
1426 if ( tmpCStat & TLAN_CSTAT_EOC )
1427 eoc = 1;
1428
1429 dev->stats.tx_bytes += head_list->frameSize;
1430
1431 head_list->cStat = TLAN_CSTAT_UNUSED;
1432 netif_start_queue(dev);
1433 CIRC_INC( priv->txHead, TLAN_NUM_TX_LISTS );
1434 head_list = priv->txList + priv->txHead;
1435 }
1436
1437 if (!ack)
1438 printk(KERN_INFO "TLAN: Received interrupt for uncompleted TX frame.\n");
1439
1440 if ( eoc ) {
1441 TLAN_DBG( TLAN_DEBUG_TX,
1442 "TRANSMIT: Handling TX EOC (Head=%d Tail=%d)\n",
1443 priv->txHead, priv->txTail );
1444 head_list = priv->txList + priv->txHead;
1445 head_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txHead;
1446 if ( ( head_list->cStat & TLAN_CSTAT_READY ) == TLAN_CSTAT_READY ) {
1447 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM );
1448 ack |= TLAN_HC_GO;
1449 } else {
1450 priv->txInProgress = 0;
1451 }
1452 }
1453
1454 if ( priv->adapter->flags & TLAN_ADAPTER_ACTIVITY_LED ) {
1455 TLan_DioWrite8( dev->base_addr,
1456 TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT );
1457 if ( priv->timer.function == NULL ) {
1458 priv->timer.function = &TLan_Timer;
1459 priv->timer.data = (unsigned long) dev;
1460 priv->timer.expires = jiffies + TLAN_TIMER_ACT_DELAY;
1461 priv->timerSetAt = jiffies;
1462 priv->timerType = TLAN_TIMER_ACTIVITY;
1463 add_timer(&priv->timer);
1464 } else if ( priv->timerType == TLAN_TIMER_ACTIVITY ) {
1465 priv->timerSetAt = jiffies;
1466 }
1467 }
1468
1469 return ack;
1470
1471}
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493static u32 TLan_HandleStatOverflow( struct net_device *dev, u16 host_int )
1494{
1495 TLan_ReadAndClearStats( dev, TLAN_RECORD );
1496
1497 return 1;
1498
1499}
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529static u32 TLan_HandleRxEOF( struct net_device *dev, u16 host_int )
1530{
1531 TLanPrivateInfo *priv = netdev_priv(dev);
1532 u32 ack = 0;
1533 int eoc = 0;
1534 TLanList *head_list;
1535 struct sk_buff *skb;
1536 TLanList *tail_list;
1537 u16 tmpCStat;
1538 dma_addr_t head_list_phys;
1539
1540 TLAN_DBG( TLAN_DEBUG_RX, "RECEIVE: Handling RX EOF (Head=%d Tail=%d)\n",
1541 priv->rxHead, priv->rxTail );
1542 head_list = priv->rxList + priv->rxHead;
1543 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1544
1545 while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP) && (ack < 255)) {
1546 dma_addr_t frameDma = head_list->buffer[0].address;
1547 u32 frameSize = head_list->frameSize;
1548 struct sk_buff *new_skb;
1549
1550 ack++;
1551 if (tmpCStat & TLAN_CSTAT_EOC)
1552 eoc = 1;
1553
1554 new_skb = netdev_alloc_skb(dev, TLAN_MAX_FRAME_SIZE + 7 );
1555 if ( !new_skb )
1556 goto drop_and_reuse;
1557
1558 skb = TLan_GetSKB(head_list);
1559 pci_unmap_single(priv->pciDev, frameDma,
1560 TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE);
1561 skb_put( skb, frameSize );
1562
1563 dev->stats.rx_bytes += frameSize;
1564
1565 skb->protocol = eth_type_trans( skb, dev );
1566 netif_rx( skb );
1567
1568 skb_reserve( new_skb, NET_IP_ALIGN );
1569 head_list->buffer[0].address = pci_map_single(priv->pciDev,
1570 new_skb->data,
1571 TLAN_MAX_FRAME_SIZE,
1572 PCI_DMA_FROMDEVICE);
1573
1574 TLan_StoreSKB(head_list, new_skb);
1575drop_and_reuse:
1576 head_list->forward = 0;
1577 head_list->cStat = 0;
1578 tail_list = priv->rxList + priv->rxTail;
1579 tail_list->forward = head_list_phys;
1580
1581 CIRC_INC( priv->rxHead, TLAN_NUM_RX_LISTS );
1582 CIRC_INC( priv->rxTail, TLAN_NUM_RX_LISTS );
1583 head_list = priv->rxList + priv->rxHead;
1584 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1585 }
1586
1587 if (!ack)
1588 printk(KERN_INFO "TLAN: Received interrupt for uncompleted RX frame.\n");
1589
1590
1591 if ( eoc ) {
1592 TLAN_DBG( TLAN_DEBUG_RX,
1593 "RECEIVE: Handling RX EOC (Head=%d Tail=%d)\n",
1594 priv->rxHead, priv->rxTail );
1595 head_list = priv->rxList + priv->rxHead;
1596 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1597 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM );
1598 ack |= TLAN_HC_GO | TLAN_HC_RT;
1599 priv->rxEocCount++;
1600 }
1601
1602 if ( priv->adapter->flags & TLAN_ADAPTER_ACTIVITY_LED ) {
1603 TLan_DioWrite8( dev->base_addr,
1604 TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT );
1605 if ( priv->timer.function == NULL ) {
1606 priv->timer.function = &TLan_Timer;
1607 priv->timer.data = (unsigned long) dev;
1608 priv->timer.expires = jiffies + TLAN_TIMER_ACT_DELAY;
1609 priv->timerSetAt = jiffies;
1610 priv->timerType = TLAN_TIMER_ACTIVITY;
1611 add_timer(&priv->timer);
1612 } else if ( priv->timerType == TLAN_TIMER_ACTIVITY ) {
1613 priv->timerSetAt = jiffies;
1614 }
1615 }
1616
1617 return ack;
1618
1619}
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641static u32 TLan_HandleDummy( struct net_device *dev, u16 host_int )
1642{
1643 printk( "TLAN: Test interrupt on %s.\n", dev->name );
1644 return 1;
1645
1646}
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671static u32 TLan_HandleTxEOC( struct net_device *dev, u16 host_int )
1672{
1673 TLanPrivateInfo *priv = netdev_priv(dev);
1674 TLanList *head_list;
1675 dma_addr_t head_list_phys;
1676 u32 ack = 1;
1677
1678 host_int = 0;
1679 if ( priv->tlanRev < 0x30 ) {
1680 TLAN_DBG( TLAN_DEBUG_TX,
1681 "TRANSMIT: Handling TX EOC (Head=%d Tail=%d) -- IRQ\n",
1682 priv->txHead, priv->txTail );
1683 head_list = priv->txList + priv->txHead;
1684 head_list_phys = priv->txListDMA + sizeof(TLanList) * priv->txHead;
1685 if ( ( head_list->cStat & TLAN_CSTAT_READY ) == TLAN_CSTAT_READY ) {
1686 netif_stop_queue(dev);
1687 outl( head_list_phys, dev->base_addr + TLAN_CH_PARM );
1688 ack |= TLAN_HC_GO;
1689 } else {
1690 priv->txInProgress = 0;
1691 }
1692 }
1693
1694 return ack;
1695
1696}
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721static u32 TLan_HandleStatusCheck( struct net_device *dev, u16 host_int )
1722{
1723 TLanPrivateInfo *priv = netdev_priv(dev);
1724 u32 ack;
1725 u32 error;
1726 u8 net_sts;
1727 u32 phy;
1728 u16 tlphy_ctl;
1729 u16 tlphy_sts;
1730
1731 ack = 1;
1732 if ( host_int & TLAN_HI_IV_MASK ) {
1733 netif_stop_queue( dev );
1734 error = inl( dev->base_addr + TLAN_CH_PARM );
1735 printk( "TLAN: %s: Adaptor Error = 0x%x\n", dev->name, error );
1736 TLan_ReadAndClearStats( dev, TLAN_RECORD );
1737 outl( TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD );
1738
1739 schedule_work(&priv->tlan_tqueue);
1740
1741 netif_wake_queue(dev);
1742 ack = 0;
1743 } else {
1744 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Status Check\n", dev->name );
1745 phy = priv->phy[priv->phyNum];
1746
1747 net_sts = TLan_DioRead8( dev->base_addr, TLAN_NET_STS );
1748 if ( net_sts ) {
1749 TLan_DioWrite8( dev->base_addr, TLAN_NET_STS, net_sts );
1750 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Net_Sts = %x\n",
1751 dev->name, (unsigned) net_sts );
1752 }
1753 if ( ( net_sts & TLAN_NET_STS_MIRQ ) && ( priv->phyNum == 0 ) ) {
1754 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_STS, &tlphy_sts );
1755 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl );
1756 if ( ! ( tlphy_sts & TLAN_TS_POLOK ) &&
1757 ! ( tlphy_ctl & TLAN_TC_SWAPOL ) ) {
1758 tlphy_ctl |= TLAN_TC_SWAPOL;
1759 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);
1760 } else if ( ( tlphy_sts & TLAN_TS_POLOK )
1761 && ( tlphy_ctl & TLAN_TC_SWAPOL ) ) {
1762 tlphy_ctl &= ~TLAN_TC_SWAPOL;
1763 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl);
1764 }
1765
1766 if (debug) {
1767 TLan_PhyPrint( dev );
1768 }
1769 }
1770 }
1771
1772 return ack;
1773
1774}
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799static u32 TLan_HandleRxEOC( struct net_device *dev, u16 host_int )
1800{
1801 TLanPrivateInfo *priv = netdev_priv(dev);
1802 dma_addr_t head_list_phys;
1803 u32 ack = 1;
1804
1805 if ( priv->tlanRev < 0x30 ) {
1806 TLAN_DBG( TLAN_DEBUG_RX,
1807 "RECEIVE: Handling RX EOC (Head=%d Tail=%d) -- IRQ\n",
1808 priv->rxHead, priv->rxTail );
1809 head_list_phys = priv->rxListDMA + sizeof(TLanList) * priv->rxHead;
1810 outl( head_list_phys, dev->base_addr + TLAN_CH_PARM );
1811 ack |= TLAN_HC_GO | TLAN_HC_RT;
1812 priv->rxEocCount++;
1813 }
1814
1815 return ack;
1816
1817}
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
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1841
1842
1843
1844
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1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861static void TLan_Timer( unsigned long data )
1862{
1863 struct net_device *dev = (struct net_device *) data;
1864 TLanPrivateInfo *priv = netdev_priv(dev);
1865 u32 elapsed;
1866 unsigned long flags = 0;
1867
1868 priv->timer.function = NULL;
1869
1870 switch ( priv->timerType ) {
1871#ifdef MONITOR
1872 case TLAN_TIMER_LINK_BEAT:
1873 TLan_PhyMonitor( dev );
1874 break;
1875#endif
1876 case TLAN_TIMER_PHY_PDOWN:
1877 TLan_PhyPowerDown( dev );
1878 break;
1879 case TLAN_TIMER_PHY_PUP:
1880 TLan_PhyPowerUp( dev );
1881 break;
1882 case TLAN_TIMER_PHY_RESET:
1883 TLan_PhyReset( dev );
1884 break;
1885 case TLAN_TIMER_PHY_START_LINK:
1886 TLan_PhyStartLink( dev );
1887 break;
1888 case TLAN_TIMER_PHY_FINISH_AN:
1889 TLan_PhyFinishAutoNeg( dev );
1890 break;
1891 case TLAN_TIMER_FINISH_RESET:
1892 TLan_FinishReset( dev );
1893 break;
1894 case TLAN_TIMER_ACTIVITY:
1895 spin_lock_irqsave(&priv->lock, flags);
1896 if ( priv->timer.function == NULL ) {
1897 elapsed = jiffies - priv->timerSetAt;
1898 if ( elapsed >= TLAN_TIMER_ACT_DELAY ) {
1899 TLan_DioWrite8( dev->base_addr,
1900 TLAN_LED_REG, TLAN_LED_LINK );
1901 } else {
1902 priv->timer.function = &TLan_Timer;
1903 priv->timer.expires = priv->timerSetAt
1904 + TLAN_TIMER_ACT_DELAY;
1905 spin_unlock_irqrestore(&priv->lock, flags);
1906 add_timer( &priv->timer );
1907 break;
1908 }
1909 }
1910 spin_unlock_irqrestore(&priv->lock, flags);
1911 break;
1912 default:
1913 break;
1914 }
1915
1916}
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944static void TLan_ResetLists( struct net_device *dev )
1945{
1946 TLanPrivateInfo *priv = netdev_priv(dev);
1947 int i;
1948 TLanList *list;
1949 dma_addr_t list_phys;
1950 struct sk_buff *skb;
1951
1952 priv->txHead = 0;
1953 priv->txTail = 0;
1954 for ( i = 0; i < TLAN_NUM_TX_LISTS; i++ ) {
1955 list = priv->txList + i;
1956 list->cStat = TLAN_CSTAT_UNUSED;
1957 list->buffer[0].address = 0;
1958 list->buffer[2].count = 0;
1959 list->buffer[2].address = 0;
1960 list->buffer[8].address = 0;
1961 list->buffer[9].address = 0;
1962 }
1963
1964 priv->rxHead = 0;
1965 priv->rxTail = TLAN_NUM_RX_LISTS - 1;
1966 for ( i = 0; i < TLAN_NUM_RX_LISTS; i++ ) {
1967 list = priv->rxList + i;
1968 list_phys = priv->rxListDMA + sizeof(TLanList) * i;
1969 list->cStat = TLAN_CSTAT_READY;
1970 list->frameSize = TLAN_MAX_FRAME_SIZE;
1971 list->buffer[0].count = TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER;
1972 skb = netdev_alloc_skb(dev, TLAN_MAX_FRAME_SIZE + 7 );
1973 if ( !skb ) {
1974 pr_err("TLAN: out of memory for received data.\n" );
1975 break;
1976 }
1977
1978 skb_reserve( skb, NET_IP_ALIGN );
1979 list->buffer[0].address = pci_map_single(priv->pciDev,
1980 skb->data,
1981 TLAN_MAX_FRAME_SIZE,
1982 PCI_DMA_FROMDEVICE);
1983 TLan_StoreSKB(list, skb);
1984 list->buffer[1].count = 0;
1985 list->buffer[1].address = 0;
1986 list->forward = list_phys + sizeof(TLanList);
1987 }
1988
1989
1990 while (i < TLAN_NUM_RX_LISTS) {
1991 TLan_StoreSKB(priv->rxList + i, NULL);
1992 ++i;
1993 }
1994 list->forward = 0;
1995
1996}
1997
1998
1999static void TLan_FreeLists( struct net_device *dev )
2000{
2001 TLanPrivateInfo *priv = netdev_priv(dev);
2002 int i;
2003 TLanList *list;
2004 struct sk_buff *skb;
2005
2006 for ( i = 0; i < TLAN_NUM_TX_LISTS; i++ ) {
2007 list = priv->txList + i;
2008 skb = TLan_GetSKB(list);
2009 if ( skb ) {
2010 pci_unmap_single(
2011 priv->pciDev,
2012 list->buffer[0].address,
2013 max(skb->len,
2014 (unsigned int)TLAN_MIN_FRAME_SIZE),
2015 PCI_DMA_TODEVICE);
2016 dev_kfree_skb_any( skb );
2017 list->buffer[8].address = 0;
2018 list->buffer[9].address = 0;
2019 }
2020 }
2021
2022 for ( i = 0; i < TLAN_NUM_RX_LISTS; i++ ) {
2023 list = priv->rxList + i;
2024 skb = TLan_GetSKB(list);
2025 if ( skb ) {
2026 pci_unmap_single(priv->pciDev,
2027 list->buffer[0].address,
2028 TLAN_MAX_FRAME_SIZE,
2029 PCI_DMA_FROMDEVICE);
2030 dev_kfree_skb_any( skb );
2031 list->buffer[8].address = 0;
2032 list->buffer[9].address = 0;
2033 }
2034 }
2035}
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054static void TLan_PrintDio( u16 io_base )
2055{
2056 u32 data0, data1;
2057 int i;
2058
2059 printk( "TLAN: Contents of internal registers for io base 0x%04hx.\n",
2060 io_base );
2061 printk( "TLAN: Off. +0 +4\n" );
2062 for ( i = 0; i < 0x4C; i+= 8 ) {
2063 data0 = TLan_DioRead32( io_base, i );
2064 data1 = TLan_DioRead32( io_base, i + 0x4 );
2065 printk( "TLAN: 0x%02x 0x%08x 0x%08x\n", i, data0, data1 );
2066 }
2067
2068}
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090static void TLan_PrintList( TLanList *list, char *type, int num)
2091{
2092 int i;
2093
2094 printk( "TLAN: %s List %d at %p\n", type, num, list );
2095 printk( "TLAN: Forward = 0x%08x\n", list->forward );
2096 printk( "TLAN: CSTAT = 0x%04hx\n", list->cStat );
2097 printk( "TLAN: Frame Size = 0x%04hx\n", list->frameSize );
2098
2099 for ( i = 0; i < 2; i++ ) {
2100 printk( "TLAN: Buffer[%d].count, addr = 0x%08x, 0x%08x\n",
2101 i, list->buffer[i].count, list->buffer[i].address );
2102 }
2103
2104}
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127static void TLan_ReadAndClearStats( struct net_device *dev, int record )
2128{
2129 u32 tx_good, tx_under;
2130 u32 rx_good, rx_over;
2131 u32 def_tx, crc, code;
2132 u32 multi_col, single_col;
2133 u32 excess_col, late_col, loss;
2134
2135 outw( TLAN_GOOD_TX_FRMS, dev->base_addr + TLAN_DIO_ADR );
2136 tx_good = inb( dev->base_addr + TLAN_DIO_DATA );
2137 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
2138 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 2 ) << 16;
2139 tx_under = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
2140
2141 outw( TLAN_GOOD_RX_FRMS, dev->base_addr + TLAN_DIO_ADR );
2142 rx_good = inb( dev->base_addr + TLAN_DIO_DATA );
2143 rx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
2144 rx_good += inb( dev->base_addr + TLAN_DIO_DATA + 2 ) << 16;
2145 rx_over = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
2146
2147 outw( TLAN_DEFERRED_TX, dev->base_addr + TLAN_DIO_ADR );
2148 def_tx = inb( dev->base_addr + TLAN_DIO_DATA );
2149 def_tx += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
2150 crc = inb( dev->base_addr + TLAN_DIO_DATA + 2 );
2151 code = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
2152
2153 outw( TLAN_MULTICOL_FRMS, dev->base_addr + TLAN_DIO_ADR );
2154 multi_col = inb( dev->base_addr + TLAN_DIO_DATA );
2155 multi_col += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
2156 single_col = inb( dev->base_addr + TLAN_DIO_DATA + 2 );
2157 single_col += inb( dev->base_addr + TLAN_DIO_DATA + 3 ) << 8;
2158
2159 outw( TLAN_EXCESSCOL_FRMS, dev->base_addr + TLAN_DIO_ADR );
2160 excess_col = inb( dev->base_addr + TLAN_DIO_DATA );
2161 late_col = inb( dev->base_addr + TLAN_DIO_DATA + 1 );
2162 loss = inb( dev->base_addr + TLAN_DIO_DATA + 2 );
2163
2164 if ( record ) {
2165 dev->stats.rx_packets += rx_good;
2166 dev->stats.rx_errors += rx_over + crc + code;
2167 dev->stats.tx_packets += tx_good;
2168 dev->stats.tx_errors += tx_under + loss;
2169 dev->stats.collisions += multi_col + single_col + excess_col + late_col;
2170
2171 dev->stats.rx_over_errors += rx_over;
2172 dev->stats.rx_crc_errors += crc;
2173 dev->stats.rx_frame_errors += code;
2174
2175 dev->stats.tx_aborted_errors += tx_under;
2176 dev->stats.tx_carrier_errors += loss;
2177 }
2178
2179}
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201static void
2202TLan_ResetAdapter( struct net_device *dev )
2203{
2204 TLanPrivateInfo *priv = netdev_priv(dev);
2205 int i;
2206 u32 addr;
2207 u32 data;
2208 u8 data8;
2209
2210 priv->tlanFullDuplex = FALSE;
2211 priv->phyOnline=0;
2212 netif_carrier_off(dev);
2213
2214
2215
2216 data = inl(dev->base_addr + TLAN_HOST_CMD);
2217 data |= TLAN_HC_AD_RST;
2218 outl(data, dev->base_addr + TLAN_HOST_CMD);
2219
2220 udelay(1000);
2221
2222
2223
2224 data = inl(dev->base_addr + TLAN_HOST_CMD);
2225 data |= TLAN_HC_INT_OFF;
2226 outl(data, dev->base_addr + TLAN_HOST_CMD);
2227
2228
2229
2230 for ( i = TLAN_AREG_0; i <= TLAN_HASH_2; i += 4 ) {
2231 TLan_DioWrite32( dev->base_addr, (u16) i, 0 );
2232 }
2233
2234
2235
2236 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
2237 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, (u16) data );
2238
2239
2240
2241 outl( TLAN_HC_LD_TMR | 0x3f, dev->base_addr + TLAN_HOST_CMD );
2242 outl( TLAN_HC_LD_THR | 0x9, dev->base_addr + TLAN_HOST_CMD );
2243
2244
2245
2246 outw( TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR );
2247 addr = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO;
2248 TLan_SetBit( TLAN_NET_SIO_NMRST, addr );
2249
2250
2251
2252 if ( priv->tlanRev >= 0x30 ) {
2253 data8 = TLAN_ID_TX_EOC | TLAN_ID_RX_EOC;
2254 TLan_DioWrite8( dev->base_addr, TLAN_INT_DIS, data8 );
2255 }
2256 TLan_PhyDetect( dev );
2257 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN;
2258
2259 if ( priv->adapter->flags & TLAN_ADAPTER_BIT_RATE_PHY ) {
2260 data |= TLAN_NET_CFG_BIT;
2261 if ( priv->aui == 1 ) {
2262 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x0a );
2263 } else if ( priv->duplex == TLAN_DUPLEX_FULL ) {
2264 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x00 );
2265 priv->tlanFullDuplex = TRUE;
2266 } else {
2267 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x08 );
2268 }
2269 }
2270
2271 if ( priv->phyNum == 0 ) {
2272 data |= TLAN_NET_CFG_PHY_EN;
2273 }
2274 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, (u16) data );
2275
2276 if ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) {
2277 TLan_FinishReset( dev );
2278 } else {
2279 TLan_PhyPowerDown( dev );
2280 }
2281
2282}
2283
2284
2285
2286
2287static void
2288TLan_FinishReset( struct net_device *dev )
2289{
2290 TLanPrivateInfo *priv = netdev_priv(dev);
2291 u8 data;
2292 u32 phy;
2293 u8 sio;
2294 u16 status;
2295 u16 partner;
2296 u16 tlphy_ctl;
2297 u16 tlphy_par;
2298 u16 tlphy_id1, tlphy_id2;
2299 int i;
2300
2301 phy = priv->phy[priv->phyNum];
2302
2303 data = TLAN_NET_CMD_NRESET | TLAN_NET_CMD_NWRAP;
2304 if ( priv->tlanFullDuplex ) {
2305 data |= TLAN_NET_CMD_DUPLEX;
2306 }
2307 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, data );
2308 data = TLAN_NET_MASK_MASK4 | TLAN_NET_MASK_MASK5;
2309 if ( priv->phyNum == 0 ) {
2310 data |= TLAN_NET_MASK_MASK7;
2311 }
2312 TLan_DioWrite8( dev->base_addr, TLAN_NET_MASK, data );
2313 TLan_DioWrite16( dev->base_addr, TLAN_MAX_RX, ((1536)+7)&~7 );
2314 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &tlphy_id1 );
2315 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &tlphy_id2 );
2316
2317 if ( ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) ||
2318 ( priv->aui ) ) {
2319 status = MII_GS_LINK;
2320 printk( "TLAN: %s: Link forced.\n", dev->name );
2321 } else {
2322 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2323 udelay( 1000 );
2324 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2325 if ( (status & MII_GS_LINK) &&
2326
2327 (tlphy_id1 == NAT_SEM_ID1) &&
2328 (tlphy_id2 == NAT_SEM_ID2) ) {
2329 TLan_MiiReadReg( dev, phy, MII_AN_LPA, &partner );
2330 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_PAR, &tlphy_par );
2331
2332 printk( "TLAN: %s: Link active with ", dev->name );
2333 if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) {
2334 printk( "forced 10%sMbps %s-Duplex\n",
2335 tlphy_par & TLAN_PHY_SPEED_100 ? "" : "0",
2336 tlphy_par & TLAN_PHY_DUPLEX_FULL ? "Full" : "Half");
2337 } else {
2338 printk( "AutoNegotiation enabled, at 10%sMbps %s-Duplex\n",
2339 tlphy_par & TLAN_PHY_SPEED_100 ? "" : "0",
2340 tlphy_par & TLAN_PHY_DUPLEX_FULL ? "Full" : "Half");
2341 printk("TLAN: Partner capability: ");
2342 for (i = 5; i <= 10; i++)
2343 if (partner & (1<<i))
2344 printk("%s",media[i-5]);
2345 printk("\n");
2346 }
2347
2348 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK );
2349#ifdef MONITOR
2350
2351 priv->link = 1;
2352
2353 TLan_SetTimer( dev, (10*HZ), TLAN_TIMER_LINK_BEAT );
2354#endif
2355 } else if (status & MII_GS_LINK) {
2356 printk( "TLAN: %s: Link active\n", dev->name );
2357 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK );
2358 }
2359 }
2360
2361 if ( priv->phyNum == 0 ) {
2362 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tlphy_ctl );
2363 tlphy_ctl |= TLAN_TC_INTEN;
2364 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tlphy_ctl );
2365 sio = TLan_DioRead8( dev->base_addr, TLAN_NET_SIO );
2366 sio |= TLAN_NET_SIO_MINTEN;
2367 TLan_DioWrite8( dev->base_addr, TLAN_NET_SIO, sio );
2368 }
2369
2370 if ( status & MII_GS_LINK ) {
2371 TLan_SetMac( dev, 0, dev->dev_addr );
2372 priv->phyOnline = 1;
2373 outb( ( TLAN_HC_INT_ON >> 8 ), dev->base_addr + TLAN_HOST_CMD + 1 );
2374 if ( debug >= 1 && debug != TLAN_DEBUG_PROBE ) {
2375 outb( ( TLAN_HC_REQ_INT >> 8 ), dev->base_addr + TLAN_HOST_CMD + 1 );
2376 }
2377 outl( priv->rxListDMA, dev->base_addr + TLAN_CH_PARM );
2378 outl( TLAN_HC_GO | TLAN_HC_RT, dev->base_addr + TLAN_HOST_CMD );
2379 netif_carrier_on(dev);
2380 } else {
2381 printk( "TLAN: %s: Link inactive, will retry in 10 secs...\n",
2382 dev->name );
2383 TLan_SetTimer( dev, (10*HZ), TLAN_TIMER_FINISH_RESET );
2384 return;
2385 }
2386 TLan_SetMulticastList(dev);
2387
2388}
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414static void TLan_SetMac( struct net_device *dev, int areg, char *mac )
2415{
2416 int i;
2417
2418 areg *= 6;
2419
2420 if ( mac != NULL ) {
2421 for ( i = 0; i < 6; i++ )
2422 TLan_DioWrite8( dev->base_addr,
2423 TLAN_AREG_0 + areg + i, mac[i] );
2424 } else {
2425 for ( i = 0; i < 6; i++ )
2426 TLan_DioWrite8( dev->base_addr,
2427 TLAN_AREG_0 + areg + i, 0 );
2428 }
2429
2430}
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458static void TLan_PhyPrint( struct net_device *dev )
2459{
2460 TLanPrivateInfo *priv = netdev_priv(dev);
2461 u16 i, data0, data1, data2, data3, phy;
2462
2463 phy = priv->phy[priv->phyNum];
2464
2465 if ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) {
2466 printk( "TLAN: Device %s, Unmanaged PHY.\n", dev->name );
2467 } else if ( phy <= TLAN_PHY_MAX_ADDR ) {
2468 printk( "TLAN: Device %s, PHY 0x%02x.\n", dev->name, phy );
2469 printk( "TLAN: Off. +0 +1 +2 +3 \n" );
2470 for ( i = 0; i < 0x20; i+= 4 ) {
2471 printk( "TLAN: 0x%02x", i );
2472 TLan_MiiReadReg( dev, phy, i, &data0 );
2473 printk( " 0x%04hx", data0 );
2474 TLan_MiiReadReg( dev, phy, i + 1, &data1 );
2475 printk( " 0x%04hx", data1 );
2476 TLan_MiiReadReg( dev, phy, i + 2, &data2 );
2477 printk( " 0x%04hx", data2 );
2478 TLan_MiiReadReg( dev, phy, i + 3, &data3 );
2479 printk( " 0x%04hx\n", data3 );
2480 }
2481 } else {
2482 printk( "TLAN: Device %s, Invalid PHY.\n", dev->name );
2483 }
2484
2485}
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507static void TLan_PhyDetect( struct net_device *dev )
2508{
2509 TLanPrivateInfo *priv = netdev_priv(dev);
2510 u16 control;
2511 u16 hi;
2512 u16 lo;
2513 u32 phy;
2514
2515 if ( priv->adapter->flags & TLAN_ADAPTER_UNMANAGED_PHY ) {
2516 priv->phyNum = 0xFFFF;
2517 return;
2518 }
2519
2520 TLan_MiiReadReg( dev, TLAN_PHY_MAX_ADDR, MII_GEN_ID_HI, &hi );
2521
2522 if ( hi != 0xFFFF ) {
2523 priv->phy[0] = TLAN_PHY_MAX_ADDR;
2524 } else {
2525 priv->phy[0] = TLAN_PHY_NONE;
2526 }
2527
2528 priv->phy[1] = TLAN_PHY_NONE;
2529 for ( phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++ ) {
2530 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &control );
2531 TLan_MiiReadReg( dev, phy, MII_GEN_ID_HI, &hi );
2532 TLan_MiiReadReg( dev, phy, MII_GEN_ID_LO, &lo );
2533 if ( ( control != 0xFFFF ) ||
2534 ( hi != 0xFFFF ) || ( lo != 0xFFFF ) ) {
2535 TLAN_DBG( TLAN_DEBUG_GNRL,
2536 "PHY found at %02x %04x %04x %04x\n",
2537 phy, control, hi, lo );
2538 if ( ( priv->phy[1] == TLAN_PHY_NONE ) &&
2539 ( phy != TLAN_PHY_MAX_ADDR ) ) {
2540 priv->phy[1] = phy;
2541 }
2542 }
2543 }
2544
2545 if ( priv->phy[1] != TLAN_PHY_NONE ) {
2546 priv->phyNum = 1;
2547 } else if ( priv->phy[0] != TLAN_PHY_NONE ) {
2548 priv->phyNum = 0;
2549 } else {
2550 printk( "TLAN: Cannot initialize device, no PHY was found!\n" );
2551 }
2552
2553}
2554
2555
2556
2557
2558static void TLan_PhyPowerDown( struct net_device *dev )
2559{
2560 TLanPrivateInfo *priv = netdev_priv(dev);
2561 u16 value;
2562
2563 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Powering down PHY(s).\n", dev->name );
2564 value = MII_GC_PDOWN | MII_GC_LOOPBK | MII_GC_ISOLATE;
2565 TLan_MiiSync( dev->base_addr );
2566 TLan_MiiWriteReg( dev, priv->phy[priv->phyNum], MII_GEN_CTL, value );
2567 if ( ( priv->phyNum == 0 ) &&
2568 ( priv->phy[1] != TLAN_PHY_NONE ) &&
2569 ( ! ( priv->adapter->flags & TLAN_ADAPTER_USE_INTERN_10 ) ) ) {
2570 TLan_MiiSync( dev->base_addr );
2571 TLan_MiiWriteReg( dev, priv->phy[1], MII_GEN_CTL, value );
2572 }
2573
2574
2575
2576
2577
2578 TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_PUP );
2579
2580}
2581
2582
2583
2584
2585static void TLan_PhyPowerUp( struct net_device *dev )
2586{
2587 TLanPrivateInfo *priv = netdev_priv(dev);
2588 u16 value;
2589
2590 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Powering up PHY.\n", dev->name );
2591 TLan_MiiSync( dev->base_addr );
2592 value = MII_GC_LOOPBK;
2593 TLan_MiiWriteReg( dev, priv->phy[priv->phyNum], MII_GEN_CTL, value );
2594 TLan_MiiSync(dev->base_addr);
2595
2596
2597
2598
2599 TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_RESET );
2600
2601}
2602
2603
2604
2605
2606static void TLan_PhyReset( struct net_device *dev )
2607{
2608 TLanPrivateInfo *priv = netdev_priv(dev);
2609 u16 phy;
2610 u16 value;
2611
2612 phy = priv->phy[priv->phyNum];
2613
2614 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Reseting PHY.\n", dev->name );
2615 TLan_MiiSync( dev->base_addr );
2616 value = MII_GC_LOOPBK | MII_GC_RESET;
2617 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, value );
2618 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &value );
2619 while ( value & MII_GC_RESET ) {
2620 TLan_MiiReadReg( dev, phy, MII_GEN_CTL, &value );
2621 }
2622
2623
2624
2625
2626
2627 TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_START_LINK );
2628
2629}
2630
2631
2632
2633
2634static void TLan_PhyStartLink( struct net_device *dev )
2635{
2636 TLanPrivateInfo *priv = netdev_priv(dev);
2637 u16 ability;
2638 u16 control;
2639 u16 data;
2640 u16 phy;
2641 u16 status;
2642 u16 tctl;
2643
2644 phy = priv->phy[priv->phyNum];
2645 TLAN_DBG( TLAN_DEBUG_GNRL, "%s: Trying to activate link.\n", dev->name );
2646 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2647 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &ability );
2648
2649 if ( ( status & MII_GS_AUTONEG ) &&
2650 ( ! priv->aui ) ) {
2651 ability = status >> 11;
2652 if ( priv->speed == TLAN_SPEED_10 &&
2653 priv->duplex == TLAN_DUPLEX_HALF) {
2654 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x0000);
2655 } else if ( priv->speed == TLAN_SPEED_10 &&
2656 priv->duplex == TLAN_DUPLEX_FULL) {
2657 priv->tlanFullDuplex = TRUE;
2658 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x0100);
2659 } else if ( priv->speed == TLAN_SPEED_100 &&
2660 priv->duplex == TLAN_DUPLEX_HALF) {
2661 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x2000);
2662 } else if ( priv->speed == TLAN_SPEED_100 &&
2663 priv->duplex == TLAN_DUPLEX_FULL) {
2664 priv->tlanFullDuplex = TRUE;
2665 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x2100);
2666 } else {
2667
2668
2669 TLan_MiiWriteReg( dev, phy, MII_AN_ADV, (ability << 5) | 1);
2670
2671 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x1000 );
2672
2673 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, 0x1200 );
2674
2675
2676
2677
2678
2679 printk( "TLAN: %s: Starting autonegotiation.\n", dev->name );
2680 TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_PHY_FINISH_AN );
2681 return;
2682 }
2683
2684 }
2685
2686 if ( ( priv->aui ) && ( priv->phyNum != 0 ) ) {
2687 priv->phyNum = 0;
2688 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
2689 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, data );
2690 TLan_SetTimer( dev, (40*HZ/1000), TLAN_TIMER_PHY_PDOWN );
2691 return;
2692 } else if ( priv->phyNum == 0 ) {
2693 control = 0;
2694 TLan_MiiReadReg( dev, phy, TLAN_TLPHY_CTL, &tctl );
2695 if ( priv->aui ) {
2696 tctl |= TLAN_TC_AUISEL;
2697 } else {
2698 tctl &= ~TLAN_TC_AUISEL;
2699 if ( priv->duplex == TLAN_DUPLEX_FULL ) {
2700 control |= MII_GC_DUPLEX;
2701 priv->tlanFullDuplex = TRUE;
2702 }
2703 if ( priv->speed == TLAN_SPEED_100 ) {
2704 control |= MII_GC_SPEEDSEL;
2705 }
2706 }
2707 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, control );
2708 TLan_MiiWriteReg( dev, phy, TLAN_TLPHY_CTL, tctl );
2709 }
2710
2711
2712
2713
2714 TLan_SetTimer( dev, (4*HZ), TLAN_TIMER_FINISH_RESET );
2715
2716}
2717
2718
2719
2720
2721static void TLan_PhyFinishAutoNeg( struct net_device *dev )
2722{
2723 TLanPrivateInfo *priv = netdev_priv(dev);
2724 u16 an_adv;
2725 u16 an_lpa;
2726 u16 data;
2727 u16 mode;
2728 u16 phy;
2729 u16 status;
2730
2731 phy = priv->phy[priv->phyNum];
2732
2733 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2734 udelay( 1000 );
2735 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &status );
2736
2737 if ( ! ( status & MII_GS_AUTOCMPLT ) ) {
2738
2739
2740
2741 if (!priv->neg_be_verbose++) {
2742 pr_info("TLAN: Giving autonegotiation more time.\n");
2743 pr_info("TLAN: Please check that your adapter has\n");
2744 pr_info("TLAN: been properly connected to a HUB or Switch.\n");
2745 pr_info("TLAN: Trying to establish link in the background...\n");
2746 }
2747 TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN );
2748 return;
2749 }
2750
2751 printk( "TLAN: %s: Autonegotiation complete.\n", dev->name );
2752 TLan_MiiReadReg( dev, phy, MII_AN_ADV, &an_adv );
2753 TLan_MiiReadReg( dev, phy, MII_AN_LPA, &an_lpa );
2754 mode = an_adv & an_lpa & 0x03E0;
2755 if ( mode & 0x0100 ) {
2756 priv->tlanFullDuplex = TRUE;
2757 } else if ( ! ( mode & 0x0080 ) && ( mode & 0x0040 ) ) {
2758 priv->tlanFullDuplex = TRUE;
2759 }
2760
2761 if ( ( ! ( mode & 0x0180 ) ) &&
2762 ( priv->adapter->flags & TLAN_ADAPTER_USE_INTERN_10 ) &&
2763 ( priv->phyNum != 0 ) ) {
2764 priv->phyNum = 0;
2765 data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
2766 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, data );
2767 TLan_SetTimer( dev, (400*HZ/1000), TLAN_TIMER_PHY_PDOWN );
2768 return;
2769 }
2770
2771 if ( priv->phyNum == 0 ) {
2772 if ( ( priv->duplex == TLAN_DUPLEX_FULL ) ||
2773 ( an_adv & an_lpa & 0x0040 ) ) {
2774 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL,
2775 MII_GC_AUTOENB | MII_GC_DUPLEX );
2776 pr_info("TLAN: Starting internal PHY with FULL-DUPLEX\n" );
2777 } else {
2778 TLan_MiiWriteReg( dev, phy, MII_GEN_CTL, MII_GC_AUTOENB );
2779 pr_info( "TLAN: Starting internal PHY with HALF-DUPLEX\n" );
2780 }
2781 }
2782
2783
2784
2785 TLan_SetTimer( dev, (HZ/10), TLAN_TIMER_FINISH_RESET );
2786
2787}
2788
2789#ifdef MONITOR
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809void TLan_PhyMonitor( struct net_device *dev )
2810{
2811 TLanPrivateInfo *priv = netdev_priv(dev);
2812 u16 phy;
2813 u16 phy_status;
2814
2815 phy = priv->phy[priv->phyNum];
2816
2817
2818 TLan_MiiReadReg( dev, phy, MII_GEN_STS, &phy_status );
2819
2820
2821 if (!(phy_status & MII_GS_LINK)) {
2822 if (priv->link) {
2823 priv->link = 0;
2824 printk(KERN_DEBUG "TLAN: %s has lost link\n", dev->name);
2825 netif_carrier_off(dev);
2826 TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT );
2827 return;
2828 }
2829 }
2830
2831
2832 if ((phy_status & MII_GS_LINK) && !priv->link) {
2833 priv->link = 1;
2834 printk(KERN_DEBUG "TLAN: %s has reestablished link\n", dev->name);
2835 netif_carrier_on(dev);
2836 }
2837
2838
2839 TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT );
2840}
2841
2842#endif
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881static int TLan_MiiReadReg( struct net_device *dev, u16 phy, u16 reg, u16 *val )
2882{
2883 u8 nack;
2884 u16 sio, tmp;
2885 u32 i;
2886 int err;
2887 int minten;
2888 TLanPrivateInfo *priv = netdev_priv(dev);
2889 unsigned long flags = 0;
2890
2891 err = FALSE;
2892 outw(TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR);
2893 sio = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO;
2894
2895 if (!in_irq())
2896 spin_lock_irqsave(&priv->lock, flags);
2897
2898 TLan_MiiSync(dev->base_addr);
2899
2900 minten = TLan_GetBit( TLAN_NET_SIO_MINTEN, sio );
2901 if ( minten )
2902 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
2903
2904 TLan_MiiSendData( dev->base_addr, 0x1, 2 );
2905 TLan_MiiSendData( dev->base_addr, 0x2, 2 );
2906 TLan_MiiSendData( dev->base_addr, phy, 5 );
2907 TLan_MiiSendData( dev->base_addr, reg, 5 );
2908
2909
2910 TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio);
2911
2912 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2913 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2914 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2915
2916 nack = TLan_GetBit(TLAN_NET_SIO_MDATA, sio);
2917 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2918 if (nack) {
2919 for (i = 0; i < 16; i++) {
2920 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2921 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2922 }
2923 tmp = 0xffff;
2924 err = TRUE;
2925 } else {
2926 for (tmp = 0, i = 0x8000; i; i >>= 1) {
2927 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2928 if (TLan_GetBit(TLAN_NET_SIO_MDATA, sio))
2929 tmp |= i;
2930 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2931 }
2932 }
2933
2934
2935 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
2936 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
2937
2938 if ( minten )
2939 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
2940
2941 *val = tmp;
2942
2943 if (!in_irq())
2944 spin_unlock_irqrestore(&priv->lock, flags);
2945
2946 return err;
2947
2948}
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971static void TLan_MiiSendData( u16 base_port, u32 data, unsigned num_bits )
2972{
2973 u16 sio;
2974 u32 i;
2975
2976 if ( num_bits == 0 )
2977 return;
2978
2979 outw( TLAN_NET_SIO, base_port + TLAN_DIO_ADR );
2980 sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
2981 TLan_SetBit( TLAN_NET_SIO_MTXEN, sio );
2982
2983 for ( i = ( 0x1 << ( num_bits - 1 ) ); i; i >>= 1 ) {
2984 TLan_ClearBit( TLAN_NET_SIO_MCLK, sio );
2985 (void) TLan_GetBit( TLAN_NET_SIO_MCLK, sio );
2986 if ( data & i )
2987 TLan_SetBit( TLAN_NET_SIO_MDATA, sio );
2988 else
2989 TLan_ClearBit( TLAN_NET_SIO_MDATA, sio );
2990 TLan_SetBit( TLAN_NET_SIO_MCLK, sio );
2991 (void) TLan_GetBit( TLAN_NET_SIO_MCLK, sio );
2992 }
2993
2994}
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013static void TLan_MiiSync( u16 base_port )
3014{
3015 int i;
3016 u16 sio;
3017
3018 outw( TLAN_NET_SIO, base_port + TLAN_DIO_ADR );
3019 sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
3020
3021 TLan_ClearBit( TLAN_NET_SIO_MTXEN, sio );
3022 for ( i = 0; i < 32; i++ ) {
3023 TLan_ClearBit( TLAN_NET_SIO_MCLK, sio );
3024 TLan_SetBit( TLAN_NET_SIO_MCLK, sio );
3025 }
3026
3027}
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052static void TLan_MiiWriteReg( struct net_device *dev, u16 phy, u16 reg, u16 val )
3053{
3054 u16 sio;
3055 int minten;
3056 unsigned long flags = 0;
3057 TLanPrivateInfo *priv = netdev_priv(dev);
3058
3059 outw(TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR);
3060 sio = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO;
3061
3062 if (!in_irq())
3063 spin_lock_irqsave(&priv->lock, flags);
3064
3065 TLan_MiiSync( dev->base_addr );
3066
3067 minten = TLan_GetBit( TLAN_NET_SIO_MINTEN, sio );
3068 if ( minten )
3069 TLan_ClearBit( TLAN_NET_SIO_MINTEN, sio );
3070
3071 TLan_MiiSendData( dev->base_addr, 0x1, 2 );
3072 TLan_MiiSendData( dev->base_addr, 0x1, 2 );
3073 TLan_MiiSendData( dev->base_addr, phy, 5 );
3074 TLan_MiiSendData( dev->base_addr, reg, 5 );
3075
3076 TLan_MiiSendData( dev->base_addr, 0x2, 2 );
3077 TLan_MiiSendData( dev->base_addr, val, 16 );
3078
3079 TLan_ClearBit( TLAN_NET_SIO_MCLK, sio );
3080 TLan_SetBit( TLAN_NET_SIO_MCLK, sio );
3081
3082 if ( minten )
3083 TLan_SetBit( TLAN_NET_SIO_MINTEN, sio );
3084
3085 if (!in_irq())
3086 spin_unlock_irqrestore(&priv->lock, flags);
3087
3088}
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122static void TLan_EeSendStart( u16 io_base )
3123{
3124 u16 sio;
3125
3126 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR );
3127 sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
3128
3129 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3130 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3131 TLan_SetBit( TLAN_NET_SIO_ETXEN, sio );
3132 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3133 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3134
3135}
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162static int TLan_EeSendByte( u16 io_base, u8 data, int stop )
3163{
3164 int err;
3165 u8 place;
3166 u16 sio;
3167
3168 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR );
3169 sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
3170
3171
3172 for ( place = 0x80; place != 0; place >>= 1 ) {
3173 if ( place & data )
3174 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3175 else
3176 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3177 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3178 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3179 }
3180 TLan_ClearBit( TLAN_NET_SIO_ETXEN, sio );
3181 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3182 err = TLan_GetBit( TLAN_NET_SIO_EDATA, sio );
3183 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3184 TLan_SetBit( TLAN_NET_SIO_ETXEN, sio );
3185
3186 if ( ( ! err ) && stop ) {
3187
3188 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3189 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3190 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3191 }
3192
3193 return ( err );
3194
3195}
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224static void TLan_EeReceiveByte( u16 io_base, u8 *data, int stop )
3225{
3226 u8 place;
3227 u16 sio;
3228
3229 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR );
3230 sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
3231 *data = 0;
3232
3233
3234 TLan_ClearBit( TLAN_NET_SIO_ETXEN, sio );
3235 for ( place = 0x80; place; place >>= 1 ) {
3236 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3237 if ( TLan_GetBit( TLAN_NET_SIO_EDATA, sio ) )
3238 *data |= place;
3239 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3240 }
3241
3242 TLan_SetBit( TLAN_NET_SIO_ETXEN, sio );
3243 if ( ! stop ) {
3244 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3245 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3246 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3247 } else {
3248 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3249 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3250 TLan_ClearBit( TLAN_NET_SIO_ECLOK, sio );
3251
3252 TLan_ClearBit( TLAN_NET_SIO_EDATA, sio );
3253 TLan_SetBit( TLAN_NET_SIO_ECLOK, sio );
3254 TLan_SetBit( TLAN_NET_SIO_EDATA, sio );
3255 }
3256
3257}
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283static int TLan_EeReadByte( struct net_device *dev, u8 ee_addr, u8 *data )
3284{
3285 int err;
3286 TLanPrivateInfo *priv = netdev_priv(dev);
3287 unsigned long flags = 0;
3288 int ret=0;
3289
3290 spin_lock_irqsave(&priv->lock, flags);
3291
3292 TLan_EeSendStart( dev->base_addr );
3293 err = TLan_EeSendByte( dev->base_addr, 0xA0, TLAN_EEPROM_ACK );
3294 if (err)
3295 {
3296 ret=1;
3297 goto fail;
3298 }
3299 err = TLan_EeSendByte( dev->base_addr, ee_addr, TLAN_EEPROM_ACK );
3300 if (err)
3301 {
3302 ret=2;
3303 goto fail;
3304 }
3305 TLan_EeSendStart( dev->base_addr );
3306 err = TLan_EeSendByte( dev->base_addr, 0xA1, TLAN_EEPROM_ACK );
3307 if (err)
3308 {
3309 ret=3;
3310 goto fail;
3311 }
3312 TLan_EeReceiveByte( dev->base_addr, data, TLAN_EEPROM_STOP );
3313fail:
3314 spin_unlock_irqrestore(&priv->lock, flags);
3315
3316 return ret;
3317
3318}
3319
3320
3321
3322