linux/drivers/char/synclinkmp.c
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   1/*
   2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   3 *
   4 * Device driver for Microgate SyncLink Multiport
   5 * high speed multiprotocol serial adapter.
   6 *
   7 * written by Paul Fulghum for Microgate Corporation
   8 * paulkf@microgate.com
   9 *
  10 * Microgate and SyncLink are trademarks of Microgate Corporation
  11 *
  12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13 * This code is released under the GNU General Public License (GPL)
  14 *
  15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25 * OF THE POSSIBILITY OF SUCH DAMAGE.
  26 */
  27
  28#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29#if defined(__i386__)
  30#  define BREAKPOINT() asm("   int $3");
  31#else
  32#  define BREAKPOINT() { }
  33#endif
  34
  35#define MAX_DEVICES 12
  36
  37#include <linux/module.h>
  38#include <linux/errno.h>
  39#include <linux/signal.h>
  40#include <linux/sched.h>
  41#include <linux/timer.h>
  42#include <linux/interrupt.h>
  43#include <linux/pci.h>
  44#include <linux/tty.h>
  45#include <linux/tty_flip.h>
  46#include <linux/serial.h>
  47#include <linux/major.h>
  48#include <linux/string.h>
  49#include <linux/fcntl.h>
  50#include <linux/ptrace.h>
  51#include <linux/ioport.h>
  52#include <linux/mm.h>
  53#include <linux/seq_file.h>
  54#include <linux/slab.h>
  55#include <linux/smp_lock.h>
  56#include <linux/netdevice.h>
  57#include <linux/vmalloc.h>
  58#include <linux/init.h>
  59#include <linux/delay.h>
  60#include <linux/ioctl.h>
  61
  62#include <asm/system.h>
  63#include <asm/io.h>
  64#include <asm/irq.h>
  65#include <asm/dma.h>
  66#include <linux/bitops.h>
  67#include <asm/types.h>
  68#include <linux/termios.h>
  69#include <linux/workqueue.h>
  70#include <linux/hdlc.h>
  71#include <linux/synclink.h>
  72
  73#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
  74#define SYNCLINK_GENERIC_HDLC 1
  75#else
  76#define SYNCLINK_GENERIC_HDLC 0
  77#endif
  78
  79#define GET_USER(error,value,addr) error = get_user(value,addr)
  80#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  81#define PUT_USER(error,value,addr) error = put_user(value,addr)
  82#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  83
  84#include <asm/uaccess.h>
  85
  86static MGSL_PARAMS default_params = {
  87        MGSL_MODE_HDLC,                 /* unsigned long mode */
  88        0,                              /* unsigned char loopback; */
  89        HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  90        HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  91        0,                              /* unsigned long clock_speed; */
  92        0xff,                           /* unsigned char addr_filter; */
  93        HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  94        HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  95        HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  96        9600,                           /* unsigned long data_rate; */
  97        8,                              /* unsigned char data_bits; */
  98        1,                              /* unsigned char stop_bits; */
  99        ASYNC_PARITY_NONE               /* unsigned char parity; */
 100};
 101
 102/* size in bytes of DMA data buffers */
 103#define SCABUFSIZE      1024
 104#define SCA_MEM_SIZE    0x40000
 105#define SCA_BASE_SIZE   512
 106#define SCA_REG_SIZE    16
 107#define SCA_MAX_PORTS   4
 108#define SCAMAXDESC      128
 109
 110#define BUFFERLISTSIZE  4096
 111
 112/* SCA-I style DMA buffer descriptor */
 113typedef struct _SCADESC
 114{
 115        u16     next;           /* lower l6 bits of next descriptor addr */
 116        u16     buf_ptr;        /* lower 16 bits of buffer addr */
 117        u8      buf_base;       /* upper 8 bits of buffer addr */
 118        u8      pad1;
 119        u16     length;         /* length of buffer */
 120        u8      status;         /* status of buffer */
 121        u8      pad2;
 122} SCADESC, *PSCADESC;
 123
 124typedef struct _SCADESC_EX
 125{
 126        /* device driver bookkeeping section */
 127        char    *virt_addr;     /* virtual address of data buffer */
 128        u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 129} SCADESC_EX, *PSCADESC_EX;
 130
 131/* The queue of BH actions to be performed */
 132
 133#define BH_RECEIVE  1
 134#define BH_TRANSMIT 2
 135#define BH_STATUS   4
 136
 137#define IO_PIN_SHUTDOWN_LIMIT 100
 138
 139struct  _input_signal_events {
 140        int     ri_up;
 141        int     ri_down;
 142        int     dsr_up;
 143        int     dsr_down;
 144        int     dcd_up;
 145        int     dcd_down;
 146        int     cts_up;
 147        int     cts_down;
 148};
 149
 150/*
 151 * Device instance data structure
 152 */
 153typedef struct _synclinkmp_info {
 154        void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 155        int                     magic;
 156        struct tty_port         port;
 157        int                     line;
 158        unsigned short          close_delay;
 159        unsigned short          closing_wait;   /* time to wait before closing */
 160
 161        struct mgsl_icount      icount;
 162
 163        int                     timeout;
 164        int                     x_char;         /* xon/xoff character */
 165        u16                     read_status_mask1;  /* break detection (SR1 indications) */
 166        u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 167        unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 168        unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 169        unsigned char           *tx_buf;
 170        int                     tx_put;
 171        int                     tx_get;
 172        int                     tx_count;
 173
 174        wait_queue_head_t       status_event_wait_q;
 175        wait_queue_head_t       event_wait_q;
 176        struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 177        struct _synclinkmp_info *next_device;   /* device list link */
 178        struct timer_list       status_timer;   /* input signal status check timer */
 179
 180        spinlock_t lock;                /* spinlock for synchronizing with ISR */
 181        struct work_struct task;                        /* task structure for scheduling bh */
 182
 183        u32 max_frame_size;                     /* as set by device config */
 184
 185        u32 pending_bh;
 186
 187        bool bh_running;                                /* Protection from multiple */
 188        int isr_overflow;
 189        bool bh_requested;
 190
 191        int dcd_chkcount;                       /* check counts to prevent */
 192        int cts_chkcount;                       /* too many IRQs if a signal */
 193        int dsr_chkcount;                       /* is floating */
 194        int ri_chkcount;
 195
 196        char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 197        unsigned long buffer_list_phys;
 198
 199        unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 200        SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 201        SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 202        unsigned int current_rx_buf;
 203
 204        unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 205        SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 206        SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 207        unsigned int last_tx_buf;
 208
 209        unsigned char *tmp_rx_buf;
 210        unsigned int tmp_rx_buf_count;
 211
 212        bool rx_enabled;
 213        bool rx_overflow;
 214
 215        bool tx_enabled;
 216        bool tx_active;
 217        u32 idle_mode;
 218
 219        unsigned char ie0_value;
 220        unsigned char ie1_value;
 221        unsigned char ie2_value;
 222        unsigned char ctrlreg_value;
 223        unsigned char old_signals;
 224
 225        char device_name[25];                   /* device instance name */
 226
 227        int port_count;
 228        int adapter_num;
 229        int port_num;
 230
 231        struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 232
 233        unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 234
 235        unsigned int irq_level;                 /* interrupt level */
 236        unsigned long irq_flags;
 237        bool irq_requested;                     /* true if IRQ requested */
 238
 239        MGSL_PARAMS params;                     /* communications parameters */
 240
 241        unsigned char serial_signals;           /* current serial signal states */
 242
 243        bool irq_occurred;                      /* for diagnostics use */
 244        unsigned int init_error;                /* Initialization startup error */
 245
 246        u32 last_mem_alloc;
 247        unsigned char* memory_base;             /* shared memory address (PCI only) */
 248        u32 phys_memory_base;
 249        int shared_mem_requested;
 250
 251        unsigned char* sca_base;                /* HD64570 SCA Memory address */
 252        u32 phys_sca_base;
 253        u32 sca_offset;
 254        bool sca_base_requested;
 255
 256        unsigned char* lcr_base;                /* local config registers (PCI only) */
 257        u32 phys_lcr_base;
 258        u32 lcr_offset;
 259        int lcr_mem_requested;
 260
 261        unsigned char* statctrl_base;           /* status/control register memory */
 262        u32 phys_statctrl_base;
 263        u32 statctrl_offset;
 264        bool sca_statctrl_requested;
 265
 266        u32 misc_ctrl_value;
 267        char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 268        char char_buf[MAX_ASYNC_BUFFER_SIZE];
 269        bool drop_rts_on_tx_done;
 270
 271        struct  _input_signal_events    input_signal_events;
 272
 273        /* SPPP/Cisco HDLC device parts */
 274        int netcount;
 275        spinlock_t netlock;
 276
 277#if SYNCLINK_GENERIC_HDLC
 278        struct net_device *netdev;
 279#endif
 280
 281} SLMP_INFO;
 282
 283#define MGSL_MAGIC 0x5401
 284
 285/*
 286 * define serial signal status change macros
 287 */
 288#define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 289#define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 290#define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 291#define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 292
 293/* Common Register macros */
 294#define LPR     0x00
 295#define PABR0   0x02
 296#define PABR1   0x03
 297#define WCRL    0x04
 298#define WCRM    0x05
 299#define WCRH    0x06
 300#define DPCR    0x08
 301#define DMER    0x09
 302#define ISR0    0x10
 303#define ISR1    0x11
 304#define ISR2    0x12
 305#define IER0    0x14
 306#define IER1    0x15
 307#define IER2    0x16
 308#define ITCR    0x18
 309#define INTVR   0x1a
 310#define IMVR    0x1c
 311
 312/* MSCI Register macros */
 313#define TRB     0x20
 314#define TRBL    0x20
 315#define TRBH    0x21
 316#define SR0     0x22
 317#define SR1     0x23
 318#define SR2     0x24
 319#define SR3     0x25
 320#define FST     0x26
 321#define IE0     0x28
 322#define IE1     0x29
 323#define IE2     0x2a
 324#define FIE     0x2b
 325#define CMD     0x2c
 326#define MD0     0x2e
 327#define MD1     0x2f
 328#define MD2     0x30
 329#define CTL     0x31
 330#define SA0     0x32
 331#define SA1     0x33
 332#define IDL     0x34
 333#define TMC     0x35
 334#define RXS     0x36
 335#define TXS     0x37
 336#define TRC0    0x38
 337#define TRC1    0x39
 338#define RRC     0x3a
 339#define CST0    0x3c
 340#define CST1    0x3d
 341
 342/* Timer Register Macros */
 343#define TCNT    0x60
 344#define TCNTL   0x60
 345#define TCNTH   0x61
 346#define TCONR   0x62
 347#define TCONRL  0x62
 348#define TCONRH  0x63
 349#define TMCS    0x64
 350#define TEPR    0x65
 351
 352/* DMA Controller Register macros */
 353#define DARL    0x80
 354#define DARH    0x81
 355#define DARB    0x82
 356#define BAR     0x80
 357#define BARL    0x80
 358#define BARH    0x81
 359#define BARB    0x82
 360#define SAR     0x84
 361#define SARL    0x84
 362#define SARH    0x85
 363#define SARB    0x86
 364#define CPB     0x86
 365#define CDA     0x88
 366#define CDAL    0x88
 367#define CDAH    0x89
 368#define EDA     0x8a
 369#define EDAL    0x8a
 370#define EDAH    0x8b
 371#define BFL     0x8c
 372#define BFLL    0x8c
 373#define BFLH    0x8d
 374#define BCR     0x8e
 375#define BCRL    0x8e
 376#define BCRH    0x8f
 377#define DSR     0x90
 378#define DMR     0x91
 379#define FCT     0x93
 380#define DIR     0x94
 381#define DCMD    0x95
 382
 383/* combine with timer or DMA register address */
 384#define TIMER0  0x00
 385#define TIMER1  0x08
 386#define TIMER2  0x10
 387#define TIMER3  0x18
 388#define RXDMA   0x00
 389#define TXDMA   0x20
 390
 391/* SCA Command Codes */
 392#define NOOP            0x00
 393#define TXRESET         0x01
 394#define TXENABLE        0x02
 395#define TXDISABLE       0x03
 396#define TXCRCINIT       0x04
 397#define TXCRCEXCL       0x05
 398#define TXEOM           0x06
 399#define TXABORT         0x07
 400#define MPON            0x08
 401#define TXBUFCLR        0x09
 402#define RXRESET         0x11
 403#define RXENABLE        0x12
 404#define RXDISABLE       0x13
 405#define RXCRCINIT       0x14
 406#define RXREJECT        0x15
 407#define SEARCHMP        0x16
 408#define RXCRCEXCL       0x17
 409#define RXCRCCALC       0x18
 410#define CHRESET         0x21
 411#define HUNT            0x31
 412
 413/* DMA command codes */
 414#define SWABORT         0x01
 415#define FEICLEAR        0x02
 416
 417/* IE0 */
 418#define TXINTE          BIT7
 419#define RXINTE          BIT6
 420#define TXRDYE          BIT1
 421#define RXRDYE          BIT0
 422
 423/* IE1 & SR1 */
 424#define UDRN    BIT7
 425#define IDLE    BIT6
 426#define SYNCD   BIT4
 427#define FLGD    BIT4
 428#define CCTS    BIT3
 429#define CDCD    BIT2
 430#define BRKD    BIT1
 431#define ABTD    BIT1
 432#define GAPD    BIT1
 433#define BRKE    BIT0
 434#define IDLD    BIT0
 435
 436/* IE2 & SR2 */
 437#define EOM     BIT7
 438#define PMP     BIT6
 439#define SHRT    BIT6
 440#define PE      BIT5
 441#define ABT     BIT5
 442#define FRME    BIT4
 443#define RBIT    BIT4
 444#define OVRN    BIT3
 445#define CRCE    BIT2
 446
 447
 448/*
 449 * Global linked list of SyncLink devices
 450 */
 451static SLMP_INFO *synclinkmp_device_list = NULL;
 452static int synclinkmp_adapter_count = -1;
 453static int synclinkmp_device_count = 0;
 454
 455/*
 456 * Set this param to non-zero to load eax with the
 457 * .text section address and breakpoint on module load.
 458 * This is useful for use with gdb and add-symbol-file command.
 459 */
 460static int break_on_load = 0;
 461
 462/*
 463 * Driver major number, defaults to zero to get auto
 464 * assigned major number. May be forced as module parameter.
 465 */
 466static int ttymajor = 0;
 467
 468/*
 469 * Array of user specified options for ISA adapters.
 470 */
 471static int debug_level = 0;
 472static int maxframe[MAX_DEVICES] = {0,};
 473
 474module_param(break_on_load, bool, 0);
 475module_param(ttymajor, int, 0);
 476module_param(debug_level, int, 0);
 477module_param_array(maxframe, int, NULL, 0);
 478
 479static char *driver_name = "SyncLink MultiPort driver";
 480static char *driver_version = "$Revision: 4.38 $";
 481
 482static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 483static void synclinkmp_remove_one(struct pci_dev *dev);
 484
 485static struct pci_device_id synclinkmp_pci_tbl[] = {
 486        { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 487        { 0, }, /* terminate list */
 488};
 489MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 490
 491MODULE_LICENSE("GPL");
 492
 493static struct pci_driver synclinkmp_pci_driver = {
 494        .name           = "synclinkmp",
 495        .id_table       = synclinkmp_pci_tbl,
 496        .probe          = synclinkmp_init_one,
 497        .remove         = __devexit_p(synclinkmp_remove_one),
 498};
 499
 500
 501static struct tty_driver *serial_driver;
 502
 503/* number of characters left in xmit buffer before we ask for more */
 504#define WAKEUP_CHARS 256
 505
 506
 507/* tty callbacks */
 508
 509static int  open(struct tty_struct *tty, struct file * filp);
 510static void close(struct tty_struct *tty, struct file * filp);
 511static void hangup(struct tty_struct *tty);
 512static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 513
 514static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 515static int put_char(struct tty_struct *tty, unsigned char ch);
 516static void send_xchar(struct tty_struct *tty, char ch);
 517static void wait_until_sent(struct tty_struct *tty, int timeout);
 518static int  write_room(struct tty_struct *tty);
 519static void flush_chars(struct tty_struct *tty);
 520static void flush_buffer(struct tty_struct *tty);
 521static void tx_hold(struct tty_struct *tty);
 522static void tx_release(struct tty_struct *tty);
 523
 524static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 525static int  chars_in_buffer(struct tty_struct *tty);
 526static void throttle(struct tty_struct * tty);
 527static void unthrottle(struct tty_struct * tty);
 528static int set_break(struct tty_struct *tty, int break_state);
 529
 530#if SYNCLINK_GENERIC_HDLC
 531#define dev_to_port(D) (dev_to_hdlc(D)->priv)
 532static void hdlcdev_tx_done(SLMP_INFO *info);
 533static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 534static int  hdlcdev_init(SLMP_INFO *info);
 535static void hdlcdev_exit(SLMP_INFO *info);
 536#endif
 537
 538/* ioctl handlers */
 539
 540static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 541static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 542static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 543static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 544static int  set_txidle(SLMP_INFO *info, int idle_mode);
 545static int  tx_enable(SLMP_INFO *info, int enable);
 546static int  tx_abort(SLMP_INFO *info);
 547static int  rx_enable(SLMP_INFO *info, int enable);
 548static int  modem_input_wait(SLMP_INFO *info,int arg);
 549static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 550static int  tiocmget(struct tty_struct *tty, struct file *file);
 551static int  tiocmset(struct tty_struct *tty, struct file *file,
 552                     unsigned int set, unsigned int clear);
 553static int  set_break(struct tty_struct *tty, int break_state);
 554
 555static void add_device(SLMP_INFO *info);
 556static void device_init(int adapter_num, struct pci_dev *pdev);
 557static int  claim_resources(SLMP_INFO *info);
 558static void release_resources(SLMP_INFO *info);
 559
 560static int  startup(SLMP_INFO *info);
 561static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 562static int carrier_raised(struct tty_port *port);
 563static void shutdown(SLMP_INFO *info);
 564static void program_hw(SLMP_INFO *info);
 565static void change_params(SLMP_INFO *info);
 566
 567static bool init_adapter(SLMP_INFO *info);
 568static bool register_test(SLMP_INFO *info);
 569static bool irq_test(SLMP_INFO *info);
 570static bool loopback_test(SLMP_INFO *info);
 571static int  adapter_test(SLMP_INFO *info);
 572static bool memory_test(SLMP_INFO *info);
 573
 574static void reset_adapter(SLMP_INFO *info);
 575static void reset_port(SLMP_INFO *info);
 576static void async_mode(SLMP_INFO *info);
 577static void hdlc_mode(SLMP_INFO *info);
 578
 579static void rx_stop(SLMP_INFO *info);
 580static void rx_start(SLMP_INFO *info);
 581static void rx_reset_buffers(SLMP_INFO *info);
 582static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 583static bool rx_get_frame(SLMP_INFO *info);
 584
 585static void tx_start(SLMP_INFO *info);
 586static void tx_stop(SLMP_INFO *info);
 587static void tx_load_fifo(SLMP_INFO *info);
 588static void tx_set_idle(SLMP_INFO *info);
 589static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 590
 591static void get_signals(SLMP_INFO *info);
 592static void set_signals(SLMP_INFO *info);
 593static void enable_loopback(SLMP_INFO *info, int enable);
 594static void set_rate(SLMP_INFO *info, u32 data_rate);
 595
 596static int  bh_action(SLMP_INFO *info);
 597static void bh_handler(struct work_struct *work);
 598static void bh_receive(SLMP_INFO *info);
 599static void bh_transmit(SLMP_INFO *info);
 600static void bh_status(SLMP_INFO *info);
 601static void isr_timer(SLMP_INFO *info);
 602static void isr_rxint(SLMP_INFO *info);
 603static void isr_rxrdy(SLMP_INFO *info);
 604static void isr_txint(SLMP_INFO *info);
 605static void isr_txrdy(SLMP_INFO *info);
 606static void isr_rxdmaok(SLMP_INFO *info);
 607static void isr_rxdmaerror(SLMP_INFO *info);
 608static void isr_txdmaok(SLMP_INFO *info);
 609static void isr_txdmaerror(SLMP_INFO *info);
 610static void isr_io_pin(SLMP_INFO *info, u16 status);
 611
 612static int  alloc_dma_bufs(SLMP_INFO *info);
 613static void free_dma_bufs(SLMP_INFO *info);
 614static int  alloc_buf_list(SLMP_INFO *info);
 615static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 616static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 617static void free_tmp_rx_buf(SLMP_INFO *info);
 618
 619static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 620static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 621static void tx_timeout(unsigned long context);
 622static void status_timeout(unsigned long context);
 623
 624static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 625static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 626static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 627static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 628static unsigned char read_status_reg(SLMP_INFO * info);
 629static void write_control_reg(SLMP_INFO * info);
 630
 631
 632static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 633static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 634static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 635
 636static u32 misc_ctrl_value = 0x007e4040;
 637static u32 lcr1_brdr_value = 0x00800028;
 638
 639static u32 read_ahead_count = 8;
 640
 641/* DPCR, DMA Priority Control
 642 *
 643 * 07..05  Not used, must be 0
 644 * 04      BRC, bus release condition: 0=all transfers complete
 645 *              1=release after 1 xfer on all channels
 646 * 03      CCC, channel change condition: 0=every cycle
 647 *              1=after each channel completes all xfers
 648 * 02..00  PR<2..0>, priority 100=round robin
 649 *
 650 * 00000100 = 0x00
 651 */
 652static unsigned char dma_priority = 0x04;
 653
 654// Number of bytes that can be written to shared RAM
 655// in a single write operation
 656static u32 sca_pci_load_interval = 64;
 657
 658/*
 659 * 1st function defined in .text section. Calling this function in
 660 * init_module() followed by a breakpoint allows a remote debugger
 661 * (gdb) to get the .text address for the add-symbol-file command.
 662 * This allows remote debugging of dynamically loadable modules.
 663 */
 664static void* synclinkmp_get_text_ptr(void);
 665static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 666
 667static inline int sanity_check(SLMP_INFO *info,
 668                               char *name, const char *routine)
 669{
 670#ifdef SANITY_CHECK
 671        static const char *badmagic =
 672                "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 673        static const char *badinfo =
 674                "Warning: null synclinkmp_struct for (%s) in %s\n";
 675
 676        if (!info) {
 677                printk(badinfo, name, routine);
 678                return 1;
 679        }
 680        if (info->magic != MGSL_MAGIC) {
 681                printk(badmagic, name, routine);
 682                return 1;
 683        }
 684#else
 685        if (!info)
 686                return 1;
 687#endif
 688        return 0;
 689}
 690
 691/**
 692 * line discipline callback wrappers
 693 *
 694 * The wrappers maintain line discipline references
 695 * while calling into the line discipline.
 696 *
 697 * ldisc_receive_buf  - pass receive data to line discipline
 698 */
 699
 700static void ldisc_receive_buf(struct tty_struct *tty,
 701                              const __u8 *data, char *flags, int count)
 702{
 703        struct tty_ldisc *ld;
 704        if (!tty)
 705                return;
 706        ld = tty_ldisc_ref(tty);
 707        if (ld) {
 708                if (ld->ops->receive_buf)
 709                        ld->ops->receive_buf(tty, data, flags, count);
 710                tty_ldisc_deref(ld);
 711        }
 712}
 713
 714/* tty callbacks */
 715
 716/* Called when a port is opened.  Init and enable port.
 717 */
 718static int open(struct tty_struct *tty, struct file *filp)
 719{
 720        SLMP_INFO *info;
 721        int retval, line;
 722        unsigned long flags;
 723
 724        line = tty->index;
 725        if ((line < 0) || (line >= synclinkmp_device_count)) {
 726                printk("%s(%d): open with invalid line #%d.\n",
 727                        __FILE__,__LINE__,line);
 728                return -ENODEV;
 729        }
 730
 731        info = synclinkmp_device_list;
 732        while(info && info->line != line)
 733                info = info->next_device;
 734        if (sanity_check(info, tty->name, "open"))
 735                return -ENODEV;
 736        if ( info->init_error ) {
 737                printk("%s(%d):%s device is not allocated, init error=%d\n",
 738                        __FILE__,__LINE__,info->device_name,info->init_error);
 739                return -ENODEV;
 740        }
 741
 742        tty->driver_data = info;
 743        info->port.tty = tty;
 744
 745        if (debug_level >= DEBUG_LEVEL_INFO)
 746                printk("%s(%d):%s open(), old ref count = %d\n",
 747                         __FILE__,__LINE__,tty->driver->name, info->port.count);
 748
 749        /* If port is closing, signal caller to try again */
 750        if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 751                if (info->port.flags & ASYNC_CLOSING)
 752                        interruptible_sleep_on(&info->port.close_wait);
 753                retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 754                        -EAGAIN : -ERESTARTSYS);
 755                goto cleanup;
 756        }
 757
 758        info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 759
 760        spin_lock_irqsave(&info->netlock, flags);
 761        if (info->netcount) {
 762                retval = -EBUSY;
 763                spin_unlock_irqrestore(&info->netlock, flags);
 764                goto cleanup;
 765        }
 766        info->port.count++;
 767        spin_unlock_irqrestore(&info->netlock, flags);
 768
 769        if (info->port.count == 1) {
 770                /* 1st open on this device, init hardware */
 771                retval = startup(info);
 772                if (retval < 0)
 773                        goto cleanup;
 774        }
 775
 776        retval = block_til_ready(tty, filp, info);
 777        if (retval) {
 778                if (debug_level >= DEBUG_LEVEL_INFO)
 779                        printk("%s(%d):%s block_til_ready() returned %d\n",
 780                                 __FILE__,__LINE__, info->device_name, retval);
 781                goto cleanup;
 782        }
 783
 784        if (debug_level >= DEBUG_LEVEL_INFO)
 785                printk("%s(%d):%s open() success\n",
 786                         __FILE__,__LINE__, info->device_name);
 787        retval = 0;
 788
 789cleanup:
 790        if (retval) {
 791                if (tty->count == 1)
 792                        info->port.tty = NULL; /* tty layer will release tty struct */
 793                if(info->port.count)
 794                        info->port.count--;
 795        }
 796
 797        return retval;
 798}
 799
 800/* Called when port is closed. Wait for remaining data to be
 801 * sent. Disable port and free resources.
 802 */
 803static void close(struct tty_struct *tty, struct file *filp)
 804{
 805        SLMP_INFO * info = tty->driver_data;
 806
 807        if (sanity_check(info, tty->name, "close"))
 808                return;
 809
 810        if (debug_level >= DEBUG_LEVEL_INFO)
 811                printk("%s(%d):%s close() entry, count=%d\n",
 812                         __FILE__,__LINE__, info->device_name, info->port.count);
 813
 814        if (tty_port_close_start(&info->port, tty, filp) == 0)
 815                goto cleanup;
 816                
 817        if (info->port.flags & ASYNC_INITIALIZED)
 818                wait_until_sent(tty, info->timeout);
 819
 820        flush_buffer(tty);
 821        tty_ldisc_flush(tty);
 822        shutdown(info);
 823
 824        tty_port_close_end(&info->port, tty);
 825        info->port.tty = NULL;
 826cleanup:
 827        if (debug_level >= DEBUG_LEVEL_INFO)
 828                printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 829                        tty->driver->name, info->port.count);
 830}
 831
 832/* Called by tty_hangup() when a hangup is signaled.
 833 * This is the same as closing all open descriptors for the port.
 834 */
 835static void hangup(struct tty_struct *tty)
 836{
 837        SLMP_INFO *info = tty->driver_data;
 838
 839        if (debug_level >= DEBUG_LEVEL_INFO)
 840                printk("%s(%d):%s hangup()\n",
 841                         __FILE__,__LINE__, info->device_name );
 842
 843        if (sanity_check(info, tty->name, "hangup"))
 844                return;
 845
 846        flush_buffer(tty);
 847        shutdown(info);
 848
 849        info->port.count = 0;
 850        info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 851        info->port.tty = NULL;
 852
 853        wake_up_interruptible(&info->port.open_wait);
 854}
 855
 856/* Set new termios settings
 857 */
 858static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 859{
 860        SLMP_INFO *info = tty->driver_data;
 861        unsigned long flags;
 862
 863        if (debug_level >= DEBUG_LEVEL_INFO)
 864                printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 865                        tty->driver->name );
 866
 867        change_params(info);
 868
 869        /* Handle transition to B0 status */
 870        if (old_termios->c_cflag & CBAUD &&
 871            !(tty->termios->c_cflag & CBAUD)) {
 872                info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 873                spin_lock_irqsave(&info->lock,flags);
 874                set_signals(info);
 875                spin_unlock_irqrestore(&info->lock,flags);
 876        }
 877
 878        /* Handle transition away from B0 status */
 879        if (!(old_termios->c_cflag & CBAUD) &&
 880            tty->termios->c_cflag & CBAUD) {
 881                info->serial_signals |= SerialSignal_DTR;
 882                if (!(tty->termios->c_cflag & CRTSCTS) ||
 883                    !test_bit(TTY_THROTTLED, &tty->flags)) {
 884                        info->serial_signals |= SerialSignal_RTS;
 885                }
 886                spin_lock_irqsave(&info->lock,flags);
 887                set_signals(info);
 888                spin_unlock_irqrestore(&info->lock,flags);
 889        }
 890
 891        /* Handle turning off CRTSCTS */
 892        if (old_termios->c_cflag & CRTSCTS &&
 893            !(tty->termios->c_cflag & CRTSCTS)) {
 894                tty->hw_stopped = 0;
 895                tx_release(tty);
 896        }
 897}
 898
 899/* Send a block of data
 900 *
 901 * Arguments:
 902 *
 903 *      tty             pointer to tty information structure
 904 *      buf             pointer to buffer containing send data
 905 *      count           size of send data in bytes
 906 *
 907 * Return Value:        number of characters written
 908 */
 909static int write(struct tty_struct *tty,
 910                 const unsigned char *buf, int count)
 911{
 912        int     c, ret = 0;
 913        SLMP_INFO *info = tty->driver_data;
 914        unsigned long flags;
 915
 916        if (debug_level >= DEBUG_LEVEL_INFO)
 917                printk("%s(%d):%s write() count=%d\n",
 918                       __FILE__,__LINE__,info->device_name,count);
 919
 920        if (sanity_check(info, tty->name, "write"))
 921                goto cleanup;
 922
 923        if (!info->tx_buf)
 924                goto cleanup;
 925
 926        if (info->params.mode == MGSL_MODE_HDLC) {
 927                if (count > info->max_frame_size) {
 928                        ret = -EIO;
 929                        goto cleanup;
 930                }
 931                if (info->tx_active)
 932                        goto cleanup;
 933                if (info->tx_count) {
 934                        /* send accumulated data from send_char() calls */
 935                        /* as frame and wait before accepting more data. */
 936                        tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 937                        goto start;
 938                }
 939                ret = info->tx_count = count;
 940                tx_load_dma_buffer(info, buf, count);
 941                goto start;
 942        }
 943
 944        for (;;) {
 945                c = min_t(int, count,
 946                        min(info->max_frame_size - info->tx_count - 1,
 947                            info->max_frame_size - info->tx_put));
 948                if (c <= 0)
 949                        break;
 950                        
 951                memcpy(info->tx_buf + info->tx_put, buf, c);
 952
 953                spin_lock_irqsave(&info->lock,flags);
 954                info->tx_put += c;
 955                if (info->tx_put >= info->max_frame_size)
 956                        info->tx_put -= info->max_frame_size;
 957                info->tx_count += c;
 958                spin_unlock_irqrestore(&info->lock,flags);
 959
 960                buf += c;
 961                count -= c;
 962                ret += c;
 963        }
 964
 965        if (info->params.mode == MGSL_MODE_HDLC) {
 966                if (count) {
 967                        ret = info->tx_count = 0;
 968                        goto cleanup;
 969                }
 970                tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 971        }
 972start:
 973        if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 974                spin_lock_irqsave(&info->lock,flags);
 975                if (!info->tx_active)
 976                        tx_start(info);
 977                spin_unlock_irqrestore(&info->lock,flags);
 978        }
 979
 980cleanup:
 981        if (debug_level >= DEBUG_LEVEL_INFO)
 982                printk( "%s(%d):%s write() returning=%d\n",
 983                        __FILE__,__LINE__,info->device_name,ret);
 984        return ret;
 985}
 986
 987/* Add a character to the transmit buffer.
 988 */
 989static int put_char(struct tty_struct *tty, unsigned char ch)
 990{
 991        SLMP_INFO *info = tty->driver_data;
 992        unsigned long flags;
 993        int ret = 0;
 994
 995        if ( debug_level >= DEBUG_LEVEL_INFO ) {
 996                printk( "%s(%d):%s put_char(%d)\n",
 997                        __FILE__,__LINE__,info->device_name,ch);
 998        }
 999
1000        if (sanity_check(info, tty->name, "put_char"))
1001                return 0;
1002
1003        if (!info->tx_buf)
1004                return 0;
1005
1006        spin_lock_irqsave(&info->lock,flags);
1007
1008        if ( (info->params.mode != MGSL_MODE_HDLC) ||
1009             !info->tx_active ) {
1010
1011                if (info->tx_count < info->max_frame_size - 1) {
1012                        info->tx_buf[info->tx_put++] = ch;
1013                        if (info->tx_put >= info->max_frame_size)
1014                                info->tx_put -= info->max_frame_size;
1015                        info->tx_count++;
1016                        ret = 1;
1017                }
1018        }
1019
1020        spin_unlock_irqrestore(&info->lock,flags);
1021        return ret;
1022}
1023
1024/* Send a high-priority XON/XOFF character
1025 */
1026static void send_xchar(struct tty_struct *tty, char ch)
1027{
1028        SLMP_INFO *info = tty->driver_data;
1029        unsigned long flags;
1030
1031        if (debug_level >= DEBUG_LEVEL_INFO)
1032                printk("%s(%d):%s send_xchar(%d)\n",
1033                         __FILE__,__LINE__, info->device_name, ch );
1034
1035        if (sanity_check(info, tty->name, "send_xchar"))
1036                return;
1037
1038        info->x_char = ch;
1039        if (ch) {
1040                /* Make sure transmit interrupts are on */
1041                spin_lock_irqsave(&info->lock,flags);
1042                if (!info->tx_enabled)
1043                        tx_start(info);
1044                spin_unlock_irqrestore(&info->lock,flags);
1045        }
1046}
1047
1048/* Wait until the transmitter is empty.
1049 */
1050static void wait_until_sent(struct tty_struct *tty, int timeout)
1051{
1052        SLMP_INFO * info = tty->driver_data;
1053        unsigned long orig_jiffies, char_time;
1054
1055        if (!info )
1056                return;
1057
1058        if (debug_level >= DEBUG_LEVEL_INFO)
1059                printk("%s(%d):%s wait_until_sent() entry\n",
1060                         __FILE__,__LINE__, info->device_name );
1061
1062        if (sanity_check(info, tty->name, "wait_until_sent"))
1063                return;
1064
1065        lock_kernel();
1066
1067        if (!(info->port.flags & ASYNC_INITIALIZED))
1068                goto exit;
1069
1070        orig_jiffies = jiffies;
1071
1072        /* Set check interval to 1/5 of estimated time to
1073         * send a character, and make it at least 1. The check
1074         * interval should also be less than the timeout.
1075         * Note: use tight timings here to satisfy the NIST-PCTS.
1076         */
1077
1078        if ( info->params.data_rate ) {
1079                char_time = info->timeout/(32 * 5);
1080                if (!char_time)
1081                        char_time++;
1082        } else
1083                char_time = 1;
1084
1085        if (timeout)
1086                char_time = min_t(unsigned long, char_time, timeout);
1087
1088        if ( info->params.mode == MGSL_MODE_HDLC ) {
1089                while (info->tx_active) {
1090                        msleep_interruptible(jiffies_to_msecs(char_time));
1091                        if (signal_pending(current))
1092                                break;
1093                        if (timeout && time_after(jiffies, orig_jiffies + timeout))
1094                                break;
1095                }
1096        } else {
1097                //TODO: determine if there is something similar to USC16C32
1098                //      TXSTATUS_ALL_SENT status
1099                while ( info->tx_active && info->tx_enabled) {
1100                        msleep_interruptible(jiffies_to_msecs(char_time));
1101                        if (signal_pending(current))
1102                                break;
1103                        if (timeout && time_after(jiffies, orig_jiffies + timeout))
1104                                break;
1105                }
1106        }
1107
1108exit:
1109        unlock_kernel();
1110        if (debug_level >= DEBUG_LEVEL_INFO)
1111                printk("%s(%d):%s wait_until_sent() exit\n",
1112                         __FILE__,__LINE__, info->device_name );
1113}
1114
1115/* Return the count of free bytes in transmit buffer
1116 */
1117static int write_room(struct tty_struct *tty)
1118{
1119        SLMP_INFO *info = tty->driver_data;
1120        int ret;
1121
1122        if (sanity_check(info, tty->name, "write_room"))
1123                return 0;
1124
1125        lock_kernel();
1126        if (info->params.mode == MGSL_MODE_HDLC) {
1127                ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1128        } else {
1129                ret = info->max_frame_size - info->tx_count - 1;
1130                if (ret < 0)
1131                        ret = 0;
1132        }
1133        unlock_kernel();
1134
1135        if (debug_level >= DEBUG_LEVEL_INFO)
1136                printk("%s(%d):%s write_room()=%d\n",
1137                       __FILE__, __LINE__, info->device_name, ret);
1138
1139        return ret;
1140}
1141
1142/* enable transmitter and send remaining buffered characters
1143 */
1144static void flush_chars(struct tty_struct *tty)
1145{
1146        SLMP_INFO *info = tty->driver_data;
1147        unsigned long flags;
1148
1149        if ( debug_level >= DEBUG_LEVEL_INFO )
1150                printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1151                        __FILE__,__LINE__,info->device_name,info->tx_count);
1152
1153        if (sanity_check(info, tty->name, "flush_chars"))
1154                return;
1155
1156        if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1157            !info->tx_buf)
1158                return;
1159
1160        if ( debug_level >= DEBUG_LEVEL_INFO )
1161                printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1162                        __FILE__,__LINE__,info->device_name );
1163
1164        spin_lock_irqsave(&info->lock,flags);
1165
1166        if (!info->tx_active) {
1167                if ( (info->params.mode == MGSL_MODE_HDLC) &&
1168                        info->tx_count ) {
1169                        /* operating in synchronous (frame oriented) mode */
1170                        /* copy data from circular tx_buf to */
1171                        /* transmit DMA buffer. */
1172                        tx_load_dma_buffer(info,
1173                                 info->tx_buf,info->tx_count);
1174                }
1175                tx_start(info);
1176        }
1177
1178        spin_unlock_irqrestore(&info->lock,flags);
1179}
1180
1181/* Discard all data in the send buffer
1182 */
1183static void flush_buffer(struct tty_struct *tty)
1184{
1185        SLMP_INFO *info = tty->driver_data;
1186        unsigned long flags;
1187
1188        if (debug_level >= DEBUG_LEVEL_INFO)
1189                printk("%s(%d):%s flush_buffer() entry\n",
1190                         __FILE__,__LINE__, info->device_name );
1191
1192        if (sanity_check(info, tty->name, "flush_buffer"))
1193                return;
1194
1195        spin_lock_irqsave(&info->lock,flags);
1196        info->tx_count = info->tx_put = info->tx_get = 0;
1197        del_timer(&info->tx_timer);
1198        spin_unlock_irqrestore(&info->lock,flags);
1199
1200        tty_wakeup(tty);
1201}
1202
1203/* throttle (stop) transmitter
1204 */
1205static void tx_hold(struct tty_struct *tty)
1206{
1207        SLMP_INFO *info = tty->driver_data;
1208        unsigned long flags;
1209
1210        if (sanity_check(info, tty->name, "tx_hold"))
1211                return;
1212
1213        if ( debug_level >= DEBUG_LEVEL_INFO )
1214                printk("%s(%d):%s tx_hold()\n",
1215                        __FILE__,__LINE__,info->device_name);
1216
1217        spin_lock_irqsave(&info->lock,flags);
1218        if (info->tx_enabled)
1219                tx_stop(info);
1220        spin_unlock_irqrestore(&info->lock,flags);
1221}
1222
1223/* release (start) transmitter
1224 */
1225static void tx_release(struct tty_struct *tty)
1226{
1227        SLMP_INFO *info = tty->driver_data;
1228        unsigned long flags;
1229
1230        if (sanity_check(info, tty->name, "tx_release"))
1231                return;
1232
1233        if ( debug_level >= DEBUG_LEVEL_INFO )
1234                printk("%s(%d):%s tx_release()\n",
1235                        __FILE__,__LINE__,info->device_name);
1236
1237        spin_lock_irqsave(&info->lock,flags);
1238        if (!info->tx_enabled)
1239                tx_start(info);
1240        spin_unlock_irqrestore(&info->lock,flags);
1241}
1242
1243/* Service an IOCTL request
1244 *
1245 * Arguments:
1246 *
1247 *      tty     pointer to tty instance data
1248 *      file    pointer to associated file object for device
1249 *      cmd     IOCTL command code
1250 *      arg     command argument/context
1251 *
1252 * Return Value:        0 if success, otherwise error code
1253 */
1254static int do_ioctl(struct tty_struct *tty, struct file *file,
1255                 unsigned int cmd, unsigned long arg)
1256{
1257        SLMP_INFO *info = tty->driver_data;
1258        int error;
1259        struct mgsl_icount cnow;        /* kernel counter temps */
1260        struct serial_icounter_struct __user *p_cuser;  /* user space */
1261        unsigned long flags;
1262        void __user *argp = (void __user *)arg;
1263
1264        if (debug_level >= DEBUG_LEVEL_INFO)
1265                printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1266                        info->device_name, cmd );
1267
1268        if (sanity_check(info, tty->name, "ioctl"))
1269                return -ENODEV;
1270
1271        if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1272            (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1273                if (tty->flags & (1 << TTY_IO_ERROR))
1274                    return -EIO;
1275        }
1276
1277        switch (cmd) {
1278        case MGSL_IOCGPARAMS:
1279                return get_params(info, argp);
1280        case MGSL_IOCSPARAMS:
1281                return set_params(info, argp);
1282        case MGSL_IOCGTXIDLE:
1283                return get_txidle(info, argp);
1284        case MGSL_IOCSTXIDLE:
1285                return set_txidle(info, (int)arg);
1286        case MGSL_IOCTXENABLE:
1287                return tx_enable(info, (int)arg);
1288        case MGSL_IOCRXENABLE:
1289                return rx_enable(info, (int)arg);
1290        case MGSL_IOCTXABORT:
1291                return tx_abort(info);
1292        case MGSL_IOCGSTATS:
1293                return get_stats(info, argp);
1294        case MGSL_IOCWAITEVENT:
1295                return wait_mgsl_event(info, argp);
1296        case MGSL_IOCLOOPTXDONE:
1297                return 0; // TODO: Not supported, need to document
1298                /* Wait for modem input (DCD,RI,DSR,CTS) change
1299                 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1300                 */
1301        case TIOCMIWAIT:
1302                return modem_input_wait(info,(int)arg);
1303                
1304                /*
1305                 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1306                 * Return: write counters to the user passed counter struct
1307                 * NB: both 1->0 and 0->1 transitions are counted except for
1308                 *     RI where only 0->1 is counted.
1309                 */
1310        case TIOCGICOUNT:
1311                spin_lock_irqsave(&info->lock,flags);
1312                cnow = info->icount;
1313                spin_unlock_irqrestore(&info->lock,flags);
1314                p_cuser = argp;
1315                PUT_USER(error,cnow.cts, &p_cuser->cts);
1316                if (error) return error;
1317                PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1318                if (error) return error;
1319                PUT_USER(error,cnow.rng, &p_cuser->rng);
1320                if (error) return error;
1321                PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1322                if (error) return error;
1323                PUT_USER(error,cnow.rx, &p_cuser->rx);
1324                if (error) return error;
1325                PUT_USER(error,cnow.tx, &p_cuser->tx);
1326                if (error) return error;
1327                PUT_USER(error,cnow.frame, &p_cuser->frame);
1328                if (error) return error;
1329                PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1330                if (error) return error;
1331                PUT_USER(error,cnow.parity, &p_cuser->parity);
1332                if (error) return error;
1333                PUT_USER(error,cnow.brk, &p_cuser->brk);
1334                if (error) return error;
1335                PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1336                if (error) return error;
1337                return 0;
1338        default:
1339                return -ENOIOCTLCMD;
1340        }
1341        return 0;
1342}
1343
1344static int ioctl(struct tty_struct *tty, struct file *file,
1345                 unsigned int cmd, unsigned long arg)
1346{
1347        int ret;
1348        lock_kernel();
1349        ret = do_ioctl(tty, file, cmd, arg);
1350        unlock_kernel();
1351        return ret;
1352}
1353
1354/*
1355 * /proc fs routines....
1356 */
1357
1358static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1359{
1360        char    stat_buf[30];
1361        unsigned long flags;
1362
1363        seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1364                       "\tIRQ=%d MaxFrameSize=%u\n",
1365                info->device_name,
1366                info->phys_sca_base,
1367                info->phys_memory_base,
1368                info->phys_statctrl_base,
1369                info->phys_lcr_base,
1370                info->irq_level,
1371                info->max_frame_size );
1372
1373        /* output current serial signal states */
1374        spin_lock_irqsave(&info->lock,flags);
1375        get_signals(info);
1376        spin_unlock_irqrestore(&info->lock,flags);
1377
1378        stat_buf[0] = 0;
1379        stat_buf[1] = 0;
1380        if (info->serial_signals & SerialSignal_RTS)
1381                strcat(stat_buf, "|RTS");
1382        if (info->serial_signals & SerialSignal_CTS)
1383                strcat(stat_buf, "|CTS");
1384        if (info->serial_signals & SerialSignal_DTR)
1385                strcat(stat_buf, "|DTR");
1386        if (info->serial_signals & SerialSignal_DSR)
1387                strcat(stat_buf, "|DSR");
1388        if (info->serial_signals & SerialSignal_DCD)
1389                strcat(stat_buf, "|CD");
1390        if (info->serial_signals & SerialSignal_RI)
1391                strcat(stat_buf, "|RI");
1392
1393        if (info->params.mode == MGSL_MODE_HDLC) {
1394                seq_printf(m, "\tHDLC txok:%d rxok:%d",
1395                              info->icount.txok, info->icount.rxok);
1396                if (info->icount.txunder)
1397                        seq_printf(m, " txunder:%d", info->icount.txunder);
1398                if (info->icount.txabort)
1399                        seq_printf(m, " txabort:%d", info->icount.txabort);
1400                if (info->icount.rxshort)
1401                        seq_printf(m, " rxshort:%d", info->icount.rxshort);
1402                if (info->icount.rxlong)
1403                        seq_printf(m, " rxlong:%d", info->icount.rxlong);
1404                if (info->icount.rxover)
1405                        seq_printf(m, " rxover:%d", info->icount.rxover);
1406                if (info->icount.rxcrc)
1407                        seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1408        } else {
1409                seq_printf(m, "\tASYNC tx:%d rx:%d",
1410                              info->icount.tx, info->icount.rx);
1411                if (info->icount.frame)
1412                        seq_printf(m, " fe:%d", info->icount.frame);
1413                if (info->icount.parity)
1414                        seq_printf(m, " pe:%d", info->icount.parity);
1415                if (info->icount.brk)
1416                        seq_printf(m, " brk:%d", info->icount.brk);
1417                if (info->icount.overrun)
1418                        seq_printf(m, " oe:%d", info->icount.overrun);
1419        }
1420
1421        /* Append serial signal status to end */
1422        seq_printf(m, " %s\n", stat_buf+1);
1423
1424        seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1425         info->tx_active,info->bh_requested,info->bh_running,
1426         info->pending_bh);
1427}
1428
1429/* Called to print information about devices
1430 */
1431static int synclinkmp_proc_show(struct seq_file *m, void *v)
1432{
1433        SLMP_INFO *info;
1434
1435        seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1436
1437        info = synclinkmp_device_list;
1438        while( info ) {
1439                line_info(m, info);
1440                info = info->next_device;
1441        }
1442        return 0;
1443}
1444
1445static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1446{
1447        return single_open(file, synclinkmp_proc_show, NULL);
1448}
1449
1450static const struct file_operations synclinkmp_proc_fops = {
1451        .owner          = THIS_MODULE,
1452        .open           = synclinkmp_proc_open,
1453        .read           = seq_read,
1454        .llseek         = seq_lseek,
1455        .release        = single_release,
1456};
1457
1458/* Return the count of bytes in transmit buffer
1459 */
1460static int chars_in_buffer(struct tty_struct *tty)
1461{
1462        SLMP_INFO *info = tty->driver_data;
1463
1464        if (sanity_check(info, tty->name, "chars_in_buffer"))
1465                return 0;
1466
1467        if (debug_level >= DEBUG_LEVEL_INFO)
1468                printk("%s(%d):%s chars_in_buffer()=%d\n",
1469                       __FILE__, __LINE__, info->device_name, info->tx_count);
1470
1471        return info->tx_count;
1472}
1473
1474/* Signal remote device to throttle send data (our receive data)
1475 */
1476static void throttle(struct tty_struct * tty)
1477{
1478        SLMP_INFO *info = tty->driver_data;
1479        unsigned long flags;
1480
1481        if (debug_level >= DEBUG_LEVEL_INFO)
1482                printk("%s(%d):%s throttle() entry\n",
1483                         __FILE__,__LINE__, info->device_name );
1484
1485        if (sanity_check(info, tty->name, "throttle"))
1486                return;
1487
1488        if (I_IXOFF(tty))
1489                send_xchar(tty, STOP_CHAR(tty));
1490
1491        if (tty->termios->c_cflag & CRTSCTS) {
1492                spin_lock_irqsave(&info->lock,flags);
1493                info->serial_signals &= ~SerialSignal_RTS;
1494                set_signals(info);
1495                spin_unlock_irqrestore(&info->lock,flags);
1496        }
1497}
1498
1499/* Signal remote device to stop throttling send data (our receive data)
1500 */
1501static void unthrottle(struct tty_struct * tty)
1502{
1503        SLMP_INFO *info = tty->driver_data;
1504        unsigned long flags;
1505
1506        if (debug_level >= DEBUG_LEVEL_INFO)
1507                printk("%s(%d):%s unthrottle() entry\n",
1508                         __FILE__,__LINE__, info->device_name );
1509
1510        if (sanity_check(info, tty->name, "unthrottle"))
1511                return;
1512
1513        if (I_IXOFF(tty)) {
1514                if (info->x_char)
1515                        info->x_char = 0;
1516                else
1517                        send_xchar(tty, START_CHAR(tty));
1518        }
1519
1520        if (tty->termios->c_cflag & CRTSCTS) {
1521                spin_lock_irqsave(&info->lock,flags);
1522                info->serial_signals |= SerialSignal_RTS;
1523                set_signals(info);
1524                spin_unlock_irqrestore(&info->lock,flags);
1525        }
1526}
1527
1528/* set or clear transmit break condition
1529 * break_state  -1=set break condition, 0=clear
1530 */
1531static int set_break(struct tty_struct *tty, int break_state)
1532{
1533        unsigned char RegValue;
1534        SLMP_INFO * info = tty->driver_data;
1535        unsigned long flags;
1536
1537        if (debug_level >= DEBUG_LEVEL_INFO)
1538                printk("%s(%d):%s set_break(%d)\n",
1539                         __FILE__,__LINE__, info->device_name, break_state);
1540
1541        if (sanity_check(info, tty->name, "set_break"))
1542                return -EINVAL;
1543
1544        spin_lock_irqsave(&info->lock,flags);
1545        RegValue = read_reg(info, CTL);
1546        if (break_state == -1)
1547                RegValue |= BIT3;
1548        else
1549                RegValue &= ~BIT3;
1550        write_reg(info, CTL, RegValue);
1551        spin_unlock_irqrestore(&info->lock,flags);
1552        return 0;
1553}
1554
1555#if SYNCLINK_GENERIC_HDLC
1556
1557/**
1558 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1559 * set encoding and frame check sequence (FCS) options
1560 *
1561 * dev       pointer to network device structure
1562 * encoding  serial encoding setting
1563 * parity    FCS setting
1564 *
1565 * returns 0 if success, otherwise error code
1566 */
1567static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1568                          unsigned short parity)
1569{
1570        SLMP_INFO *info = dev_to_port(dev);
1571        unsigned char  new_encoding;
1572        unsigned short new_crctype;
1573
1574        /* return error if TTY interface open */
1575        if (info->port.count)
1576                return -EBUSY;
1577
1578        switch (encoding)
1579        {
1580        case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1581        case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1582        case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1583        case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1584        case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1585        default: return -EINVAL;
1586        }
1587
1588        switch (parity)
1589        {
1590        case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1591        case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1592        case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1593        default: return -EINVAL;
1594        }
1595
1596        info->params.encoding = new_encoding;
1597        info->params.crc_type = new_crctype;
1598
1599        /* if network interface up, reprogram hardware */
1600        if (info->netcount)
1601                program_hw(info);
1602
1603        return 0;
1604}
1605
1606/**
1607 * called by generic HDLC layer to send frame
1608 *
1609 * skb  socket buffer containing HDLC frame
1610 * dev  pointer to network device structure
1611 *
1612 * returns 0 if success, otherwise error code
1613 */
1614static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1615{
1616        SLMP_INFO *info = dev_to_port(dev);
1617        unsigned long flags;
1618
1619        if (debug_level >= DEBUG_LEVEL_INFO)
1620                printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1621
1622        /* stop sending until this frame completes */
1623        netif_stop_queue(dev);
1624
1625        /* copy data to device buffers */
1626        info->tx_count = skb->len;
1627        tx_load_dma_buffer(info, skb->data, skb->len);
1628
1629        /* update network statistics */
1630        dev->stats.tx_packets++;
1631        dev->stats.tx_bytes += skb->len;
1632
1633        /* done with socket buffer, so free it */
1634        dev_kfree_skb(skb);
1635
1636        /* save start time for transmit timeout detection */
1637        dev->trans_start = jiffies;
1638
1639        /* start hardware transmitter if necessary */
1640        spin_lock_irqsave(&info->lock,flags);
1641        if (!info->tx_active)
1642                tx_start(info);
1643        spin_unlock_irqrestore(&info->lock,flags);
1644
1645        return 0;
1646}
1647
1648/**
1649 * called by network layer when interface enabled
1650 * claim resources and initialize hardware
1651 *
1652 * dev  pointer to network device structure
1653 *
1654 * returns 0 if success, otherwise error code
1655 */
1656static int hdlcdev_open(struct net_device *dev)
1657{
1658        SLMP_INFO *info = dev_to_port(dev);
1659        int rc;
1660        unsigned long flags;
1661
1662        if (debug_level >= DEBUG_LEVEL_INFO)
1663                printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1664
1665        /* generic HDLC layer open processing */
1666        if ((rc = hdlc_open(dev)))
1667                return rc;
1668
1669        /* arbitrate between network and tty opens */
1670        spin_lock_irqsave(&info->netlock, flags);
1671        if (info->port.count != 0 || info->netcount != 0) {
1672                printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1673                spin_unlock_irqrestore(&info->netlock, flags);
1674                return -EBUSY;
1675        }
1676        info->netcount=1;
1677        spin_unlock_irqrestore(&info->netlock, flags);
1678
1679        /* claim resources and init adapter */
1680        if ((rc = startup(info)) != 0) {
1681                spin_lock_irqsave(&info->netlock, flags);
1682                info->netcount=0;
1683                spin_unlock_irqrestore(&info->netlock, flags);
1684                return rc;
1685        }
1686
1687        /* assert DTR and RTS, apply hardware settings */
1688        info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1689        program_hw(info);
1690
1691        /* enable network layer transmit */
1692        dev->trans_start = jiffies;
1693        netif_start_queue(dev);
1694
1695        /* inform generic HDLC layer of current DCD status */
1696        spin_lock_irqsave(&info->lock, flags);
1697        get_signals(info);
1698        spin_unlock_irqrestore(&info->lock, flags);
1699        if (info->serial_signals & SerialSignal_DCD)
1700                netif_carrier_on(dev);
1701        else
1702                netif_carrier_off(dev);
1703        return 0;
1704}
1705
1706/**
1707 * called by network layer when interface is disabled
1708 * shutdown hardware and release resources
1709 *
1710 * dev  pointer to network device structure
1711 *
1712 * returns 0 if success, otherwise error code
1713 */
1714static int hdlcdev_close(struct net_device *dev)
1715{
1716        SLMP_INFO *info = dev_to_port(dev);
1717        unsigned long flags;
1718
1719        if (debug_level >= DEBUG_LEVEL_INFO)
1720                printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1721
1722        netif_stop_queue(dev);
1723
1724        /* shutdown adapter and release resources */
1725        shutdown(info);
1726
1727        hdlc_close(dev);
1728
1729        spin_lock_irqsave(&info->netlock, flags);
1730        info->netcount=0;
1731        spin_unlock_irqrestore(&info->netlock, flags);
1732
1733        return 0;
1734}
1735
1736/**
1737 * called by network layer to process IOCTL call to network device
1738 *
1739 * dev  pointer to network device structure
1740 * ifr  pointer to network interface request structure
1741 * cmd  IOCTL command code
1742 *
1743 * returns 0 if success, otherwise error code
1744 */
1745static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1746{
1747        const size_t size = sizeof(sync_serial_settings);
1748        sync_serial_settings new_line;
1749        sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1750        SLMP_INFO *info = dev_to_port(dev);
1751        unsigned int flags;
1752
1753        if (debug_level >= DEBUG_LEVEL_INFO)
1754                printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1755
1756        /* return error if TTY interface open */
1757        if (info->port.count)
1758                return -EBUSY;
1759
1760        if (cmd != SIOCWANDEV)
1761                return hdlc_ioctl(dev, ifr, cmd);
1762
1763        switch(ifr->ifr_settings.type) {
1764        case IF_GET_IFACE: /* return current sync_serial_settings */
1765
1766                ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1767                if (ifr->ifr_settings.size < size) {
1768                        ifr->ifr_settings.size = size; /* data size wanted */
1769                        return -ENOBUFS;
1770                }
1771
1772                flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1773                                              HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1774                                              HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1775                                              HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1776
1777                switch (flags){
1778                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1779                case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1780                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1781                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1782                default: new_line.clock_type = CLOCK_DEFAULT;
1783                }
1784
1785                new_line.clock_rate = info->params.clock_speed;
1786                new_line.loopback   = info->params.loopback ? 1:0;
1787
1788                if (copy_to_user(line, &new_line, size))
1789                        return -EFAULT;
1790                return 0;
1791
1792        case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1793
1794                if(!capable(CAP_NET_ADMIN))
1795                        return -EPERM;
1796                if (copy_from_user(&new_line, line, size))
1797                        return -EFAULT;
1798
1799                switch (new_line.clock_type)
1800                {
1801                case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1802                case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1803                case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1804                case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1805                case CLOCK_DEFAULT:  flags = info->params.flags &
1806                                             (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1807                                              HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1808                                              HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1809                                              HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1810                default: return -EINVAL;
1811                }
1812
1813                if (new_line.loopback != 0 && new_line.loopback != 1)
1814                        return -EINVAL;
1815
1816                info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1817                                        HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1818                                        HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1819                                        HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1820                info->params.flags |= flags;
1821
1822                info->params.loopback = new_line.loopback;
1823
1824                if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1825                        info->params.clock_speed = new_line.clock_rate;
1826                else
1827                        info->params.clock_speed = 0;
1828
1829                /* if network interface up, reprogram hardware */
1830                if (info->netcount)
1831                        program_hw(info);
1832                return 0;
1833
1834        default:
1835                return hdlc_ioctl(dev, ifr, cmd);
1836        }
1837}
1838
1839/**
1840 * called by network layer when transmit timeout is detected
1841 *
1842 * dev  pointer to network device structure
1843 */
1844static void hdlcdev_tx_timeout(struct net_device *dev)
1845{
1846        SLMP_INFO *info = dev_to_port(dev);
1847        unsigned long flags;
1848
1849        if (debug_level >= DEBUG_LEVEL_INFO)
1850                printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1851
1852        dev->stats.tx_errors++;
1853        dev->stats.tx_aborted_errors++;
1854
1855        spin_lock_irqsave(&info->lock,flags);
1856        tx_stop(info);
1857        spin_unlock_irqrestore(&info->lock,flags);
1858
1859        netif_wake_queue(dev);
1860}
1861
1862/**
1863 * called by device driver when transmit completes
1864 * reenable network layer transmit if stopped
1865 *
1866 * info  pointer to device instance information
1867 */
1868static void hdlcdev_tx_done(SLMP_INFO *info)
1869{
1870        if (netif_queue_stopped(info->netdev))
1871                netif_wake_queue(info->netdev);
1872}
1873
1874/**
1875 * called by device driver when frame received
1876 * pass frame to network layer
1877 *
1878 * info  pointer to device instance information
1879 * buf   pointer to buffer contianing frame data
1880 * size  count of data bytes in buf
1881 */
1882static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1883{
1884        struct sk_buff *skb = dev_alloc_skb(size);
1885        struct net_device *dev = info->netdev;
1886
1887        if (debug_level >= DEBUG_LEVEL_INFO)
1888                printk("hdlcdev_rx(%s)\n",dev->name);
1889
1890        if (skb == NULL) {
1891                printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1892                       dev->name);
1893                dev->stats.rx_dropped++;
1894                return;
1895        }
1896
1897        memcpy(skb_put(skb, size), buf, size);
1898
1899        skb->protocol = hdlc_type_trans(skb, dev);
1900
1901        dev->stats.rx_packets++;
1902        dev->stats.rx_bytes += size;
1903
1904        netif_rx(skb);
1905}
1906
1907static const struct net_device_ops hdlcdev_ops = {
1908        .ndo_open       = hdlcdev_open,
1909        .ndo_stop       = hdlcdev_close,
1910        .ndo_change_mtu = hdlc_change_mtu,
1911        .ndo_start_xmit = hdlc_start_xmit,
1912        .ndo_do_ioctl   = hdlcdev_ioctl,
1913        .ndo_tx_timeout = hdlcdev_tx_timeout,
1914};
1915
1916/**
1917 * called by device driver when adding device instance
1918 * do generic HDLC initialization
1919 *
1920 * info  pointer to device instance information
1921 *
1922 * returns 0 if success, otherwise error code
1923 */
1924static int hdlcdev_init(SLMP_INFO *info)
1925{
1926        int rc;
1927        struct net_device *dev;
1928        hdlc_device *hdlc;
1929
1930        /* allocate and initialize network and HDLC layer objects */
1931
1932        if (!(dev = alloc_hdlcdev(info))) {
1933                printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1934                return -ENOMEM;
1935        }
1936
1937        /* for network layer reporting purposes only */
1938        dev->mem_start = info->phys_sca_base;
1939        dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1940        dev->irq       = info->irq_level;
1941
1942        /* network layer callbacks and settings */
1943        dev->netdev_ops     = &hdlcdev_ops;
1944        dev->watchdog_timeo = 10 * HZ;
1945        dev->tx_queue_len   = 50;
1946
1947        /* generic HDLC layer callbacks and settings */
1948        hdlc         = dev_to_hdlc(dev);
1949        hdlc->attach = hdlcdev_attach;
1950        hdlc->xmit   = hdlcdev_xmit;
1951
1952        /* register objects with HDLC layer */
1953        if ((rc = register_hdlc_device(dev))) {
1954                printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1955                free_netdev(dev);
1956                return rc;
1957        }
1958
1959        info->netdev = dev;
1960        return 0;
1961}
1962
1963/**
1964 * called by device driver when removing device instance
1965 * do generic HDLC cleanup
1966 *
1967 * info  pointer to device instance information
1968 */
1969static void hdlcdev_exit(SLMP_INFO *info)
1970{
1971        unregister_hdlc_device(info->netdev);
1972        free_netdev(info->netdev);
1973        info->netdev = NULL;
1974}
1975
1976#endif /* CONFIG_HDLC */
1977
1978
1979/* Return next bottom half action to perform.
1980 * Return Value:        BH action code or 0 if nothing to do.
1981 */
1982static int bh_action(SLMP_INFO *info)
1983{
1984        unsigned long flags;
1985        int rc = 0;
1986
1987        spin_lock_irqsave(&info->lock,flags);
1988
1989        if (info->pending_bh & BH_RECEIVE) {
1990                info->pending_bh &= ~BH_RECEIVE;
1991                rc = BH_RECEIVE;
1992        } else if (info->pending_bh & BH_TRANSMIT) {
1993                info->pending_bh &= ~BH_TRANSMIT;
1994                rc = BH_TRANSMIT;
1995        } else if (info->pending_bh & BH_STATUS) {
1996                info->pending_bh &= ~BH_STATUS;
1997                rc = BH_STATUS;
1998        }
1999
2000        if (!rc) {
2001                /* Mark BH routine as complete */
2002                info->bh_running = false;
2003                info->bh_requested = false;
2004        }
2005
2006        spin_unlock_irqrestore(&info->lock,flags);
2007
2008        return rc;
2009}
2010
2011/* Perform bottom half processing of work items queued by ISR.
2012 */
2013static void bh_handler(struct work_struct *work)
2014{
2015        SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2016        int action;
2017
2018        if (!info)
2019                return;
2020
2021        if ( debug_level >= DEBUG_LEVEL_BH )
2022                printk( "%s(%d):%s bh_handler() entry\n",
2023                        __FILE__,__LINE__,info->device_name);
2024
2025        info->bh_running = true;
2026
2027        while((action = bh_action(info)) != 0) {
2028
2029                /* Process work item */
2030                if ( debug_level >= DEBUG_LEVEL_BH )
2031                        printk( "%s(%d):%s bh_handler() work item action=%d\n",
2032                                __FILE__,__LINE__,info->device_name, action);
2033
2034                switch (action) {
2035
2036                case BH_RECEIVE:
2037                        bh_receive(info);
2038                        break;
2039                case BH_TRANSMIT:
2040                        bh_transmit(info);
2041                        break;
2042                case BH_STATUS:
2043                        bh_status(info);
2044                        break;
2045                default:
2046                        /* unknown work item ID */
2047                        printk("%s(%d):%s Unknown work item ID=%08X!\n",
2048                                __FILE__,__LINE__,info->device_name,action);
2049                        break;
2050                }
2051        }
2052
2053        if ( debug_level >= DEBUG_LEVEL_BH )
2054                printk( "%s(%d):%s bh_handler() exit\n",
2055                        __FILE__,__LINE__,info->device_name);
2056}
2057
2058static void bh_receive(SLMP_INFO *info)
2059{
2060        if ( debug_level >= DEBUG_LEVEL_BH )
2061                printk( "%s(%d):%s bh_receive()\n",
2062                        __FILE__,__LINE__,info->device_name);
2063
2064        while( rx_get_frame(info) );
2065}
2066
2067static void bh_transmit(SLMP_INFO *info)
2068{
2069        struct tty_struct *tty = info->port.tty;
2070
2071        if ( debug_level >= DEBUG_LEVEL_BH )
2072                printk( "%s(%d):%s bh_transmit() entry\n",
2073                        __FILE__,__LINE__,info->device_name);
2074
2075        if (tty)
2076                tty_wakeup(tty);
2077}
2078
2079static void bh_status(SLMP_INFO *info)
2080{
2081        if ( debug_level >= DEBUG_LEVEL_BH )
2082                printk( "%s(%d):%s bh_status() entry\n",
2083                        __FILE__,__LINE__,info->device_name);
2084
2085        info->ri_chkcount = 0;
2086        info->dsr_chkcount = 0;
2087        info->dcd_chkcount = 0;
2088        info->cts_chkcount = 0;
2089}
2090
2091static void isr_timer(SLMP_INFO * info)
2092{
2093        unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2094
2095        /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2096        write_reg(info, IER2, 0);
2097
2098        /* TMCS, Timer Control/Status Register
2099         *
2100         * 07      CMF, Compare match flag (read only) 1=match
2101         * 06      ECMI, CMF Interrupt Enable: 0=disabled
2102         * 05      Reserved, must be 0
2103         * 04      TME, Timer Enable
2104         * 03..00  Reserved, must be 0
2105         *
2106         * 0000 0000
2107         */
2108        write_reg(info, (unsigned char)(timer + TMCS), 0);
2109
2110        info->irq_occurred = true;
2111
2112        if ( debug_level >= DEBUG_LEVEL_ISR )
2113                printk("%s(%d):%s isr_timer()\n",
2114                        __FILE__,__LINE__,info->device_name);
2115}
2116
2117static void isr_rxint(SLMP_INFO * info)
2118{
2119        struct tty_struct *tty = info->port.tty;
2120        struct  mgsl_icount *icount = &info->icount;
2121        unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2122        unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2123
2124        /* clear status bits */
2125        if (status)
2126                write_reg(info, SR1, status);
2127
2128        if (status2)
2129                write_reg(info, SR2, status2);
2130        
2131        if ( debug_level >= DEBUG_LEVEL_ISR )
2132                printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2133                        __FILE__,__LINE__,info->device_name,status,status2);
2134
2135        if (info->params.mode == MGSL_MODE_ASYNC) {
2136                if (status & BRKD) {
2137                        icount->brk++;
2138
2139                        /* process break detection if tty control
2140                         * is not set to ignore it
2141                         */
2142                        if ( tty ) {
2143                                if (!(status & info->ignore_status_mask1)) {
2144                                        if (info->read_status_mask1 & BRKD) {
2145                                                tty_insert_flip_char(tty, 0, TTY_BREAK);
2146                                                if (info->port.flags & ASYNC_SAK)
2147                                                        do_SAK(tty);
2148                                        }
2149                                }
2150                        }
2151                }
2152        }
2153        else {
2154                if (status & (FLGD|IDLD)) {
2155                        if (status & FLGD)
2156                                info->icount.exithunt++;
2157                        else if (status & IDLD)
2158                                info->icount.rxidle++;
2159                        wake_up_interruptible(&info->event_wait_q);
2160                }
2161        }
2162
2163        if (status & CDCD) {
2164                /* simulate a common modem status change interrupt
2165                 * for our handler
2166                 */
2167                get_signals( info );
2168                isr_io_pin(info,
2169                        MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2170        }
2171}
2172
2173/*
2174 * handle async rx data interrupts
2175 */
2176static void isr_rxrdy(SLMP_INFO * info)
2177{
2178        u16 status;
2179        unsigned char DataByte;
2180        struct tty_struct *tty = info->port.tty;
2181        struct  mgsl_icount *icount = &info->icount;
2182
2183        if ( debug_level >= DEBUG_LEVEL_ISR )
2184                printk("%s(%d):%s isr_rxrdy\n",
2185                        __FILE__,__LINE__,info->device_name);
2186
2187        while((status = read_reg(info,CST0)) & BIT0)
2188        {
2189                int flag = 0;
2190                bool over = false;
2191                DataByte = read_reg(info,TRB);
2192
2193                icount->rx++;
2194
2195                if ( status & (PE + FRME + OVRN) ) {
2196                        printk("%s(%d):%s rxerr=%04X\n",
2197                                __FILE__,__LINE__,info->device_name,status);
2198
2199                        /* update error statistics */
2200                        if (status & PE)
2201                                icount->parity++;
2202                        else if (status & FRME)
2203                                icount->frame++;
2204                        else if (status & OVRN)
2205                                icount->overrun++;
2206
2207                        /* discard char if tty control flags say so */
2208                        if (status & info->ignore_status_mask2)
2209                                continue;
2210
2211                        status &= info->read_status_mask2;
2212
2213                        if ( tty ) {
2214                                if (status & PE)
2215                                        flag = TTY_PARITY;
2216                                else if (status & FRME)
2217                                        flag = TTY_FRAME;
2218                                if (status & OVRN) {
2219                                        /* Overrun is special, since it's
2220                                         * reported immediately, and doesn't
2221                                         * affect the current character
2222                                         */
2223                                        over = true;
2224                                }
2225                        }
2226                }       /* end of if (error) */
2227
2228                if ( tty ) {
2229                        tty_insert_flip_char(tty, DataByte, flag);
2230                        if (over)
2231                                tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2232                }
2233        }
2234
2235        if ( debug_level >= DEBUG_LEVEL_ISR ) {
2236                printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2237                        __FILE__,__LINE__,info->device_name,
2238                        icount->rx,icount->brk,icount->parity,
2239                        icount->frame,icount->overrun);
2240        }
2241
2242        if ( tty )
2243                tty_flip_buffer_push(tty);
2244}
2245
2246static void isr_txeom(SLMP_INFO * info, unsigned char status)
2247{
2248        if ( debug_level >= DEBUG_LEVEL_ISR )
2249                printk("%s(%d):%s isr_txeom status=%02x\n",
2250                        __FILE__,__LINE__,info->device_name,status);
2251
2252        write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2253        write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2254        write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2255
2256        if (status & UDRN) {
2257                write_reg(info, CMD, TXRESET);
2258                write_reg(info, CMD, TXENABLE);
2259        } else
2260                write_reg(info, CMD, TXBUFCLR);
2261
2262        /* disable and clear tx interrupts */
2263        info->ie0_value &= ~TXRDYE;
2264        info->ie1_value &= ~(IDLE + UDRN);
2265        write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2266        write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2267
2268        if ( info->tx_active ) {
2269                if (info->params.mode != MGSL_MODE_ASYNC) {
2270                        if (status & UDRN)
2271                                info->icount.txunder++;
2272                        else if (status & IDLE)
2273                                info->icount.txok++;
2274                }
2275
2276                info->tx_active = false;
2277                info->tx_count = info->tx_put = info->tx_get = 0;
2278
2279                del_timer(&info->tx_timer);
2280
2281                if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2282                        info->serial_signals &= ~SerialSignal_RTS;
2283                        info->drop_rts_on_tx_done = false;
2284                        set_signals(info);
2285                }
2286
2287#if SYNCLINK_GENERIC_HDLC
2288                if (info->netcount)
2289                        hdlcdev_tx_done(info);
2290                else
2291#endif
2292                {
2293                        if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2294                                tx_stop(info);
2295                                return;
2296                        }
2297                        info->pending_bh |= BH_TRANSMIT;
2298                }
2299        }
2300}
2301
2302
2303/*
2304 * handle tx status interrupts
2305 */
2306static void isr_txint(SLMP_INFO * info)
2307{
2308        unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2309
2310        /* clear status bits */
2311        write_reg(info, SR1, status);
2312
2313        if ( debug_level >= DEBUG_LEVEL_ISR )
2314                printk("%s(%d):%s isr_txint status=%02x\n",
2315                        __FILE__,__LINE__,info->device_name,status);
2316
2317        if (status & (UDRN + IDLE))
2318                isr_txeom(info, status);
2319
2320        if (status & CCTS) {
2321                /* simulate a common modem status change interrupt
2322                 * for our handler
2323                 */
2324                get_signals( info );
2325                isr_io_pin(info,
2326                        MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2327
2328        }
2329}
2330
2331/*
2332 * handle async tx data interrupts
2333 */
2334static void isr_txrdy(SLMP_INFO * info)
2335{
2336        if ( debug_level >= DEBUG_LEVEL_ISR )
2337                printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2338                        __FILE__,__LINE__,info->device_name,info->tx_count);
2339
2340        if (info->params.mode != MGSL_MODE_ASYNC) {
2341                /* disable TXRDY IRQ, enable IDLE IRQ */
2342                info->ie0_value &= ~TXRDYE;
2343                info->ie1_value |= IDLE;
2344                write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2345                return;
2346        }
2347
2348        if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2349                tx_stop(info);
2350                return;
2351        }
2352
2353        if ( info->tx_count )
2354                tx_load_fifo( info );
2355        else {
2356                info->tx_active = false;
2357                info->ie0_value &= ~TXRDYE;
2358                write_reg(info, IE0, info->ie0_value);
2359        }
2360
2361        if (info->tx_count < WAKEUP_CHARS)
2362                info->pending_bh |= BH_TRANSMIT;
2363}
2364
2365static void isr_rxdmaok(SLMP_INFO * info)
2366{
2367        /* BIT7 = EOT (end of transfer)
2368         * BIT6 = EOM (end of message/frame)
2369         */
2370        unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2371
2372        /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2373        write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2374
2375        if ( debug_level >= DEBUG_LEVEL_ISR )
2376                printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2377                        __FILE__,__LINE__,info->device_name,status);
2378
2379        info->pending_bh |= BH_RECEIVE;
2380}
2381
2382static void isr_rxdmaerror(SLMP_INFO * info)
2383{
2384        /* BIT5 = BOF (buffer overflow)
2385         * BIT4 = COF (counter overflow)
2386         */
2387        unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2388
2389        /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2390        write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2391
2392        if ( debug_level >= DEBUG_LEVEL_ISR )
2393                printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2394                        __FILE__,__LINE__,info->device_name,status);
2395
2396        info->rx_overflow = true;
2397        info->pending_bh |= BH_RECEIVE;
2398}
2399
2400static void isr_txdmaok(SLMP_INFO * info)
2401{
2402        unsigned char status_reg1 = read_reg(info, SR1);
2403
2404        write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2405        write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2406        write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2407
2408        if ( debug_level >= DEBUG_LEVEL_ISR )
2409                printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2410                        __FILE__,__LINE__,info->device_name,status_reg1);
2411
2412        /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2413        write_reg16(info, TRC0, 0);
2414        info->ie0_value |= TXRDYE;
2415        write_reg(info, IE0, info->ie0_value);
2416}
2417
2418static void isr_txdmaerror(SLMP_INFO * info)
2419{
2420        /* BIT5 = BOF (buffer overflow)
2421         * BIT4 = COF (counter overflow)
2422         */
2423        unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2424
2425        /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2426        write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2427
2428        if ( debug_level >= DEBUG_LEVEL_ISR )
2429                printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2430                        __FILE__,__LINE__,info->device_name,status);
2431}
2432
2433/* handle input serial signal changes
2434 */
2435static void isr_io_pin( SLMP_INFO *info, u16 status )
2436{
2437        struct  mgsl_icount *icount;
2438
2439        if ( debug_level >= DEBUG_LEVEL_ISR )
2440                printk("%s(%d):isr_io_pin status=%04X\n",
2441                        __FILE__,__LINE__,status);
2442
2443        if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2444                      MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2445                icount = &info->icount;
2446                /* update input line counters */
2447                if (status & MISCSTATUS_RI_LATCHED) {
2448                        icount->rng++;
2449                        if ( status & SerialSignal_RI )
2450                                info->input_signal_events.ri_up++;
2451                        else
2452                                info->input_signal_events.ri_down++;
2453                }
2454                if (status & MISCSTATUS_DSR_LATCHED) {
2455                        icount->dsr++;
2456                        if ( status & SerialSignal_DSR )
2457                                info->input_signal_events.dsr_up++;
2458                        else
2459                                info->input_signal_events.dsr_down++;
2460                }
2461                if (status & MISCSTATUS_DCD_LATCHED) {
2462                        if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2463                                info->ie1_value &= ~CDCD;
2464                                write_reg(info, IE1, info->ie1_value);
2465                        }
2466                        icount->dcd++;
2467                        if (status & SerialSignal_DCD) {
2468                                info->input_signal_events.dcd_up++;
2469                        } else
2470                                info->input_signal_events.dcd_down++;
2471#if SYNCLINK_GENERIC_HDLC
2472                        if (info->netcount) {
2473                                if (status & SerialSignal_DCD)
2474                                        netif_carrier_on(info->netdev);
2475                                else
2476                                        netif_carrier_off(info->netdev);
2477                        }
2478#endif
2479                }
2480                if (status & MISCSTATUS_CTS_LATCHED)
2481                {
2482                        if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2483                                info->ie1_value &= ~CCTS;
2484                                write_reg(info, IE1, info->ie1_value);
2485                        }
2486                        icount->cts++;
2487                        if ( status & SerialSignal_CTS )
2488                                info->input_signal_events.cts_up++;
2489                        else
2490                                info->input_signal_events.cts_down++;
2491                }
2492                wake_up_interruptible(&info->status_event_wait_q);
2493                wake_up_interruptible(&info->event_wait_q);
2494
2495                if ( (info->port.flags & ASYNC_CHECK_CD) &&
2496                     (status & MISCSTATUS_DCD_LATCHED) ) {
2497                        if ( debug_level >= DEBUG_LEVEL_ISR )
2498                                printk("%s CD now %s...", info->device_name,
2499                                       (status & SerialSignal_DCD) ? "on" : "off");
2500                        if (status & SerialSignal_DCD)
2501                                wake_up_interruptible(&info->port.open_wait);
2502                        else {
2503                                if ( debug_level >= DEBUG_LEVEL_ISR )
2504                                        printk("doing serial hangup...");
2505                                if (info->port.tty)
2506                                        tty_hangup(info->port.tty);
2507                        }
2508                }
2509
2510                if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2511                     (status & MISCSTATUS_CTS_LATCHED) ) {
2512                        if ( info->port.tty ) {
2513                                if (info->port.tty->hw_stopped) {
2514                                        if (status & SerialSignal_CTS) {
2515                                                if ( debug_level >= DEBUG_LEVEL_ISR )
2516                                                        printk("CTS tx start...");
2517                                                info->port.tty->hw_stopped = 0;
2518                                                tx_start(info);
2519                                                info->pending_bh |= BH_TRANSMIT;
2520                                                return;
2521                                        }
2522                                } else {
2523                                        if (!(status & SerialSignal_CTS)) {
2524                                                if ( debug_level >= DEBUG_LEVEL_ISR )
2525                                                        printk("CTS tx stop...");
2526                                                info->port.tty->hw_stopped = 1;
2527                                                tx_stop(info);
2528                                        }
2529                                }
2530                        }
2531                }
2532        }
2533
2534        info->pending_bh |= BH_STATUS;
2535}
2536
2537/* Interrupt service routine entry point.
2538 *
2539 * Arguments:
2540 *      irq             interrupt number that caused interrupt
2541 *      dev_id          device ID supplied during interrupt registration
2542 *      regs            interrupted processor context
2543 */
2544static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2545{
2546        SLMP_INFO *info = dev_id;
2547        unsigned char status, status0, status1=0;
2548        unsigned char dmastatus, dmastatus0, dmastatus1=0;
2549        unsigned char timerstatus0, timerstatus1=0;
2550        unsigned char shift;
2551        unsigned int i;
2552        unsigned short tmp;
2553
2554        if ( debug_level >= DEBUG_LEVEL_ISR )
2555                printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2556                        __FILE__, __LINE__, info->irq_level);
2557
2558        spin_lock(&info->lock);
2559
2560        for(;;) {
2561
2562                /* get status for SCA0 (ports 0-1) */
2563                tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2564                status0 = (unsigned char)tmp;
2565                dmastatus0 = (unsigned char)(tmp>>8);
2566                timerstatus0 = read_reg(info, ISR2);
2567
2568                if ( debug_level >= DEBUG_LEVEL_ISR )
2569                        printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2570                                __FILE__, __LINE__, info->device_name,
2571                                status0, dmastatus0, timerstatus0);
2572
2573                if (info->port_count == 4) {
2574                        /* get status for SCA1 (ports 2-3) */
2575                        tmp = read_reg16(info->port_array[2], ISR0);
2576                        status1 = (unsigned char)tmp;
2577                        dmastatus1 = (unsigned char)(tmp>>8);
2578                        timerstatus1 = read_reg(info->port_array[2], ISR2);
2579
2580                        if ( debug_level >= DEBUG_LEVEL_ISR )
2581                                printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2582                                        __FILE__,__LINE__,info->device_name,
2583                                        status1,dmastatus1,timerstatus1);
2584                }
2585
2586                if (!status0 && !dmastatus0 && !timerstatus0 &&
2587                         !status1 && !dmastatus1 && !timerstatus1)
2588                        break;
2589
2590                for(i=0; i < info->port_count ; i++) {
2591                        if (info->port_array[i] == NULL)
2592                                continue;
2593                        if (i < 2) {
2594                                status = status0;
2595                                dmastatus = dmastatus0;
2596                        } else {
2597                                status = status1;
2598                                dmastatus = dmastatus1;
2599                        }
2600
2601                        shift = i & 1 ? 4 :0;
2602
2603                        if (status & BIT0 << shift)
2604                                isr_rxrdy(info->port_array[i]);
2605                        if (status & BIT1 << shift)
2606                                isr_txrdy(info->port_array[i]);
2607                        if (status & BIT2 << shift)
2608                                isr_rxint(info->port_array[i]);
2609                        if (status & BIT3 << shift)
2610                                isr_txint(info->port_array[i]);
2611
2612                        if (dmastatus & BIT0 << shift)
2613                                isr_rxdmaerror(info->port_array[i]);
2614                        if (dmastatus & BIT1 << shift)
2615                                isr_rxdmaok(info->port_array[i]);
2616                        if (dmastatus & BIT2 << shift)
2617                                isr_txdmaerror(info->port_array[i]);
2618                        if (dmastatus & BIT3 << shift)
2619                                isr_txdmaok(info->port_array[i]);
2620                }
2621
2622                if (timerstatus0 & (BIT5 | BIT4))
2623                        isr_timer(info->port_array[0]);
2624                if (timerstatus0 & (BIT7 | BIT6))
2625                        isr_timer(info->port_array[1]);
2626                if (timerstatus1 & (BIT5 | BIT4))
2627                        isr_timer(info->port_array[2]);
2628                if (timerstatus1 & (BIT7 | BIT6))
2629                        isr_timer(info->port_array[3]);
2630        }
2631
2632        for(i=0; i < info->port_count ; i++) {
2633                SLMP_INFO * port = info->port_array[i];
2634
2635                /* Request bottom half processing if there's something
2636                 * for it to do and the bh is not already running.
2637                 *
2638                 * Note: startup adapter diags require interrupts.
2639                 * do not request bottom half processing if the
2640                 * device is not open in a normal mode.
2641                 */
2642                if ( port && (port->port.count || port->netcount) &&
2643                     port->pending_bh && !port->bh_running &&
2644                     !port->bh_requested ) {
2645                        if ( debug_level >= DEBUG_LEVEL_ISR )
2646                                printk("%s(%d):%s queueing bh task.\n",
2647                                        __FILE__,__LINE__,port->device_name);
2648                        schedule_work(&port->task);
2649                        port->bh_requested = true;
2650                }
2651        }
2652
2653        spin_unlock(&info->lock);
2654
2655        if ( debug_level >= DEBUG_LEVEL_ISR )
2656                printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2657                        __FILE__, __LINE__, info->irq_level);
2658        return IRQ_HANDLED;
2659}
2660
2661/* Initialize and start device.
2662 */
2663static int startup(SLMP_INFO * info)
2664{
2665        if ( debug_level >= DEBUG_LEVEL_INFO )
2666                printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2667
2668        if (info->port.flags & ASYNC_INITIALIZED)
2669                return 0;
2670
2671        if (!info->tx_buf) {
2672                info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2673                if (!info->tx_buf) {
2674                        printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2675                                __FILE__,__LINE__,info->device_name);
2676                        return -ENOMEM;
2677                }
2678        }
2679
2680        info->pending_bh = 0;
2681
2682        memset(&info->icount, 0, sizeof(info->icount));
2683
2684        /* program hardware for current parameters */
2685        reset_port(info);
2686
2687        change_params(info);
2688
2689        mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2690
2691        if (info->port.tty)
2692                clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2693
2694        info->port.flags |= ASYNC_INITIALIZED;
2695
2696        return 0;
2697}
2698
2699/* Called by close() and hangup() to shutdown hardware
2700 */
2701static void shutdown(SLMP_INFO * info)
2702{
2703        unsigned long flags;
2704
2705        if (!(info->port.flags & ASYNC_INITIALIZED))
2706                return;
2707
2708        if (debug_level >= DEBUG_LEVEL_INFO)
2709                printk("%s(%d):%s synclinkmp_shutdown()\n",
2710                         __FILE__,__LINE__, info->device_name );
2711
2712        /* clear status wait queue because status changes */
2713        /* can't happen after shutting down the hardware */
2714        wake_up_interruptible(&info->status_event_wait_q);
2715        wake_up_interruptible(&info->event_wait_q);
2716
2717        del_timer(&info->tx_timer);
2718        del_timer(&info->status_timer);
2719
2720        kfree(info->tx_buf);
2721        info->tx_buf = NULL;
2722
2723        spin_lock_irqsave(&info->lock,flags);
2724
2725        reset_port(info);
2726
2727        if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2728                info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2729                set_signals(info);
2730        }
2731
2732        spin_unlock_irqrestore(&info->lock,flags);
2733
2734        if (info->port.tty)
2735                set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2736
2737        info->port.flags &= ~ASYNC_INITIALIZED;
2738}
2739
2740static void program_hw(SLMP_INFO *info)
2741{
2742        unsigned long flags;
2743
2744        spin_lock_irqsave(&info->lock,flags);
2745
2746        rx_stop(info);
2747        tx_stop(info);
2748
2749        info->tx_count = info->tx_put = info->tx_get = 0;
2750
2751        if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2752                hdlc_mode(info);
2753        else
2754                async_mode(info);
2755
2756        set_signals(info);
2757
2758        info->dcd_chkcount = 0;
2759        info->cts_chkcount = 0;
2760        info->ri_chkcount = 0;
2761        info->dsr_chkcount = 0;
2762
2763        info->ie1_value |= (CDCD|CCTS);
2764        write_reg(info, IE1, info->ie1_value);
2765
2766        get_signals(info);
2767
2768        if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2769                rx_start(info);
2770
2771        spin_unlock_irqrestore(&info->lock,flags);
2772}
2773
2774/* Reconfigure adapter based on new parameters
2775 */
2776static void change_params(SLMP_INFO *info)
2777{
2778        unsigned cflag;
2779        int bits_per_char;
2780
2781        if (!info->port.tty || !info->port.tty->termios)
2782                return;
2783
2784        if (debug_level >= DEBUG_LEVEL_INFO)
2785                printk("%s(%d):%s change_params()\n",
2786                         __FILE__,__LINE__, info->device_name );
2787
2788        cflag = info->port.tty->termios->c_cflag;
2789
2790        /* if B0 rate (hangup) specified then negate DTR and RTS */
2791        /* otherwise assert DTR and RTS */
2792        if (cflag & CBAUD)
2793                info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2794        else
2795                info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2796
2797        /* byte size and parity */
2798
2799        switch (cflag & CSIZE) {
2800              case CS5: info->params.data_bits = 5; break;
2801              case CS6: info->params.data_bits = 6; break;
2802              case CS7: info->params.data_bits = 7; break;
2803              case CS8: info->params.data_bits = 8; break;
2804              /* Never happens, but GCC is too dumb to figure it out */
2805              default:  info->params.data_bits = 7; break;
2806              }
2807
2808        if (cflag & CSTOPB)
2809                info->params.stop_bits = 2;
2810        else
2811                info->params.stop_bits = 1;
2812
2813        info->params.parity = ASYNC_PARITY_NONE;
2814        if (cflag & PARENB) {
2815                if (cflag & PARODD)
2816                        info->params.parity = ASYNC_PARITY_ODD;
2817                else
2818                        info->params.parity = ASYNC_PARITY_EVEN;
2819#ifdef CMSPAR
2820                if (cflag & CMSPAR)
2821                        info->params.parity = ASYNC_PARITY_SPACE;
2822#endif
2823        }
2824
2825        /* calculate number of jiffies to transmit a full
2826         * FIFO (32 bytes) at specified data rate
2827         */
2828        bits_per_char = info->params.data_bits +
2829                        info->params.stop_bits + 1;
2830
2831        /* if port data rate is set to 460800 or less then
2832         * allow tty settings to override, otherwise keep the
2833         * current data rate.
2834         */
2835        if (info->params.data_rate <= 460800) {
2836                info->params.data_rate = tty_get_baud_rate(info->port.tty);
2837        }
2838
2839        if ( info->params.data_rate ) {
2840                info->timeout = (32*HZ*bits_per_char) /
2841                                info->params.data_rate;
2842        }
2843        info->timeout += HZ/50;         /* Add .02 seconds of slop */
2844
2845        if (cflag & CRTSCTS)
2846                info->port.flags |= ASYNC_CTS_FLOW;
2847        else
2848                info->port.flags &= ~ASYNC_CTS_FLOW;
2849
2850        if (cflag & CLOCAL)
2851                info->port.flags &= ~ASYNC_CHECK_CD;
2852        else
2853                info->port.flags |= ASYNC_CHECK_CD;
2854
2855        /* process tty input control flags */
2856
2857        info->read_status_mask2 = OVRN;
2858        if (I_INPCK(info->port.tty))
2859                info->read_status_mask2 |= PE | FRME;
2860        if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2861                info->read_status_mask1 |= BRKD;
2862        if (I_IGNPAR(info->port.tty))
2863                info->ignore_status_mask2 |= PE | FRME;
2864        if (I_IGNBRK(info->port.tty)) {
2865                info->ignore_status_mask1 |= BRKD;
2866                /* If ignoring parity and break indicators, ignore
2867                 * overruns too.  (For real raw support).
2868                 */
2869                if (I_IGNPAR(info->port.tty))
2870                        info->ignore_status_mask2 |= OVRN;
2871        }
2872
2873        program_hw(info);
2874}
2875
2876static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2877{
2878        int err;
2879
2880        if (debug_level >= DEBUG_LEVEL_INFO)
2881                printk("%s(%d):%s get_params()\n",
2882                         __FILE__,__LINE__, info->device_name);
2883
2884        if (!user_icount) {
2885                memset(&info->icount, 0, sizeof(info->icount));
2886        } else {
2887                COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2888                if (err)
2889                        return -EFAULT;
2890        }
2891
2892        return 0;
2893}
2894
2895static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2896{
2897        int err;
2898        if (debug_level >= DEBUG_LEVEL_INFO)
2899                printk("%s(%d):%s get_params()\n",
2900                         __FILE__,__LINE__, info->device_name);
2901
2902        COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2903        if (err) {
2904                if ( debug_level >= DEBUG_LEVEL_INFO )
2905                        printk( "%s(%d):%s get_params() user buffer copy failed\n",
2906                                __FILE__,__LINE__,info->device_name);
2907                return -EFAULT;
2908        }
2909
2910        return 0;
2911}
2912
2913static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2914{
2915        unsigned long flags;
2916        MGSL_PARAMS tmp_params;
2917        int err;
2918
2919        if (debug_level >= DEBUG_LEVEL_INFO)
2920                printk("%s(%d):%s set_params\n",
2921                        __FILE__,__LINE__,info->device_name );
2922        COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2923        if (err) {
2924                if ( debug_level >= DEBUG_LEVEL_INFO )
2925                        printk( "%s(%d):%s set_params() user buffer copy failed\n",
2926                                __FILE__,__LINE__,info->device_name);
2927                return -EFAULT;
2928        }
2929
2930        spin_lock_irqsave(&info->lock,flags);
2931        memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2932        spin_unlock_irqrestore(&info->lock,flags);
2933
2934        change_params(info);
2935
2936        return 0;
2937}
2938
2939static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2940{
2941        int err;
2942
2943        if (debug_level >= DEBUG_LEVEL_INFO)
2944                printk("%s(%d):%s get_txidle()=%d\n",
2945                         __FILE__,__LINE__, info->device_name, info->idle_mode);
2946
2947        COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2948        if (err) {
2949                if ( debug_level >= DEBUG_LEVEL_INFO )
2950                        printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2951                                __FILE__,__LINE__,info->device_name);
2952                return -EFAULT;
2953        }
2954
2955        return 0;
2956}
2957
2958static int set_txidle(SLMP_INFO * info, int idle_mode)
2959{
2960        unsigned long flags;
2961
2962        if (debug_level >= DEBUG_LEVEL_INFO)
2963                printk("%s(%d):%s set_txidle(%d)\n",
2964                        __FILE__,__LINE__,info->device_name, idle_mode );
2965
2966        spin_lock_irqsave(&info->lock,flags);
2967        info->idle_mode = idle_mode;
2968        tx_set_idle( info );
2969        spin_unlock_irqrestore(&info->lock,flags);
2970        return 0;
2971}
2972
2973static int tx_enable(SLMP_INFO * info, int enable)
2974{
2975        unsigned long flags;
2976
2977        if (debug_level >= DEBUG_LEVEL_INFO)
2978                printk("%s(%d):%s tx_enable(%d)\n",
2979                        __FILE__,__LINE__,info->device_name, enable);
2980
2981        spin_lock_irqsave(&info->lock,flags);
2982        if ( enable ) {
2983                if ( !info->tx_enabled ) {
2984                        tx_start(info);
2985                }
2986        } else {
2987                if ( info->tx_enabled )
2988                        tx_stop(info);
2989        }
2990        spin_unlock_irqrestore(&info->lock,flags);
2991        return 0;
2992}
2993
2994/* abort send HDLC frame
2995 */
2996static int tx_abort(SLMP_INFO * info)
2997{
2998        unsigned long flags;
2999
3000        if (debug_level >= DEBUG_LEVEL_INFO)
3001                printk("%s(%d):%s tx_abort()\n",
3002                        __FILE__,__LINE__,info->device_name);
3003
3004        spin_lock_irqsave(&info->lock,flags);
3005        if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3006                info->ie1_value &= ~UDRN;
3007                info->ie1_value |= IDLE;
3008                write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3009                write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3010
3011                write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3012                write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3013
3014                write_reg(info, CMD, TXABORT);
3015        }
3016        spin_unlock_irqrestore(&info->lock,flags);
3017        return 0;
3018}
3019
3020static int rx_enable(SLMP_INFO * info, int enable)
3021{
3022        unsigned long flags;
3023
3024        if (debug_level >= DEBUG_LEVEL_INFO)
3025                printk("%s(%d):%s rx_enable(%d)\n",
3026                        __FILE__,__LINE__,info->device_name,enable);
3027
3028        spin_lock_irqsave(&info->lock,flags);
3029        if ( enable ) {
3030                if ( !info->rx_enabled )
3031                        rx_start(info);
3032        } else {
3033                if ( info->rx_enabled )
3034                        rx_stop(info);
3035        }
3036        spin_unlock_irqrestore(&info->lock,flags);
3037        return 0;
3038}
3039
3040/* wait for specified event to occur
3041 */
3042static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3043{
3044        unsigned long flags;
3045        int s;
3046        int rc=0;
3047        struct mgsl_icount cprev, cnow;
3048        int events;
3049        int mask;
3050        struct  _input_signal_events oldsigs, newsigs;
3051        DECLARE_WAITQUEUE(wait, current);
3052
3053        COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3054        if (rc) {
3055                return  -EFAULT;
3056        }
3057
3058        if (debug_level >= DEBUG_LEVEL_INFO)
3059                printk("%s(%d):%s wait_mgsl_event(%d)\n",
3060                        __FILE__,__LINE__,info->device_name,mask);
3061
3062        spin_lock_irqsave(&info->lock,flags);
3063
3064        /* return immediately if state matches requested events */
3065        get_signals(info);
3066        s = info->serial_signals;
3067
3068        events = mask &
3069                ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3070                  ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3071                  ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3072                  ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3073        if (events) {
3074                spin_unlock_irqrestore(&info->lock,flags);
3075                goto exit;
3076        }
3077
3078        /* save current irq counts */
3079        cprev = info->icount;
3080        oldsigs = info->input_signal_events;
3081
3082        /* enable hunt and idle irqs if needed */
3083        if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3084                unsigned char oldval = info->ie1_value;
3085                unsigned char newval = oldval +
3086                         (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3087                         (mask & MgslEvent_IdleReceived ? IDLD:0);
3088                if ( oldval != newval ) {
3089                        info->ie1_value = newval;
3090                        write_reg(info, IE1, info->ie1_value);
3091                }
3092        }
3093
3094        set_current_state(TASK_INTERRUPTIBLE);
3095        add_wait_queue(&info->event_wait_q, &wait);
3096
3097        spin_unlock_irqrestore(&info->lock,flags);
3098
3099        for(;;) {
3100                schedule();
3101                if (signal_pending(current)) {
3102                        rc = -ERESTARTSYS;
3103                        break;
3104                }
3105
3106                /* get current irq counts */
3107                spin_lock_irqsave(&info->lock,flags);
3108                cnow = info->icount;
3109                newsigs = info->input_signal_events;
3110                set_current_state(TASK_INTERRUPTIBLE);
3111                spin_unlock_irqrestore(&info->lock,flags);
3112
3113                /* if no change, wait aborted for some reason */
3114                if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3115                    newsigs.dsr_down == oldsigs.dsr_down &&
3116                    newsigs.dcd_up   == oldsigs.dcd_up   &&
3117                    newsigs.dcd_down == oldsigs.dcd_down &&
3118                    newsigs.cts_up   == oldsigs.cts_up   &&
3119                    newsigs.cts_down == oldsigs.cts_down &&
3120                    newsigs.ri_up    == oldsigs.ri_up    &&
3121                    newsigs.ri_down  == oldsigs.ri_down  &&
3122                    cnow.exithunt    == cprev.exithunt   &&
3123                    cnow.rxidle      == cprev.rxidle) {
3124                        rc = -EIO;
3125                        break;
3126                }
3127
3128                events = mask &
3129                        ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3130                          (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3131                          (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3132                          (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3133                          (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3134                          (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3135                          (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3136                          (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3137                          (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3138                          (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3139                if (events)
3140                        break;
3141
3142                cprev = cnow;
3143                oldsigs = newsigs;
3144        }
3145
3146        remove_wait_queue(&info->event_wait_q, &wait);
3147        set_current_state(TASK_RUNNING);
3148
3149
3150        if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3151                spin_lock_irqsave(&info->lock,flags);
3152                if (!waitqueue_active(&info->event_wait_q)) {
3153                        /* disable enable exit hunt mode/idle rcvd IRQs */
3154                        info->ie1_value &= ~(FLGD|IDLD);
3155                        write_reg(info, IE1, info->ie1_value);
3156                }
3157                spin_unlock_irqrestore(&info->lock,flags);
3158        }
3159exit:
3160        if ( rc == 0 )
3161                PUT_USER(rc, events, mask_ptr);
3162
3163        return rc;
3164}
3165
3166static int modem_input_wait(SLMP_INFO *info,int arg)
3167{
3168        unsigned long flags;
3169        int rc;
3170        struct mgsl_icount cprev, cnow;
3171        DECLARE_WAITQUEUE(wait, current);
3172
3173        /* save current irq counts */
3174        spin_lock_irqsave(&info->lock,flags);
3175        cprev = info->icount;
3176        add_wait_queue(&info->status_event_wait_q, &wait);
3177        set_current_state(TASK_INTERRUPTIBLE);
3178        spin_unlock_irqrestore(&info->lock,flags);
3179
3180        for(;;) {
3181                schedule();
3182                if (signal_pending(current)) {
3183                        rc = -ERESTARTSYS;
3184                        break;
3185                }
3186
3187                /* get new irq counts */
3188                spin_lock_irqsave(&info->lock,flags);
3189                cnow = info->icount;
3190                set_current_state(TASK_INTERRUPTIBLE);
3191                spin_unlock_irqrestore(&info->lock,flags);
3192
3193                /* if no change, wait aborted for some reason */
3194                if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3195                    cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3196                        rc = -EIO;
3197                        break;
3198                }
3199
3200                /* check for change in caller specified modem input */
3201                if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3202                    (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3203                    (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3204                    (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3205                        rc = 0;
3206                        break;
3207                }
3208
3209                cprev = cnow;
3210        }
3211        remove_wait_queue(&info->status_event_wait_q, &wait);
3212        set_current_state(TASK_RUNNING);
3213        return rc;
3214}
3215
3216/* return the state of the serial control and status signals
3217 */
3218static int tiocmget(struct tty_struct *tty, struct file *file)
3219{
3220        SLMP_INFO *info = tty->driver_data;
3221        unsigned int result;
3222        unsigned long flags;
3223
3224        spin_lock_irqsave(&info->lock,flags);
3225        get_signals(info);
3226        spin_unlock_irqrestore(&info->lock,flags);
3227
3228        result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3229                ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3230                ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3231                ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3232                ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3233                ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3234
3235        if (debug_level >= DEBUG_LEVEL_INFO)
3236                printk("%s(%d):%s tiocmget() value=%08X\n",
3237                         __FILE__,__LINE__, info->device_name, result );
3238        return result;
3239}
3240
3241/* set modem control signals (DTR/RTS)
3242 */
3243static int tiocmset(struct tty_struct *tty, struct file *file,
3244                    unsigned int set, unsigned int clear)
3245{
3246        SLMP_INFO *info = tty->driver_data;
3247        unsigned long flags;
3248
3249        if (debug_level >= DEBUG_LEVEL_INFO)
3250                printk("%s(%d):%s tiocmset(%x,%x)\n",
3251                        __FILE__,__LINE__,info->device_name, set, clear);
3252
3253        if (set & TIOCM_RTS)
3254                info->serial_signals |= SerialSignal_RTS;
3255        if (set & TIOCM_DTR)
3256                info->serial_signals |= SerialSignal_DTR;
3257        if (clear & TIOCM_RTS)
3258                info->serial_signals &= ~SerialSignal_RTS;
3259        if (clear & TIOCM_DTR)
3260                info->serial_signals &= ~SerialSignal_DTR;
3261
3262        spin_lock_irqsave(&info->lock,flags);
3263        set_signals(info);
3264        spin_unlock_irqrestore(&info->lock,flags);
3265
3266        return 0;
3267}
3268
3269static int carrier_raised(struct tty_port *port)
3270{
3271        SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3272        unsigned long flags;
3273
3274        spin_lock_irqsave(&info->lock,flags);
3275        get_signals(info);
3276        spin_unlock_irqrestore(&info->lock,flags);
3277
3278        return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3279}
3280
3281static void dtr_rts(struct tty_port *port, int on)
3282{
3283        SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3284        unsigned long flags;
3285
3286        spin_lock_irqsave(&info->lock,flags);
3287        if (on)
3288                info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3289        else
3290                info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3291        set_signals(info);
3292        spin_unlock_irqrestore(&info->lock,flags);
3293}
3294
3295/* Block the current process until the specified port is ready to open.
3296 */
3297static int block_til_ready(struct tty_struct *tty, struct file *filp,
3298                           SLMP_INFO *info)
3299{
3300        DECLARE_WAITQUEUE(wait, current);
3301        int             retval;
3302        bool            do_clocal = false;
3303        bool            extra_count = false;
3304        unsigned long   flags;
3305        int             cd;
3306        struct tty_port *port = &info->port;
3307
3308        if (debug_level >= DEBUG_LEVEL_INFO)
3309                printk("%s(%d):%s block_til_ready()\n",
3310                         __FILE__,__LINE__, tty->driver->name );
3311
3312        if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3313                /* nonblock mode is set or port is not enabled */
3314                /* just verify that callout device is not active */
3315                port->flags |= ASYNC_NORMAL_ACTIVE;
3316                return 0;
3317        }
3318
3319        if (tty->termios->c_cflag & CLOCAL)
3320                do_clocal = true;
3321
3322        /* Wait for carrier detect and the line to become
3323         * free (i.e., not in use by the callout).  While we are in
3324         * this loop, port->count is dropped by one, so that
3325         * close() knows when to free things.  We restore it upon
3326         * exit, either normal or abnormal.
3327         */
3328
3329        retval = 0;
3330        add_wait_queue(&port->open_wait, &wait);
3331
3332        if (debug_level >= DEBUG_LEVEL_INFO)
3333                printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3334                         __FILE__,__LINE__, tty->driver->name, port->count );
3335
3336        spin_lock_irqsave(&info->lock, flags);
3337        if (!tty_hung_up_p(filp)) {
3338                extra_count = true;
3339                port->count--;
3340        }
3341        spin_unlock_irqrestore(&info->lock, flags);
3342        port->blocked_open++;
3343
3344        while (1) {
3345                if (tty->termios->c_cflag & CBAUD)
3346                        tty_port_raise_dtr_rts(port);
3347
3348                set_current_state(TASK_INTERRUPTIBLE);
3349
3350                if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3351                        retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3352                                        -EAGAIN : -ERESTARTSYS;
3353                        break;
3354                }
3355
3356                cd = tty_port_carrier_raised(port);
3357
3358                if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3359                        break;
3360
3361                if (signal_pending(current)) {
3362                        retval = -ERESTARTSYS;
3363                        break;
3364                }
3365
3366                if (debug_level >= DEBUG_LEVEL_INFO)
3367                        printk("%s(%d):%s block_til_ready() count=%d\n",
3368                                 __FILE__,__LINE__, tty->driver->name, port->count );
3369
3370                schedule();
3371        }
3372
3373        set_current_state(TASK_RUNNING);
3374        remove_wait_queue(&port->open_wait, &wait);
3375
3376        if (extra_count)
3377                port->count++;
3378        port->blocked_open--;
3379
3380        if (debug_level >= DEBUG_LEVEL_INFO)
3381                printk("%s(%d):%s block_til_ready() after, count=%d\n",
3382                         __FILE__,__LINE__, tty->driver->name, port->count );
3383
3384        if (!retval)
3385                port->flags |= ASYNC_NORMAL_ACTIVE;
3386
3387        return retval;
3388}
3389
3390static int alloc_dma_bufs(SLMP_INFO *info)
3391{
3392        unsigned short BuffersPerFrame;
3393        unsigned short BufferCount;
3394
3395        // Force allocation to start at 64K boundary for each port.
3396        // This is necessary because *all* buffer descriptors for a port
3397        // *must* be in the same 64K block. All descriptors on a port
3398        // share a common 'base' address (upper 8 bits of 24 bits) programmed
3399        // into the CBP register.
3400        info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3401
3402        /* Calculate the number of DMA buffers necessary to hold the */
3403        /* largest allowable frame size. Note: If the max frame size is */
3404        /* not an even multiple of the DMA buffer size then we need to */
3405        /* round the buffer count per frame up one. */
3406
3407        BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3408        if ( info->max_frame_size % SCABUFSIZE )
3409                BuffersPerFrame++;
3410
3411        /* calculate total number of data buffers (SCABUFSIZE) possible
3412         * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3413         * for the descriptor list (BUFFERLISTSIZE).
3414         */
3415        BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3416
3417        /* limit number of buffers to maximum amount of descriptors */
3418        if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3419                BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3420
3421        /* use enough buffers to transmit one max size frame */
3422        info->tx_buf_count = BuffersPerFrame + 1;
3423
3424        /* never use more than half the available buffers for transmit */
3425        if (info->tx_buf_count > (BufferCount/2))
3426                info->tx_buf_count = BufferCount/2;
3427
3428        if (info->tx_buf_count > SCAMAXDESC)
3429                info->tx_buf_count = SCAMAXDESC;
3430
3431        /* use remaining buffers for receive */
3432        info->rx_buf_count = BufferCount - info->tx_buf_count;
3433
3434        if (info->rx_buf_count > SCAMAXDESC)
3435                info->rx_buf_count = SCAMAXDESC;
3436
3437        if ( debug_level >= DEBUG_LEVEL_INFO )
3438                printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3439                        __FILE__,__LINE__, info->device_name,
3440                        info->tx_buf_count,info->rx_buf_count);
3441
3442        if ( alloc_buf_list( info ) < 0 ||
3443                alloc_frame_bufs(info,
3444                                        info->rx_buf_list,
3445                                        info->rx_buf_list_ex,
3446                                        info->rx_buf_count) < 0 ||
3447                alloc_frame_bufs(info,
3448                                        info->tx_buf_list,
3449                                        info->tx_buf_list_ex,
3450                                        info->tx_buf_count) < 0 ||
3451                alloc_tmp_rx_buf(info) < 0 ) {
3452                printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3453                        __FILE__,__LINE__, info->device_name);
3454                return -ENOMEM;
3455        }
3456
3457        rx_reset_buffers( info );
3458
3459        return 0;
3460}
3461
3462/* Allocate DMA buffers for the transmit and receive descriptor lists.
3463 */
3464static int alloc_buf_list(SLMP_INFO *info)
3465{
3466        unsigned int i;
3467
3468        /* build list in adapter shared memory */
3469        info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3470        info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3471        info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3472
3473        memset(info->buffer_list, 0, BUFFERLISTSIZE);
3474
3475        /* Save virtual address pointers to the receive and */
3476        /* transmit buffer lists. (Receive 1st). These pointers will */
3477        /* be used by the processor to access the lists. */
3478        info->rx_buf_list = (SCADESC *)info->buffer_list;
3479
3480        info->tx_buf_list = (SCADESC *)info->buffer_list;
3481        info->tx_buf_list += info->rx_buf_count;
3482
3483        /* Build links for circular buffer entry lists (tx and rx)
3484         *
3485         * Note: links are physical addresses read by the SCA device
3486         * to determine the next buffer entry to use.
3487         */
3488
3489        for ( i = 0; i < info->rx_buf_count; i++ ) {
3490                /* calculate and store physical address of this buffer entry */
3491                info->rx_buf_list_ex[i].phys_entry =
3492                        info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3493
3494                /* calculate and store physical address of */
3495                /* next entry in cirular list of entries */
3496                info->rx_buf_list[i].next = info->buffer_list_phys;
3497                if ( i < info->rx_buf_count - 1 )
3498                        info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3499
3500                info->rx_buf_list[i].length = SCABUFSIZE;
3501        }
3502
3503        for ( i = 0; i < info->tx_buf_count; i++ ) {
3504                /* calculate and store physical address of this buffer entry */
3505                info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3506                        ((info->rx_buf_count + i) * sizeof(SCADESC));
3507
3508                /* calculate and store physical address of */
3509                /* next entry in cirular list of entries */
3510
3511                info->tx_buf_list[i].next = info->buffer_list_phys +
3512                        info->rx_buf_count * sizeof(SCADESC);
3513
3514                if ( i < info->tx_buf_count - 1 )
3515                        info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3516        }
3517
3518        return 0;
3519}
3520
3521/* Allocate the frame DMA buffers used by the specified buffer list.
3522 */
3523static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3524{
3525        int i;
3526        unsigned long phys_addr;
3527
3528        for ( i = 0; i < count; i++ ) {
3529                buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3530                phys_addr = info->port_array[0]->last_mem_alloc;
3531                info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3532
3533                buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3534                buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3535        }
3536
3537        return 0;
3538}
3539
3540static void free_dma_bufs(SLMP_INFO *info)
3541{
3542        info->buffer_list = NULL;
3543        info->rx_buf_list = NULL;
3544        info->tx_buf_list = NULL;
3545}
3546
3547/* allocate buffer large enough to hold max_frame_size.
3548 * This buffer is used to pass an assembled frame to the line discipline.
3549 */
3550static int alloc_tmp_rx_buf(SLMP_INFO *info)
3551{
3552        info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3553        if (info->tmp_rx_buf == NULL)
3554                return -ENOMEM;
3555        return 0;
3556}
3557
3558static void free_tmp_rx_buf(SLMP_INFO *info)
3559{
3560        kfree(info->tmp_rx_buf);
3561        info->tmp_rx_buf = NULL;
3562}
3563
3564static int claim_resources(SLMP_INFO *info)
3565{
3566        if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3567                printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3568                        __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3569                info->init_error = DiagStatus_AddressConflict;
3570                goto errout;
3571        }
3572        else
3573                info->shared_mem_requested = true;
3574
3575        if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3576                printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3577                        __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3578                info->init_error = DiagStatus_AddressConflict;
3579                goto errout;
3580        }
3581        else
3582                info->lcr_mem_requested = true;
3583
3584        if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3585                printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3586                        __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3587                info->init_error = DiagStatus_AddressConflict;
3588                goto errout;
3589        }
3590        else
3591                info->sca_base_requested = true;
3592
3593        if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3594                printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3595                        __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3596                info->init_error = DiagStatus_AddressConflict;
3597                goto errout;
3598        }
3599        else
3600                info->sca_statctrl_requested = true;
3601
3602        info->memory_base = ioremap_nocache(info->phys_memory_base,
3603                                                                SCA_MEM_SIZE);
3604        if (!info->memory_base) {
3605                printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3606                        __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3607                info->init_error = DiagStatus_CantAssignPciResources;
3608                goto errout;
3609        }
3610
3611        info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3612        if (!info->lcr_base) {
3613                printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3614                        __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3615                info->init_error = DiagStatus_CantAssignPciResources;
3616                goto errout;
3617        }
3618        info->lcr_base += info->lcr_offset;
3619
3620        info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3621        if (!info->sca_base) {
3622                printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3623                        __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3624                info->init_error = DiagStatus_CantAssignPciResources;
3625                goto errout;
3626        }
3627        info->sca_base += info->sca_offset;
3628
3629        info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3630                                                                PAGE_SIZE);
3631        if (!info->statctrl_base) {
3632                printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3633                        __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3634                info->init_error = DiagStatus_CantAssignPciResources;
3635                goto errout;
3636        }
3637        info->statctrl_base += info->statctrl_offset;
3638
3639        if ( !memory_test(info) ) {
3640                printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3641                        __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3642                info->init_error = DiagStatus_MemoryError;
3643                goto errout;
3644        }
3645
3646        return 0;
3647
3648errout:
3649        release_resources( info );
3650        return -ENODEV;
3651}
3652
3653static void release_resources(SLMP_INFO *info)
3654{
3655        if ( debug_level >= DEBUG_LEVEL_INFO )
3656                printk( "%s(%d):%s release_resources() entry\n",
3657                        __FILE__,__LINE__,info->device_name );
3658
3659        if ( info->irq_requested ) {
3660                free_irq(info->irq_level, info);
3661                info->irq_requested = false;
3662        }
3663
3664        if ( info->shared_mem_requested ) {
3665                release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3666                info->shared_mem_requested = false;
3667        }
3668        if ( info->lcr_mem_requested ) {
3669                release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3670                info->lcr_mem_requested = false;
3671        }
3672        if ( info->sca_base_requested ) {
3673                release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3674                info->sca_base_requested = false;
3675        }
3676        if ( info->sca_statctrl_requested ) {
3677                release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3678                info->sca_statctrl_requested = false;
3679        }
3680
3681        if (info->memory_base){
3682                iounmap(info->memory_base);
3683                info->memory_base = NULL;
3684        }
3685
3686        if (info->sca_base) {
3687                iounmap(info->sca_base - info->sca_offset);
3688                info->sca_base=NULL;
3689        }
3690
3691        if (info->statctrl_base) {
3692                iounmap(info->statctrl_base - info->statctrl_offset);
3693                info->statctrl_base=NULL;
3694        }
3695
3696        if (info->lcr_base){
3697                iounmap(info->lcr_base - info->lcr_offset);
3698                info->lcr_base = NULL;
3699        }
3700
3701        if ( debug_level >= DEBUG_LEVEL_INFO )
3702                printk( "%s(%d):%s release_resources() exit\n",
3703                        __FILE__,__LINE__,info->device_name );
3704}
3705
3706/* Add the specified device instance data structure to the
3707 * global linked list of devices and increment the device count.
3708 */
3709static void add_device(SLMP_INFO *info)
3710{
3711        info->next_device = NULL;
3712        info->line = synclinkmp_device_count;
3713        sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3714
3715        if (info->line < MAX_DEVICES) {
3716                if (maxframe[info->line])
3717                        info->max_frame_size = maxframe[info->line];
3718        }
3719
3720        synclinkmp_device_count++;
3721
3722        if ( !synclinkmp_device_list )
3723                synclinkmp_device_list = info;
3724        else {
3725                SLMP_INFO *current_dev = synclinkmp_device_list;
3726                while( current_dev->next_device )
3727                        current_dev = current_dev->next_device;
3728                current_dev->next_device = info;
3729        }
3730
3731        if ( info->max_frame_size < 4096 )
3732                info->max_frame_size = 4096;
3733        else if ( info->max_frame_size > 65535 )
3734                info->max_frame_size = 65535;
3735
3736        printk( "SyncLink MultiPort %s: "
3737                "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3738                info->device_name,
3739                info->phys_sca_base,
3740                info->phys_memory_base,
3741                info->phys_statctrl_base,
3742                info->phys_lcr_base,
3743                info->irq_level,
3744                info->max_frame_size );
3745
3746#if SYNCLINK_GENERIC_HDLC
3747        hdlcdev_init(info);
3748#endif
3749}
3750
3751static const struct tty_port_operations port_ops = {
3752        .carrier_raised = carrier_raised,
3753        .dtr_rts = dtr_rts,
3754};
3755
3756/* Allocate and initialize a device instance structure
3757 *
3758 * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3759 */
3760static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3761{
3762        SLMP_INFO *info;
3763
3764        info = kzalloc(sizeof(SLMP_INFO),
3765                 GFP_KERNEL);
3766
3767        if (!info) {
3768                printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3769                        __FILE__,__LINE__, adapter_num, port_num);
3770        } else {
3771                tty_port_init(&info->port);
3772                info->port.ops = &port_ops;
3773                info->magic = MGSL_MAGIC;
3774                INIT_WORK(&info->task, bh_handler);
3775                info->max_frame_size = 4096;
3776                info->port.close_delay = 5*HZ/10;
3777                info->port.closing_wait = 30*HZ;
3778                init_waitqueue_head(&info->status_event_wait_q);
3779                init_waitqueue_head(&info->event_wait_q);
3780                spin_lock_init(&info->netlock);
3781                memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3782                info->idle_mode = HDLC_TXIDLE_FLAGS;
3783                info->adapter_num = adapter_num;
3784                info->port_num = port_num;
3785
3786                /* Copy configuration info to device instance data */
3787                info->irq_level = pdev->irq;
3788                info->phys_lcr_base = pci_resource_start(pdev,0);
3789                info->phys_sca_base = pci_resource_start(pdev,2);
3790                info->phys_memory_base = pci_resource_start(pdev,3);
3791                info->phys_statctrl_base = pci_resource_start(pdev,4);
3792
3793                /* Because veremap only works on page boundaries we must map
3794                 * a larger area than is actually implemented for the LCR
3795                 * memory range. We map a full page starting at the page boundary.
3796                 */
3797                info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3798                info->phys_lcr_base &= ~(PAGE_SIZE-1);
3799
3800                info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3801                info->phys_sca_base &= ~(PAGE_SIZE-1);
3802
3803                info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3804                info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3805
3806                info->bus_type = MGSL_BUS_TYPE_PCI;
3807                info->irq_flags = IRQF_SHARED;
3808
3809                setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3810                setup_timer(&info->status_timer, status_timeout,
3811                                (unsigned long)info);
3812
3813                /* Store the PCI9050 misc control register value because a flaw
3814                 * in the PCI9050 prevents LCR registers from being read if
3815                 * BIOS assigns an LCR base address with bit 7 set.
3816                 *
3817                 * Only the misc control register is accessed for which only
3818                 * write access is needed, so set an initial value and change
3819                 * bits to the device instance data as we write the value
3820                 * to the actual misc control register.
3821                 */
3822                info->misc_ctrl_value = 0x087e4546;
3823
3824                /* initial port state is unknown - if startup errors
3825                 * occur, init_error will be set to indicate the
3826                 * problem. Once the port is fully initialized,
3827                 * this value will be set to 0 to indicate the
3828                 * port is available.
3829                 */
3830                info->init_error = -1;
3831        }
3832
3833        return info;
3834}
3835
3836static void device_init(int adapter_num, struct pci_dev *pdev)
3837{
3838        SLMP_INFO *port_array[SCA_MAX_PORTS];
3839        int port;
3840
3841        /* allocate device instances for up to SCA_MAX_PORTS devices */
3842        for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3843                port_array[port] = alloc_dev(adapter_num,port,pdev);
3844                if( port_array[port] == NULL ) {
3845                        for ( --port; port >= 0; --port )
3846                                kfree(port_array[port]);
3847                        return;
3848                }
3849        }
3850
3851        /* give copy of port_array to all ports and add to device list  */
3852        for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3853                memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3854                add_device( port_array[port] );
3855                spin_lock_init(&port_array[port]->lock);
3856        }
3857
3858        /* Allocate and claim adapter resources */
3859        if ( !claim_resources(port_array[0]) ) {
3860
3861                alloc_dma_bufs(port_array[0]);
3862
3863                /* copy resource information from first port to others */
3864                for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3865                        port_array[port]->lock  = port_array[0]->lock;
3866                        port_array[port]->irq_level     = port_array[0]->irq_level;
3867                        port_array[port]->memory_base   = port_array[0]->memory_base;
3868                        port_array[port]->sca_base      = port_array[0]->sca_base;
3869                        port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3870                        port_array[port]->lcr_base      = port_array[0]->lcr_base;
3871                        alloc_dma_bufs(port_array[port]);
3872                }
3873
3874                if ( request_irq(port_array[0]->irq_level,
3875                                        synclinkmp_interrupt,
3876                                        port_array[0]->irq_flags,
3877                                        port_array[0]->device_name,
3878                                        port_array[0]) < 0 ) {
3879                        printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3880                                __FILE__,__LINE__,
3881                                port_array[0]->device_name,
3882                                port_array[0]->irq_level );
3883                }
3884                else {
3885                        port_array[0]->irq_requested = true;
3886                        adapter_test(port_array[0]);
3887                }
3888        }
3889}
3890
3891static const struct tty_operations ops = {
3892        .open = open,
3893        .close = close,
3894        .write = write,
3895        .put_char = put_char,
3896        .flush_chars = flush_chars,
3897        .write_room = write_room,
3898        .chars_in_buffer = chars_in_buffer,
3899        .flush_buffer = flush_buffer,
3900        .ioctl = ioctl,
3901        .throttle = throttle,
3902        .unthrottle = unthrottle,
3903        .send_xchar = send_xchar,
3904        .break_ctl = set_break,
3905        .wait_until_sent = wait_until_sent,
3906        .set_termios = set_termios,
3907        .stop = tx_hold,
3908        .start = tx_release,
3909        .hangup = hangup,
3910        .tiocmget = tiocmget,
3911        .tiocmset = tiocmset,
3912        .proc_fops = &synclinkmp_proc_fops,
3913};
3914
3915
3916static void synclinkmp_cleanup(void)
3917{
3918        int rc;
3919        SLMP_INFO *info;
3920        SLMP_INFO *tmp;
3921
3922        printk("Unloading %s %s\n", driver_name, driver_version);
3923
3924        if (serial_driver) {
3925                if ((rc = tty_unregister_driver(serial_driver)))
3926                        printk("%s(%d) failed to unregister tty driver err=%d\n",
3927                               __FILE__,__LINE__,rc);
3928                put_tty_driver(serial_driver);
3929        }
3930
3931        /* reset devices */
3932        info = synclinkmp_device_list;
3933        while(info) {
3934                reset_port(info);
3935                info = info->next_device;
3936        }
3937
3938        /* release devices */
3939        info = synclinkmp_device_list;
3940        while(info) {
3941#if SYNCLINK_GENERIC_HDLC
3942                hdlcdev_exit(info);
3943#endif
3944                free_dma_bufs(info);
3945                free_tmp_rx_buf(info);
3946                if ( info->port_num == 0 ) {
3947                        if (info->sca_base)
3948                                write_reg(info, LPR, 1); /* set low power mode */
3949                        release_resources(info);
3950                }
3951                tmp = info;
3952                info = info->next_device;
3953                kfree(tmp);
3954        }
3955
3956        pci_unregister_driver(&synclinkmp_pci_driver);
3957}
3958
3959/* Driver initialization entry point.
3960 */
3961
3962static int __init synclinkmp_init(void)
3963{
3964        int rc;
3965
3966        if (break_on_load) {
3967                synclinkmp_get_text_ptr();
3968                BREAKPOINT();
3969        }
3970
3971        printk("%s %s\n", driver_name, driver_version);
3972
3973        if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3974                printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3975                return rc;
3976        }
3977
3978        serial_driver = alloc_tty_driver(128);
3979        if (!serial_driver) {
3980                rc = -ENOMEM;
3981                goto error;
3982        }
3983
3984        /* Initialize the tty_driver structure */
3985
3986        serial_driver->owner = THIS_MODULE;
3987        serial_driver->driver_name = "synclinkmp";
3988        serial_driver->name = "ttySLM";
3989        serial_driver->major = ttymajor;
3990        serial_driver->minor_start = 64;
3991        serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3992        serial_driver->subtype = SERIAL_TYPE_NORMAL;
3993        serial_driver->init_termios = tty_std_termios;
3994        serial_driver->init_termios.c_cflag =
3995                B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3996        serial_driver->init_termios.c_ispeed = 9600;
3997        serial_driver->init_termios.c_ospeed = 9600;
3998        serial_driver->flags = TTY_DRIVER_REAL_RAW;
3999        tty_set_operations(serial_driver, &ops);
4000        if ((rc = tty_register_driver(serial_driver)) < 0) {
4001                printk("%s(%d):Couldn't register serial driver\n",
4002                        __FILE__,__LINE__);
4003                put_tty_driver(serial_driver);
4004                serial_driver = NULL;
4005                goto error;
4006        }
4007
4008        printk("%s %s, tty major#%d\n",
4009                driver_name, driver_version,
4010                serial_driver->major);
4011
4012        return 0;
4013
4014error:
4015        synclinkmp_cleanup();
4016        return rc;
4017}
4018
4019static void __exit synclinkmp_exit(void)
4020{
4021        synclinkmp_cleanup();
4022}
4023
4024module_init(synclinkmp_init);
4025module_exit(synclinkmp_exit);
4026
4027/* Set the port for internal loopback mode.
4028 * The TxCLK and RxCLK signals are generated from the BRG and
4029 * the TxD is looped back to the RxD internally.
4030 */
4031static void enable_loopback(SLMP_INFO *info, int enable)
4032{
4033        if (enable) {
4034                /* MD2 (Mode Register 2)
4035                 * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4036                 */
4037                write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4038
4039                /* degate external TxC clock source */
4040                info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4041                write_control_reg(info);
4042
4043                /* RXS/TXS (Rx/Tx clock source)
4044                 * 07      Reserved, must be 0
4045                 * 06..04  Clock Source, 100=BRG
4046                 * 03..00  Clock Divisor, 0000=1
4047                 */
4048                write_reg(info, RXS, 0x40);
4049                write_reg(info, TXS, 0x40);
4050
4051        } else {
4052                /* MD2 (Mode Register 2)
4053                 * 01..00  CNCT<1..0> Channel connection, 0=normal
4054                 */
4055                write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4056
4057                /* RXS/TXS (Rx/Tx clock source)
4058                 * 07      Reserved, must be 0
4059                 * 06..04  Clock Source, 000=RxC/TxC Pin
4060                 * 03..00  Clock Divisor, 0000=1
4061                 */
4062                write_reg(info, RXS, 0x00);
4063                write_reg(info, TXS, 0x00);
4064        }
4065
4066        /* set LinkSpeed if available, otherwise default to 2Mbps */
4067        if (info->params.clock_speed)
4068                set_rate(info, info->params.clock_speed);
4069        else
4070                set_rate(info, 3686400);
4071}
4072
4073/* Set the baud rate register to the desired speed
4074 *
4075 *      data_rate       data rate of clock in bits per second
4076 *                      A data rate of 0 disables the AUX clock.
4077 */
4078static void set_rate( SLMP_INFO *info, u32 data_rate )
4079{
4080        u32 TMCValue;
4081        unsigned char BRValue;
4082        u32 Divisor=0;
4083
4084        /* fBRG = fCLK/(TMC * 2^BR)
4085         */
4086        if (data_rate != 0) {
4087                Divisor = 14745600/data_rate;
4088                if (!Divisor)
4089                        Divisor = 1;
4090
4091                TMCValue = Divisor;
4092
4093                BRValue = 0;
4094                if (TMCValue != 1 && TMCValue != 2) {
4095                        /* BRValue of 0 provides 50/50 duty cycle *only* when
4096                         * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4097                         * 50/50 duty cycle.
4098                         */
4099                        BRValue = 1;
4100                        TMCValue >>= 1;
4101                }
4102
4103                /* while TMCValue is too big for TMC register, divide
4104                 * by 2 and increment BR exponent.
4105                 */
4106                for(; TMCValue > 256 && BRValue < 10; BRValue++)
4107                        TMCValue >>= 1;
4108
4109                write_reg(info, TXS,
4110                        (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4111                write_reg(info, RXS,
4112                        (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4113                write_reg(info, TMC, (unsigned char)TMCValue);
4114        }
4115        else {
4116                write_reg(info, TXS,0);
4117                write_reg(info, RXS,0);
4118                write_reg(info, TMC, 0);
4119        }
4120}
4121
4122/* Disable receiver
4123 */
4124static void rx_stop(SLMP_INFO *info)
4125{
4126        if (debug_level >= DEBUG_LEVEL_ISR)
4127                printk("%s(%d):%s rx_stop()\n",
4128                         __FILE__,__LINE__, info->device_name );
4129
4130        write_reg(info, CMD, RXRESET);
4131
4132        info->ie0_value &= ~RXRDYE;
4133        write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4134
4135        write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4136        write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4137        write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4138
4139        info->rx_enabled = false;
4140        info->rx_overflow = false;
4141}
4142
4143/* enable the receiver
4144 */
4145static void rx_start(SLMP_INFO *info)
4146{
4147        int i;
4148
4149        if (debug_level >= DEBUG_LEVEL_ISR)
4150                printk("%s(%d):%s rx_start()\n",
4151                         __FILE__,__LINE__, info->device_name );
4152
4153        write_reg(info, CMD, RXRESET);
4154
4155        if ( info->params.mode == MGSL_MODE_HDLC ) {
4156                /* HDLC, disabe IRQ on rxdata */
4157                info->ie0_value &= ~RXRDYE;
4158                write_reg(info, IE0, info->ie0_value);
4159
4160                /* Reset all Rx DMA buffers and program rx dma */
4161                write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4162                write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4163
4164                for (i = 0; i < info->rx_buf_count; i++) {
4165                        info->rx_buf_list[i].status = 0xff;
4166
4167                        // throttle to 4 shared memory writes at a time to prevent
4168                        // hogging local bus (keep latency time for DMA requests low).
4169                        if (!(i % 4))
4170                                read_status_reg(info);
4171                }
4172                info->current_rx_buf = 0;
4173
4174                /* set current/1st descriptor address */
4175                write_reg16(info, RXDMA + CDA,
4176                        info->rx_buf_list_ex[0].phys_entry);
4177
4178                /* set new last rx descriptor address */
4179                write_reg16(info, RXDMA + EDA,
4180                        info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4181
4182                /* set buffer length (shared by all rx dma data buffers) */
4183                write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4184
4185                write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4186                write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4187        } else {
4188                /* async, enable IRQ on rxdata */
4189                info->ie0_value |= RXRDYE;
4190                write_reg(info, IE0, info->ie0_value);
4191        }
4192
4193        write_reg(info, CMD, RXENABLE);
4194
4195        info->rx_overflow = false;
4196        info->rx_enabled = true;
4197}
4198
4199/* Enable the transmitter and send a transmit frame if
4200 * one is loaded in the DMA buffers.
4201 */
4202static void tx_start(SLMP_INFO *info)
4203{
4204        if (debug_level >= DEBUG_LEVEL_ISR)
4205                printk("%s(%d):%s tx_start() tx_count=%d\n",
4206                         __FILE__,__LINE__, info->device_name,info->tx_count );
4207
4208        if (!info->tx_enabled ) {
4209                write_reg(info, CMD, TXRESET);
4210                write_reg(info, CMD, TXENABLE);
4211                info->tx_enabled = true;
4212        }
4213
4214        if ( info->tx_count ) {
4215
4216                /* If auto RTS enabled and RTS is inactive, then assert */
4217                /* RTS and set a flag indicating that the driver should */
4218                /* negate RTS when the transmission completes. */
4219
4220                info->drop_rts_on_tx_done = false;
4221
4222                if (info->params.mode != MGSL_MODE_ASYNC) {
4223
4224                        if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4225                                get_signals( info );
4226                                if ( !(info->serial_signals & SerialSignal_RTS) ) {
4227                                        info->serial_signals |= SerialSignal_RTS;
4228                                        set_signals( info );
4229                                        info->drop_rts_on_tx_done = true;
4230                                }
4231                        }
4232
4233                        write_reg16(info, TRC0,
4234                                (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4235
4236                        write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4237                        write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4238        
4239                        /* set TX CDA (current descriptor address) */
4240                        write_reg16(info, TXDMA + CDA,
4241                                info->tx_buf_list_ex[0].phys_entry);
4242        
4243                        /* set TX EDA (last descriptor address) */
4244                        write_reg16(info, TXDMA + EDA,
4245                                info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4246        
4247                        /* enable underrun IRQ */
4248                        info->ie1_value &= ~IDLE;
4249                        info->ie1_value |= UDRN;
4250                        write_reg(info, IE1, info->ie1_value);
4251                        write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4252        
4253                        write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4254                        write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4255        
4256                        mod_timer(&info->tx_timer, jiffies +
4257                                        msecs_to_jiffies(5000));
4258                }
4259                else {
4260                        tx_load_fifo(info);
4261                        /* async, enable IRQ on txdata */
4262                        info->ie0_value |= TXRDYE;
4263                        write_reg(info, IE0, info->ie0_value);
4264                }
4265
4266                info->tx_active = true;
4267        }
4268}
4269
4270/* stop the transmitter and DMA
4271 */
4272static void tx_stop( SLMP_INFO *info )
4273{
4274        if (debug_level >= DEBUG_LEVEL_ISR)
4275                printk("%s(%d):%s tx_stop()\n",
4276                         __FILE__,__LINE__, info->device_name );
4277
4278        del_timer(&info->tx_timer);
4279
4280        write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4281        write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4282
4283        write_reg(info, CMD, TXRESET);
4284
4285        info->ie1_value &= ~(UDRN + IDLE);
4286        write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4287        write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4288
4289        info->ie0_value &= ~TXRDYE;
4290        write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4291
4292        info->tx_enabled = false;
4293        info->tx_active = false;
4294}
4295
4296/* Fill the transmit FIFO until the FIFO is full or
4297 * there is no more data to load.
4298 */
4299static void tx_load_fifo(SLMP_INFO *info)
4300{
4301        u8 TwoBytes[2];
4302
4303        /* do nothing is now tx data available and no XON/XOFF pending */
4304
4305        if ( !info->tx_count && !info->x_char )
4306                return;
4307
4308        /* load the Transmit FIFO until FIFOs full or all data sent */
4309
4310        while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4311
4312                /* there is more space in the transmit FIFO and */
4313                /* there is more data in transmit buffer */
4314
4315                if ( (info->tx_count > 1) && !info->x_char ) {
4316                        /* write 16-bits */
4317                        TwoBytes[0] = info->tx_buf[info->tx_get++];
4318                        if (info->tx_get >= info->max_frame_size)
4319                                info->tx_get -= info->max_frame_size;
4320                        TwoBytes[1] = info->tx_buf[info->tx_get++];
4321                        if (info->tx_get >= info->max_frame_size)
4322                                info->tx_get -= info->max_frame_size;
4323
4324                        write_reg16(info, TRB, *((u16 *)TwoBytes));
4325
4326                        info->tx_count -= 2;
4327                        info->icount.tx += 2;
4328                } else {
4329                        /* only 1 byte left to transmit or 1 FIFO slot left */
4330
4331                        if (info->x_char) {
4332                                /* transmit pending high priority char */
4333                                write_reg(info, TRB, info->x_char);
4334                                info->x_char = 0;
4335                        } else {
4336                                write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4337                                if (info->tx_get >= info->max_frame_size)
4338                                        info->tx_get -= info->max_frame_size;
4339                                info->tx_count--;
4340                        }
4341                        info->icount.tx++;
4342                }
4343        }
4344}
4345
4346/* Reset a port to a known state
4347 */
4348static void reset_port(SLMP_INFO *info)
4349{
4350        if (info->sca_base) {
4351
4352                tx_stop(info);
4353                rx_stop(info);
4354
4355                info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4356                set_signals(info);
4357
4358                /* disable all port interrupts */
4359                info->ie0_value = 0;
4360                info->ie1_value = 0;
4361                info->ie2_value = 0;
4362                write_reg(info, IE0, info->ie0_value);
4363                write_reg(info, IE1, info->ie1_value);
4364                write_reg(info, IE2, info->ie2_value);
4365
4366                write_reg(info, CMD, CHRESET);
4367        }
4368}
4369
4370/* Reset all the ports to a known state.
4371 */
4372static void reset_adapter(SLMP_INFO *info)
4373{
4374        int i;
4375
4376        for ( i=0; i < SCA_MAX_PORTS; ++i) {
4377                if (info->port_array[i])
4378                        reset_port(info->port_array[i]);
4379        }
4380}
4381
4382/* Program port for asynchronous communications.
4383 */
4384static void async_mode(SLMP_INFO *info)
4385{
4386
4387        unsigned char RegValue;
4388
4389        tx_stop(info);
4390        rx_stop(info);
4391
4392        /* MD0, Mode Register 0
4393         *
4394         * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4395         * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4396         * 03      Reserved, must be 0
4397         * 02      CRCCC, CRC Calculation, 0=disabled
4398         * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4399         *
4400         * 0000 0000
4401         */
4402        RegValue = 0x00;
4403        if (info->params.stop_bits != 1)
4404                RegValue |= BIT1;
4405        write_reg(info, MD0, RegValue);
4406
4407        /* MD1, Mode Register 1
4408         *
4409         * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4410         * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4411         * 03..02  RXCHR<1..0>, rx char size
4412         * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4413         *
4414         * 0100 0000
4415         */
4416        RegValue = 0x40;
4417        switch (info->params.data_bits) {
4418        case 7: RegValue |= BIT4 + BIT2; break;
4419        case 6: RegValue |= BIT5 + BIT3; break;
4420        case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4421        }
4422        if (info->params.parity != ASYNC_PARITY_NONE) {
4423                RegValue |= BIT1;
4424                if (info->params.parity == ASYNC_PARITY_ODD)
4425                        RegValue |= BIT0;
4426        }
4427        write_reg(info, MD1, RegValue);
4428
4429        /* MD2, Mode Register 2
4430         *
4431         * 07..02  Reserved, must be 0
4432         * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4433         *
4434         * 0000 0000
4435         */
4436        RegValue = 0x00;
4437        if (info->params.loopback)
4438                RegValue |= (BIT1 + BIT0);
4439        write_reg(info, MD2, RegValue);
4440
4441        /* RXS, Receive clock source
4442         *
4443         * 07      Reserved, must be 0
4444         * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4445         * 03..00  RXBR<3..0>, rate divisor, 0000=1
4446         */
4447        RegValue=BIT6;
4448        write_reg(info, RXS, RegValue);
4449
4450        /* TXS, Transmit clock source
4451         *
4452         * 07      Reserved, must be 0
4453         * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4454         * 03..00  RXBR<3..0>, rate divisor, 0000=1
4455         */
4456        RegValue=BIT6;
4457        write_reg(info, TXS, RegValue);
4458
4459        /* Control Register
4460         *
4461         * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4462         */
4463        info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4464        write_control_reg(info);
4465
4466        tx_set_idle(info);
4467
4468        /* RRC Receive Ready Control 0
4469         *
4470         * 07..05  Reserved, must be 0
4471         * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4472         */
4473        write_reg(info, RRC, 0x00);
4474
4475        /* TRC0 Transmit Ready Control 0
4476         *
4477         * 07..05  Reserved, must be 0
4478         * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4479         */
4480        write_reg(info, TRC0, 0x10);
4481
4482        /* TRC1 Transmit Ready Control 1
4483         *
4484         * 07..05  Reserved, must be 0
4485         * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4486         */
4487        write_reg(info, TRC1, 0x1e);
4488
4489        /* CTL, MSCI control register
4490         *
4491         * 07..06  Reserved, set to 0
4492         * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4493         * 04      IDLC, idle control, 0=mark 1=idle register
4494         * 03      BRK, break, 0=off 1 =on (async)
4495         * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4496         * 01      GOP, go active on poll (LOOP mode) 1=enabled
4497         * 00      RTS, RTS output control, 0=active 1=inactive
4498         *
4499         * 0001 0001
4500         */
4501        RegValue = 0x10;
4502        if (!(info->serial_signals & SerialSignal_RTS))
4503                RegValue |= 0x01;
4504        write_reg(info, CTL, RegValue);
4505
4506        /* enable status interrupts */
4507        info->ie0_value |= TXINTE + RXINTE;
4508        write_reg(info, IE0, info->ie0_value);
4509
4510        /* enable break detect interrupt */
4511        info->ie1_value = BRKD;
4512        write_reg(info, IE1, info->ie1_value);
4513
4514        /* enable rx overrun interrupt */
4515        info->ie2_value = OVRN;
4516        write_reg(info, IE2, info->ie2_value);
4517
4518        set_rate( info, info->params.data_rate * 16 );
4519}
4520
4521/* Program the SCA for HDLC communications.
4522 */
4523static void hdlc_mode(SLMP_INFO *info)
4524{
4525        unsigned char RegValue;
4526        u32 DpllDivisor;
4527
4528        // Can't use DPLL because SCA outputs recovered clock on RxC when
4529        // DPLL mode selected. This causes output contention with RxC receiver.
4530        // Use of DPLL would require external hardware to disable RxC receiver
4531        // when DPLL mode selected.
4532        info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4533
4534        /* disable DMA interrupts */
4535        write_reg(info, TXDMA + DIR, 0);
4536        write_reg(info, RXDMA + DIR, 0);
4537
4538        /* MD0, Mode Register 0
4539         *
4540         * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4541         * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4542         * 03      Reserved, must be 0
4543         * 02      CRCCC, CRC Calculation, 1=enabled
4544         * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4545         * 00      CRC0, CRC initial value, 1 = all 1s
4546         *
4547         * 1000 0001
4548         */
4549        RegValue = 0x81;
4550        if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4551                RegValue |= BIT4;
4552        if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4553                RegValue |= BIT4;
4554        if (info->params.crc_type == HDLC_CRC_16_CCITT)
4555                RegValue |= BIT2 + BIT1;
4556        write_reg(info, MD0, RegValue);
4557
4558        /* MD1, Mode Register 1
4559         *
4560         * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4561         * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4562         * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4563         * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4564         *
4565         * 0000 0000
4566         */
4567        RegValue = 0x00;
4568        write_reg(info, MD1, RegValue);
4569
4570        /* MD2, Mode Register 2
4571         *
4572         * 07      NRZFM, 0=NRZ, 1=FM
4573         * 06..05  CODE<1..0> Encoding, 00=NRZ
4574         * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4575         * 02      Reserved, must be 0
4576         * 01..00  CNCT<1..0> Channel connection, 0=normal
4577         *
4578         * 0000 0000
4579         */
4580        RegValue = 0x00;
4581        switch(info->params.encoding) {
4582        case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4583        case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4584        case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4585        case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4586#if 0
4587        case HDLC_ENCODING_NRZB:                                        /* not supported */
4588        case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4589        case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4590#endif
4591        }
4592        if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4593                DpllDivisor = 16;
4594                RegValue |= BIT3;
4595        } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4596                DpllDivisor = 8;
4597        } else {
4598                DpllDivisor = 32;
4599                RegValue |= BIT4;
4600        }
4601        write_reg(info, MD2, RegValue);
4602
4603
4604        /* RXS, Receive clock source
4605         *
4606         * 07      Reserved, must be 0
4607         * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4608         * 03..00  RXBR<3..0>, rate divisor, 0000=1
4609         */
4610        RegValue=0;
4611        if (info->params.flags & HDLC_FLAG_RXC_BRG)
4612                RegValue |= BIT6;
4613        if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4614                RegValue |= BIT6 + BIT5;
4615        write_reg(info, RXS, RegValue);
4616
4617        /* TXS, Transmit clock source
4618         *
4619         * 07      Reserved, must be 0
4620         * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4621         * 03..00  RXBR<3..0>, rate divisor, 0000=1
4622         */
4623        RegValue=0;
4624        if (info->params.flags & HDLC_FLAG_TXC_BRG)
4625                RegValue |= BIT6;
4626        if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4627                RegValue |= BIT6 + BIT5;
4628        write_reg(info, TXS, RegValue);
4629
4630        if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4631                set_rate(info, info->params.clock_speed * DpllDivisor);
4632        else
4633                set_rate(info, info->params.clock_speed);
4634
4635        /* GPDATA (General Purpose I/O Data Register)
4636         *
4637         * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4638         */
4639        if (info->params.flags & HDLC_FLAG_TXC_BRG)
4640                info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4641        else
4642                info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4643        write_control_reg(info);
4644
4645        /* RRC Receive Ready Control 0
4646         *
4647         * 07..05  Reserved, must be 0
4648         * 04..00  RRC<4..0> Rx FIFO trigger active
4649         */
4650        write_reg(info, RRC, rx_active_fifo_level);
4651
4652        /* TRC0 Transmit Ready Control 0
4653         *
4654         * 07..05  Reserved, must be 0
4655         * 04..00  TRC<4..0> Tx FIFO trigger active
4656         */
4657        write_reg(info, TRC0, tx_active_fifo_level);
4658
4659        /* TRC1 Transmit Ready Control 1
4660         *
4661         * 07..05  Reserved, must be 0
4662         * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4663         */
4664        write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4665
4666        /* DMR, DMA Mode Register
4667         *
4668         * 07..05  Reserved, must be 0
4669         * 04      TMOD, Transfer Mode: 1=chained-block
4670         * 03      Reserved, must be 0
4671         * 02      NF, Number of Frames: 1=multi-frame
4672         * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4673         * 00      Reserved, must be 0
4674         *
4675         * 0001 0100
4676         */
4677        write_reg(info, TXDMA + DMR, 0x14);
4678        write_reg(info, RXDMA + DMR, 0x14);
4679
4680        /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4681        write_reg(info, RXDMA + CPB,
4682                (unsigned char)(info->buffer_list_phys >> 16));
4683
4684        /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4685        write_reg(info, TXDMA + CPB,
4686                (unsigned char)(info->buffer_list_phys >> 16));
4687
4688        /* enable status interrupts. other code enables/disables
4689         * the individual sources for these two interrupt classes.
4690         */
4691        info->ie0_value |= TXINTE + RXINTE;
4692        write_reg(info, IE0, info->ie0_value);
4693
4694        /* CTL, MSCI control register
4695         *
4696         * 07..06  Reserved, set to 0
4697         * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4698         * 04      IDLC, idle control, 0=mark 1=idle register
4699         * 03      BRK, break, 0=off 1 =on (async)
4700         * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4701         * 01      GOP, go active on poll (LOOP mode) 1=enabled
4702         * 00      RTS, RTS output control, 0=active 1=inactive
4703         *
4704         * 0001 0001
4705         */
4706        RegValue = 0x10;
4707        if (!(info->serial_signals & SerialSignal_RTS))
4708                RegValue |= 0x01;
4709        write_reg(info, CTL, RegValue);
4710
4711        /* preamble not supported ! */
4712
4713        tx_set_idle(info);
4714        tx_stop(info);
4715        rx_stop(info);
4716
4717        set_rate(info, info->params.clock_speed);
4718
4719        if (info->params.loopback)
4720                enable_loopback(info,1);
4721}
4722
4723/* Set the transmit HDLC idle mode
4724 */
4725static void tx_set_idle(SLMP_INFO *info)
4726{
4727        unsigned char RegValue = 0xff;
4728
4729        /* Map API idle mode to SCA register bits */
4730        switch(info->idle_mode) {
4731        case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4732        case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4733        case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4734        case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4735        case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4736        case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4737        case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4738        }
4739
4740        write_reg(info, IDL, RegValue);
4741}
4742
4743/* Query the adapter for the state of the V24 status (input) signals.
4744 */
4745static void get_signals(SLMP_INFO *info)
4746{
4747        u16 status = read_reg(info, SR3);
4748        u16 gpstatus = read_status_reg(info);
4749        u16 testbit;
4750
4751        /* clear all serial signals except DTR and RTS */
4752        info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4753
4754        /* set serial signal bits to reflect MISR */
4755
4756        if (!(status & BIT3))
4757                info->serial_signals |= SerialSignal_CTS;
4758
4759        if ( !(status & BIT2))
4760                info->serial_signals |= SerialSignal_DCD;
4761
4762        testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4763        if (!(gpstatus & testbit))
4764                info->serial_signals |= SerialSignal_RI;
4765
4766        testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4767        if (!(gpstatus & testbit))
4768                info->serial_signals |= SerialSignal_DSR;
4769}
4770
4771/* Set the state of DTR and RTS based on contents of
4772 * serial_signals member of device context.
4773 */
4774static void set_signals(SLMP_INFO *info)
4775{
4776        unsigned char RegValue;
4777        u16 EnableBit;
4778
4779        RegValue = read_reg(info, CTL);
4780        if (info->serial_signals & SerialSignal_RTS)
4781                RegValue &= ~BIT0;
4782        else
4783                RegValue |= BIT0;
4784        write_reg(info, CTL, RegValue);
4785
4786        // Port 0..3 DTR is ctrl reg <1,3,5,7>
4787        EnableBit = BIT1 << (info->port_num*2);
4788        if (info->serial_signals & SerialSignal_DTR)
4789                info->port_array[0]->ctrlreg_value &= ~EnableBit;
4790        else
4791                info->port_array[0]->ctrlreg_value |= EnableBit;
4792        write_control_reg(info);
4793}
4794
4795/*******************/
4796/* DMA Buffer Code */
4797/*******************/
4798
4799/* Set the count for all receive buffers to SCABUFSIZE
4800 * and set the current buffer to the first buffer. This effectively
4801 * makes all buffers free and discards any data in buffers.
4802 */
4803static void rx_reset_buffers(SLMP_INFO *info)
4804{
4805        rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4806}
4807
4808/* Free the buffers used by a received frame
4809 *
4810 * info   pointer to device instance data
4811 * first  index of 1st receive buffer of frame
4812 * last   index of last receive buffer of frame
4813 */
4814static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4815{
4816        bool done = false;
4817
4818        while(!done) {
4819                /* reset current buffer for reuse */
4820                info->rx_buf_list[first].status = 0xff;
4821
4822                if (first == last) {
4823                        done = true;
4824                        /* set new last rx descriptor address */
4825                        write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4826                }
4827
4828                first++;
4829                if (first == info->rx_buf_count)
4830                        first = 0;
4831        }
4832
4833        /* set current buffer to next buffer after last buffer of frame */
4834        info->current_rx_buf = first;
4835}
4836
4837/* Return a received frame from the receive DMA buffers.
4838 * Only frames received without errors are returned.
4839 *
4840 * Return Value:        true if frame returned, otherwise false
4841 */
4842static bool rx_get_frame(SLMP_INFO *info)
4843{
4844        unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4845        unsigned short status;
4846        unsigned int framesize = 0;
4847        bool ReturnCode = false;
4848        unsigned long flags;
4849        struct tty_struct *tty = info->port.tty;
4850        unsigned char addr_field = 0xff;
4851        SCADESC *desc;
4852        SCADESC_EX *desc_ex;
4853
4854CheckAgain:
4855        /* assume no frame returned, set zero length */
4856        framesize = 0;
4857        addr_field = 0xff;
4858
4859        /*
4860         * current_rx_buf points to the 1st buffer of the next available
4861         * receive frame. To find the last buffer of the frame look for
4862         * a non-zero status field in the buffer entries. (The status
4863         * field is set by the 16C32 after completing a receive frame.
4864         */
4865        StartIndex = EndIndex = info->current_rx_buf;
4866
4867        for ( ;; ) {
4868                desc = &info->rx_buf_list[EndIndex];
4869                desc_ex = &info->rx_buf_list_ex[EndIndex];
4870
4871                if (desc->status == 0xff)
4872                        goto Cleanup;   /* current desc still in use, no frames available */
4873
4874                if (framesize == 0 && info->params.addr_filter != 0xff)
4875                        addr_field = desc_ex->virt_addr[0];
4876
4877                framesize += desc->length;
4878
4879                /* Status != 0 means last buffer of frame */
4880                if (desc->status)
4881                        break;
4882
4883                EndIndex++;
4884                if (EndIndex == info->rx_buf_count)
4885                        EndIndex = 0;
4886
4887                if (EndIndex == info->current_rx_buf) {
4888                        /* all buffers have been 'used' but none mark      */
4889                        /* the end of a frame. Reset buffers and receiver. */
4890                        if ( info->rx_enabled ){
4891                                spin_lock_irqsave(&info->lock,flags);
4892                                rx_start(info);
4893                                spin_unlock_irqrestore(&info->lock,flags);
4894                        }
4895                        goto Cleanup;
4896                }
4897
4898        }
4899
4900        /* check status of receive frame */
4901
4902        /* frame status is byte stored after frame data
4903         *
4904         * 7 EOM (end of msg), 1 = last buffer of frame
4905         * 6 Short Frame, 1 = short frame
4906         * 5 Abort, 1 = frame aborted
4907         * 4 Residue, 1 = last byte is partial
4908         * 3 Overrun, 1 = overrun occurred during frame reception
4909         * 2 CRC,     1 = CRC error detected
4910         *
4911         */
4912        status = desc->status;
4913
4914        /* ignore CRC bit if not using CRC (bit is undefined) */
4915        /* Note:CRC is not save to data buffer */
4916        if (info->params.crc_type == HDLC_CRC_NONE)
4917                status &= ~BIT2;
4918
4919        if (framesize == 0 ||
4920                 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4921                /* discard 0 byte frames, this seems to occur sometime
4922                 * when remote is idling flags.
4923                 */
4924                rx_free_frame_buffers(info, StartIndex, EndIndex);
4925                goto CheckAgain;
4926        }
4927
4928        if (framesize < 2)
4929                status |= BIT6;
4930
4931        if (status & (BIT6+BIT5+BIT3+BIT2)) {
4932                /* received frame has errors,
4933                 * update counts and mark frame size as 0
4934                 */
4935                if (status & BIT6)
4936                        info->icount.rxshort++;
4937                else if (status & BIT5)
4938                        info->icount.rxabort++;
4939                else if (status & BIT3)
4940                        info->icount.rxover++;
4941                else
4942                        info->icount.rxcrc++;
4943
4944                framesize = 0;
4945#if SYNCLINK_GENERIC_HDLC
4946                {
4947                        info->netdev->stats.rx_errors++;
4948                        info->netdev->stats.rx_frame_errors++;
4949                }
4950#endif
4951        }
4952
4953        if ( debug_level >= DEBUG_LEVEL_BH )
4954                printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4955                        __FILE__,__LINE__,info->device_name,status,framesize);
4956
4957        if ( debug_level >= DEBUG_LEVEL_DATA )
4958                trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4959                        min_t(int, framesize,SCABUFSIZE),0);
4960
4961        if (framesize) {
4962                if (framesize > info->max_frame_size)
4963                        info->icount.rxlong++;
4964                else {
4965                        /* copy dma buffer(s) to contiguous intermediate buffer */
4966                        int copy_count = framesize;
4967                        int index = StartIndex;
4968                        unsigned char *ptmp = info->tmp_rx_buf;
4969                        info->tmp_rx_buf_count = framesize;
4970
4971                        info->icount.rxok++;
4972
4973                        while(copy_count) {
4974                                int partial_count = min(copy_count,SCABUFSIZE);
4975                                memcpy( ptmp,
4976                                        info->rx_buf_list_ex[index].virt_addr,
4977                                        partial_count );
4978                                ptmp += partial_count;
4979                                copy_count -= partial_count;
4980
4981                                if ( ++index == info->rx_buf_count )
4982                                        index = 0;
4983                        }
4984
4985#if SYNCLINK_GENERIC_HDLC
4986                        if (info->netcount)
4987                                hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4988                        else
4989#endif
4990                                ldisc_receive_buf(tty,info->tmp_rx_buf,
4991                                                  info->flag_buf, framesize);
4992                }
4993        }
4994        /* Free the buffers used by this frame. */
4995        rx_free_frame_buffers( info, StartIndex, EndIndex );
4996
4997        ReturnCode = true;
4998
4999Cleanup:
5000        if ( info->rx_enabled && info->rx_overflow ) {
5001                /* Receiver is enabled, but needs to restarted due to
5002                 * rx buffer overflow. If buffers are empty, restart receiver.
5003                 */
5004                if (info->rx_buf_list[EndIndex].status == 0xff) {
5005                        spin_lock_irqsave(&info->lock,flags);
5006                        rx_start(info);
5007                        spin_unlock_irqrestore(&info->lock,flags);
5008                }
5009        }
5010
5011        return ReturnCode;
5012}
5013
5014/* load the transmit DMA buffer with data
5015 */
5016static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5017{
5018        unsigned short copy_count;
5019        unsigned int i = 0;
5020        SCADESC *desc;
5021        SCADESC_EX *desc_ex;
5022
5023        if ( debug_level >= DEBUG_LEVEL_DATA )
5024                trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5025
5026        /* Copy source buffer to one or more DMA buffers, starting with
5027         * the first transmit dma buffer.
5028         */
5029        for(i=0;;)
5030        {
5031                copy_count = min_t(unsigned short,count,SCABUFSIZE);
5032
5033                desc = &info->tx_buf_list[i];
5034                desc_ex = &info->tx_buf_list_ex[i];
5035
5036                load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5037
5038                desc->length = copy_count;
5039                desc->status = 0;
5040
5041                buf += copy_count;
5042                count -= copy_count;
5043
5044                if (!count)
5045                        break;
5046
5047                i++;
5048                if (i >= info->tx_buf_count)
5049                        i = 0;
5050        }
5051
5052        info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5053        info->last_tx_buf = ++i;
5054}
5055
5056static bool register_test(SLMP_INFO *info)
5057{
5058        static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5059        static unsigned int count = ARRAY_SIZE(testval);
5060        unsigned int i;
5061        bool rc = true;
5062        unsigned long flags;
5063
5064        spin_lock_irqsave(&info->lock,flags);
5065        reset_port(info);
5066
5067        /* assume failure */
5068        info->init_error = DiagStatus_AddressFailure;
5069
5070        /* Write bit patterns to various registers but do it out of */
5071        /* sync, then read back and verify values. */
5072
5073        for (i = 0 ; i < count ; i++) {
5074                write_reg(info, TMC, testval[i]);
5075                write_reg(info, IDL, testval[(i+1)%count]);
5076                write_reg(info, SA0, testval[(i+2)%count]);
5077                write_reg(info, SA1, testval[(i+3)%count]);
5078
5079                if ( (read_reg(info, TMC) != testval[i]) ||
5080                          (read_reg(info, IDL) != testval[(i+1)%count]) ||
5081                          (read_reg(info, SA0) != testval[(i+2)%count]) ||
5082                          (read_reg(info, SA1) != testval[(i+3)%count]) )
5083                {
5084                        rc = false;
5085                        break;
5086                }
5087        }
5088
5089        reset_port(info);
5090        spin_unlock_irqrestore(&info->lock,flags);
5091
5092        return rc;
5093}
5094
5095static bool irq_test(SLMP_INFO *info)
5096{
5097        unsigned long timeout;
5098        unsigned long flags;
5099
5100        unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5101
5102        spin_lock_irqsave(&info->lock,flags);
5103        reset_port(info);
5104
5105        /* assume failure */
5106        info->init_error = DiagStatus_IrqFailure;
5107        info->irq_occurred = false;
5108
5109        /* setup timer0 on SCA0 to interrupt */
5110
5111        /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5112        write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5113
5114        write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5115        write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5116
5117
5118        /* TMCS, Timer Control/Status Register
5119         *
5120         * 07      CMF, Compare match flag (read only) 1=match
5121         * 06      ECMI, CMF Interrupt Enable: 1=enabled
5122         * 05      Reserved, must be 0
5123         * 04      TME, Timer Enable
5124         * 03..00  Reserved, must be 0
5125         *
5126         * 0101 0000
5127         */
5128        write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5129
5130        spin_unlock_irqrestore(&info->lock,flags);
5131
5132        timeout=100;
5133        while( timeout-- && !info->irq_occurred ) {
5134                msleep_interruptible(10);
5135        }
5136
5137        spin_lock_irqsave(&info->lock,flags);
5138        reset_port(info);
5139        spin_unlock_irqrestore(&info->lock,flags);
5140
5141        return info->irq_occurred;
5142}
5143
5144/* initialize individual SCA device (2 ports)
5145 */
5146static bool sca_init(SLMP_INFO *info)
5147{
5148        /* set wait controller to single mem partition (low), no wait states */
5149        write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5150        write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5151        write_reg(info, WCRL, 0);       /* wait controller low range */
5152        write_reg(info, WCRM, 0);       /* wait controller mid range */
5153        write_reg(info, WCRH, 0);       /* wait controller high range */
5154
5155        /* DPCR, DMA Priority Control
5156         *
5157         * 07..05  Not used, must be 0
5158         * 04      BRC, bus release condition: 0=all transfers complete
5159         * 03      CCC, channel change condition: 0=every cycle
5160         * 02..00  PR<2..0>, priority 100=round robin
5161         *
5162         * 00000100 = 0x04
5163         */
5164        write_reg(info, DPCR, dma_priority);
5165
5166        /* DMA Master Enable, BIT7: 1=enable all channels */
5167        write_reg(info, DMER, 0x80);
5168
5169        /* enable all interrupt classes */
5170        write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5171        write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5172        write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5173
5174        /* ITCR, interrupt control register
5175         * 07      IPC, interrupt priority, 0=MSCI->DMA
5176         * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5177         * 04      VOS, Vector Output, 0=unmodified vector
5178         * 03..00  Reserved, must be 0
5179         */
5180        write_reg(info, ITCR, 0);
5181
5182        return true;
5183}
5184
5185/* initialize adapter hardware
5186 */
5187static bool init_adapter(SLMP_INFO *info)
5188{
5189        int i;
5190
5191        /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5192        volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5193        u32 readval;
5194
5195        info->misc_ctrl_value |= BIT30;
5196        *MiscCtrl = info->misc_ctrl_value;
5197
5198        /*
5199         * Force at least 170ns delay before clearing
5200         * reset bit. Each read from LCR takes at least
5201         * 30ns so 10 times for 300ns to be safe.
5202         */
5203        for(i=0;i<10;i++)
5204                readval = *MiscCtrl;
5205
5206        info->misc_ctrl_value &= ~BIT30;
5207        *MiscCtrl = info->misc_ctrl_value;
5208
5209        /* init control reg (all DTRs off, all clksel=input) */
5210        info->ctrlreg_value = 0xaa;
5211        write_control_reg(info);
5212
5213        {
5214                volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5215                lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5216
5217                switch(read_ahead_count)
5218                {
5219                case 16:
5220                        lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5221                        break;
5222                case 8:
5223                        lcr1_brdr_value |= BIT5 + BIT4;
5224                        break;
5225                case 4:
5226                        lcr1_brdr_value |= BIT5 + BIT3;
5227                        break;
5228                case 0:
5229                        lcr1_brdr_value |= BIT5;
5230                        break;
5231                }
5232
5233                *LCR1BRDR = lcr1_brdr_value;
5234                *MiscCtrl = misc_ctrl_value;
5235        }
5236
5237        sca_init(info->port_array[0]);
5238        sca_init(info->port_array[2]);
5239
5240        return true;
5241}
5242
5243/* Loopback an HDLC frame to test the hardware
5244 * interrupt and DMA functions.
5245 */
5246static bool loopback_test(SLMP_INFO *info)
5247{
5248#define TESTFRAMESIZE 20
5249
5250        unsigned long timeout;
5251        u16 count = TESTFRAMESIZE;
5252        unsigned char buf[TESTFRAMESIZE];
5253        bool rc = false;
5254        unsigned long flags;
5255
5256        struct tty_struct *oldtty = info->port.tty;
5257        u32 speed = info->params.clock_speed;
5258
5259        info->params.clock_speed = 3686400;
5260        info->port.tty = NULL;
5261
5262        /* assume failure */
5263        info->init_error = DiagStatus_DmaFailure;
5264
5265        /* build and send transmit frame */
5266        for (count = 0; count < TESTFRAMESIZE;++count)
5267                buf[count] = (unsigned char)count;
5268
5269        memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5270
5271        /* program hardware for HDLC and enabled receiver */
5272        spin_lock_irqsave(&info->lock,flags);
5273        hdlc_mode(info);
5274        enable_loopback(info,1);
5275        rx_start(info);
5276        info->tx_count = count;
5277        tx_load_dma_buffer(info,buf,count);
5278        tx_start(info);
5279        spin_unlock_irqrestore(&info->lock,flags);
5280
5281        /* wait for receive complete */
5282        /* Set a timeout for waiting for interrupt. */
5283        for ( timeout = 100; timeout; --timeout ) {
5284                msleep_interruptible(10);
5285
5286                if (rx_get_frame(info)) {
5287                        rc = true;
5288                        break;
5289                }
5290        }
5291
5292        /* verify received frame length and contents */
5293        if (rc &&
5294            ( info->tmp_rx_buf_count != count ||
5295              memcmp(buf, info->tmp_rx_buf,count))) {
5296                rc = false;
5297        }
5298
5299        spin_lock_irqsave(&info->lock,flags);
5300        reset_adapter(info);
5301        spin_unlock_irqrestore(&info->lock,flags);
5302
5303        info->params.clock_speed = speed;
5304        info->port.tty = oldtty;
5305
5306        return rc;
5307}
5308
5309/* Perform diagnostics on hardware
5310 */
5311static int adapter_test( SLMP_INFO *info )
5312{
5313        unsigned long flags;
5314        if ( debug_level >= DEBUG_LEVEL_INFO )
5315                printk( "%s(%d):Testing device %s\n",
5316                        __FILE__,__LINE__,info->device_name );
5317
5318        spin_lock_irqsave(&info->lock,flags);
5319        init_adapter(info);
5320        spin_unlock_irqrestore(&info->lock,flags);
5321
5322        info->port_array[0]->port_count = 0;
5323
5324        if ( register_test(info->port_array[0]) &&
5325                register_test(info->port_array[1])) {
5326
5327                info->port_array[0]->port_count = 2;
5328
5329                if ( register_test(info->port_array[2]) &&
5330                        register_test(info->port_array[3]) )
5331                        info->port_array[0]->port_count += 2;
5332        }
5333        else {
5334                printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5335                        __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5336                return -ENODEV;
5337        }
5338
5339        if ( !irq_test(info->port_array[0]) ||
5340                !irq_test(info->port_array[1]) ||
5341                 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5342                 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5343                printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5344                        __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5345                return -ENODEV;
5346        }
5347
5348        if (!loopback_test(info->port_array[0]) ||
5349                !loopback_test(info->port_array[1]) ||
5350                 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5351                 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5352                printk( "%s(%d):DMA test failure for device %s\n",
5353                        __FILE__,__LINE__,info->device_name);
5354                return -ENODEV;
5355        }
5356
5357        if ( debug_level >= DEBUG_LEVEL_INFO )
5358                printk( "%s(%d):device %s passed diagnostics\n",
5359                        __FILE__,__LINE__,info->device_name );
5360
5361        info->port_array[0]->init_error = 0;
5362        info->port_array[1]->init_error = 0;
5363        if ( info->port_count > 2 ) {
5364                info->port_array[2]->init_error = 0;
5365                info->port_array[3]->init_error = 0;
5366        }
5367
5368        return 0;
5369}
5370
5371/* Test the shared memory on a PCI adapter.
5372 */
5373static bool memory_test(SLMP_INFO *info)
5374{
5375        static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5376                0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5377        unsigned long count = ARRAY_SIZE(testval);
5378        unsigned long i;
5379        unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5380        unsigned long * addr = (unsigned long *)info->memory_base;
5381
5382        /* Test data lines with test pattern at one location. */
5383
5384        for ( i = 0 ; i < count ; i++ ) {
5385                *addr = testval[i];
5386                if ( *addr != testval[i] )
5387                        return false;
5388        }
5389
5390        /* Test address lines with incrementing pattern over */
5391        /* entire address range. */
5392
5393        for ( i = 0 ; i < limit ; i++ ) {
5394                *addr = i * 4;
5395                addr++;
5396        }
5397
5398        addr = (unsigned long *)info->memory_base;
5399
5400        for ( i = 0 ; i < limit ; i++ ) {
5401                if ( *addr != i * 4 )
5402                        return false;
5403                addr++;
5404        }
5405
5406        memset( info->memory_base, 0, SCA_MEM_SIZE );
5407        return true;
5408}
5409
5410/* Load data into PCI adapter shared memory.
5411 *
5412 * The PCI9050 releases control of the local bus
5413 * after completing the current read or write operation.
5414 *
5415 * While the PCI9050 write FIFO not empty, the
5416 * PCI9050 treats all of the writes as a single transaction
5417 * and does not release the bus. This causes DMA latency problems
5418 * at high speeds when copying large data blocks to the shared memory.
5419 *
5420 * This function breaks a write into multiple transations by
5421 * interleaving a read which flushes the write FIFO and 'completes'
5422 * the write transation. This allows any pending DMA request to gain control
5423 * of the local bus in a timely fasion.
5424 */
5425static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5426{
5427        /* A load interval of 16 allows for 4 32-bit writes at */
5428        /* 136ns each for a maximum latency of 542ns on the local bus.*/
5429
5430        unsigned short interval = count / sca_pci_load_interval;
5431        unsigned short i;
5432
5433        for ( i = 0 ; i < interval ; i++ )
5434        {
5435                memcpy(dest, src, sca_pci_load_interval);
5436                read_status_reg(info);
5437                dest += sca_pci_load_interval;
5438                src += sca_pci_load_interval;
5439        }
5440
5441        memcpy(dest, src, count % sca_pci_load_interval);
5442}
5443
5444static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5445{
5446        int i;
5447        int linecount;
5448        if (xmit)
5449                printk("%s tx data:\n",info->device_name);
5450        else
5451                printk("%s rx data:\n",info->device_name);
5452
5453        while(count) {
5454                if (count > 16)
5455                        linecount = 16;
5456                else
5457                        linecount = count;
5458
5459                for(i=0;i<linecount;i++)
5460                        printk("%02X ",(unsigned char)data[i]);
5461                for(;i<17;i++)
5462                        printk("   ");
5463                for(i=0;i<linecount;i++) {
5464                        if (data[i]>=040 && data[i]<=0176)
5465                                printk("%c",data[i]);
5466                        else
5467                                printk(".");
5468                }
5469                printk("\n");
5470
5471                data  += linecount;
5472                count -= linecount;
5473        }
5474}       /* end of trace_block() */
5475
5476/* called when HDLC frame times out
5477 * update stats and do tx completion processing
5478 */
5479static void tx_timeout(unsigned long context)
5480{
5481        SLMP_INFO *info = (SLMP_INFO*)context;
5482        unsigned long flags;
5483
5484        if ( debug_level >= DEBUG_LEVEL_INFO )
5485                printk( "%s(%d):%s tx_timeout()\n",
5486                        __FILE__,__LINE__,info->device_name);
5487        if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5488                info->icount.txtimeout++;
5489        }
5490        spin_lock_irqsave(&info->lock,flags);
5491        info->tx_active = false;
5492        info->tx_count = info->tx_put = info->tx_get = 0;
5493
5494        spin_unlock_irqrestore(&info->lock,flags);
5495
5496#if SYNCLINK_GENERIC_HDLC
5497        if (info->netcount)
5498                hdlcdev_tx_done(info);
5499        else
5500#endif
5501                bh_transmit(info);
5502}
5503
5504/* called to periodically check the DSR/RI modem signal input status
5505 */
5506static void status_timeout(unsigned long context)
5507{
5508        u16 status = 0;
5509        SLMP_INFO *info = (SLMP_INFO*)context;
5510        unsigned long flags;
5511        unsigned char delta;
5512
5513
5514        spin_lock_irqsave(&info->lock,flags);
5515        get_signals(info);
5516        spin_unlock_irqrestore(&info->lock,flags);
5517
5518        /* check for DSR/RI state change */
5519
5520        delta = info->old_signals ^ info->serial_signals;
5521        info->old_signals = info->serial_signals;
5522
5523        if (delta & SerialSignal_DSR)
5524                status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5525
5526        if (delta & SerialSignal_RI)
5527                status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5528
5529        if (delta & SerialSignal_DCD)
5530                status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5531
5532        if (delta & SerialSignal_CTS)
5533                status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5534
5535        if (status)
5536                isr_io_pin(info,status);
5537
5538        mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5539}
5540
5541
5542/* Register Access Routines -
5543 * All registers are memory mapped
5544 */
5545#define CALC_REGADDR() \
5546        unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5547        if (info->port_num > 1) \
5548                RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5549        if ( info->port_num & 1) { \
5550                if (Addr > 0x7f) \
5551                        RegAddr += 0x40;        /* DMA access */ \
5552                else if (Addr > 0x1f && Addr < 0x60) \
5553                        RegAddr += 0x20;        /* MSCI access */ \
5554        }
5555
5556
5557static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5558{
5559        CALC_REGADDR();
5560        return *RegAddr;
5561}
5562static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5563{
5564        CALC_REGADDR();
5565        *RegAddr = Value;
5566}
5567
5568static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5569{
5570        CALC_REGADDR();
5571        return *((u16 *)RegAddr);
5572}
5573
5574static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5575{
5576        CALC_REGADDR();
5577        *((u16 *)RegAddr) = Value;
5578}
5579
5580static unsigned char read_status_reg(SLMP_INFO * info)
5581{
5582        unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5583        return *RegAddr;
5584}
5585
5586static void write_control_reg(SLMP_INFO * info)
5587{
5588        unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5589        *RegAddr = info->port_array[0]->ctrlreg_value;
5590}
5591
5592
5593static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5594                                          const struct pci_device_id *ent)
5595{
5596        if (pci_enable_device(dev)) {
5597                printk("error enabling pci device %p\n", dev);
5598                return -EIO;
5599        }
5600        device_init( ++synclinkmp_adapter_count, dev );
5601        return 0;
5602}
5603
5604static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5605{
5606}
5607
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