linux/sound/soc/codecs/wm8903.c
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   1/*
   2 * wm8903.c  --  WM8903 ALSA SoC Audio driver
   3 *
   4 * Copyright 2008 Wolfson Microelectronics
   5 *
   6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11 *
  12 * TODO:
  13 *  - TDM mode configuration.
  14 *  - Mic detect.
  15 *  - Digital microphone support.
  16 *  - Interrupt support (mic detect and sequencer).
  17 */
  18
  19#include <linux/module.h>
  20#include <linux/moduleparam.h>
  21#include <linux/init.h>
  22#include <linux/delay.h>
  23#include <linux/pm.h>
  24#include <linux/i2c.h>
  25#include <linux/platform_device.h>
  26#include <sound/core.h>
  27#include <sound/pcm.h>
  28#include <sound/pcm_params.h>
  29#include <sound/tlv.h>
  30#include <sound/soc.h>
  31#include <sound/soc-dapm.h>
  32#include <sound/initval.h>
  33
  34#include "wm8903.h"
  35
  36/* Register defaults at reset */
  37static u16 wm8903_reg_defaults[] = {
  38        0x8903,     /* R0   - SW Reset and ID */
  39        0x0000,     /* R1   - Revision Number */
  40        0x0000,     /* R2 */
  41        0x0000,     /* R3 */
  42        0x0018,     /* R4   - Bias Control 0 */
  43        0x0000,     /* R5   - VMID Control 0 */
  44        0x0000,     /* R6   - Mic Bias Control 0 */
  45        0x0000,     /* R7 */
  46        0x0001,     /* R8   - Analogue DAC 0 */
  47        0x0000,     /* R9 */
  48        0x0001,     /* R10  - Analogue ADC 0 */
  49        0x0000,     /* R11 */
  50        0x0000,     /* R12  - Power Management 0 */
  51        0x0000,     /* R13  - Power Management 1 */
  52        0x0000,     /* R14  - Power Management 2 */
  53        0x0000,     /* R15  - Power Management 3 */
  54        0x0000,     /* R16  - Power Management 4 */
  55        0x0000,     /* R17  - Power Management 5 */
  56        0x0000,     /* R18  - Power Management 6 */
  57        0x0000,     /* R19 */
  58        0x0400,     /* R20  - Clock Rates 0 */
  59        0x0D07,     /* R21  - Clock Rates 1 */
  60        0x0000,     /* R22  - Clock Rates 2 */
  61        0x0000,     /* R23 */
  62        0x0050,     /* R24  - Audio Interface 0 */
  63        0x0242,     /* R25  - Audio Interface 1 */
  64        0x0008,     /* R26  - Audio Interface 2 */
  65        0x0022,     /* R27  - Audio Interface 3 */
  66        0x0000,     /* R28 */
  67        0x0000,     /* R29 */
  68        0x00C0,     /* R30  - DAC Digital Volume Left */
  69        0x00C0,     /* R31  - DAC Digital Volume Right */
  70        0x0000,     /* R32  - DAC Digital 0 */
  71        0x0000,     /* R33  - DAC Digital 1 */
  72        0x0000,     /* R34 */
  73        0x0000,     /* R35 */
  74        0x00C0,     /* R36  - ADC Digital Volume Left */
  75        0x00C0,     /* R37  - ADC Digital Volume Right */
  76        0x0000,     /* R38  - ADC Digital 0 */
  77        0x0073,     /* R39  - Digital Microphone 0 */
  78        0x09BF,     /* R40  - DRC 0 */
  79        0x3241,     /* R41  - DRC 1 */
  80        0x0020,     /* R42  - DRC 2 */
  81        0x0000,     /* R43  - DRC 3 */
  82        0x0085,     /* R44  - Analogue Left Input 0 */
  83        0x0085,     /* R45  - Analogue Right Input 0 */
  84        0x0044,     /* R46  - Analogue Left Input 1 */
  85        0x0044,     /* R47  - Analogue Right Input 1 */
  86        0x0000,     /* R48 */
  87        0x0000,     /* R49 */
  88        0x0008,     /* R50  - Analogue Left Mix 0 */
  89        0x0004,     /* R51  - Analogue Right Mix 0 */
  90        0x0000,     /* R52  - Analogue Spk Mix Left 0 */
  91        0x0000,     /* R53  - Analogue Spk Mix Left 1 */
  92        0x0000,     /* R54  - Analogue Spk Mix Right 0 */
  93        0x0000,     /* R55  - Analogue Spk Mix Right 1 */
  94        0x0000,     /* R56 */
  95        0x002D,     /* R57  - Analogue OUT1 Left */
  96        0x002D,     /* R58  - Analogue OUT1 Right */
  97        0x0039,     /* R59  - Analogue OUT2 Left */
  98        0x0039,     /* R60  - Analogue OUT2 Right */
  99        0x0100,     /* R61 */
 100        0x0139,     /* R62  - Analogue OUT3 Left */
 101        0x0139,     /* R63  - Analogue OUT3 Right */
 102        0x0000,     /* R64 */
 103        0x0000,     /* R65  - Analogue SPK Output Control 0 */
 104        0x0000,     /* R66 */
 105        0x0010,     /* R67  - DC Servo 0 */
 106        0x0100,     /* R68 */
 107        0x00A4,     /* R69  - DC Servo 2 */
 108        0x0807,     /* R70 */
 109        0x0000,     /* R71 */
 110        0x0000,     /* R72 */
 111        0x0000,     /* R73 */
 112        0x0000,     /* R74 */
 113        0x0000,     /* R75 */
 114        0x0000,     /* R76 */
 115        0x0000,     /* R77 */
 116        0x0000,     /* R78 */
 117        0x000E,     /* R79 */
 118        0x0000,     /* R80 */
 119        0x0000,     /* R81 */
 120        0x0000,     /* R82 */
 121        0x0000,     /* R83 */
 122        0x0000,     /* R84 */
 123        0x0000,     /* R85 */
 124        0x0000,     /* R86 */
 125        0x0006,     /* R87 */
 126        0x0000,     /* R88 */
 127        0x0000,     /* R89 */
 128        0x0000,     /* R90  - Analogue HP 0 */
 129        0x0060,     /* R91 */
 130        0x0000,     /* R92 */
 131        0x0000,     /* R93 */
 132        0x0000,     /* R94  - Analogue Lineout 0 */
 133        0x0060,     /* R95 */
 134        0x0000,     /* R96 */
 135        0x0000,     /* R97 */
 136        0x0000,     /* R98  - Charge Pump 0 */
 137        0x1F25,     /* R99 */
 138        0x2B19,     /* R100 */
 139        0x01C0,     /* R101 */
 140        0x01EF,     /* R102 */
 141        0x2B00,     /* R103 */
 142        0x0000,     /* R104 - Class W 0 */
 143        0x01C0,     /* R105 */
 144        0x1C10,     /* R106 */
 145        0x0000,     /* R107 */
 146        0x0000,     /* R108 - Write Sequencer 0 */
 147        0x0000,     /* R109 - Write Sequencer 1 */
 148        0x0000,     /* R110 - Write Sequencer 2 */
 149        0x0000,     /* R111 - Write Sequencer 3 */
 150        0x0000,     /* R112 - Write Sequencer 4 */
 151        0x0000,     /* R113 */
 152        0x0000,     /* R114 - Control Interface */
 153        0x0000,     /* R115 */
 154        0x00A8,     /* R116 - GPIO Control 1 */
 155        0x00A8,     /* R117 - GPIO Control 2 */
 156        0x00A8,     /* R118 - GPIO Control 3 */
 157        0x0220,     /* R119 - GPIO Control 4 */
 158        0x01A0,     /* R120 - GPIO Control 5 */
 159        0x0000,     /* R121 - Interrupt Status 1 */
 160        0xFFFF,     /* R122 - Interrupt Status 1 Mask */
 161        0x0000,     /* R123 - Interrupt Polarity 1 */
 162        0x0000,     /* R124 */
 163        0x0003,     /* R125 */
 164        0x0000,     /* R126 - Interrupt Control */
 165        0x0000,     /* R127 */
 166        0x0005,     /* R128 */
 167        0x0000,     /* R129 - Control Interface Test 1 */
 168        0x0000,     /* R130 */
 169        0x0000,     /* R131 */
 170        0x0000,     /* R132 */
 171        0x0000,     /* R133 */
 172        0x0000,     /* R134 */
 173        0x03FF,     /* R135 */
 174        0x0007,     /* R136 */
 175        0x0040,     /* R137 */
 176        0x0000,     /* R138 */
 177        0x0000,     /* R139 */
 178        0x0000,     /* R140 */
 179        0x0000,     /* R141 */
 180        0x0000,     /* R142 */
 181        0x0000,     /* R143 */
 182        0x0000,     /* R144 */
 183        0x0000,     /* R145 */
 184        0x0000,     /* R146 */
 185        0x0000,     /* R147 */
 186        0x4000,     /* R148 */
 187        0x6810,     /* R149 - Charge Pump Test 1 */
 188        0x0004,     /* R150 */
 189        0x0000,     /* R151 */
 190        0x0000,     /* R152 */
 191        0x0000,     /* R153 */
 192        0x0000,     /* R154 */
 193        0x0000,     /* R155 */
 194        0x0000,     /* R156 */
 195        0x0000,     /* R157 */
 196        0x0000,     /* R158 */
 197        0x0000,     /* R159 */
 198        0x0000,     /* R160 */
 199        0x0000,     /* R161 */
 200        0x0000,     /* R162 */
 201        0x0000,     /* R163 */
 202        0x0028,     /* R164 - Clock Rate Test 4 */
 203        0x0004,     /* R165 */
 204        0x0000,     /* R166 */
 205        0x0060,     /* R167 */
 206        0x0000,     /* R168 */
 207        0x0000,     /* R169 */
 208        0x0000,     /* R170 */
 209        0x0000,     /* R171 */
 210        0x0000,     /* R172 - Analogue Output Bias 0 */
 211};
 212
 213struct wm8903_priv {
 214        struct snd_soc_codec codec;
 215        u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
 216
 217        int sysclk;
 218
 219        /* Reference counts */
 220        int charge_pump_users;
 221        int class_w_users;
 222        int playback_active;
 223        int capture_active;
 224
 225        struct snd_pcm_substream *master_substream;
 226        struct snd_pcm_substream *slave_substream;
 227};
 228
 229
 230static unsigned int wm8903_read_reg_cache(struct snd_soc_codec *codec,
 231                                                 unsigned int reg)
 232{
 233        u16 *cache = codec->reg_cache;
 234
 235        BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
 236
 237        return cache[reg];
 238}
 239
 240static unsigned int wm8903_hw_read(struct snd_soc_codec *codec, u8 reg)
 241{
 242        struct i2c_msg xfer[2];
 243        u16 data;
 244        int ret;
 245        struct i2c_client *client = codec->control_data;
 246
 247        /* Write register */
 248        xfer[0].addr = client->addr;
 249        xfer[0].flags = 0;
 250        xfer[0].len = 1;
 251        xfer[0].buf = &reg;
 252
 253        /* Read data */
 254        xfer[1].addr = client->addr;
 255        xfer[1].flags = I2C_M_RD;
 256        xfer[1].len = 2;
 257        xfer[1].buf = (u8 *)&data;
 258
 259        ret = i2c_transfer(client->adapter, xfer, 2);
 260        if (ret != 2) {
 261                pr_err("i2c_transfer returned %d\n", ret);
 262                return 0;
 263        }
 264
 265        return (data >> 8) | ((data & 0xff) << 8);
 266}
 267
 268static unsigned int wm8903_read(struct snd_soc_codec *codec,
 269                                unsigned int reg)
 270{
 271        switch (reg) {
 272        case WM8903_SW_RESET_AND_ID:
 273        case WM8903_REVISION_NUMBER:
 274        case WM8903_INTERRUPT_STATUS_1:
 275        case WM8903_WRITE_SEQUENCER_4:
 276                return wm8903_hw_read(codec, reg);
 277
 278        default:
 279                return wm8903_read_reg_cache(codec, reg);
 280        }
 281}
 282
 283static void wm8903_write_reg_cache(struct snd_soc_codec *codec,
 284                                   u16 reg, unsigned int value)
 285{
 286        u16 *cache = codec->reg_cache;
 287
 288        BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
 289
 290        switch (reg) {
 291        case WM8903_SW_RESET_AND_ID:
 292        case WM8903_REVISION_NUMBER:
 293                break;
 294
 295        default:
 296                cache[reg] = value;
 297                break;
 298        }
 299}
 300
 301static int wm8903_write(struct snd_soc_codec *codec, unsigned int reg,
 302                        unsigned int value)
 303{
 304        u8 data[3];
 305
 306        wm8903_write_reg_cache(codec, reg, value);
 307
 308        /* Data format is 1 byte of address followed by 2 bytes of data */
 309        data[0] = reg;
 310        data[1] = (value >> 8) & 0xff;
 311        data[2] = value & 0xff;
 312
 313        if (codec->hw_write(codec->control_data, data, 3) == 2)
 314                return 0;
 315        else
 316                return -EIO;
 317}
 318
 319static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
 320{
 321        u16 reg[5];
 322        struct i2c_client *i2c = codec->control_data;
 323
 324        BUG_ON(start > 48);
 325
 326        /* Enable the sequencer */
 327        reg[0] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_0);
 328        reg[0] |= WM8903_WSEQ_ENA;
 329        wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
 330
 331        dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
 332
 333        wm8903_write(codec, WM8903_WRITE_SEQUENCER_3,
 334                     start | WM8903_WSEQ_START);
 335
 336        /* Wait for it to complete.  If we have the interrupt wired up then
 337         * we could block waiting for an interrupt, though polling may still
 338         * be desirable for diagnostic purposes.
 339         */
 340        do {
 341                msleep(10);
 342
 343                reg[4] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_4);
 344        } while (reg[4] & WM8903_WSEQ_BUSY);
 345
 346        dev_dbg(&i2c->dev, "Sequence complete\n");
 347
 348        /* Disable the sequencer again */
 349        wm8903_write(codec, WM8903_WRITE_SEQUENCER_0,
 350                     reg[0] & ~WM8903_WSEQ_ENA);
 351
 352        return 0;
 353}
 354
 355static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
 356{
 357        int i;
 358
 359        /* There really ought to be something better we can do here :/ */
 360        for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
 361                cache[i] = wm8903_hw_read(codec, i);
 362}
 363
 364static void wm8903_reset(struct snd_soc_codec *codec)
 365{
 366        wm8903_write(codec, WM8903_SW_RESET_AND_ID, 0);
 367        memcpy(codec->reg_cache, wm8903_reg_defaults,
 368               sizeof(wm8903_reg_defaults));
 369}
 370
 371#define WM8903_OUTPUT_SHORT 0x8
 372#define WM8903_OUTPUT_OUT   0x4
 373#define WM8903_OUTPUT_INT   0x2
 374#define WM8903_OUTPUT_IN    0x1
 375
 376/*
 377 * Event for headphone and line out amplifier power changes.  Special
 378 * power up/down sequences are required in order to maximise pop/click
 379 * performance.
 380 */
 381static int wm8903_output_event(struct snd_soc_dapm_widget *w,
 382                               struct snd_kcontrol *kcontrol, int event)
 383{
 384        struct snd_soc_codec *codec = w->codec;
 385        struct wm8903_priv *wm8903 = codec->private_data;
 386        struct i2c_client *i2c = codec->control_data;
 387        u16 val;
 388        u16 reg;
 389        int shift;
 390        u16 cp_reg = wm8903_read(codec, WM8903_CHARGE_PUMP_0);
 391
 392        switch (w->reg) {
 393        case WM8903_POWER_MANAGEMENT_2:
 394                reg = WM8903_ANALOGUE_HP_0;
 395                break;
 396        case WM8903_POWER_MANAGEMENT_3:
 397                reg = WM8903_ANALOGUE_LINEOUT_0;
 398                break;
 399        default:
 400                BUG();
 401                return -EINVAL;  /* Spurious warning from some compilers */
 402        }
 403
 404        switch (w->shift) {
 405        case 0:
 406                shift = 0;
 407                break;
 408        case 1:
 409                shift = 4;
 410                break;
 411        default:
 412                BUG();
 413                return -EINVAL;  /* Spurious warning from some compilers */
 414        }
 415
 416        if (event & SND_SOC_DAPM_PRE_PMU) {
 417                val = wm8903_read(codec, reg);
 418
 419                /* Short the output */
 420                val &= ~(WM8903_OUTPUT_SHORT << shift);
 421                wm8903_write(codec, reg, val);
 422
 423                wm8903->charge_pump_users++;
 424
 425                dev_dbg(&i2c->dev, "Charge pump use count now %d\n",
 426                        wm8903->charge_pump_users);
 427
 428                if (wm8903->charge_pump_users == 1) {
 429                        dev_dbg(&i2c->dev, "Enabling charge pump\n");
 430                        wm8903_write(codec, WM8903_CHARGE_PUMP_0,
 431                                     cp_reg | WM8903_CP_ENA);
 432                        mdelay(4);
 433                }
 434        }
 435
 436        if (event & SND_SOC_DAPM_POST_PMU) {
 437                val = wm8903_read(codec, reg);
 438
 439                val |= (WM8903_OUTPUT_IN << shift);
 440                wm8903_write(codec, reg, val);
 441
 442                val |= (WM8903_OUTPUT_INT << shift);
 443                wm8903_write(codec, reg, val);
 444
 445                /* Turn on the output ENA_OUTP */
 446                val |= (WM8903_OUTPUT_OUT << shift);
 447                wm8903_write(codec, reg, val);
 448
 449                /* Remove the short */
 450                val |= (WM8903_OUTPUT_SHORT << shift);
 451                wm8903_write(codec, reg, val);
 452        }
 453
 454        if (event & SND_SOC_DAPM_PRE_PMD) {
 455                val = wm8903_read(codec, reg);
 456
 457                /* Short the output */
 458                val &= ~(WM8903_OUTPUT_SHORT << shift);
 459                wm8903_write(codec, reg, val);
 460
 461                /* Then disable the intermediate and output stages */
 462                val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
 463                          WM8903_OUTPUT_IN) << shift);
 464                wm8903_write(codec, reg, val);
 465        }
 466
 467        if (event & SND_SOC_DAPM_POST_PMD) {
 468                wm8903->charge_pump_users--;
 469
 470                dev_dbg(&i2c->dev, "Charge pump use count now %d\n",
 471                        wm8903->charge_pump_users);
 472
 473                if (wm8903->charge_pump_users == 0) {
 474                        dev_dbg(&i2c->dev, "Disabling charge pump\n");
 475                        wm8903_write(codec, WM8903_CHARGE_PUMP_0,
 476                                     cp_reg & ~WM8903_CP_ENA);
 477                }
 478        }
 479
 480        return 0;
 481}
 482
 483/*
 484 * When used with DAC outputs only the WM8903 charge pump supports
 485 * operation in class W mode, providing very low power consumption
 486 * when used with digital sources.  Enable and disable this mode
 487 * automatically depending on the mixer configuration.
 488 *
 489 * All the relevant controls are simple switches.
 490 */
 491static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
 492                              struct snd_ctl_elem_value *ucontrol)
 493{
 494        struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
 495        struct snd_soc_codec *codec = widget->codec;
 496        struct wm8903_priv *wm8903 = codec->private_data;
 497        struct i2c_client *i2c = codec->control_data;
 498        u16 reg;
 499        int ret;
 500
 501        reg = wm8903_read(codec, WM8903_CLASS_W_0);
 502
 503        /* Turn it off if we're about to enable bypass */
 504        if (ucontrol->value.integer.value[0]) {
 505                if (wm8903->class_w_users == 0) {
 506                        dev_dbg(&i2c->dev, "Disabling Class W\n");
 507                        wm8903_write(codec, WM8903_CLASS_W_0, reg &
 508                                     ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
 509                }
 510                wm8903->class_w_users++;
 511        }
 512
 513        /* Implement the change */
 514        ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
 515
 516        /* If we've just disabled the last bypass path turn Class W on */
 517        if (!ucontrol->value.integer.value[0]) {
 518                if (wm8903->class_w_users == 1) {
 519                        dev_dbg(&i2c->dev, "Enabling Class W\n");
 520                        wm8903_write(codec, WM8903_CLASS_W_0, reg |
 521                                     WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
 522                }
 523                wm8903->class_w_users--;
 524        }
 525
 526        dev_dbg(&i2c->dev, "Bypass use count now %d\n",
 527                wm8903->class_w_users);
 528
 529        return ret;
 530}
 531
 532#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
 533{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 534        .info = snd_soc_info_volsw, \
 535        .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
 536        .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
 537
 538
 539/* ALSA can only do steps of .01dB */
 540static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 541
 542static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
 543
 544static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
 545static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
 546static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
 547static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
 548static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
 549
 550static const char *drc_slope_text[] = {
 551        "1", "1/2", "1/4", "1/8", "1/16", "0"
 552};
 553
 554static const struct soc_enum drc_slope_r0 =
 555        SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
 556
 557static const struct soc_enum drc_slope_r1 =
 558        SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
 559
 560static const char *drc_attack_text[] = {
 561        "instantaneous",
 562        "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
 563        "46.4ms", "92.8ms", "185.6ms"
 564};
 565
 566static const struct soc_enum drc_attack =
 567        SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
 568
 569static const char *drc_decay_text[] = {
 570        "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
 571        "23.87s", "47.56s"
 572};
 573
 574static const struct soc_enum drc_decay =
 575        SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
 576
 577static const char *drc_ff_delay_text[] = {
 578        "5 samples", "9 samples"
 579};
 580
 581static const struct soc_enum drc_ff_delay =
 582        SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
 583
 584static const char *drc_qr_decay_text[] = {
 585        "0.725ms", "1.45ms", "5.8ms"
 586};
 587
 588static const struct soc_enum drc_qr_decay =
 589        SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
 590
 591static const char *drc_smoothing_text[] = {
 592        "Low", "Medium", "High"
 593};
 594
 595static const struct soc_enum drc_smoothing =
 596        SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
 597
 598static const char *soft_mute_text[] = {
 599        "Fast (fs/2)", "Slow (fs/32)"
 600};
 601
 602static const struct soc_enum soft_mute =
 603        SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
 604
 605static const char *mute_mode_text[] = {
 606        "Hard", "Soft"
 607};
 608
 609static const struct soc_enum mute_mode =
 610        SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
 611
 612static const char *dac_deemphasis_text[] = {
 613        "Disabled", "32kHz", "44.1kHz", "48kHz"
 614};
 615
 616static const struct soc_enum dac_deemphasis =
 617        SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
 618
 619static const char *companding_text[] = {
 620        "ulaw", "alaw"
 621};
 622
 623static const struct soc_enum dac_companding =
 624        SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
 625
 626static const struct soc_enum adc_companding =
 627        SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
 628
 629static const char *input_mode_text[] = {
 630        "Single-Ended", "Differential Line", "Differential Mic"
 631};
 632
 633static const struct soc_enum linput_mode_enum =
 634        SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
 635
 636static const struct soc_enum rinput_mode_enum =
 637        SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
 638
 639static const char *linput_mux_text[] = {
 640        "IN1L", "IN2L", "IN3L"
 641};
 642
 643static const struct soc_enum linput_enum =
 644        SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
 645
 646static const struct soc_enum linput_inv_enum =
 647        SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
 648
 649static const char *rinput_mux_text[] = {
 650        "IN1R", "IN2R", "IN3R"
 651};
 652
 653static const struct soc_enum rinput_enum =
 654        SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
 655
 656static const struct soc_enum rinput_inv_enum =
 657        SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
 658
 659
 660static const struct snd_kcontrol_new wm8903_snd_controls[] = {
 661
 662/* Input PGAs - No TLV since the scale depends on PGA mode */
 663SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
 664           7, 1, 1),
 665SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
 666           0, 31, 0),
 667SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
 668           6, 1, 0),
 669
 670SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
 671           7, 1, 1),
 672SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
 673           0, 31, 0),
 674SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
 675           6, 1, 0),
 676
 677/* ADCs */
 678SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
 679SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
 680SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
 681SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8903_DRC_3, 5, 124, 1,
 682               drc_tlv_thresh),
 683SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
 684SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
 685SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
 686SOC_ENUM("DRC Attack Rate", drc_attack),
 687SOC_ENUM("DRC Decay Rate", drc_decay),
 688SOC_ENUM("DRC FF Delay", drc_ff_delay),
 689SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
 690SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
 691SOC_SINGLE_TLV("DRC QR Threashold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
 692SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
 693SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
 694SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
 695SOC_ENUM("DRC Smoothing Threashold", drc_smoothing),
 696SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
 697
 698SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
 699                 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
 700SOC_ENUM("ADC Companding Mode", adc_companding),
 701SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
 702
 703/* DAC */
 704SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
 705                 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
 706SOC_ENUM("DAC Soft Mute Rate", soft_mute),
 707SOC_ENUM("DAC Mute Mode", mute_mode),
 708SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
 709SOC_ENUM("DAC De-emphasis", dac_deemphasis),
 710SOC_SINGLE("DAC Sloping Stopband Filter Switch",
 711           WM8903_DAC_DIGITAL_1, 11, 1, 0),
 712SOC_ENUM("DAC Companding Mode", dac_companding),
 713SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
 714
 715/* Headphones */
 716SOC_DOUBLE_R("Headphone Switch",
 717             WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
 718             8, 1, 1),
 719SOC_DOUBLE_R("Headphone ZC Switch",
 720             WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
 721             6, 1, 0),
 722SOC_DOUBLE_R_TLV("Headphone Volume",
 723                 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
 724                 0, 63, 0, out_tlv),
 725
 726/* Line out */
 727SOC_DOUBLE_R("Line Out Switch",
 728             WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
 729             8, 1, 1),
 730SOC_DOUBLE_R("Line Out ZC Switch",
 731             WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
 732             6, 1, 0),
 733SOC_DOUBLE_R_TLV("Line Out Volume",
 734                 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
 735                 0, 63, 0, out_tlv),
 736
 737/* Speaker */
 738SOC_DOUBLE_R("Speaker Switch",
 739             WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
 740SOC_DOUBLE_R("Speaker ZC Switch",
 741             WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
 742SOC_DOUBLE_R_TLV("Speaker Volume",
 743                 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
 744                 0, 63, 0, out_tlv),
 745};
 746
 747static const struct snd_kcontrol_new linput_mode_mux =
 748        SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
 749
 750static const struct snd_kcontrol_new rinput_mode_mux =
 751        SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
 752
 753static const struct snd_kcontrol_new linput_mux =
 754        SOC_DAPM_ENUM("Left Input Mux", linput_enum);
 755
 756static const struct snd_kcontrol_new linput_inv_mux =
 757        SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
 758
 759static const struct snd_kcontrol_new rinput_mux =
 760        SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
 761
 762static const struct snd_kcontrol_new rinput_inv_mux =
 763        SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
 764
 765static const struct snd_kcontrol_new left_output_mixer[] = {
 766SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
 767SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
 768SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
 769SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
 770};
 771
 772static const struct snd_kcontrol_new right_output_mixer[] = {
 773SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
 774SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
 775SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
 776SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
 777};
 778
 779static const struct snd_kcontrol_new left_speaker_mixer[] = {
 780SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
 781SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
 782SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
 783SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
 784                0, 1, 0),
 785};
 786
 787static const struct snd_kcontrol_new right_speaker_mixer[] = {
 788SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
 789SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
 790SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
 791                1, 1, 0),
 792SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
 793                0, 1, 0),
 794};
 795
 796static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
 797SND_SOC_DAPM_INPUT("IN1L"),
 798SND_SOC_DAPM_INPUT("IN1R"),
 799SND_SOC_DAPM_INPUT("IN2L"),
 800SND_SOC_DAPM_INPUT("IN2R"),
 801SND_SOC_DAPM_INPUT("IN3L"),
 802SND_SOC_DAPM_INPUT("IN3R"),
 803
 804SND_SOC_DAPM_OUTPUT("HPOUTL"),
 805SND_SOC_DAPM_OUTPUT("HPOUTR"),
 806SND_SOC_DAPM_OUTPUT("LINEOUTL"),
 807SND_SOC_DAPM_OUTPUT("LINEOUTR"),
 808SND_SOC_DAPM_OUTPUT("LOP"),
 809SND_SOC_DAPM_OUTPUT("LON"),
 810SND_SOC_DAPM_OUTPUT("ROP"),
 811SND_SOC_DAPM_OUTPUT("RON"),
 812
 813SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
 814
 815SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
 816SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
 817                 &linput_inv_mux),
 818SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
 819
 820SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
 821SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
 822                 &rinput_inv_mux),
 823SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
 824
 825SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
 826SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
 827
 828SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
 829SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
 830
 831SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
 832SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
 833
 834SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
 835                   left_output_mixer, ARRAY_SIZE(left_output_mixer)),
 836SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
 837                   right_output_mixer, ARRAY_SIZE(right_output_mixer)),
 838
 839SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
 840                   left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
 841SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
 842                   right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
 843
 844SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
 845                   1, 0, NULL, 0, wm8903_output_event,
 846                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 847                   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
 848SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
 849                   0, 0, NULL, 0, wm8903_output_event,
 850                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 851                   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
 852
 853SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
 854                   NULL, 0, wm8903_output_event,
 855                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 856                   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
 857SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
 858                   NULL, 0, wm8903_output_event,
 859                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 860                   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
 861
 862SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
 863                 NULL, 0),
 864SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
 865                 NULL, 0),
 866
 867};
 868
 869static const struct snd_soc_dapm_route intercon[] = {
 870
 871        { "Left Input Mux", "IN1L", "IN1L" },
 872        { "Left Input Mux", "IN2L", "IN2L" },
 873        { "Left Input Mux", "IN3L", "IN3L" },
 874
 875        { "Left Input Inverting Mux", "IN1L", "IN1L" },
 876        { "Left Input Inverting Mux", "IN2L", "IN2L" },
 877        { "Left Input Inverting Mux", "IN3L", "IN3L" },
 878
 879        { "Right Input Mux", "IN1R", "IN1R" },
 880        { "Right Input Mux", "IN2R", "IN2R" },
 881        { "Right Input Mux", "IN3R", "IN3R" },
 882
 883        { "Right Input Inverting Mux", "IN1R", "IN1R" },
 884        { "Right Input Inverting Mux", "IN2R", "IN2R" },
 885        { "Right Input Inverting Mux", "IN3R", "IN3R" },
 886
 887        { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
 888        { "Left Input Mode Mux", "Differential Line",
 889          "Left Input Mux" },
 890        { "Left Input Mode Mux", "Differential Line",
 891          "Left Input Inverting Mux" },
 892        { "Left Input Mode Mux", "Differential Mic",
 893          "Left Input Mux" },
 894        { "Left Input Mode Mux", "Differential Mic",
 895          "Left Input Inverting Mux" },
 896
 897        { "Right Input Mode Mux", "Single-Ended",
 898          "Right Input Inverting Mux" },
 899        { "Right Input Mode Mux", "Differential Line",
 900          "Right Input Mux" },
 901        { "Right Input Mode Mux", "Differential Line",
 902          "Right Input Inverting Mux" },
 903        { "Right Input Mode Mux", "Differential Mic",
 904          "Right Input Mux" },
 905        { "Right Input Mode Mux", "Differential Mic",
 906          "Right Input Inverting Mux" },
 907
 908        { "Left Input PGA", NULL, "Left Input Mode Mux" },
 909        { "Right Input PGA", NULL, "Right Input Mode Mux" },
 910
 911        { "ADCL", NULL, "Left Input PGA" },
 912        { "ADCR", NULL, "Right Input PGA" },
 913
 914        { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
 915        { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
 916        { "Left Output Mixer", "DACL Switch", "DACL" },
 917        { "Left Output Mixer", "DACR Switch", "DACR" },
 918
 919        { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
 920        { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
 921        { "Right Output Mixer", "DACL Switch", "DACL" },
 922        { "Right Output Mixer", "DACR Switch", "DACR" },
 923
 924        { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
 925        { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
 926        { "Left Speaker Mixer", "DACL Switch", "DACL" },
 927        { "Left Speaker Mixer", "DACR Switch", "DACR" },
 928
 929        { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
 930        { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
 931        { "Right Speaker Mixer", "DACL Switch", "DACL" },
 932        { "Right Speaker Mixer", "DACR Switch", "DACR" },
 933
 934        { "Left Line Output PGA", NULL, "Left Output Mixer" },
 935        { "Right Line Output PGA", NULL, "Right Output Mixer" },
 936
 937        { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
 938        { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
 939
 940        { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
 941        { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
 942
 943        { "HPOUTL", NULL, "Left Headphone Output PGA" },
 944        { "HPOUTR", NULL, "Right Headphone Output PGA" },
 945
 946        { "LINEOUTL", NULL, "Left Line Output PGA" },
 947        { "LINEOUTR", NULL, "Right Line Output PGA" },
 948
 949        { "LOP", NULL, "Left Speaker PGA" },
 950        { "LON", NULL, "Left Speaker PGA" },
 951
 952        { "ROP", NULL, "Right Speaker PGA" },
 953        { "RON", NULL, "Right Speaker PGA" },
 954};
 955
 956static int wm8903_add_widgets(struct snd_soc_codec *codec)
 957{
 958        snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
 959                                  ARRAY_SIZE(wm8903_dapm_widgets));
 960
 961        snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
 962
 963        snd_soc_dapm_new_widgets(codec);
 964
 965        return 0;
 966}
 967
 968static int wm8903_set_bias_level(struct snd_soc_codec *codec,
 969                                 enum snd_soc_bias_level level)
 970{
 971        struct i2c_client *i2c = codec->control_data;
 972        u16 reg, reg2;
 973
 974        switch (level) {
 975        case SND_SOC_BIAS_ON:
 976        case SND_SOC_BIAS_PREPARE:
 977                reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
 978                reg &= ~(WM8903_VMID_RES_MASK);
 979                reg |= WM8903_VMID_RES_50K;
 980                wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
 981                break;
 982
 983        case SND_SOC_BIAS_STANDBY:
 984                if (codec->bias_level == SND_SOC_BIAS_OFF) {
 985                        wm8903_write(codec, WM8903_CLOCK_RATES_2,
 986                                     WM8903_CLK_SYS_ENA);
 987
 988                        wm8903_run_sequence(codec, 0);
 989                        wm8903_sync_reg_cache(codec, codec->reg_cache);
 990
 991                        /* Enable low impedence charge pump output */
 992                        reg = wm8903_read(codec,
 993                                          WM8903_CONTROL_INTERFACE_TEST_1);
 994                        wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
 995                                     reg | WM8903_TEST_KEY);
 996                        reg2 = wm8903_read(codec, WM8903_CHARGE_PUMP_TEST_1);
 997                        wm8903_write(codec, WM8903_CHARGE_PUMP_TEST_1,
 998                                     reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
 999                        wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1000                                     reg);
1001
1002                        /* By default no bypass paths are enabled so
1003                         * enable Class W support.
1004                         */
1005                        dev_dbg(&i2c->dev, "Enabling Class W\n");
1006                        wm8903_write(codec, WM8903_CLASS_W_0, reg |
1007                                     WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
1008                }
1009
1010                reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
1011                reg &= ~(WM8903_VMID_RES_MASK);
1012                reg |= WM8903_VMID_RES_250K;
1013                wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
1014                break;
1015
1016        case SND_SOC_BIAS_OFF:
1017                wm8903_run_sequence(codec, 32);
1018                reg = wm8903_read(codec, WM8903_CLOCK_RATES_2);
1019                reg &= ~WM8903_CLK_SYS_ENA;
1020                wm8903_write(codec, WM8903_CLOCK_RATES_2, reg);
1021                break;
1022        }
1023
1024        codec->bias_level = level;
1025
1026        return 0;
1027}
1028
1029static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1030                                 int clk_id, unsigned int freq, int dir)
1031{
1032        struct snd_soc_codec *codec = codec_dai->codec;
1033        struct wm8903_priv *wm8903 = codec->private_data;
1034
1035        wm8903->sysclk = freq;
1036
1037        return 0;
1038}
1039
1040static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1041                              unsigned int fmt)
1042{
1043        struct snd_soc_codec *codec = codec_dai->codec;
1044        u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1045
1046        aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1047                  WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1048
1049        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1050        case SND_SOC_DAIFMT_CBS_CFS:
1051                break;
1052        case SND_SOC_DAIFMT_CBS_CFM:
1053                aif1 |= WM8903_LRCLK_DIR;
1054                break;
1055        case SND_SOC_DAIFMT_CBM_CFM:
1056                aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1057                break;
1058        case SND_SOC_DAIFMT_CBM_CFS:
1059                aif1 |= WM8903_BCLK_DIR;
1060                break;
1061        default:
1062                return -EINVAL;
1063        }
1064
1065        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1066        case SND_SOC_DAIFMT_DSP_A:
1067                aif1 |= 0x3;
1068                break;
1069        case SND_SOC_DAIFMT_DSP_B:
1070                aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1071                break;
1072        case SND_SOC_DAIFMT_I2S:
1073                aif1 |= 0x2;
1074                break;
1075        case SND_SOC_DAIFMT_RIGHT_J:
1076                aif1 |= 0x1;
1077                break;
1078        case SND_SOC_DAIFMT_LEFT_J:
1079                break;
1080        default:
1081                return -EINVAL;
1082        }
1083
1084        /* Clock inversion */
1085        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1086        case SND_SOC_DAIFMT_DSP_A:
1087        case SND_SOC_DAIFMT_DSP_B:
1088                /* frame inversion not valid for DSP modes */
1089                switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1090                case SND_SOC_DAIFMT_NB_NF:
1091                        break;
1092                case SND_SOC_DAIFMT_IB_NF:
1093                        aif1 |= WM8903_AIF_BCLK_INV;
1094                        break;
1095                default:
1096                        return -EINVAL;
1097                }
1098                break;
1099        case SND_SOC_DAIFMT_I2S:
1100        case SND_SOC_DAIFMT_RIGHT_J:
1101        case SND_SOC_DAIFMT_LEFT_J:
1102                switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1103                case SND_SOC_DAIFMT_NB_NF:
1104                        break;
1105                case SND_SOC_DAIFMT_IB_IF:
1106                        aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1107                        break;
1108                case SND_SOC_DAIFMT_IB_NF:
1109                        aif1 |= WM8903_AIF_BCLK_INV;
1110                        break;
1111                case SND_SOC_DAIFMT_NB_IF:
1112                        aif1 |= WM8903_AIF_LRCLK_INV;
1113                        break;
1114                default:
1115                        return -EINVAL;
1116                }
1117                break;
1118        default:
1119                return -EINVAL;
1120        }
1121
1122        wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1123
1124        return 0;
1125}
1126
1127static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1128{
1129        struct snd_soc_codec *codec = codec_dai->codec;
1130        u16 reg;
1131
1132        reg = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1133
1134        if (mute)
1135                reg |= WM8903_DAC_MUTE;
1136        else
1137                reg &= ~WM8903_DAC_MUTE;
1138
1139        wm8903_write(codec, WM8903_DAC_DIGITAL_1, reg);
1140
1141        return 0;
1142}
1143
1144/* Lookup table for CLK_SYS/fs ratio.  256fs or more is recommended
1145 * for optimal performance so we list the lower rates first and match
1146 * on the last match we find. */
1147static struct {
1148        int div;
1149        int rate;
1150        int mode;
1151        int mclk_div;
1152} clk_sys_ratios[] = {
1153        {   64, 0x0, 0x0, 1 },
1154        {   68, 0x0, 0x1, 1 },
1155        {  125, 0x0, 0x2, 1 },
1156        {  128, 0x1, 0x0, 1 },
1157        {  136, 0x1, 0x1, 1 },
1158        {  192, 0x2, 0x0, 1 },
1159        {  204, 0x2, 0x1, 1 },
1160
1161        {   64, 0x0, 0x0, 2 },
1162        {   68, 0x0, 0x1, 2 },
1163        {  125, 0x0, 0x2, 2 },
1164        {  128, 0x1, 0x0, 2 },
1165        {  136, 0x1, 0x1, 2 },
1166        {  192, 0x2, 0x0, 2 },
1167        {  204, 0x2, 0x1, 2 },
1168
1169        {  250, 0x2, 0x2, 1 },
1170        {  256, 0x3, 0x0, 1 },
1171        {  272, 0x3, 0x1, 1 },
1172        {  384, 0x4, 0x0, 1 },
1173        {  408, 0x4, 0x1, 1 },
1174        {  375, 0x4, 0x2, 1 },
1175        {  512, 0x5, 0x0, 1 },
1176        {  544, 0x5, 0x1, 1 },
1177        {  500, 0x5, 0x2, 1 },
1178        {  768, 0x6, 0x0, 1 },
1179        {  816, 0x6, 0x1, 1 },
1180        {  750, 0x6, 0x2, 1 },
1181        { 1024, 0x7, 0x0, 1 },
1182        { 1088, 0x7, 0x1, 1 },
1183        { 1000, 0x7, 0x2, 1 },
1184        { 1408, 0x8, 0x0, 1 },
1185        { 1496, 0x8, 0x1, 1 },
1186        { 1536, 0x9, 0x0, 1 },
1187        { 1632, 0x9, 0x1, 1 },
1188        { 1500, 0x9, 0x2, 1 },
1189
1190        {  250, 0x2, 0x2, 2 },
1191        {  256, 0x3, 0x0, 2 },
1192        {  272, 0x3, 0x1, 2 },
1193        {  384, 0x4, 0x0, 2 },
1194        {  408, 0x4, 0x1, 2 },
1195        {  375, 0x4, 0x2, 2 },
1196        {  512, 0x5, 0x0, 2 },
1197        {  544, 0x5, 0x1, 2 },
1198        {  500, 0x5, 0x2, 2 },
1199        {  768, 0x6, 0x0, 2 },
1200        {  816, 0x6, 0x1, 2 },
1201        {  750, 0x6, 0x2, 2 },
1202        { 1024, 0x7, 0x0, 2 },
1203        { 1088, 0x7, 0x1, 2 },
1204        { 1000, 0x7, 0x2, 2 },
1205        { 1408, 0x8, 0x0, 2 },
1206        { 1496, 0x8, 0x1, 2 },
1207        { 1536, 0x9, 0x0, 2 },
1208        { 1632, 0x9, 0x1, 2 },
1209        { 1500, 0x9, 0x2, 2 },
1210};
1211
1212/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1213static struct {
1214        int ratio;
1215        int div;
1216} bclk_divs[] = {
1217        {  10,  0 },
1218        {  15,  1 },
1219        {  20,  2 },
1220        {  30,  3 },
1221        {  40,  4 },
1222        {  50,  5 },
1223        {  55,  6 },
1224        {  60,  7 },
1225        {  80,  8 },
1226        { 100,  9 },
1227        { 110, 10 },
1228        { 120, 11 },
1229        { 160, 12 },
1230        { 200, 13 },
1231        { 220, 14 },
1232        { 240, 15 },
1233        { 250, 16 },
1234        { 300, 17 },
1235        { 320, 18 },
1236        { 440, 19 },
1237        { 480, 20 },
1238};
1239
1240/* Sample rates for DSP */
1241static struct {
1242        int rate;
1243        int value;
1244} sample_rates[] = {
1245        {  8000,  0 },
1246        { 11025,  1 },
1247        { 12000,  2 },
1248        { 16000,  3 },
1249        { 22050,  4 },
1250        { 24000,  5 },
1251        { 32000,  6 },
1252        { 44100,  7 },
1253        { 48000,  8 },
1254        { 88200,  9 },
1255        { 96000, 10 },
1256        { 0,      0 },
1257};
1258
1259static int wm8903_startup(struct snd_pcm_substream *substream,
1260                          struct snd_soc_dai *dai)
1261{
1262        struct snd_soc_pcm_runtime *rtd = substream->private_data;
1263        struct snd_soc_device *socdev = rtd->socdev;
1264        struct snd_soc_codec *codec = socdev->card->codec;
1265        struct wm8903_priv *wm8903 = codec->private_data;
1266        struct i2c_client *i2c = codec->control_data;
1267        struct snd_pcm_runtime *master_runtime;
1268
1269        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1270                wm8903->playback_active++;
1271        else
1272                wm8903->capture_active++;
1273
1274        /* The DAI has shared clocks so if we already have a playback or
1275         * capture going then constrain this substream to match it.
1276         */
1277        if (wm8903->master_substream) {
1278                master_runtime = wm8903->master_substream->runtime;
1279
1280                dev_dbg(&i2c->dev, "Constraining to %d bits at %dHz\n",
1281                        master_runtime->sample_bits,
1282                        master_runtime->rate);
1283
1284                snd_pcm_hw_constraint_minmax(substream->runtime,
1285                                             SNDRV_PCM_HW_PARAM_RATE,
1286                                             master_runtime->rate,
1287                                             master_runtime->rate);
1288
1289                snd_pcm_hw_constraint_minmax(substream->runtime,
1290                                             SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1291                                             master_runtime->sample_bits,
1292                                             master_runtime->sample_bits);
1293
1294                wm8903->slave_substream = substream;
1295        } else
1296                wm8903->master_substream = substream;
1297
1298        return 0;
1299}
1300
1301static void wm8903_shutdown(struct snd_pcm_substream *substream,
1302                            struct snd_soc_dai *dai)
1303{
1304        struct snd_soc_pcm_runtime *rtd = substream->private_data;
1305        struct snd_soc_device *socdev = rtd->socdev;
1306        struct snd_soc_codec *codec = socdev->card->codec;
1307        struct wm8903_priv *wm8903 = codec->private_data;
1308
1309        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1310                wm8903->playback_active--;
1311        else
1312                wm8903->capture_active--;
1313
1314        if (wm8903->master_substream == substream)
1315                wm8903->master_substream = wm8903->slave_substream;
1316
1317        wm8903->slave_substream = NULL;
1318}
1319
1320static int wm8903_hw_params(struct snd_pcm_substream *substream,
1321                            struct snd_pcm_hw_params *params,
1322                            struct snd_soc_dai *dai)
1323{
1324        struct snd_soc_pcm_runtime *rtd = substream->private_data;
1325        struct snd_soc_device *socdev = rtd->socdev;
1326        struct snd_soc_codec *codec = socdev->card->codec;
1327        struct wm8903_priv *wm8903 = codec->private_data;
1328        struct i2c_client *i2c = codec->control_data;
1329        int fs = params_rate(params);
1330        int bclk;
1331        int bclk_div;
1332        int i;
1333        int dsp_config;
1334        int clk_config;
1335        int best_val;
1336        int cur_val;
1337        int clk_sys;
1338
1339        u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1340        u16 aif2 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_2);
1341        u16 aif3 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_3);
1342        u16 clock0 = wm8903_read(codec, WM8903_CLOCK_RATES_0);
1343        u16 clock1 = wm8903_read(codec, WM8903_CLOCK_RATES_1);
1344
1345        if (substream == wm8903->slave_substream) {
1346                dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
1347                return 0;
1348        }
1349
1350        /* Configure sample rate logic for DSP - choose nearest rate */
1351        dsp_config = 0;
1352        best_val = abs(sample_rates[dsp_config].rate - fs);
1353        for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1354                cur_val = abs(sample_rates[i].rate - fs);
1355                if (cur_val <= best_val) {
1356                        dsp_config = i;
1357                        best_val = cur_val;
1358                }
1359        }
1360
1361        /* Constraints should stop us hitting this but let's make sure */
1362        if (wm8903->capture_active)
1363                switch (sample_rates[dsp_config].rate) {
1364                case 88200:
1365                case 96000:
1366                        dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
1367                                fs);
1368                        return -EINVAL;
1369
1370                default:
1371                        break;
1372                }
1373
1374        dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1375        clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1376        clock1 |= sample_rates[dsp_config].value;
1377
1378        aif1 &= ~WM8903_AIF_WL_MASK;
1379        bclk = 2 * fs;
1380        switch (params_format(params)) {
1381        case SNDRV_PCM_FORMAT_S16_LE:
1382                bclk *= 16;
1383                break;
1384        case SNDRV_PCM_FORMAT_S20_3LE:
1385                bclk *= 20;
1386                aif1 |= 0x4;
1387                break;
1388        case SNDRV_PCM_FORMAT_S24_LE:
1389                bclk *= 24;
1390                aif1 |= 0x8;
1391                break;
1392        case SNDRV_PCM_FORMAT_S32_LE:
1393                bclk *= 32;
1394                aif1 |= 0xc;
1395                break;
1396        default:
1397                return -EINVAL;
1398        }
1399
1400        dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1401                wm8903->sysclk, fs);
1402
1403        /* We may not have an MCLK which allows us to generate exactly
1404         * the clock we want, particularly with USB derived inputs, so
1405         * approximate.
1406         */
1407        clk_config = 0;
1408        best_val = abs((wm8903->sysclk /
1409                        (clk_sys_ratios[0].mclk_div *
1410                         clk_sys_ratios[0].div)) - fs);
1411        for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1412                cur_val = abs((wm8903->sysclk /
1413                               (clk_sys_ratios[i].mclk_div *
1414                                clk_sys_ratios[i].div)) - fs);
1415
1416                if (cur_val <= best_val) {
1417                        clk_config = i;
1418                        best_val = cur_val;
1419                }
1420        }
1421
1422        if (clk_sys_ratios[clk_config].mclk_div == 2) {
1423                clock0 |= WM8903_MCLKDIV2;
1424                clk_sys = wm8903->sysclk / 2;
1425        } else {
1426                clock0 &= ~WM8903_MCLKDIV2;
1427                clk_sys = wm8903->sysclk;
1428        }
1429
1430        clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1431                    WM8903_CLK_SYS_MODE_MASK);
1432        clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1433        clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1434
1435        dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1436                clk_sys_ratios[clk_config].rate,
1437                clk_sys_ratios[clk_config].mode,
1438                clk_sys_ratios[clk_config].div);
1439
1440        dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1441
1442        /* We may not get quite the right frequency if using
1443         * approximate clocks so look for the closest match that is
1444         * higher than the target (we need to ensure that there enough
1445         * BCLKs to clock out the samples).
1446         */
1447        bclk_div = 0;
1448        best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1449        i = 1;
1450        while (i < ARRAY_SIZE(bclk_divs)) {
1451                cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1452                if (cur_val < 0) /* BCLK table is sorted */
1453                        break;
1454                bclk_div = i;
1455                best_val = cur_val;
1456                i++;
1457        }
1458
1459        aif2 &= ~WM8903_BCLK_DIV_MASK;
1460        aif3 &= ~WM8903_LRCLK_RATE_MASK;
1461
1462        dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1463                bclk_divs[bclk_div].ratio / 10, bclk,
1464                (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1465
1466        aif2 |= bclk_divs[bclk_div].div;
1467        aif3 |= bclk / fs;
1468
1469        wm8903_write(codec, WM8903_CLOCK_RATES_0, clock0);
1470        wm8903_write(codec, WM8903_CLOCK_RATES_1, clock1);
1471        wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1472        wm8903_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1473        wm8903_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1474
1475        return 0;
1476}
1477
1478#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1479                               SNDRV_PCM_RATE_11025 |   \
1480                               SNDRV_PCM_RATE_16000 |   \
1481                               SNDRV_PCM_RATE_22050 |   \
1482                               SNDRV_PCM_RATE_32000 |   \
1483                               SNDRV_PCM_RATE_44100 |   \
1484                               SNDRV_PCM_RATE_48000 |   \
1485                               SNDRV_PCM_RATE_88200 |   \
1486                               SNDRV_PCM_RATE_96000)
1487
1488#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1489                              SNDRV_PCM_RATE_11025 |    \
1490                              SNDRV_PCM_RATE_16000 |    \
1491                              SNDRV_PCM_RATE_22050 |    \
1492                              SNDRV_PCM_RATE_32000 |    \
1493                              SNDRV_PCM_RATE_44100 |    \
1494                              SNDRV_PCM_RATE_48000)
1495
1496#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1497                        SNDRV_PCM_FMTBIT_S20_3LE |\
1498                        SNDRV_PCM_FMTBIT_S24_LE)
1499
1500static struct snd_soc_dai_ops wm8903_dai_ops = {
1501        .startup        = wm8903_startup,
1502        .shutdown       = wm8903_shutdown,
1503        .hw_params      = wm8903_hw_params,
1504        .digital_mute   = wm8903_digital_mute,
1505        .set_fmt        = wm8903_set_dai_fmt,
1506        .set_sysclk     = wm8903_set_dai_sysclk,
1507};
1508
1509struct snd_soc_dai wm8903_dai = {
1510        .name = "WM8903",
1511        .playback = {
1512                .stream_name = "Playback",
1513                .channels_min = 2,
1514                .channels_max = 2,
1515                .rates = WM8903_PLAYBACK_RATES,
1516                .formats = WM8903_FORMATS,
1517        },
1518        .capture = {
1519                 .stream_name = "Capture",
1520                 .channels_min = 2,
1521                 .channels_max = 2,
1522                 .rates = WM8903_CAPTURE_RATES,
1523                 .formats = WM8903_FORMATS,
1524         },
1525        .ops = &wm8903_dai_ops,
1526};
1527EXPORT_SYMBOL_GPL(wm8903_dai);
1528
1529static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
1530{
1531        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1532        struct snd_soc_codec *codec = socdev->card->codec;
1533
1534        wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1535
1536        return 0;
1537}
1538
1539static int wm8903_resume(struct platform_device *pdev)
1540{
1541        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1542        struct snd_soc_codec *codec = socdev->card->codec;
1543        struct i2c_client *i2c = codec->control_data;
1544        int i;
1545        u16 *reg_cache = codec->reg_cache;
1546        u16 *tmp_cache = kmemdup(codec->reg_cache, sizeof(wm8903_reg_defaults),
1547                                 GFP_KERNEL);
1548
1549        /* Bring the codec back up to standby first to minimise pop/clicks */
1550        wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1551        wm8903_set_bias_level(codec, codec->suspend_bias_level);
1552
1553        /* Sync back everything else */
1554        if (tmp_cache) {
1555                for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1556                        if (tmp_cache[i] != reg_cache[i])
1557                                wm8903_write(codec, i, tmp_cache[i]);
1558        } else {
1559                dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
1560        }
1561
1562        return 0;
1563}
1564
1565static struct snd_soc_codec *wm8903_codec;
1566
1567static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1568                                      const struct i2c_device_id *id)
1569{
1570        struct wm8903_priv *wm8903;
1571        struct snd_soc_codec *codec;
1572        int ret;
1573        u16 val;
1574
1575        wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1576        if (wm8903 == NULL)
1577                return -ENOMEM;
1578
1579        codec = &wm8903->codec;
1580
1581        mutex_init(&codec->mutex);
1582        INIT_LIST_HEAD(&codec->dapm_widgets);
1583        INIT_LIST_HEAD(&codec->dapm_paths);
1584
1585        codec->dev = &i2c->dev;
1586        codec->name = "WM8903";
1587        codec->owner = THIS_MODULE;
1588        codec->read = wm8903_read;
1589        codec->write = wm8903_write;
1590        codec->hw_write = (hw_write_t)i2c_master_send;
1591        codec->bias_level = SND_SOC_BIAS_OFF;
1592        codec->set_bias_level = wm8903_set_bias_level;
1593        codec->dai = &wm8903_dai;
1594        codec->num_dai = 1;
1595        codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
1596        codec->reg_cache = &wm8903->reg_cache[0];
1597        codec->private_data = wm8903;
1598
1599        i2c_set_clientdata(i2c, codec);
1600        codec->control_data = i2c;
1601
1602        val = wm8903_hw_read(codec, WM8903_SW_RESET_AND_ID);
1603        if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1604                dev_err(&i2c->dev,
1605                        "Device with ID register %x is not a WM8903\n", val);
1606                return -ENODEV;
1607        }
1608
1609        val = wm8903_read(codec, WM8903_REVISION_NUMBER);
1610        dev_info(&i2c->dev, "WM8903 revision %d\n",
1611                 val & WM8903_CHIP_REV_MASK);
1612
1613        wm8903_reset(codec);
1614
1615        /* power on device */
1616        wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1617
1618        /* Latch volume update bits */
1619        val = wm8903_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
1620        val |= WM8903_ADCVU;
1621        wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1622        wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
1623
1624        val = wm8903_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
1625        val |= WM8903_DACVU;
1626        wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1627        wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
1628
1629        val = wm8903_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
1630        val |= WM8903_HPOUTVU;
1631        wm8903_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1632        wm8903_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
1633
1634        val = wm8903_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
1635        val |= WM8903_LINEOUTVU;
1636        wm8903_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1637        wm8903_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
1638
1639        val = wm8903_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
1640        val |= WM8903_SPKVU;
1641        wm8903_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1642        wm8903_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
1643
1644        /* Enable DAC soft mute by default */
1645        val = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1646        val |= WM8903_DAC_MUTEMODE;
1647        wm8903_write(codec, WM8903_DAC_DIGITAL_1, val);
1648
1649        wm8903_dai.dev = &i2c->dev;
1650        wm8903_codec = codec;
1651
1652        ret = snd_soc_register_codec(codec);
1653        if (ret != 0) {
1654                dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1655                goto err;
1656        }
1657
1658        ret = snd_soc_register_dai(&wm8903_dai);
1659        if (ret != 0) {
1660                dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1661                goto err_codec;
1662        }
1663
1664        return ret;
1665
1666err_codec:
1667        snd_soc_unregister_codec(codec);
1668err:
1669        wm8903_codec = NULL;
1670        kfree(wm8903);
1671        return ret;
1672}
1673
1674static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1675{
1676        struct snd_soc_codec *codec = i2c_get_clientdata(client);
1677
1678        snd_soc_unregister_dai(&wm8903_dai);
1679        snd_soc_unregister_codec(codec);
1680
1681        wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1682
1683        kfree(codec->private_data);
1684
1685        wm8903_codec = NULL;
1686        wm8903_dai.dev = NULL;
1687
1688        return 0;
1689}
1690
1691/* i2c codec control layer */
1692static const struct i2c_device_id wm8903_i2c_id[] = {
1693       { "wm8903", 0 },
1694       { }
1695};
1696MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1697
1698static struct i2c_driver wm8903_i2c_driver = {
1699        .driver = {
1700                .name = "WM8903",
1701                .owner = THIS_MODULE,
1702        },
1703        .probe    = wm8903_i2c_probe,
1704        .remove   = __devexit_p(wm8903_i2c_remove),
1705        .id_table = wm8903_i2c_id,
1706};
1707
1708static int wm8903_probe(struct platform_device *pdev)
1709{
1710        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1711        int ret = 0;
1712
1713        if (!wm8903_codec) {
1714                dev_err(&pdev->dev, "I2C device not yet probed\n");
1715                goto err;
1716        }
1717
1718        socdev->card->codec = wm8903_codec;
1719
1720        /* register pcms */
1721        ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1722        if (ret < 0) {
1723                dev_err(&pdev->dev, "failed to create pcms\n");
1724                goto err;
1725        }
1726
1727        snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls,
1728                                ARRAY_SIZE(wm8903_snd_controls));
1729        wm8903_add_widgets(socdev->card->codec);
1730
1731        ret = snd_soc_init_card(socdev);
1732        if (ret < 0) {
1733                dev_err(&pdev->dev, "wm8903: failed to register card\n");
1734                goto card_err;
1735        }
1736
1737        return ret;
1738
1739card_err:
1740        snd_soc_free_pcms(socdev);
1741        snd_soc_dapm_free(socdev);
1742err:
1743        return ret;
1744}
1745
1746/* power down chip */
1747static int wm8903_remove(struct platform_device *pdev)
1748{
1749        struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1750        struct snd_soc_codec *codec = socdev->card->codec;
1751
1752        if (codec->control_data)
1753                wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1754
1755        snd_soc_free_pcms(socdev);
1756        snd_soc_dapm_free(socdev);
1757
1758        return 0;
1759}
1760
1761struct snd_soc_codec_device soc_codec_dev_wm8903 = {
1762        .probe =        wm8903_probe,
1763        .remove =       wm8903_remove,
1764        .suspend =      wm8903_suspend,
1765        .resume =       wm8903_resume,
1766};
1767EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
1768
1769static int __init wm8903_modinit(void)
1770{
1771        return i2c_add_driver(&wm8903_i2c_driver);
1772}
1773module_init(wm8903_modinit);
1774
1775static void __exit wm8903_exit(void)
1776{
1777        i2c_del_driver(&wm8903_i2c_driver);
1778}
1779module_exit(wm8903_exit);
1780
1781MODULE_DESCRIPTION("ASoC WM8903 driver");
1782MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1783MODULE_LICENSE("GPL");
1784
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