linux/drivers/usb/musb/davinci.c
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   1/*
   2 * Copyright (C) 2005-2006 by Texas Instruments
   3 *
   4 * This file is part of the Inventra Controller Driver for Linux.
   5 *
   6 * The Inventra Controller Driver for Linux is free software; you
   7 * can redistribute it and/or modify it under the terms of the GNU
   8 * General Public License version 2 as published by the Free Software
   9 * Foundation.
  10 *
  11 * The Inventra Controller Driver for Linux is distributed in
  12 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  13 * without even the implied warranty of MERCHANTABILITY or
  14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 * License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with The Inventra Controller Driver for Linux ; if not,
  19 * write to the Free Software Foundation, Inc., 59 Temple Place,
  20 * Suite 330, Boston, MA  02111-1307  USA
  21 *
  22 */
  23
  24#include <linux/module.h>
  25#include <linux/kernel.h>
  26#include <linux/sched.h>
  27#include <linux/slab.h>
  28#include <linux/init.h>
  29#include <linux/list.h>
  30#include <linux/delay.h>
  31#include <linux/clk.h>
  32#include <linux/io.h>
  33#include <linux/gpio.h>
  34
  35#include <mach/hardware.h>
  36#include <mach/memory.h>
  37#include <mach/gpio.h>
  38
  39#include <asm/mach-types.h>
  40
  41#include "musb_core.h"
  42
  43#ifdef CONFIG_MACH_DAVINCI_EVM
  44#define GPIO_nVBUS_DRV          87
  45#endif
  46
  47#include "davinci.h"
  48#include "cppi_dma.h"
  49
  50
  51#define USB_PHY_CTRL    IO_ADDRESS(USBPHY_CTL_PADDR)
  52#define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR)
  53
  54/* REVISIT (PM) we should be able to keep the PHY in low power mode most
  55 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
  56 * and, when in host mode, autosuspending idle root ports... PHYPLLON
  57 * (overriding SUSPENDM?) then likely needs to stay off.
  58 */
  59
  60static inline void phy_on(void)
  61{
  62        u32     phy_ctrl = __raw_readl(USB_PHY_CTRL);
  63
  64        /* power everything up; start the on-chip PHY and its PLL */
  65        phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
  66        phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
  67        __raw_writel(phy_ctrl, USB_PHY_CTRL);
  68
  69        /* wait for PLL to lock before proceeding */
  70        while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
  71                cpu_relax();
  72}
  73
  74static inline void phy_off(void)
  75{
  76        u32     phy_ctrl = __raw_readl(USB_PHY_CTRL);
  77
  78        /* powerdown the on-chip PHY, its PLL, and the OTG block */
  79        phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON);
  80        phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN;
  81        __raw_writel(phy_ctrl, USB_PHY_CTRL);
  82}
  83
  84static int dma_off = 1;
  85
  86void musb_platform_enable(struct musb *musb)
  87{
  88        u32     tmp, old, val;
  89
  90        /* workaround:  setup irqs through both register sets */
  91        tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
  92                        << DAVINCI_USB_TXINT_SHIFT;
  93        musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
  94        old = tmp;
  95        tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
  96                        << DAVINCI_USB_RXINT_SHIFT;
  97        musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
  98        tmp |= old;
  99
 100        val = ~MUSB_INTR_SOF;
 101        tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
 102        musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
 103
 104        if (is_dma_capable() && !dma_off)
 105                printk(KERN_WARNING "%s %s: dma not reactivated\n",
 106                                __FILE__, __func__);
 107        else
 108                dma_off = 0;
 109
 110        /* force a DRVVBUS irq so we can start polling for ID change */
 111        if (is_otg_enabled(musb))
 112                musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
 113                        DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
 114}
 115
 116/*
 117 * Disable the HDRC and flush interrupts
 118 */
 119void musb_platform_disable(struct musb *musb)
 120{
 121        /* because we don't set CTRLR.UINT, "important" to:
 122         *  - not read/write INTRUSB/INTRUSBE
 123         *  - (except during initial setup, as workaround)
 124         *  - use INTSETR/INTCLRR instead
 125         */
 126        musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
 127                          DAVINCI_USB_USBINT_MASK
 128                        | DAVINCI_USB_TXINT_MASK
 129                        | DAVINCI_USB_RXINT_MASK);
 130        musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
 131        musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
 132
 133        if (is_dma_capable() && !dma_off)
 134                WARNING("dma still active\n");
 135}
 136
 137
 138#ifdef CONFIG_USB_MUSB_HDRC_HCD
 139#define portstate(stmt)         stmt
 140#else
 141#define portstate(stmt)
 142#endif
 143
 144
 145/*
 146 * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
 147 * which doesn't wire DRVVBUS to the FET that switches it.  Unclear
 148 * if that's a problem with the DM6446 chip or just with that board.
 149 *
 150 * In either case, the DM355 EVM automates DRVVBUS the normal way,
 151 * when J10 is out, and TI documents it as handling OTG.
 152 */
 153
 154#ifdef CONFIG_MACH_DAVINCI_EVM
 155
 156static int vbus_state = -1;
 157
 158/* I2C operations are always synchronous, and require a task context.
 159 * With unloaded systems, using the shared workqueue seems to suffice
 160 * to satisfy the 100msec A_WAIT_VRISE timeout...
 161 */
 162static void evm_deferred_drvvbus(struct work_struct *ignored)
 163{
 164        gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
 165        vbus_state = !vbus_state;
 166}
 167
 168#endif  /* EVM */
 169
 170static void davinci_source_power(struct musb *musb, int is_on, int immediate)
 171{
 172#ifdef CONFIG_MACH_DAVINCI_EVM
 173        if (is_on)
 174                is_on = 1;
 175
 176        if (vbus_state == is_on)
 177                return;
 178        vbus_state = !is_on;            /* 0/1 vs "-1 == unknown/init" */
 179
 180        if (machine_is_davinci_evm()) {
 181                static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
 182
 183                if (immediate)
 184                        gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
 185                else
 186                        schedule_work(&evm_vbus_work);
 187        }
 188        if (immediate)
 189                vbus_state = is_on;
 190#endif
 191}
 192
 193static void davinci_set_vbus(struct musb *musb, int is_on)
 194{
 195        WARN_ON(is_on && is_peripheral_active(musb));
 196        davinci_source_power(musb, is_on, 0);
 197}
 198
 199
 200#define POLL_SECONDS    2
 201
 202static struct timer_list otg_workaround;
 203
 204static void otg_timer(unsigned long _musb)
 205{
 206        struct musb             *musb = (void *)_musb;
 207        void __iomem            *mregs = musb->mregs;
 208        u8                      devctl;
 209        unsigned long           flags;
 210
 211        /* We poll because DaVinci's won't expose several OTG-critical
 212        * status change events (from the transceiver) otherwise.
 213         */
 214        devctl = musb_readb(mregs, MUSB_DEVCTL);
 215        DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
 216
 217        spin_lock_irqsave(&musb->lock, flags);
 218        switch (musb->xceiv.state) {
 219        case OTG_STATE_A_WAIT_VFALL:
 220                /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
 221                 * seems to mis-handle session "start" otherwise (or in our
 222                 * case "recover"), in routine "VBUS was valid by the time
 223                 * VBUSERR got reported during enumeration" cases.
 224                 */
 225                if (devctl & MUSB_DEVCTL_VBUS) {
 226                        mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 227                        break;
 228                }
 229                musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
 230                musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
 231                        MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
 232                break;
 233        case OTG_STATE_B_IDLE:
 234                if (!is_peripheral_enabled(musb))
 235                        break;
 236
 237                /* There's no ID-changed IRQ, so we have no good way to tell
 238                 * when to switch to the A-Default state machine (by setting
 239                 * the DEVCTL.SESSION flag).
 240                 *
 241                 * Workaround:  whenever we're in B_IDLE, try setting the
 242                 * session flag every few seconds.  If it works, ID was
 243                 * grounded and we're now in the A-Default state machine.
 244                 *
 245                 * NOTE setting the session flag is _supposed_ to trigger
 246                 * SRP, but clearly it doesn't.
 247                 */
 248                musb_writeb(mregs, MUSB_DEVCTL,
 249                                devctl | MUSB_DEVCTL_SESSION);
 250                devctl = musb_readb(mregs, MUSB_DEVCTL);
 251                if (devctl & MUSB_DEVCTL_BDEVICE)
 252                        mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 253                else
 254                        musb->xceiv.state = OTG_STATE_A_IDLE;
 255                break;
 256        default:
 257                break;
 258        }
 259        spin_unlock_irqrestore(&musb->lock, flags);
 260}
 261
 262static irqreturn_t davinci_interrupt(int irq, void *__hci)
 263{
 264        unsigned long   flags;
 265        irqreturn_t     retval = IRQ_NONE;
 266        struct musb     *musb = __hci;
 267        void __iomem    *tibase = musb->ctrl_base;
 268        u32             tmp;
 269
 270        spin_lock_irqsave(&musb->lock, flags);
 271
 272        /* NOTE: DaVinci shadows the Mentor IRQs.  Don't manage them through
 273         * the Mentor registers (except for setup), use the TI ones and EOI.
 274         *
 275         * Docs describe irq "vector" registers asociated with the CPPI and
 276         * USB EOI registers.  These hold a bitmask corresponding to the
 277         * current IRQ, not an irq handler address.  Would using those bits
 278         * resolve some of the races observed in this dispatch code??
 279         */
 280
 281        /* CPPI interrupts share the same IRQ line, but have their own
 282         * mask, state, "vector", and EOI registers.
 283         */
 284        if (is_cppi_enabled()) {
 285                u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
 286                u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
 287
 288                if (cppi_tx || cppi_rx) {
 289                        DBG(4, "CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx);
 290                        cppi_completion(musb, cppi_rx, cppi_tx);
 291                        retval = IRQ_HANDLED;
 292                }
 293        }
 294
 295        /* ack and handle non-CPPI interrupts */
 296        tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
 297        musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
 298        DBG(4, "IRQ %08x\n", tmp);
 299
 300        musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
 301                        >> DAVINCI_USB_RXINT_SHIFT;
 302        musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
 303                        >> DAVINCI_USB_TXINT_SHIFT;
 304        musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
 305                        >> DAVINCI_USB_USBINT_SHIFT;
 306
 307        /* DRVVBUS irqs are the only proxy we have (a very poor one!) for
 308         * DaVinci's missing ID change IRQ.  We need an ID change IRQ to
 309         * switch appropriately between halves of the OTG state machine.
 310         * Managing DEVCTL.SESSION per Mentor docs requires we know its
 311         * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
 312         * Also, DRVVBUS pulses for SRP (but not at 5V) ...
 313         */
 314        if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
 315                int     drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
 316                void __iomem *mregs = musb->mregs;
 317                u8      devctl = musb_readb(mregs, MUSB_DEVCTL);
 318                int     err = musb->int_usb & MUSB_INTR_VBUSERROR;
 319
 320                err = is_host_enabled(musb)
 321                                && (musb->int_usb & MUSB_INTR_VBUSERROR);
 322                if (err) {
 323                        /* The Mentor core doesn't debounce VBUS as needed
 324                         * to cope with device connect current spikes. This
 325                         * means it's not uncommon for bus-powered devices
 326                         * to get VBUS errors during enumeration.
 327                         *
 328                         * This is a workaround, but newer RTL from Mentor
 329                         * seems to allow a better one: "re"starting sessions
 330                         * without waiting (on EVM, a **long** time) for VBUS
 331                         * to stop registering in devctl.
 332                         */
 333                        musb->int_usb &= ~MUSB_INTR_VBUSERROR;
 334                        musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
 335                        mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 336                        WARNING("VBUS error workaround (delay coming)\n");
 337                } else if (is_host_enabled(musb) && drvvbus) {
 338                        musb->is_active = 1;
 339                        MUSB_HST_MODE(musb);
 340                        musb->xceiv.default_a = 1;
 341                        musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
 342                        portstate(musb->port1_status |= USB_PORT_STAT_POWER);
 343                        del_timer(&otg_workaround);
 344                } else {
 345                        musb->is_active = 0;
 346                        MUSB_DEV_MODE(musb);
 347                        musb->xceiv.default_a = 0;
 348                        musb->xceiv.state = OTG_STATE_B_IDLE;
 349                        portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
 350                }
 351
 352                /* NOTE:  this must complete poweron within 100 msec */
 353                davinci_source_power(musb, drvvbus, 0);
 354                DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
 355                                drvvbus ? "on" : "off",
 356                                otg_state_string(musb),
 357                                err ? " ERROR" : "",
 358                                devctl);
 359                retval = IRQ_HANDLED;
 360        }
 361
 362        if (musb->int_tx || musb->int_rx || musb->int_usb)
 363                retval |= musb_interrupt(musb);
 364
 365        /* irq stays asserted until EOI is written */
 366        musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
 367
 368        /* poll for ID change */
 369        if (is_otg_enabled(musb)
 370                        && musb->xceiv.state == OTG_STATE_B_IDLE)
 371                mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 372
 373        spin_unlock_irqrestore(&musb->lock, flags);
 374
 375        /* REVISIT we sometimes get unhandled IRQs
 376         * (e.g. ep0).  not clear why...
 377         */
 378        if (retval != IRQ_HANDLED)
 379                DBG(5, "unhandled? %08x\n", tmp);
 380        return IRQ_HANDLED;
 381}
 382
 383int musb_platform_set_mode(struct musb *musb, u8 mode)
 384{
 385        /* EVM can't do this (right?) */
 386        return -EIO;
 387}
 388
 389int __init musb_platform_init(struct musb *musb)
 390{
 391        void __iomem    *tibase = musb->ctrl_base;
 392        u32             revision;
 393
 394        musb->mregs += DAVINCI_BASE_OFFSET;
 395
 396        clk_enable(musb->clock);
 397
 398        /* returns zero if e.g. not clocked */
 399        revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
 400        if (revision == 0)
 401                return -ENODEV;
 402
 403        if (is_host_enabled(musb))
 404                setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
 405
 406        musb->board_set_vbus = davinci_set_vbus;
 407        davinci_source_power(musb, 0, 1);
 408
 409        /* dm355 EVM swaps D+/D- for signal integrity, and
 410         * is clocked from the main 24 MHz crystal.
 411         */
 412        if (machine_is_davinci_dm355_evm()) {
 413                u32     phy_ctrl = __raw_readl(USB_PHY_CTRL);
 414
 415                phy_ctrl &= ~(3 << 9);
 416                phy_ctrl |= USBPHY_DATAPOL;
 417                __raw_writel(phy_ctrl, USB_PHY_CTRL);
 418        }
 419
 420        /* reset the controller */
 421        musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
 422
 423        /* start the on-chip PHY and its PLL */
 424        phy_on();
 425
 426        msleep(5);
 427
 428        /* NOTE:  irqs are in mixed mode, not bypass to pure-musb */
 429        pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
 430                revision, __raw_readl(USB_PHY_CTRL),
 431                musb_readb(tibase, DAVINCI_USB_CTRL_REG));
 432
 433        musb->isr = davinci_interrupt;
 434        return 0;
 435}
 436
 437int musb_platform_exit(struct musb *musb)
 438{
 439        if (is_host_enabled(musb))
 440                del_timer_sync(&otg_workaround);
 441
 442        davinci_source_power(musb, 0 /*off*/, 1);
 443
 444        /* delay, to avoid problems with module reload */
 445        if (is_host_enabled(musb) && musb->xceiv.default_a) {
 446                int     maxdelay = 30;
 447                u8      devctl, warn = 0;
 448
 449                /* if there's no peripheral connected, this can take a
 450                 * long time to fall, especially on EVM with huge C133.
 451                 */
 452                do {
 453                        devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 454                        if (!(devctl & MUSB_DEVCTL_VBUS))
 455                                break;
 456                        if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
 457                                warn = devctl & MUSB_DEVCTL_VBUS;
 458                                DBG(1, "VBUS %d\n",
 459                                        warn >> MUSB_DEVCTL_VBUS_SHIFT);
 460                        }
 461                        msleep(1000);
 462                        maxdelay--;
 463                } while (maxdelay > 0);
 464
 465                /* in OTG mode, another host might be connected */
 466                if (devctl & MUSB_DEVCTL_VBUS)
 467                        DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
 468        }
 469
 470        phy_off();
 471
 472        clk_disable(musb->clock);
 473
 474        return 0;
 475}
 476