1/* 2 * Author: MontaVista Software, Inc. 3 * source@mvista.com 4 * 5 * Copyright 2001-2006 MontaVista Software Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27#ifndef __ASM_TXX9_TX4927_H 28#define __ASM_TXX9_TX4927_H 29 30#include <linux/types.h> 31#include <linux/io.h> 32#include <asm/txx9irq.h> 33#include <asm/txx9/tx4927pcic.h> 34 35#ifdef CONFIG_64BIT 36#define TX4927_REG_BASE 0xffffffffff1f0000UL 37#else 38#define TX4927_REG_BASE 0xff1f0000UL 39#endif 40#define TX4927_REG_SIZE 0x00010000 41 42#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000) 43#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000) 44#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000) 45#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000) 46#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600) 47#define TX4927_NR_TMR 3 48#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100) 49#define TX4927_NR_SIO 2 50#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100) 51#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500) 52 53#define TX4927_IR_ECCERR 0 54#define TX4927_IR_WTOERR 1 55#define TX4927_NUM_IR_INT 6 56#define TX4927_IR_INT(n) (2 + (n)) 57#define TX4927_NUM_IR_SIO 2 58#define TX4927_IR_SIO(n) (8 + (n)) 59#define TX4927_NUM_IR_DMA 4 60#define TX4927_IR_DMA(n) (10 + (n)) 61#define TX4927_IR_PIO 14 62#define TX4927_IR_PDMAC 15 63#define TX4927_IR_PCIC 16 64#define TX4927_NUM_IR_TMR 3 65#define TX4927_IR_TMR(n) (17 + (n)) 66#define TX4927_IR_PCIERR 22 67#define TX4927_IR_PCIPME 23 68#define TX4927_IR_ACLC 24 69#define TX4927_IR_ACLCPME 25 70#define TX4927_NUM_IR 32 71 72#define TX4927_IRC_INT 2 /* IP[2] in Status register */ 73 74#define TX4927_NUM_PIO 16 75 76struct tx4927_sdramc_reg { 77 u64 cr[4]; 78 u64 unused0[4]; 79 u64 tr; 80 u64 unused1[2]; 81 u64 cmd; 82}; 83 84struct tx4927_ebusc_reg { 85 u64 cr[8]; 86}; 87 88struct tx4927_ccfg_reg { 89 u64 ccfg; 90 u64 crir; 91 u64 pcfg; 92 u64 toea; 93 u64 clkctr; 94 u64 unused0; 95 u64 garbc; 96 u64 unused1; 97 u64 unused2; 98 u64 ramp; 99}; 100 101/* 102 * CCFG 103 */ 104/* CCFG : Chip Configuration */ 105#define TX4927_CCFG_WDRST 0x0000020000000000ULL 106#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL 107#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL 108#define TX4927_CCFG_TINTDIS 0x01000000 109#define TX4927_CCFG_PCI66 0x00800000 110#define TX4927_CCFG_PCIMODE 0x00400000 111#define TX4927_CCFG_DIVMODE_MASK 0x000e0000 112#define TX4927_CCFG_DIVMODE_8 (0x0 << 17) 113#define TX4927_CCFG_DIVMODE_12 (0x1 << 17) 114#define TX4927_CCFG_DIVMODE_16 (0x2 << 17) 115#define TX4927_CCFG_DIVMODE_10 (0x3 << 17) 116#define TX4927_CCFG_DIVMODE_2 (0x4 << 17) 117#define TX4927_CCFG_DIVMODE_3 (0x5 << 17) 118#define TX4927_CCFG_DIVMODE_4 (0x6 << 17) 119#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17) 120#define TX4927_CCFG_BEOW 0x00010000 121#define TX4927_CCFG_WR 0x00008000 122#define TX4927_CCFG_TOE 0x00004000 123#define TX4927_CCFG_PCIARB 0x00002000 124#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 125#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 126#define TX4927_CCFG_PCIDIVMODE_3 0x00000800 127#define TX4927_CCFG_PCIDIVMODE_5 0x00001000 128#define TX4927_CCFG_PCIDIVMODE_6 0x00001800 129#define TX4927_CCFG_SYSSP_MASK 0x000000c0 130#define TX4927_CCFG_ENDIAN 0x00000004 131#define TX4927_CCFG_HALT 0x00000002 132#define TX4927_CCFG_ACEHOLD 0x00000001 133#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW) 134 135/* PCFG : Pin Configuration */ 136#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000 137#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28) 138#define TX4927_PCFG_SYSCLKEN 0x08000000 139#define TX4927_PCFG_SDCLKEN_ALL 0x07800000 140#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) 141#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 142#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) 143#define TX4927_PCFG_SEL2 0x00000200 144#define TX4927_PCFG_SEL1 0x00000100 145#define TX4927_PCFG_DMASEL_ALL 0x000000ff 146#define TX4927_PCFG_DMASEL0_MASK 0x00000003 147#define TX4927_PCFG_DMASEL1_MASK 0x0000000c 148#define TX4927_PCFG_DMASEL2_MASK 0x00000030 149#define TX4927_PCFG_DMASEL3_MASK 0x000000c0 150#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000 151#define TX4927_PCFG_DMASEL0_SIO1 0x00000001 152#define TX4927_PCFG_DMASEL0_ACL0 0x00000002 153#define TX4927_PCFG_DMASEL0_ACL2 0x00000003 154#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000 155#define TX4927_PCFG_DMASEL1_SIO1 0x00000004 156#define TX4927_PCFG_DMASEL1_ACL1 0x00000008 157#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c 158#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */ 159#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */ 160#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */ 161#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */ 162#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */ 163#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000 164#define TX4927_PCFG_DMASEL3_SIO0 0x00000040 165#define TX4927_PCFG_DMASEL3_ACL3 0x00000080 166#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0 167 168/* CLKCTR : Clock Control */ 169#define TX4927_CLKCTR_ACLCKD 0x02000000 170#define TX4927_CLKCTR_PIOCKD 0x01000000 171#define TX4927_CLKCTR_DMACKD 0x00800000 172#define TX4927_CLKCTR_PCICKD 0x00400000 173#define TX4927_CLKCTR_TM0CKD 0x00100000 174#define TX4927_CLKCTR_TM1CKD 0x00080000 175#define TX4927_CLKCTR_TM2CKD 0x00040000 176#define TX4927_CLKCTR_SIO0CKD 0x00020000 177#define TX4927_CLKCTR_SIO1CKD 0x00010000 178#define TX4927_CLKCTR_ACLRST 0x00000200 179#define TX4927_CLKCTR_PIORST 0x00000100 180#define TX4927_CLKCTR_DMARST 0x00000080 181#define TX4927_CLKCTR_PCIRST 0x00000040 182#define TX4927_CLKCTR_TM0RST 0x00000010 183#define TX4927_CLKCTR_TM1RST 0x00000008 184#define TX4927_CLKCTR_TM2RST 0x00000004 185#define TX4927_CLKCTR_SIO0RST 0x00000002 186#define TX4927_CLKCTR_SIO1RST 0x00000001 187 188#define tx4927_sdramcptr \ 189 ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG) 190#define tx4927_pcicptr \ 191 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG) 192#define tx4927_ccfgptr \ 193 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG) 194#define tx4927_ebuscptr \ 195 ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG) 196#define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG) 197 198#define TX4927_REV_PCODE() \ 199 ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16) 200 201#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)]) 202#define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21) 203#define TX4927_SDRAMC_SIZE(ch) \ 204 ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21) 205 206#define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)]) 207#define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20) 208#define TX4927_EBUSC_SIZE(ch) \ 209 (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf)) 210#define TX4927_EBUSC_WIDTH(ch) \ 211 (64 >> ((__u32)(TX4927_EBUSC_CR(ch) >> 20) & 0x3)) 212 213/* utilities */ 214static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits) 215{ 216#ifdef CONFIG_32BIT 217 unsigned long flags; 218 local_irq_save(flags); 219#endif 220 ____raw_writeq(____raw_readq(adr) & ~bits, adr); 221#ifdef CONFIG_32BIT 222 local_irq_restore(flags); 223#endif 224} 225static inline void txx9_set64(__u64 __iomem *adr, __u64 bits) 226{ 227#ifdef CONFIG_32BIT 228 unsigned long flags; 229 local_irq_save(flags); 230#endif 231 ____raw_writeq(____raw_readq(adr) | bits, adr); 232#ifdef CONFIG_32BIT 233 local_irq_restore(flags); 234#endif 235} 236 237/* These functions are not interrupt safe. */ 238static inline void tx4927_ccfg_clear(__u64 bits) 239{ 240 ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg) 241 & ~(TX4927_CCFG_W1CBITS | bits), 242 &tx4927_ccfgptr->ccfg); 243} 244static inline void tx4927_ccfg_set(__u64 bits) 245{ 246 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg) 247 & ~TX4927_CCFG_W1CBITS) | bits, 248 &tx4927_ccfgptr->ccfg); 249} 250static inline void tx4927_ccfg_change(__u64 change, __u64 new) 251{ 252 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg) 253 & ~(TX4927_CCFG_W1CBITS | change)) | 254 new, 255 &tx4927_ccfgptr->ccfg); 256} 257 258unsigned int tx4927_get_mem_size(void); 259void tx4927_wdt_init(void); 260void tx4927_setup(void); 261void tx4927_time_init(unsigned int tmrnr); 262void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask); 263int tx4927_report_pciclk(void); 264int tx4927_pciclk66_setup(void); 265void tx4927_setup_pcierr_irq(void); 266void tx4927_irq_init(void); 267void tx4927_mtd_init(int ch); 268 269#endif /* __ASM_TXX9_TX4927_H */ 270