linux/Documentation/voyager.txt
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   1Running Linux on the Voyager Architecture
   2=========================================
   3
   4For full details and current project status, see
   5
   6http://www.hansenpartnership.com/voyager
   7
   8The voyager architecture was designed by NCR in the mid 80s to be a
   9fully SMP capable RAS computing architecture built around intel's 486
  10chip set.  The voyager came in three levels of architectural
  11sophistication: 3,4 and 5 --- 1 and 2 never made it out of prototype.
  12The linux patches support only the Level 5 voyager architecture (any
  13machine class 3435 and above).
  14
  15The Voyager Architecture
  16------------------------
  17
  18Voyager machines consist of a Baseboard with a 386 diagnostic
  19processor, a Power Supply Interface (PSI) a Primary and possibly
  20Secondary Microchannel bus and between 2 and 20 voyager slots.  The
  21voyager slots can be populated with memory and cpu cards (up to 4GB
  22memory and from 1 486 to 32 Pentium Pro processors).  Internally, the
  23voyager has a dual arbitrated system bus and a configuration and test
  24bus (CAT).  The voyager bus speed is 40MHz.  Therefore (since all
  25voyager cards are dual ported for each system bus) the maximum
  26transfer rate is 320Mb/s but only if you have your slot configuration
  27tuned (only memory cards can communicate with both busses at once, CPU
  28cards utilise them one at a time).
  29
  30Voyager SMP
  31-----------
  32
  33Since voyager was the first intel based SMP system, it is slightly
  34more primitive than the Intel IO-APIC approach to SMP.  Voyager allows
  35arbitrary interrupt routing (including processor affinity routing) of
  36all 16 PC type interrupts.  However it does this by using a modified
  375259 master/slave chip set instead of an APIC bus.  Additionally,
  38voyager supports Cross Processor Interrupts (CPI) equivalent to the
  39APIC IPIs.  There are two routed voyager interrupt lines provided to
  40each slot.
  41
  42Processor Cards
  43---------------
  44
  45These come in single, dyadic and quad configurations (the quads are
  46problematic--see later).  The maximum configuration is 8 quad cards
  47for 32 way SMP.
  48
  49Quad Processors
  50---------------
  51
  52Because voyager only supplies two interrupt lines to each Processor
  53card, the Quad processors have to be configured (and Bootstrapped) in
  54as a pair of Master/Slave processors.
  55
  56In fact, most Quad cards only accept one VIC interrupt line, so they
  57have one interrupt handling processor (called the VIC extended
  58processor) and three non-interrupt handling processors.
  59
  60Current Status
  61--------------
  62
  63The System will boot on Mono, Dyad and Quad cards.  There was
  64originally a Quad boot problem which has been fixed by proper gdt
  65alignment in the initial boot loader.  If you still cannot get your
  66voyager system to boot, email me at:
  67
  68<J.E.J.Bottomley@HansenPartnership.com>
  69
  70
  71The Quad cards now support using the separate Quad CPI vectors instead
  72of going through the VIC mailbox system.
  73
  74The Level 4 architecture (3430 and 3360 Machines) should also work
  75fine.
  76
  77Dump Switch
  78-----------
  79
  80The voyager dump switch sends out a broadcast NMI which the voyager
  81code intercepts and does a task dump.
  82
  83Power Switch
  84------------
  85
  86The front panel power switch is intercepted by the kernel and should
  87cause a system shutdown and power off.
  88
  89A Note About Mixed CPU Systems
  90------------------------------
  91
  92Linux isn't designed to handle mixed CPU systems very well.  In order
  93to get everything going you *must* make sure that your lowest
  94capability CPU is used for booting.  Also, mixing CPU classes
  95(e.g. 486 and 586) is really not going to work very well at all.
  96
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