linux/Documentation/kbuild/makefiles.txt
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   1Linux Kernel Makefiles
   2
   3This document describes the Linux kernel Makefiles.
   4
   5=== Table of Contents
   6
   7        === 1 Overview
   8        === 2 Who does what
   9        === 3 The kbuild files
  10           --- 3.1 Goal definitions
  11           --- 3.2 Built-in object goals - obj-y
  12           --- 3.3 Loadable module goals - obj-m
  13           --- 3.4 Objects which export symbols
  14           --- 3.5 Library file goals - lib-y
  15           --- 3.6 Descending down in directories
  16           --- 3.7 Compilation flags
  17           --- 3.8 Command line dependency
  18           --- 3.9 Dependency tracking
  19           --- 3.10 Special Rules
  20           --- 3.11 $(CC) support functions
  21
  22        === 4 Host Program support
  23           --- 4.1 Simple Host Program
  24           --- 4.2 Composite Host Programs
  25           --- 4.3 Defining shared libraries
  26           --- 4.4 Using C++ for host programs
  27           --- 4.5 Controlling compiler options for host programs
  28           --- 4.6 When host programs are actually built
  29           --- 4.7 Using hostprogs-$(CONFIG_FOO)
  30
  31        === 5 Kbuild clean infrastructure
  32
  33        === 6 Architecture Makefiles
  34           --- 6.1 Set variables to tweak the build to the architecture
  35           --- 6.2 Add prerequisites to archprepare:
  36           --- 6.3 List directories to visit when descending
  37           --- 6.4 Architecture-specific boot images
  38           --- 6.5 Building non-kbuild targets
  39           --- 6.6 Commands useful for building a boot image
  40           --- 6.7 Custom kbuild commands
  41           --- 6.8 Preprocessing linker scripts
  42
  43        === 7 Kbuild syntax for exported headers
  44                --- 7.1 header-y
  45                --- 7.2 objhdr-y
  46                --- 7.3 destination-y
  47                --- 7.4 unifdef-y (deprecated)
  48
  49        === 8 Kbuild Variables
  50        === 9 Makefile language
  51        === 10 Credits
  52        === 11 TODO
  53
  54=== 1 Overview
  55
  56The Makefiles have five parts:
  57
  58        Makefile                the top Makefile.
  59        .config                 the kernel configuration file.
  60        arch/$(ARCH)/Makefile   the arch Makefile.
  61        scripts/Makefile.*      common rules etc. for all kbuild Makefiles.
  62        kbuild Makefiles        there are about 500 of these.
  63
  64The top Makefile reads the .config file, which comes from the kernel
  65configuration process.
  66
  67The top Makefile is responsible for building two major products: vmlinux
  68(the resident kernel image) and modules (any module files).
  69It builds these goals by recursively descending into the subdirectories of
  70the kernel source tree.
  71The list of subdirectories which are visited depends upon the kernel
  72configuration. The top Makefile textually includes an arch Makefile
  73with the name arch/$(ARCH)/Makefile. The arch Makefile supplies
  74architecture-specific information to the top Makefile.
  75
  76Each subdirectory has a kbuild Makefile which carries out the commands
  77passed down from above. The kbuild Makefile uses information from the
  78.config file to construct various file lists used by kbuild to build
  79any built-in or modular targets.
  80
  81scripts/Makefile.* contains all the definitions/rules etc. that
  82are used to build the kernel based on the kbuild makefiles.
  83
  84
  85=== 2 Who does what
  86
  87People have four different relationships with the kernel Makefiles.
  88
  89*Users* are people who build kernels.  These people type commands such as
  90"make menuconfig" or "make".  They usually do not read or edit
  91any kernel Makefiles (or any other source files).
  92
  93*Normal developers* are people who work on features such as device
  94drivers, file systems, and network protocols.  These people need to
  95maintain the kbuild Makefiles for the subsystem they are
  96working on.  In order to do this effectively, they need some overall
  97knowledge about the kernel Makefiles, plus detailed knowledge about the
  98public interface for kbuild.
  99
 100*Arch developers* are people who work on an entire architecture, such
 101as sparc or ia64.  Arch developers need to know about the arch Makefile
 102as well as kbuild Makefiles.
 103
 104*Kbuild developers* are people who work on the kernel build system itself.
 105These people need to know about all aspects of the kernel Makefiles.
 106
 107This document is aimed towards normal developers and arch developers.
 108
 109
 110=== 3 The kbuild files
 111
 112Most Makefiles within the kernel are kbuild Makefiles that use the
 113kbuild infrastructure. This chapter introduces the syntax used in the
 114kbuild makefiles.
 115The preferred name for the kbuild files are 'Makefile' but 'Kbuild' can
 116be used and if both a 'Makefile' and a 'Kbuild' file exists, then the 'Kbuild'
 117file will be used.
 118
 119Section 3.1 "Goal definitions" is a quick intro, further chapters provide
 120more details, with real examples.
 121
 122--- 3.1 Goal definitions
 123
 124        Goal definitions are the main part (heart) of the kbuild Makefile.
 125        These lines define the files to be built, any special compilation
 126        options, and any subdirectories to be entered recursively.
 127
 128        The most simple kbuild makefile contains one line:
 129
 130        Example:
 131                obj-y += foo.o
 132
 133        This tells kbuild that there is one object in that directory, named
 134        foo.o. foo.o will be built from foo.c or foo.S.
 135
 136        If foo.o shall be built as a module, the variable obj-m is used.
 137        Therefore the following pattern is often used:
 138
 139        Example:
 140                obj-$(CONFIG_FOO) += foo.o
 141
 142        $(CONFIG_FOO) evaluates to either y (for built-in) or m (for module).
 143        If CONFIG_FOO is neither y nor m, then the file will not be compiled
 144        nor linked.
 145
 146--- 3.2 Built-in object goals - obj-y
 147
 148        The kbuild Makefile specifies object files for vmlinux
 149        in the $(obj-y) lists.  These lists depend on the kernel
 150        configuration.
 151
 152        Kbuild compiles all the $(obj-y) files.  It then calls
 153        "$(LD) -r" to merge these files into one built-in.o file.
 154        built-in.o is later linked into vmlinux by the parent Makefile.
 155
 156        The order of files in $(obj-y) is significant.  Duplicates in
 157        the lists are allowed: the first instance will be linked into
 158        built-in.o and succeeding instances will be ignored.
 159
 160        Link order is significant, because certain functions
 161        (module_init() / __initcall) will be called during boot in the
 162        order they appear. So keep in mind that changing the link
 163        order may e.g. change the order in which your SCSI
 164        controllers are detected, and thus your disks are renumbered.
 165
 166        Example:
 167                #drivers/isdn/i4l/Makefile
 168                # Makefile for the kernel ISDN subsystem and device drivers.
 169                # Each configuration option enables a list of files.
 170                obj-$(CONFIG_ISDN)             += isdn.o
 171                obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
 172
 173--- 3.3 Loadable module goals - obj-m
 174
 175        $(obj-m) specify object files which are built as loadable
 176        kernel modules.
 177
 178        A module may be built from one source file or several source
 179        files. In the case of one source file, the kbuild makefile
 180        simply adds the file to $(obj-m).
 181
 182        Example:
 183                #drivers/isdn/i4l/Makefile
 184                obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
 185
 186        Note: In this example $(CONFIG_ISDN_PPP_BSDCOMP) evaluates to 'm'
 187
 188        If a kernel module is built from several source files, you specify
 189        that you want to build a module in the same way as above.
 190
 191        Kbuild needs to know which the parts that you want to build your
 192        module from, so you have to tell it by setting an
 193        $(<module_name>-objs) variable.
 194
 195        Example:
 196                #drivers/isdn/i4l/Makefile
 197                obj-$(CONFIG_ISDN) += isdn.o
 198                isdn-objs := isdn_net_lib.o isdn_v110.o isdn_common.o
 199
 200        In this example, the module name will be isdn.o. Kbuild will
 201        compile the objects listed in $(isdn-objs) and then run
 202        "$(LD) -r" on the list of these files to generate isdn.o.
 203
 204        Kbuild recognises objects used for composite objects by the suffix
 205        -objs, and the suffix -y. This allows the Makefiles to use
 206        the value of a CONFIG_ symbol to determine if an object is part
 207        of a composite object.
 208
 209        Example:
 210                #fs/ext2/Makefile
 211                obj-$(CONFIG_EXT2_FS)        += ext2.o
 212                ext2-y                       := balloc.o bitmap.o
 213                ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o
 214
 215        In this example, xattr.o is only part of the composite object
 216        ext2.o if $(CONFIG_EXT2_FS_XATTR) evaluates to 'y'.
 217
 218        Note: Of course, when you are building objects into the kernel,
 219        the syntax above will also work. So, if you have CONFIG_EXT2_FS=y,
 220        kbuild will build an ext2.o file for you out of the individual
 221        parts and then link this into built-in.o, as you would expect.
 222
 223--- 3.4 Objects which export symbols
 224
 225        No special notation is required in the makefiles for
 226        modules exporting symbols.
 227
 228--- 3.5 Library file goals - lib-y
 229
 230        Objects listed with obj-* are used for modules, or
 231        combined in a built-in.o for that specific directory.
 232        There is also the possibility to list objects that will
 233        be included in a library, lib.a.
 234        All objects listed with lib-y are combined in a single
 235        library for that directory.
 236        Objects that are listed in obj-y and additionally listed in
 237        lib-y will not be included in the library, since they will
 238        be accessible anyway.
 239        For consistency, objects listed in lib-m will be included in lib.a.
 240
 241        Note that the same kbuild makefile may list files to be built-in
 242        and to be part of a library. Therefore the same directory
 243        may contain both a built-in.o and a lib.a file.
 244
 245        Example:
 246                #arch/i386/lib/Makefile
 247                lib-y    := checksum.o delay.o
 248
 249        This will create a library lib.a based on checksum.o and delay.o.
 250        For kbuild to actually recognize that there is a lib.a being built,
 251        the directory shall be listed in libs-y.
 252        See also "6.3 List directories to visit when descending".
 253
 254        Use of lib-y is normally restricted to lib/ and arch/*/lib.
 255
 256--- 3.6 Descending down in directories
 257
 258        A Makefile is only responsible for building objects in its own
 259        directory. Files in subdirectories should be taken care of by
 260        Makefiles in these subdirs. The build system will automatically
 261        invoke make recursively in subdirectories, provided you let it know of
 262        them.
 263
 264        To do so, obj-y and obj-m are used.
 265        ext2 lives in a separate directory, and the Makefile present in fs/
 266        tells kbuild to descend down using the following assignment.
 267
 268        Example:
 269                #fs/Makefile
 270                obj-$(CONFIG_EXT2_FS) += ext2/
 271
 272        If CONFIG_EXT2_FS is set to either 'y' (built-in) or 'm' (modular)
 273        the corresponding obj- variable will be set, and kbuild will descend
 274        down in the ext2 directory.
 275        Kbuild only uses this information to decide that it needs to visit
 276        the directory, it is the Makefile in the subdirectory that
 277        specifies what is modules and what is built-in.
 278
 279        It is good practice to use a CONFIG_ variable when assigning directory
 280        names. This allows kbuild to totally skip the directory if the
 281        corresponding CONFIG_ option is neither 'y' nor 'm'.
 282
 283--- 3.7 Compilation flags
 284
 285    ccflags-y, asflags-y and ldflags-y
 286        The three flags listed above applies only to the kbuild makefile
 287        where they are assigned. They are used for all the normal
 288        cc, as and ld invocation happenign during a recursive build.
 289        Note: Flags with the same behaviour were previously named:
 290        EXTRA_CFLAGS, EXTRA_AFLAGS and EXTRA_LDFLAGS.
 291        They are yet supported but their use are deprecated.
 292
 293        ccflags-y specifies options for compiling C files with $(CC).
 294
 295        Example:
 296                # drivers/sound/emu10k1/Makefile
 297                ccflags-y += -I$(obj)
 298                ccflags-$(DEBUG) += -DEMU10K1_DEBUG
 299
 300
 301        This variable is necessary because the top Makefile owns the
 302        variable $(KBUILD_CFLAGS) and uses it for compilation flags for the
 303        entire tree.
 304
 305        asflags-y is a similar string for per-directory options
 306        when compiling assembly language source.
 307
 308        Example:
 309                #arch/x86_64/kernel/Makefile
 310                asflags-y := -traditional
 311
 312
 313        ldflags-y is a string for per-directory options to $(LD).
 314
 315        Example:
 316                #arch/m68k/fpsp040/Makefile
 317                ldflags-y := -x
 318
 319    subdir-ccflags-y, subdir-asflags-y
 320        The two flags listed above are similar to ccflags-y and as-falgs-y.
 321        The difference is that the subdir- variants has effect for the kbuild
 322        file where tey are present and all subdirectories.
 323        Options specified using subdir-* are added to the commandline before
 324        the options specified using the non-subdir variants.
 325
 326        Example:
 327                subdir-ccflags-y := -Werror
 328
 329    CFLAGS_$@, AFLAGS_$@
 330
 331        CFLAGS_$@ and AFLAGS_$@ only apply to commands in current
 332        kbuild makefile.
 333
 334        $(CFLAGS_$@) specifies per-file options for $(CC).  The $@
 335        part has a literal value which specifies the file that it is for.
 336
 337        Example:
 338                # drivers/scsi/Makefile
 339                CFLAGS_aha152x.o =   -DAHA152X_STAT -DAUTOCONF
 340                CFLAGS_gdth.o    = # -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ \
 341                                     -DGDTH_STATISTICS
 342                CFLAGS_seagate.o =   -DARBITRATE -DPARITY -DSEAGATE_USE_ASM
 343
 344        These three lines specify compilation flags for aha152x.o,
 345        gdth.o, and seagate.o
 346
 347        $(AFLAGS_$@) is a similar feature for source files in assembly
 348        languages.
 349
 350        Example:
 351                # arch/arm/kernel/Makefile
 352                AFLAGS_head-armv.o := -DTEXTADDR=$(TEXTADDR) -traditional
 353                AFLAGS_head-armo.o := -DTEXTADDR=$(TEXTADDR) -traditional
 354
 355--- 3.9 Dependency tracking
 356
 357        Kbuild tracks dependencies on the following:
 358        1) All prerequisite files (both *.c and *.h)
 359        2) CONFIG_ options used in all prerequisite files
 360        3) Command-line used to compile target
 361
 362        Thus, if you change an option to $(CC) all affected files will
 363        be re-compiled.
 364
 365--- 3.10 Special Rules
 366
 367        Special rules are used when the kbuild infrastructure does
 368        not provide the required support. A typical example is
 369        header files generated during the build process.
 370        Another example are the architecture-specific Makefiles which
 371        need special rules to prepare boot images etc.
 372
 373        Special rules are written as normal Make rules.
 374        Kbuild is not executing in the directory where the Makefile is
 375        located, so all special rules shall provide a relative
 376        path to prerequisite files and target files.
 377
 378        Two variables are used when defining special rules:
 379
 380    $(src)
 381        $(src) is a relative path which points to the directory
 382        where the Makefile is located. Always use $(src) when
 383        referring to files located in the src tree.
 384
 385    $(obj)
 386        $(obj) is a relative path which points to the directory
 387        where the target is saved. Always use $(obj) when
 388        referring to generated files.
 389
 390        Example:
 391                #drivers/scsi/Makefile
 392                $(obj)/53c8xx_d.h: $(src)/53c7,8xx.scr $(src)/script_asm.pl
 393                        $(CPP) -DCHIP=810 - < $< | ... $(src)/script_asm.pl
 394
 395        This is a special rule, following the normal syntax
 396        required by make.
 397        The target file depends on two prerequisite files. References
 398        to the target file are prefixed with $(obj), references
 399        to prerequisites are referenced with $(src) (because they are not
 400        generated files).
 401
 402    $(kecho)
 403        echoing information to user in a rule is often a good practice
 404        but when execution "make -s" one does not expect to see any output
 405        except for warnings/errors.
 406        To support this kbuild define $(kecho) which will echo out the
 407        text following $(kecho) to stdout except if "make -s" is used.
 408
 409        Example:
 410                #arch/blackfin/boot/Makefile
 411                $(obj)/vmImage: $(obj)/vmlinux.gz
 412                        $(call if_changed,uimage)
 413                        @$(kecho) 'Kernel: $@ is ready'
 414
 415
 416--- 3.11 $(CC) support functions
 417
 418        The kernel may be built with several different versions of
 419        $(CC), each supporting a unique set of features and options.
 420        kbuild provide basic support to check for valid options for $(CC).
 421        $(CC) is usually the gcc compiler, but other alternatives are
 422        available.
 423
 424    as-option
 425        as-option is used to check if $(CC) -- when used to compile
 426        assembler (*.S) files -- supports the given option. An optional
 427        second option may be specified if the first option is not supported.
 428
 429        Example:
 430                #arch/sh/Makefile
 431                cflags-y += $(call as-option,-Wa$(comma)-isa=$(isa-y),)
 432
 433        In the above example, cflags-y will be assigned the option
 434        -Wa$(comma)-isa=$(isa-y) if it is supported by $(CC).
 435        The second argument is optional, and if supplied will be used
 436        if first argument is not supported.
 437
 438    ld-option
 439        ld-option is used to check if $(CC) when used to link object files
 440        supports the given option.  An optional second option may be
 441        specified if first option are not supported.
 442
 443        Example:
 444                #arch/i386/kernel/Makefile
 445                vsyscall-flags += $(call ld-option, -Wl$(comma)--hash-style=sysv)
 446
 447        In the above example, vsyscall-flags will be assigned the option
 448        -Wl$(comma)--hash-style=sysv if it is supported by $(CC).
 449        The second argument is optional, and if supplied will be used
 450        if first argument is not supported.
 451
 452    as-instr
 453        as-instr checks if the assembler reports a specific instruction
 454        and then outputs either option1 or option2
 455        C escapes are supported in the test instruction
 456        Note: as-instr-option uses KBUILD_AFLAGS for $(AS) options
 457
 458    cc-option
 459        cc-option is used to check if $(CC) supports a given option, and not
 460        supported to use an optional second option.
 461
 462        Example:
 463                #arch/i386/Makefile
 464                cflags-y += $(call cc-option,-march=pentium-mmx,-march=i586)
 465
 466        In the above example, cflags-y will be assigned the option
 467        -march=pentium-mmx if supported by $(CC), otherwise -march=i586.
 468        The second argument to cc-option is optional, and if omitted,
 469        cflags-y will be assigned no value if first option is not supported.
 470        Note: cc-option uses KBUILD_CFLAGS for $(CC) options
 471
 472   cc-option-yn
 473        cc-option-yn is used to check if gcc supports a given option
 474        and return 'y' if supported, otherwise 'n'.
 475
 476        Example:
 477                #arch/ppc/Makefile
 478                biarch := $(call cc-option-yn, -m32)
 479                aflags-$(biarch) += -a32
 480                cflags-$(biarch) += -m32
 481
 482        In the above example, $(biarch) is set to y if $(CC) supports the -m32
 483        option. When $(biarch) equals 'y', the expanded variables $(aflags-y)
 484        and $(cflags-y) will be assigned the values -a32 and -m32,
 485        respectively.
 486        Note: cc-option-yn uses KBUILD_CFLAGS for $(CC) options
 487
 488    cc-option-align
 489        gcc versions >= 3.0 changed the type of options used to specify
 490        alignment of functions, loops etc. $(cc-option-align), when used
 491        as prefix to the align options, will select the right prefix:
 492        gcc < 3.00
 493                cc-option-align = -malign
 494        gcc >= 3.00
 495                cc-option-align = -falign
 496
 497        Example:
 498                KBUILD_CFLAGS += $(cc-option-align)-functions=4
 499
 500        In the above example, the option -falign-functions=4 is used for
 501        gcc >= 3.00. For gcc < 3.00, -malign-functions=4 is used.
 502        Note: cc-option-align uses KBUILD_CFLAGS for $(CC) options
 503
 504    cc-version
 505        cc-version returns a numerical version of the $(CC) compiler version.
 506        The format is <major><minor> where both are two digits. So for example
 507        gcc 3.41 would return 0341.
 508        cc-version is useful when a specific $(CC) version is faulty in one
 509        area, for example -mregparm=3 was broken in some gcc versions
 510        even though the option was accepted by gcc.
 511
 512        Example:
 513                #arch/i386/Makefile
 514                cflags-y += $(shell \
 515                if [ $(call cc-version) -ge 0300 ] ; then \
 516                        echo "-mregparm=3"; fi ;)
 517
 518        In the above example, -mregparm=3 is only used for gcc version greater
 519        than or equal to gcc 3.0.
 520
 521    cc-ifversion
 522        cc-ifversion tests the version of $(CC) and equals last argument if
 523        version expression is true.
 524
 525        Example:
 526                #fs/reiserfs/Makefile
 527                ccflags-y := $(call cc-ifversion, -lt, 0402, -O1)
 528
 529        In this example, ccflags-y will be assigned the value -O1 if the
 530        $(CC) version is less than 4.2.
 531        cc-ifversion takes all the shell operators:
 532        -eq, -ne, -lt, -le, -gt, and -ge
 533        The third parameter may be a text as in this example, but it may also
 534        be an expanded variable or a macro.
 535
 536    cc-fullversion
 537        cc-fullversion is useful when the exact version of gcc is needed.
 538        One typical use-case is when a specific GCC version is broken.
 539        cc-fullversion points out a more specific version than cc-version does.
 540
 541        Example:
 542                #arch/powerpc/Makefile
 543                $(Q)if test "$(call cc-fullversion)" = "040200" ; then \
 544                        echo -n '*** GCC-4.2.0 cannot compile the 64-bit powerpc ' ; \
 545                        false ; \
 546                fi
 547
 548        In this example for a specific GCC version the build will error out explaining
 549        to the user why it stops.
 550
 551    cc-cross-prefix
 552        cc-cross-prefix is used to check if there exists a $(CC) in path with
 553        one of the listed prefixes. The first prefix where there exist a
 554        prefix$(CC) in the PATH is returned - and if no prefix$(CC) is found
 555        then nothing is returned.
 556        Additional prefixes are separated by a single space in the
 557        call of cc-cross-prefix.
 558        This functionality is useful for architecture Makefiles that try
 559        to set CROSS_COMPILE to well-known values but may have several
 560        values to select between.
 561        It is recommended only to try to set CROSS_COMPILE if it is a cross
 562        build (host arch is different from target arch). And if CROSS_COMPILE
 563        is already set then leave it with the old value.
 564
 565        Example:
 566                #arch/m68k/Makefile
 567                ifneq ($(SUBARCH),$(ARCH))
 568                        ifeq ($(CROSS_COMPILE),)
 569                               CROSS_COMPILE := $(call cc-cross-prefix, m68k-linux-gnu-)
 570                        endif
 571                endif
 572
 573=== 4 Host Program support
 574
 575Kbuild supports building executables on the host for use during the
 576compilation stage.
 577Two steps are required in order to use a host executable.
 578
 579The first step is to tell kbuild that a host program exists. This is
 580done utilising the variable hostprogs-y.
 581
 582The second step is to add an explicit dependency to the executable.
 583This can be done in two ways. Either add the dependency in a rule,
 584or utilise the variable $(always).
 585Both possibilities are described in the following.
 586
 587--- 4.1 Simple Host Program
 588
 589        In some cases there is a need to compile and run a program on the
 590        computer where the build is running.
 591        The following line tells kbuild that the program bin2hex shall be
 592        built on the build host.
 593
 594        Example:
 595                hostprogs-y := bin2hex
 596
 597        Kbuild assumes in the above example that bin2hex is made from a single
 598        c-source file named bin2hex.c located in the same directory as
 599        the Makefile.
 600
 601--- 4.2 Composite Host Programs
 602
 603        Host programs can be made up based on composite objects.
 604        The syntax used to define composite objects for host programs is
 605        similar to the syntax used for kernel objects.
 606        $(<executable>-objs) lists all objects used to link the final
 607        executable.
 608
 609        Example:
 610                #scripts/lxdialog/Makefile
 611                hostprogs-y   := lxdialog
 612                lxdialog-objs := checklist.o lxdialog.o
 613
 614        Objects with extension .o are compiled from the corresponding .c
 615        files. In the above example, checklist.c is compiled to checklist.o
 616        and lxdialog.c is compiled to lxdialog.o.
 617        Finally, the two .o files are linked to the executable, lxdialog.
 618        Note: The syntax <executable>-y is not permitted for host-programs.
 619
 620--- 4.3 Defining shared libraries
 621
 622        Objects with extension .so are considered shared libraries, and
 623        will be compiled as position independent objects.
 624        Kbuild provides support for shared libraries, but the usage
 625        shall be restricted.
 626        In the following example the libkconfig.so shared library is used
 627        to link the executable conf.
 628
 629        Example:
 630                #scripts/kconfig/Makefile
 631                hostprogs-y     := conf
 632                conf-objs       := conf.o libkconfig.so
 633                libkconfig-objs := expr.o type.o
 634
 635        Shared libraries always require a corresponding -objs line, and
 636        in the example above the shared library libkconfig is composed by
 637        the two objects expr.o and type.o.
 638        expr.o and type.o will be built as position independent code and
 639        linked as a shared library libkconfig.so. C++ is not supported for
 640        shared libraries.
 641
 642--- 4.4 Using C++ for host programs
 643
 644        kbuild offers support for host programs written in C++. This was
 645        introduced solely to support kconfig, and is not recommended
 646        for general use.
 647
 648        Example:
 649                #scripts/kconfig/Makefile
 650                hostprogs-y   := qconf
 651                qconf-cxxobjs := qconf.o
 652
 653        In the example above the executable is composed of the C++ file
 654        qconf.cc - identified by $(qconf-cxxobjs).
 655
 656        If qconf is composed by a mixture of .c and .cc files, then an
 657        additional line can be used to identify this.
 658
 659        Example:
 660                #scripts/kconfig/Makefile
 661                hostprogs-y   := qconf
 662                qconf-cxxobjs := qconf.o
 663                qconf-objs    := check.o
 664
 665--- 4.5 Controlling compiler options for host programs
 666
 667        When compiling host programs, it is possible to set specific flags.
 668        The programs will always be compiled utilising $(HOSTCC) passed
 669        the options specified in $(HOSTCFLAGS).
 670        To set flags that will take effect for all host programs created
 671        in that Makefile, use the variable HOST_EXTRACFLAGS.
 672
 673        Example:
 674                #scripts/lxdialog/Makefile
 675                HOST_EXTRACFLAGS += -I/usr/include/ncurses
 676
 677        To set specific flags for a single file the following construction
 678        is used:
 679
 680        Example:
 681                #arch/ppc64/boot/Makefile
 682                HOSTCFLAGS_piggyback.o := -DKERNELBASE=$(KERNELBASE)
 683
 684        It is also possible to specify additional options to the linker.
 685
 686        Example:
 687                #scripts/kconfig/Makefile
 688                HOSTLOADLIBES_qconf := -L$(QTDIR)/lib
 689
 690        When linking qconf, it will be passed the extra option
 691        "-L$(QTDIR)/lib".
 692
 693--- 4.6 When host programs are actually built
 694
 695        Kbuild will only build host-programs when they are referenced
 696        as a prerequisite.
 697        This is possible in two ways:
 698
 699        (1) List the prerequisite explicitly in a special rule.
 700
 701        Example:
 702                #drivers/pci/Makefile
 703                hostprogs-y := gen-devlist
 704                $(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
 705                        ( cd $(obj); ./gen-devlist ) < $<
 706
 707        The target $(obj)/devlist.h will not be built before
 708        $(obj)/gen-devlist is updated. Note that references to
 709        the host programs in special rules must be prefixed with $(obj).
 710
 711        (2) Use $(always)
 712        When there is no suitable special rule, and the host program
 713        shall be built when a makefile is entered, the $(always)
 714        variable shall be used.
 715
 716        Example:
 717                #scripts/lxdialog/Makefile
 718                hostprogs-y   := lxdialog
 719                always        := $(hostprogs-y)
 720
 721        This will tell kbuild to build lxdialog even if not referenced in
 722        any rule.
 723
 724--- 4.7 Using hostprogs-$(CONFIG_FOO)
 725
 726        A typical pattern in a Kbuild file looks like this:
 727
 728        Example:
 729                #scripts/Makefile
 730                hostprogs-$(CONFIG_KALLSYMS) += kallsyms
 731
 732        Kbuild knows about both 'y' for built-in and 'm' for module.
 733        So if a config symbol evaluate to 'm', kbuild will still build
 734        the binary. In other words, Kbuild handles hostprogs-m exactly
 735        like hostprogs-y. But only hostprogs-y is recommended to be used
 736        when no CONFIG symbols are involved.
 737
 738=== 5 Kbuild clean infrastructure
 739
 740"make clean" deletes most generated files in the obj tree where the kernel
 741is compiled. This includes generated files such as host programs.
 742Kbuild knows targets listed in $(hostprogs-y), $(hostprogs-m), $(always),
 743$(extra-y) and $(targets). They are all deleted during "make clean".
 744Files matching the patterns "*.[oas]", "*.ko", plus some additional files
 745generated by kbuild are deleted all over the kernel src tree when
 746"make clean" is executed.
 747
 748Additional files can be specified in kbuild makefiles by use of $(clean-files).
 749
 750        Example:
 751                #drivers/pci/Makefile
 752                clean-files := devlist.h classlist.h
 753
 754When executing "make clean", the two files "devlist.h classlist.h" will
 755be deleted. Kbuild will assume files to be in same relative directory as the
 756Makefile except if an absolute path is specified (path starting with '/').
 757
 758To delete a directory hierarchy use:
 759
 760        Example:
 761                #scripts/package/Makefile
 762                clean-dirs := $(objtree)/debian/
 763
 764This will delete the directory debian, including all subdirectories.
 765Kbuild will assume the directories to be in the same relative path as the
 766Makefile if no absolute path is specified (path does not start with '/').
 767
 768Usually kbuild descends down in subdirectories due to "obj-* := dir/",
 769but in the architecture makefiles where the kbuild infrastructure
 770is not sufficient this sometimes needs to be explicit.
 771
 772        Example:
 773                #arch/i386/boot/Makefile
 774                subdir- := compressed/
 775
 776The above assignment instructs kbuild to descend down in the
 777directory compressed/ when "make clean" is executed.
 778
 779To support the clean infrastructure in the Makefiles that builds the
 780final bootimage there is an optional target named archclean:
 781
 782        Example:
 783                #arch/i386/Makefile
 784                archclean:
 785                        $(Q)$(MAKE) $(clean)=arch/i386/boot
 786
 787When "make clean" is executed, make will descend down in arch/i386/boot,
 788and clean as usual. The Makefile located in arch/i386/boot/ may use
 789the subdir- trick to descend further down.
 790
 791Note 1: arch/$(ARCH)/Makefile cannot use "subdir-", because that file is
 792included in the top level makefile, and the kbuild infrastructure
 793is not operational at that point.
 794
 795Note 2: All directories listed in core-y, libs-y, drivers-y and net-y will
 796be visited during "make clean".
 797
 798=== 6 Architecture Makefiles
 799
 800The top level Makefile sets up the environment and does the preparation,
 801before starting to descend down in the individual directories.
 802The top level makefile contains the generic part, whereas
 803arch/$(ARCH)/Makefile contains what is required to set up kbuild
 804for said architecture.
 805To do so, arch/$(ARCH)/Makefile sets up a number of variables and defines
 806a few targets.
 807
 808When kbuild executes, the following steps are followed (roughly):
 8091) Configuration of the kernel => produce .config
 8102) Store kernel version in include/linux/version.h
 8113) Symlink include/asm to include/asm-$(ARCH)
 8124) Updating all other prerequisites to the target prepare:
 813   - Additional prerequisites are specified in arch/$(ARCH)/Makefile
 8145) Recursively descend down in all directories listed in
 815   init-* core* drivers-* net-* libs-* and build all targets.
 816   - The values of the above variables are expanded in arch/$(ARCH)/Makefile.
 8176) All object files are then linked and the resulting file vmlinux is
 818   located at the root of the obj tree.
 819   The very first objects linked are listed in head-y, assigned by
 820   arch/$(ARCH)/Makefile.
 8217) Finally, the architecture-specific part does any required post processing
 822   and builds the final bootimage.
 823   - This includes building boot records
 824   - Preparing initrd images and the like
 825
 826
 827--- 6.1 Set variables to tweak the build to the architecture
 828
 829    LDFLAGS             Generic $(LD) options
 830
 831        Flags used for all invocations of the linker.
 832        Often specifying the emulation is sufficient.
 833
 834        Example:
 835                #arch/s390/Makefile
 836                LDFLAGS         := -m elf_s390
 837        Note: ldflags-y can be used to further customise
 838        the flags used. See chapter 3.7.
 839
 840    LDFLAGS_MODULE      Options for $(LD) when linking modules
 841
 842        LDFLAGS_MODULE is used to set specific flags for $(LD) when
 843        linking the .ko files used for modules.
 844        Default is "-r", for relocatable output.
 845
 846    LDFLAGS_vmlinux     Options for $(LD) when linking vmlinux
 847
 848        LDFLAGS_vmlinux is used to specify additional flags to pass to
 849        the linker when linking the final vmlinux image.
 850        LDFLAGS_vmlinux uses the LDFLAGS_$@ support.
 851
 852        Example:
 853                #arch/i386/Makefile
 854                LDFLAGS_vmlinux := -e stext
 855
 856    OBJCOPYFLAGS        objcopy flags
 857
 858        When $(call if_changed,objcopy) is used to translate a .o file,
 859        the flags specified in OBJCOPYFLAGS will be used.
 860        $(call if_changed,objcopy) is often used to generate raw binaries on
 861        vmlinux.
 862
 863        Example:
 864                #arch/s390/Makefile
 865                OBJCOPYFLAGS := -O binary
 866
 867                #arch/s390/boot/Makefile
 868                $(obj)/image: vmlinux FORCE
 869                        $(call if_changed,objcopy)
 870
 871        In this example, the binary $(obj)/image is a binary version of
 872        vmlinux. The usage of $(call if_changed,xxx) will be described later.
 873
 874    KBUILD_AFLAGS               $(AS) assembler flags
 875
 876        Default value - see top level Makefile
 877        Append or modify as required per architecture.
 878
 879        Example:
 880                #arch/sparc64/Makefile
 881                KBUILD_AFLAGS += -m64 -mcpu=ultrasparc
 882
 883    KBUILD_CFLAGS               $(CC) compiler flags
 884
 885        Default value - see top level Makefile
 886        Append or modify as required per architecture.
 887
 888        Often, the KBUILD_CFLAGS variable depends on the configuration.
 889
 890        Example:
 891                #arch/i386/Makefile
 892                cflags-$(CONFIG_M386) += -march=i386
 893                KBUILD_CFLAGS += $(cflags-y)
 894
 895        Many arch Makefiles dynamically run the target C compiler to
 896        probe supported options:
 897
 898                #arch/i386/Makefile
 899
 900                ...
 901                cflags-$(CONFIG_MPENTIUMII)     += $(call cc-option,\
 902                                                -march=pentium2,-march=i686)
 903                ...
 904                # Disable unit-at-a-time mode ...
 905                KBUILD_CFLAGS += $(call cc-option,-fno-unit-at-a-time)
 906                ...
 907
 908
 909        The first example utilises the trick that a config option expands
 910        to 'y' when selected.
 911
 912    CFLAGS_KERNEL       $(CC) options specific for built-in
 913
 914        $(CFLAGS_KERNEL) contains extra C compiler flags used to compile
 915        resident kernel code.
 916
 917    CFLAGS_MODULE       $(CC) options specific for modules
 918
 919        $(CFLAGS_MODULE) contains extra C compiler flags used to compile code
 920        for loadable kernel modules.
 921
 922
 923--- 6.2 Add prerequisites to archprepare:
 924
 925        The archprepare: rule is used to list prerequisites that need to be
 926        built before starting to descend down in the subdirectories.
 927        This is usually used for header files containing assembler constants.
 928
 929                Example:
 930                #arch/arm/Makefile
 931                archprepare: maketools
 932
 933        In this example, the file target maketools will be processed
 934        before descending down in the subdirectories.
 935        See also chapter XXX-TODO that describe how kbuild supports
 936        generating offset header files.
 937
 938
 939--- 6.3 List directories to visit when descending
 940
 941        An arch Makefile cooperates with the top Makefile to define variables
 942        which specify how to build the vmlinux file.  Note that there is no
 943        corresponding arch-specific section for modules; the module-building
 944        machinery is all architecture-independent.
 945
 946
 947    head-y, init-y, core-y, libs-y, drivers-y, net-y
 948
 949        $(head-y) lists objects to be linked first in vmlinux.
 950        $(libs-y) lists directories where a lib.a archive can be located.
 951        The rest list directories where a built-in.o object file can be
 952        located.
 953
 954        $(init-y) objects will be located after $(head-y).
 955        Then the rest follows in this order:
 956        $(core-y), $(libs-y), $(drivers-y) and $(net-y).
 957
 958        The top level Makefile defines values for all generic directories,
 959        and arch/$(ARCH)/Makefile only adds architecture-specific directories.
 960
 961        Example:
 962                #arch/sparc64/Makefile
 963                core-y += arch/sparc64/kernel/
 964                libs-y += arch/sparc64/prom/ arch/sparc64/lib/
 965                drivers-$(CONFIG_OPROFILE)  += arch/sparc64/oprofile/
 966
 967
 968--- 6.4 Architecture-specific boot images
 969
 970        An arch Makefile specifies goals that take the vmlinux file, compress
 971        it, wrap it in bootstrapping code, and copy the resulting files
 972        somewhere. This includes various kinds of installation commands.
 973        The actual goals are not standardized across architectures.
 974
 975        It is common to locate any additional processing in a boot/
 976        directory below arch/$(ARCH)/.
 977
 978        Kbuild does not provide any smart way to support building a
 979        target specified in boot/. Therefore arch/$(ARCH)/Makefile shall
 980        call make manually to build a target in boot/.
 981
 982        The recommended approach is to include shortcuts in
 983        arch/$(ARCH)/Makefile, and use the full path when calling down
 984        into the arch/$(ARCH)/boot/Makefile.
 985
 986        Example:
 987                #arch/i386/Makefile
 988                boot := arch/i386/boot
 989                bzImage: vmlinux
 990                        $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
 991
 992        "$(Q)$(MAKE) $(build)=<dir>" is the recommended way to invoke
 993        make in a subdirectory.
 994
 995        There are no rules for naming architecture-specific targets,
 996        but executing "make help" will list all relevant targets.
 997        To support this, $(archhelp) must be defined.
 998
 999        Example:
1000                #arch/i386/Makefile
1001                define archhelp
1002                  echo  '* bzImage      - Image (arch/$(ARCH)/boot/bzImage)'
1003                endif
1004
1005        When make is executed without arguments, the first goal encountered
1006        will be built. In the top level Makefile the first goal present
1007        is all:.
1008        An architecture shall always, per default, build a bootable image.
1009        In "make help", the default goal is highlighted with a '*'.
1010        Add a new prerequisite to all: to select a default goal different
1011        from vmlinux.
1012
1013        Example:
1014                #arch/i386/Makefile
1015                all: bzImage
1016
1017        When "make" is executed without arguments, bzImage will be built.
1018
1019--- 6.5 Building non-kbuild targets
1020
1021    extra-y
1022
1023        extra-y specify additional targets created in the current
1024        directory, in addition to any targets specified by obj-*.
1025
1026        Listing all targets in extra-y is required for two purposes:
1027        1) Enable kbuild to check changes in command lines
1028           - When $(call if_changed,xxx) is used
1029        2) kbuild knows what files to delete during "make clean"
1030
1031        Example:
1032                #arch/i386/kernel/Makefile
1033                extra-y := head.o init_task.o
1034
1035        In this example, extra-y is used to list object files that
1036        shall be built, but shall not be linked as part of built-in.o.
1037
1038
1039--- 6.6 Commands useful for building a boot image
1040
1041        Kbuild provides a few macros that are useful when building a
1042        boot image.
1043
1044    if_changed
1045
1046        if_changed is the infrastructure used for the following commands.
1047
1048        Usage:
1049                target: source(s) FORCE
1050                        $(call if_changed,ld/objcopy/gzip)
1051
1052        When the rule is evaluated, it is checked to see if any files
1053        need an update, or the command line has changed since the last
1054        invocation. The latter will force a rebuild if any options
1055        to the executable have changed.
1056        Any target that utilises if_changed must be listed in $(targets),
1057        otherwise the command line check will fail, and the target will
1058        always be built.
1059        Assignments to $(targets) are without $(obj)/ prefix.
1060        if_changed may be used in conjunction with custom commands as
1061        defined in 6.7 "Custom kbuild commands".
1062
1063        Note: It is a typical mistake to forget the FORCE prerequisite.
1064        Another common pitfall is that whitespace is sometimes
1065        significant; for instance, the below will fail (note the extra space
1066        after the comma):
1067                target: source(s) FORCE
1068        #WRONG!#        $(call if_changed, ld/objcopy/gzip)
1069
1070    ld
1071        Link target. Often, LDFLAGS_$@ is used to set specific options to ld.
1072
1073    objcopy
1074        Copy binary. Uses OBJCOPYFLAGS usually specified in
1075        arch/$(ARCH)/Makefile.
1076        OBJCOPYFLAGS_$@ may be used to set additional options.
1077
1078    gzip
1079        Compress target. Use maximum compression to compress target.
1080
1081        Example:
1082                #arch/i386/boot/Makefile
1083                LDFLAGS_bootsect := -Ttext 0x0 -s --oformat binary
1084                LDFLAGS_setup    := -Ttext 0x0 -s --oformat binary -e begtext
1085
1086                targets += setup setup.o bootsect bootsect.o
1087                $(obj)/setup $(obj)/bootsect: %: %.o FORCE
1088                        $(call if_changed,ld)
1089
1090        In this example, there are two possible targets, requiring different
1091        options to the linker. The linker options are specified using the
1092        LDFLAGS_$@ syntax - one for each potential target.
1093        $(targets) are assigned all potential targets, by which kbuild knows
1094        the targets and will:
1095                1) check for commandline changes
1096                2) delete target during make clean
1097
1098        The ": %: %.o" part of the prerequisite is a shorthand that
1099        free us from listing the setup.o and bootsect.o files.
1100        Note: It is a common mistake to forget the "target :=" assignment,
1101              resulting in the target file being recompiled for no
1102              obvious reason.
1103
1104
1105--- 6.7 Custom kbuild commands
1106
1107        When kbuild is executing with KBUILD_VERBOSE=0, then only a shorthand
1108        of a command is normally displayed.
1109        To enable this behaviour for custom commands kbuild requires
1110        two variables to be set:
1111        quiet_cmd_<command>     - what shall be echoed
1112              cmd_<command>     - the command to execute
1113
1114        Example:
1115                #
1116                quiet_cmd_image = BUILD   $@
1117                      cmd_image = $(obj)/tools/build $(BUILDFLAGS) \
1118                                                     $(obj)/vmlinux.bin > $@
1119
1120                targets += bzImage
1121                $(obj)/bzImage: $(obj)/vmlinux.bin $(obj)/tools/build FORCE
1122                        $(call if_changed,image)
1123                        @echo 'Kernel: $@ is ready'
1124
1125        When updating the $(obj)/bzImage target, the line
1126
1127        BUILD    arch/i386/boot/bzImage
1128
1129        will be displayed with "make KBUILD_VERBOSE=0".
1130
1131
1132--- 6.8 Preprocessing linker scripts
1133
1134        When the vmlinux image is built, the linker script
1135        arch/$(ARCH)/kernel/vmlinux.lds is used.
1136        The script is a preprocessed variant of the file vmlinux.lds.S
1137        located in the same directory.
1138        kbuild knows .lds files and includes a rule *lds.S -> *lds.
1139
1140        Example:
1141                #arch/i386/kernel/Makefile
1142                always := vmlinux.lds
1143
1144                #Makefile
1145                export CPPFLAGS_vmlinux.lds += -P -C -U$(ARCH)
1146
1147        The assignment to $(always) is used to tell kbuild to build the
1148        target vmlinux.lds.
1149        The assignment to $(CPPFLAGS_vmlinux.lds) tells kbuild to use the
1150        specified options when building the target vmlinux.lds.
1151
1152        When building the *.lds target, kbuild uses the variables:
1153        KBUILD_CPPFLAGS : Set in top-level Makefile
1154        cppflags-y      : May be set in the kbuild makefile
1155        CPPFLAGS_$(@F)  : Target specific flags.
1156                          Note that the full filename is used in this
1157                          assignment.
1158
1159        The kbuild infrastructure for *lds file are used in several
1160        architecture-specific files.
1161
1162=== 7 Kbuild syntax for exported headers
1163
1164The kernel include a set of headers that is exported to userspace.
1165Many headers can be exported as-is but other headers requires  a
1166minimal pre-processing before they are ready for user-space.
1167The pre-processing does:
1168- drop kernel specific annotations
1169- drop include of compiler.h
1170- drop all sections that is kernel internat (guarded by ifdef __KERNEL__)
1171
1172Each relevant directory contain a file name "Kbuild" which specify the
1173headers to be exported.
1174See subsequent chapter for the syntax of the Kbuild file.
1175
1176        --- 7.1 header-y
1177
1178        header-y specify header files to be exported.
1179
1180                Example:
1181                        #include/linux/Kbuild
1182                        header-y += usb/
1183                        header-y += aio_abi.h
1184
1185        The convention is to list one file per line and
1186        preferably in alphabetic order.
1187
1188        header-y also specify which subdirectories to visit.
1189        A subdirectory is identified by a trailing '/' which
1190        can be seen in the example above for the usb subdirectory.
1191
1192        Subdirectories are visited before their parent directories.
1193
1194        --- 7.2 objhdr-y
1195
1196        objhdr-y specifies generated files to be exported.
1197        Generated files are special as they need to be looked
1198        up in another directory when doing 'make O=...' builds.
1199
1200                Example:
1201                        #include/linux/Kbuild
1202                        objhdr-y += version.h
1203
1204        --- 7.3 destination-y
1205
1206        When an architecture have a set of exported headers that needs to be
1207        exported to a different directory destination-y is used.
1208        destination-y specify the destination directory for all exported
1209        headers in the file where it is present.
1210
1211                Example:
1212                        #arch/xtensa/platforms/s6105/include/platform/Kbuild
1213                        destination-y := include/linux
1214
1215        In the example above all exported headers in the Kbuild file
1216        will be located in the directory "include/linux" when exported.
1217
1218
1219        --- 7.4 unifdef-y (deprecated)
1220
1221        unifdef-y is deprecated. A direct replacement is header-y.
1222
1223
1224=== 8 Kbuild Variables
1225
1226The top Makefile exports the following variables:
1227
1228    VERSION, PATCHLEVEL, SUBLEVEL, EXTRAVERSION
1229
1230        These variables define the current kernel version.  A few arch
1231        Makefiles actually use these values directly; they should use
1232        $(KERNELRELEASE) instead.
1233
1234        $(VERSION), $(PATCHLEVEL), and $(SUBLEVEL) define the basic
1235        three-part version number, such as "2", "4", and "0".  These three
1236        values are always numeric.
1237
1238        $(EXTRAVERSION) defines an even tinier sublevel for pre-patches
1239        or additional patches.  It is usually some non-numeric string
1240        such as "-pre4", and is often blank.
1241
1242    KERNELRELEASE
1243
1244        $(KERNELRELEASE) is a single string such as "2.4.0-pre4", suitable
1245        for constructing installation directory names or showing in
1246        version strings.  Some arch Makefiles use it for this purpose.
1247
1248    ARCH
1249
1250        This variable defines the target architecture, such as "i386",
1251        "arm", or "sparc". Some kbuild Makefiles test $(ARCH) to
1252        determine which files to compile.
1253
1254        By default, the top Makefile sets $(ARCH) to be the same as the
1255        host system architecture.  For a cross build, a user may
1256        override the value of $(ARCH) on the command line:
1257
1258            make ARCH=m68k ...
1259
1260
1261    INSTALL_PATH
1262
1263        This variable defines a place for the arch Makefiles to install
1264        the resident kernel image and System.map file.
1265        Use this for architecture-specific install targets.
1266
1267    INSTALL_MOD_PATH, MODLIB
1268
1269        $(INSTALL_MOD_PATH) specifies a prefix to $(MODLIB) for module
1270        installation.  This variable is not defined in the Makefile but
1271        may be passed in by the user if desired.
1272
1273        $(MODLIB) specifies the directory for module installation.
1274        The top Makefile defines $(MODLIB) to
1275        $(INSTALL_MOD_PATH)/lib/modules/$(KERNELRELEASE).  The user may
1276        override this value on the command line if desired.
1277
1278    INSTALL_MOD_STRIP
1279
1280        If this variable is specified, will cause modules to be stripped
1281        after they are installed.  If INSTALL_MOD_STRIP is '1', then the
1282        default option --strip-debug will be used.  Otherwise,
1283        INSTALL_MOD_STRIP will used as the option(s) to the strip command.
1284
1285
1286=== 9 Makefile language
1287
1288The kernel Makefiles are designed to be run with GNU Make.  The Makefiles
1289use only the documented features of GNU Make, but they do use many
1290GNU extensions.
1291
1292GNU Make supports elementary list-processing functions.  The kernel
1293Makefiles use a novel style of list building and manipulation with few
1294"if" statements.
1295
1296GNU Make has two assignment operators, ":=" and "=".  ":=" performs
1297immediate evaluation of the right-hand side and stores an actual string
1298into the left-hand side.  "=" is like a formula definition; it stores the
1299right-hand side in an unevaluated form and then evaluates this form each
1300time the left-hand side is used.
1301
1302There are some cases where "=" is appropriate.  Usually, though, ":="
1303is the right choice.
1304
1305=== 10 Credits
1306
1307Original version made by Michael Elizabeth Chastain, <mailto:mec@shout.net>
1308Updates by Kai Germaschewski <kai@tp1.ruhr-uni-bochum.de>
1309Updates by Sam Ravnborg <sam@ravnborg.org>
1310Language QA by Jan Engelhardt <jengelh@gmx.de>
1311
1312=== 11 TODO
1313
1314- Describe how kbuild supports shipped files with _shipped.
1315- Generating offset header files.
1316- Add more variables to section 7?
1317
1318
1319
1320