linux/Documentation/Intel-IOMMU.txt
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   1Linux IOMMU Support
   2===================
   3
   4The architecture spec can be obtained from the below location.
   5
   6http://www.intel.com/technology/virtualization/
   7
   8This guide gives a quick cheat sheet for some basic understanding.
   9
  10Some Keywords
  11
  12DMAR - DMA remapping
  13DRHD - DMA Engine Reporting Structure
  14RMRR - Reserved memory Region Reporting Structure
  15ZLR  - Zero length reads from PCI devices
  16IOVA - IO Virtual address.
  17
  18Basic stuff
  19-----------
  20
  21ACPI enumerates and lists the different DMA engines in the platform, and
  22device scope relationships between PCI devices and which DMA engine  controls
  23them.
  24
  25What is RMRR?
  26-------------
  27
  28There are some devices the BIOS controls, for e.g USB devices to perform
  29PS2 emulation. The regions of memory used for these devices are marked
  30reserved in the e820 map. When we turn on DMA translation, DMA to those
  31regions will fail. Hence BIOS uses RMRR to specify these regions along with
  32devices that need to access these regions. OS is expected to setup
  33unity mappings for these regions for these devices to access these regions.
  34
  35How is IOVA generated?
  36---------------------
  37
  38Well behaved drivers call pci_map_*() calls before sending command to device
  39that needs to perform DMA. Once DMA is completed and mapping is no longer
  40required, device performs a pci_unmap_*() calls to unmap the region.
  41
  42The Intel IOMMU driver allocates a virtual address per domain. Each PCIE
  43device has its own domain (hence protection). Devices under p2p bridges
  44share the virtual address with all devices under the p2p bridge due to
  45transaction id aliasing for p2p bridges.
  46
  47IOVA generation is pretty generic. We used the same technique as vmalloc()
  48but these are not global address spaces, but separate for each domain.
  49Different DMA engines may support different number of domains.
  50
  51We also allocate guard pages with each mapping, so we can attempt to catch
  52any overflow that might happen.
  53
  54
  55Graphics Problems?
  56------------------
  57If you encounter issues with graphics devices, you can try adding
  58option intel_iommu=igfx_off to turn off the integrated graphics engine.
  59
  60If it happens to be a PCI device included in the INCLUDE_ALL Engine,
  61then try enabling CONFIG_DMAR_GFX_WA to setup a 1-1 map. We hear
  62graphics drivers may be in process of using DMA api's in the near
  63future and at that time this option can be yanked out.
  64
  65Some exceptions to IOVA
  66-----------------------
  67Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
  68The same is true for peer to peer transactions. Hence we reserve the
  69address from PCI MMIO ranges so they are not allocated for IOVA addresses.
  70
  71
  72Fault reporting
  73---------------
  74When errors are reported, the DMA engine signals via an interrupt. The fault
  75reason and device that caused it with fault reason is printed on console.
  76
  77See below for sample.
  78
  79
  80Boot Message Sample
  81-------------------
  82
  83Something like this gets printed indicating presence of DMAR tables
  84in ACPI.
  85
  86ACPI: DMAR (v001 A M I  OEMDMAR  0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0
  87
  88When DMAR is being processed and initialized by ACPI, prints DMAR locations
  89and any RMRR's processed.
  90
  91ACPI DMAR:Host address width 36
  92ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000
  93ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000
  94ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000
  95ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff
  96ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff
  97
  98When DMAR is enabled for use, you will notice..
  99
 100PCI-DMA: Using DMAR IOMMU
 101
 102Fault reporting
 103---------------
 104
 105DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
 106DMAR:[fault reason 05] PTE Write access is not set
 107DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
 108DMAR:[fault reason 05] PTE Write access is not set
 109
 110TBD
 111----
 112
 113- For compatibility testing, could use unity map domain for all devices, just
 114  provide a 1-1 for all useful memory under a single domain for all devices.
 115- API for paravirt ops for abstracting functionality for VMM folks.
 116
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