LXR linux/drivers/staging/comedi/comedi.h

   1/*
   2    include/comedi.h (installed as /usr/include/comedi.h)
   3    header file for comedi
   4
   5    COMEDI - Linux Control and Measurement Device Interface
   6    Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org>
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU Lesser General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22*/
  23
  24#ifndef _COMEDI_H
  25#define _COMEDI_H
  26
  27#ifdef __cplusplus
  28extern "C" {
  29#endif
  30
  31#define COMEDI_MAJORVERSION     0
  32#define COMEDI_MINORVERSION     7
  33#define COMEDI_MICROVERSION     76
  34#define VERSION "0.7.76"
  35
  36/* comedi's major device number */
  37#define COMEDI_MAJOR 98
  38
  39/*
  40   maximum number of minor devices.  This can be increased, although
  41   kernel structures are currently statically allocated, thus you
  42   don't want this to be much more than you actually use.
  43 */
  44#define COMEDI_NDEVICES 16
  45
  46/* number of config options in the config structure */
  47#define COMEDI_NDEVCONFOPTS 32
  48/*length of nth chunk of firmware data*/
  49#define COMEDI_DEVCONF_AUX_DATA3_LENGTH         25
  50#define COMEDI_DEVCONF_AUX_DATA2_LENGTH         26
  51#define COMEDI_DEVCONF_AUX_DATA1_LENGTH         27
  52#define COMEDI_DEVCONF_AUX_DATA0_LENGTH         28
  53#define COMEDI_DEVCONF_AUX_DATA_HI              29      /* most significant 32 bits of pointer address (if needed) */
  54#define COMEDI_DEVCONF_AUX_DATA_LO              30      /* least significant 32 bits of pointer address */
  55#define COMEDI_DEVCONF_AUX_DATA_LENGTH          31      /* total data length */
  56
  57/* max length of device and driver names */
  58#define COMEDI_NAMELEN 20
  59
  60/* packs and unpacks a channel/range number */
  61
  62#define CR_PACK(chan, rng, aref)                ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan))
  63#define CR_PACK_FLAGS(chan, range, aref, flags) (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK))
  64
  65#define CR_CHAN(a)      ((a)&0xffff)
  66#define CR_RANGE(a)     (((a)>>16)&0xff)
  67#define CR_AREF(a)      (((a)>>24)&0x03)
  68
  69#define CR_FLAGS_MASK   0xfc000000
  70#define CR_ALT_FILTER   (1<<26)
  71#define CR_DITHER       CR_ALT_FILTER
  72#define CR_DEGLITCH     CR_ALT_FILTER
  73#define CR_ALT_SOURCE   (1<<27)
  74#define CR_EDGE         (1<<30)
  75#define CR_INVERT       (1<<31)
  76
  77#define AREF_GROUND     0x00    /* analog ref = analog ground */
  78#define AREF_COMMON     0x01    /* analog ref = analog common */
  79#define AREF_DIFF       0x02    /* analog ref = differential */
  80#define AREF_OTHER      0x03    /* analog ref = other (undefined) */
  81
  82/* counters -- these are arbitrary values */
  83#define GPCT_RESET              0x0001
  84#define GPCT_SET_SOURCE         0x0002
  85#define GPCT_SET_GATE           0x0004
  86#define GPCT_SET_DIRECTION      0x0008
  87#define GPCT_SET_OPERATION      0x0010
  88#define GPCT_ARM                0x0020
  89#define GPCT_DISARM             0x0040
  90#define GPCT_GET_INT_CLK_FRQ    0x0080
  91
  92#define GPCT_INT_CLOCK          0x0001
  93#define GPCT_EXT_PIN            0x0002
  94#define GPCT_NO_GATE            0x0004
  95#define GPCT_UP                 0x0008
  96#define GPCT_DOWN               0x0010
  97#define GPCT_HWUD               0x0020
  98#define GPCT_SIMPLE_EVENT       0x0040
  99#define GPCT_SINGLE_PERIOD      0x0080
 100#define GPCT_SINGLE_PW          0x0100
 101#define GPCT_CONT_PULSE_OUT     0x0200
 102#define GPCT_SINGLE_PULSE_OUT   0x0400
 103
 104/* instructions */
 105
 106#define INSN_MASK_WRITE         0x8000000
 107#define INSN_MASK_READ          0x4000000
 108#define INSN_MASK_SPECIAL       0x2000000
 109
 110#define INSN_READ               (0 | INSN_MASK_READ)
 111#define INSN_WRITE              (1 | INSN_MASK_WRITE)
 112#define INSN_BITS               (2 | INSN_MASK_READ|INSN_MASK_WRITE)
 113#define INSN_CONFIG             (3 | INSN_MASK_READ|INSN_MASK_WRITE)
 114#define INSN_GTOD               (4 | INSN_MASK_READ|INSN_MASK_SPECIAL)
 115#define INSN_WAIT               (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
 116#define INSN_INTTRIG            (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
 117
 118/* trigger flags */
 119/* These flags are used in comedi_trig structures */
 120
 121#define TRIG_BOGUS      0x0001  /* do the motions */
 122#define TRIG_DITHER     0x0002  /* enable dithering */
 123#define TRIG_DEGLITCH   0x0004  /* enable deglitching */
 124/*#define TRIG_RT       0x0008 */       /* perform op in real time */
 125#define TRIG_CONFIG     0x0010  /* perform configuration, not triggering */
 126#define TRIG_WAKE_EOS   0x0020  /* wake up on end-of-scan events */
 127/*#define TRIG_WRITE    0x0040*/        /* write to bidirectional devices */
 128
 129/* command flags */
 130/* These flags are used in comedi_cmd structures */
 131
 132#define CMDF_PRIORITY           0x00000008      /* try to use a real-time interrupt while performing command */
 133
 134#define TRIG_RT         CMDF_PRIORITY   /* compatibility definition */
 135
 136#define CMDF_WRITE              0x00000040
 137#define TRIG_WRITE      CMDF_WRITE      /* compatibility definition */
 138
 139#define CMDF_RAWDATA            0x00000080
 140
 141#define COMEDI_EV_START         0x00040000
 142#define COMEDI_EV_SCAN_BEGIN    0x00080000
 143#define COMEDI_EV_CONVERT       0x00100000
 144#define COMEDI_EV_SCAN_END      0x00200000
 145#define COMEDI_EV_STOP          0x00400000
 146
 147#define TRIG_ROUND_MASK         0x00030000
 148#define TRIG_ROUND_NEAREST      0x00000000
 149#define TRIG_ROUND_DOWN         0x00010000
 150#define TRIG_ROUND_UP           0x00020000
 151#define TRIG_ROUND_UP_NEXT      0x00030000
 152
 153/* trigger sources */
 154
 155#define TRIG_ANY        0xffffffff
 156#define TRIG_INVALID    0x00000000
 157
 158#define TRIG_NONE       0x00000001      /* never trigger */
 159#define TRIG_NOW        0x00000002      /* trigger now + N ns */
 160#define TRIG_FOLLOW     0x00000004      /* trigger on next lower level trig */
 161#define TRIG_TIME       0x00000008      /* trigger at time N ns */
 162#define TRIG_TIMER      0x00000010      /* trigger at rate N ns */
 163#define TRIG_COUNT      0x00000020      /* trigger when count reaches N */
 164#define TRIG_EXT        0x00000040      /* trigger on external signal N */
 165#define TRIG_INT        0x00000080      /* trigger on comedi-internal signal N */
 166#define TRIG_OTHER      0x00000100      /* driver defined */
 167
 168/* subdevice flags */
 169
 170#define SDF_BUSY        0x0001  /* device is busy */
 171#define SDF_BUSY_OWNER  0x0002  /* device is busy with your job */
 172#define SDF_LOCKED      0x0004  /* subdevice is locked */
 173#define SDF_LOCK_OWNER  0x0008  /* you own lock */
 174#define SDF_MAXDATA     0x0010  /* maxdata depends on channel */
 175#define SDF_FLAGS       0x0020  /* flags depend on channel */
 176#define SDF_RANGETYPE   0x0040  /* range type depends on channel */
 177#define SDF_MODE0       0x0080  /* can do mode 0 */
 178#define SDF_MODE1       0x0100  /* can do mode 1 */
 179#define SDF_MODE2       0x0200  /* can do mode 2 */
 180#define SDF_MODE3       0x0400  /* can do mode 3 */
 181#define SDF_MODE4       0x0800  /* can do mode 4 */
 182#define SDF_CMD         0x1000  /* can do commands (deprecated) */
 183#define SDF_SOFT_CALIBRATED     0x2000  /* subdevice uses software calibration */
 184#define SDF_CMD_WRITE           0x4000  /* can do output commands */
 185#define SDF_CMD_READ            0x8000  /* can do input commands */
 186
 187#define SDF_READABLE    0x00010000      /* subdevice can be read (e.g. analog input) */
 188#define SDF_WRITABLE    0x00020000      /* subdevice can be written (e.g. analog output) */
 189#define SDF_WRITEABLE   SDF_WRITABLE    /* spelling error in API */
 190#define SDF_INTERNAL    0x00040000      /* subdevice does not have externally visible lines */
 191#define SDF_RT          0x00080000      /* DEPRECATED: subdevice is RT capable */
 192#define SDF_GROUND      0x00100000      /* can do aref=ground */
 193#define SDF_COMMON      0x00200000      /* can do aref=common */
 194#define SDF_DIFF        0x00400000      /* can do aref=diff */
 195#define SDF_OTHER       0x00800000      /* can do aref=other */
 196#define SDF_DITHER      0x01000000      /* can do dithering */
 197#define SDF_DEGLITCH    0x02000000      /* can do deglitching */
 198#define SDF_MMAP        0x04000000      /* can do mmap() */
 199#define SDF_RUNNING     0x08000000      /* subdevice is acquiring data */
 200#define SDF_LSAMPL      0x10000000      /* subdevice uses 32-bit samples */
 201#define SDF_PACKED      0x20000000      /* subdevice can do packed DIO */
 202/* re recyle these flags for PWM */
 203#define SDF_PWM_COUNTER SDF_MODE0       /* PWM can automatically switch off */
 204#define SDF_PWM_HBRIDGE SDF_MODE1       /* PWM is signed (H-bridge) */
 205
 206
 207
 208/* subdevice types */
 209
 210enum comedi_subdevice_type {
 211        COMEDI_SUBD_UNUSED,     /* unused by driver */
 212        COMEDI_SUBD_AI, /* analog input */
 213        COMEDI_SUBD_AO, /* analog output */
 214        COMEDI_SUBD_DI, /* digital input */
 215        COMEDI_SUBD_DO, /* digital output */
 216        COMEDI_SUBD_DIO,        /* digital input/output */
 217        COMEDI_SUBD_COUNTER,    /* counter */
 218        COMEDI_SUBD_TIMER,      /* timer */
 219        COMEDI_SUBD_MEMORY,     /* memory, EEPROM, DPRAM */
 220        COMEDI_SUBD_CALIB,      /* calibration DACs */
 221        COMEDI_SUBD_PROC,       /* processor, DSP */
 222        COMEDI_SUBD_SERIAL,     /* serial IO */
 223        COMEDI_SUBD_PWM         /* PWM */
 224};
 225
 226/* configuration instructions */
 227
 228enum configuration_ids {
 229        INSN_CONFIG_DIO_INPUT = 0,
 230        INSN_CONFIG_DIO_OUTPUT = 1,
 231        INSN_CONFIG_DIO_OPENDRAIN = 2,
 232        INSN_CONFIG_ANALOG_TRIG = 16,
 233/*      INSN_CONFIG_WAVEFORM = 17, */
 234/*      INSN_CONFIG_TRIG = 18, */
 235/*      INSN_CONFIG_COUNTER = 19, */
 236        INSN_CONFIG_ALT_SOURCE = 20,
 237        INSN_CONFIG_DIGITAL_TRIG = 21,
 238        INSN_CONFIG_BLOCK_SIZE = 22,
 239        INSN_CONFIG_TIMER_1 = 23,
 240        INSN_CONFIG_FILTER = 24,
 241        INSN_CONFIG_CHANGE_NOTIFY = 25,
 242
 243         /*ALPHA*/ INSN_CONFIG_SERIAL_CLOCK = 26,
 244        INSN_CONFIG_BIDIRECTIONAL_DATA = 27,
 245        INSN_CONFIG_DIO_QUERY = 28,
 246        INSN_CONFIG_PWM_OUTPUT = 29,
 247        INSN_CONFIG_GET_PWM_OUTPUT = 30,
 248        INSN_CONFIG_ARM = 31,
 249        INSN_CONFIG_DISARM = 32,
 250        INSN_CONFIG_GET_COUNTER_STATUS = 33,
 251        INSN_CONFIG_RESET = 34,
 252        INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, /* Use CTR as single pulsegenerator */
 253        INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002,  /* Use CTR as pulsetraingenerator */
 254        INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003,     /* Use the counter as encoder */
 255        INSN_CONFIG_SET_GATE_SRC = 2001,        /* Set gate source */
 256        INSN_CONFIG_GET_GATE_SRC = 2002,        /* Get gate source */
 257        INSN_CONFIG_SET_CLOCK_SRC = 2003,       /* Set master clock source */
 258        INSN_CONFIG_GET_CLOCK_SRC = 2004,       /* Get master clock source */
 259        INSN_CONFIG_SET_OTHER_SRC = 2005,       /* Set other source */
 260/*      INSN_CONFIG_GET_OTHER_SRC = 2006,*/     /* Get other source */
 261        INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006,    /* Get size in bytes of
 262                                                           subdevice's on-board
 263                                                           fifos used during
 264                                                           streaming
 265                                                           input/output */
 266        INSN_CONFIG_SET_COUNTER_MODE = 4097,
 267        INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE,       /* deprecated */
 268        INSN_CONFIG_8254_READ_STATUS = 4098,
 269        INSN_CONFIG_SET_ROUTING = 4099,
 270        INSN_CONFIG_GET_ROUTING = 4109,
 271/* PWM */
 272        INSN_CONFIG_PWM_SET_PERIOD = 5000,   /* sets frequency */
 273        INSN_CONFIG_PWM_GET_PERIOD = 5001,   /* gets frequency */
 274        INSN_CONFIG_GET_PWM_STATUS = 5002,          /* is it running? */
 275        INSN_CONFIG_PWM_SET_H_BRIDGE = 5003, /* sets H bridge: duty cycle and sign bit for a relay  at the same time*/
 276        INSN_CONFIG_PWM_GET_H_BRIDGE = 5004  /* gets H bridge data: duty cycle and the sign bit */
 277};
 278
 279enum comedi_io_direction {
 280        COMEDI_INPUT = 0,
 281        COMEDI_OUTPUT = 1,
 282        COMEDI_OPENDRAIN = 2
 283};
 284
 285enum comedi_support_level {
 286        COMEDI_UNKNOWN_SUPPORT = 0,
 287        COMEDI_SUPPORTED,
 288        COMEDI_UNSUPPORTED
 289};
 290
 291/* ioctls */
 292
 293#define CIO 'd'
 294#define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig)
 295#define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo)
 296#define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo)
 297#define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo)
 298#define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig)
 299#define COMEDI_LOCK _IO(CIO, 5)
 300#define COMEDI_UNLOCK _IO(CIO, 6)
 301#define COMEDI_CANCEL _IO(CIO, 7)
 302#define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo)
 303#define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd)
 304#define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd)
 305#define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist)
 306#define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn)
 307#define COMEDI_BUFCONFIG _IOR(CIO, 13, struct comedi_bufconfig)
 308#define COMEDI_BUFINFO _IOWR(CIO, 14, struct comedi_bufinfo)
 309#define COMEDI_POLL _IO(CIO, 15)
 310
 311/* structures */
 312
 313struct comedi_trig {
 314        unsigned int subdev;    /* subdevice */
 315        unsigned int mode;      /* mode */
 316        unsigned int flags;
 317        unsigned int n_chan;    /* number of channels */
 318        unsigned int *chanlist; /* channel/range list */
 319        short *data;    /* data list, size depends on subd flags */
 320        unsigned int n; /* number of scans */
 321        unsigned int trigsrc;
 322        unsigned int trigvar;
 323        unsigned int trigvar1;
 324        unsigned int data_len;
 325        unsigned int unused[3];
 326};
 327
 328struct comedi_insn {
 329        unsigned int insn;
 330        unsigned int n;
 331        unsigned int *data;
 332        unsigned int subdev;
 333        unsigned int chanspec;
 334        unsigned int unused[3];
 335};
 336
 337struct comedi_insnlist {
 338        unsigned int n_insns;
 339        struct comedi_insn *insns;
 340};
 341
 342struct comedi_cmd {
 343        unsigned int subdev;
 344        unsigned int flags;
 345
 346        unsigned int start_src;
 347        unsigned int start_arg;
 348
 349        unsigned int scan_begin_src;
 350        unsigned int scan_begin_arg;
 351
 352        unsigned int convert_src;
 353        unsigned int convert_arg;
 354
 355        unsigned int scan_end_src;
 356        unsigned int scan_end_arg;
 357
 358        unsigned int stop_src;
 359        unsigned int stop_arg;
 360
 361        unsigned int *chanlist; /* channel/range list */
 362        unsigned int chanlist_len;
 363
 364        short *data;    /* data list, size depends on subd flags */
 365        unsigned int data_len;
 366};
 367
 368struct comedi_chaninfo {
 369        unsigned int subdev;
 370        unsigned int *maxdata_list;
 371        unsigned int *flaglist;
 372        unsigned int *rangelist;
 373        unsigned int unused[4];
 374};
 375
 376struct comedi_rangeinfo {
 377        unsigned int range_type;
 378        void *range_ptr;
 379};
 380
 381struct comedi_krange {
 382        int min;        /* fixed point, multiply by 1e-6 */
 383        int max;        /* fixed point, multiply by 1e-6 */
 384        unsigned int flags;
 385};
 386
 387
 388struct comedi_subdinfo {
 389        unsigned int type;
 390        unsigned int n_chan;
 391        unsigned int subd_flags;
 392        unsigned int timer_type;
 393        unsigned int len_chanlist;
 394        unsigned int maxdata;
 395        unsigned int flags;     /* channel flags */
 396        unsigned int range_type;        /* lookup in kernel */
 397        unsigned int settling_time_0;
 398        unsigned insn_bits_support;     /* see support_level enum for values*/
 399        unsigned int unused[8];
 400};
 401
 402struct comedi_devinfo {
 403        unsigned int version_code;
 404        unsigned int n_subdevs;
 405        char driver_name[COMEDI_NAMELEN];
 406        char board_name[COMEDI_NAMELEN];
 407        int read_subdevice;
 408        int write_subdevice;
 409        int unused[30];
 410};
 411
 412struct comedi_devconfig {
 413        char board_name[COMEDI_NAMELEN];
 414        int options[COMEDI_NDEVCONFOPTS];
 415};
 416
 417struct comedi_bufconfig {
 418        unsigned int subdevice;
 419        unsigned int flags;
 420
 421        unsigned int maximum_size;
 422        unsigned int size;
 423
 424        unsigned int unused[4];
 425};
 426
 427struct comedi_bufinfo {
 428        unsigned int subdevice;
 429        unsigned int bytes_read;
 430
 431        unsigned int buf_write_ptr;
 432        unsigned int buf_read_ptr;
 433        unsigned int buf_write_count;
 434        unsigned int buf_read_count;
 435
 436        unsigned int bytes_written;
 437
 438        unsigned int unused[4];
 439};
 440
 441/* range stuff */
 442
 443#define __RANGE(a, b)   ((((a)&0xffff)<<16)|((b)&0xffff))
 444
 445#define RANGE_OFFSET(a)         (((a)>>16)&0xffff)
 446#define RANGE_LENGTH(b)         ((b)&0xffff)
 447
 448#define RF_UNIT(flags)          ((flags)&0xff)
 449#define RF_EXTERNAL             (1<<8)
 450
 451#define UNIT_volt               0
 452#define UNIT_mA                 1
 453#define UNIT_none               2
 454
 455#define COMEDI_MIN_SPEED        ((unsigned int)0xffffffff)
 456
 457/* callback stuff */
 458/* only relevant to kernel modules. */
 459
 460#define COMEDI_CB_EOS           1       /* end of scan */
 461#define COMEDI_CB_EOA           2       /* end of acquisition */
 462#define COMEDI_CB_BLOCK         4       /* DEPRECATED: convenient block size */
 463#define COMEDI_CB_EOBUF         8       /* DEPRECATED: end of buffer */
 464#define COMEDI_CB_ERROR         16      /* card error during acquisition */
 465#define COMEDI_CB_OVERFLOW      32      /* buffer overflow/underflow */
 466
 467/**********************************************************/
 468/* everything after this line is ALPHA */
 469/**********************************************************/
 470
 471/*
 472  8254 specific configuration.
 473
 474  It supports two config commands:
 475
 476  0 ID: INSN_CONFIG_SET_COUNTER_MODE
 477  1 8254 Mode
 478    I8254_MODE0, I8254_MODE1, ..., I8254_MODE5
 479    OR'ed with:
 480    I8254_BCD, I8254_BINARY
 481
 482  0 ID: INSN_CONFIG_8254_READ_STATUS
 483  1 <-- Status byte returned here.
 484    B7 = Output
 485    B6 = NULL Count
 486    B5 - B0 Current mode.
 487
 488*/
 489
 490enum i8254_mode {
 491        I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */
 492        I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */
 493        I8254_MODE2 = (2 << 1), /* Rate generator */
 494        I8254_MODE3 = (3 << 1), /* Square wave mode */
 495        I8254_MODE4 = (4 << 1), /* Software triggered strobe */
 496        I8254_MODE5 = (5 << 1), /* Hardware triggered strobe (retriggerable) */
 497        I8254_BCD = 1,  /* use binary-coded decimal instead of binary (pretty useless) */
 498        I8254_BINARY = 0
 499};
 500
 501static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel)
 502{
 503        if (pfi_channel < 10)
 504                return 0x1 + pfi_channel;
 505        else
 506                return 0xb + pfi_channel;
 507}
 508static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel)
 509{
 510        if (rtsi_channel < 7)
 511                return 0xb + rtsi_channel;
 512        else
 513                return 0x1b;
 514}
 515/* mode bits for NI general-purpose counters, set with
 516 * INSN_CONFIG_SET_COUNTER_MODE */
 517#define NI_GPCT_COUNTING_MODE_SHIFT 16
 518#define NI_GPCT_INDEX_PHASE_BITSHIFT 20
 519#define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
 520enum ni_gpct_mode_bits {
 521        NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4,
 522        NI_GPCT_EDGE_GATE_MODE_MASK = 0x18,
 523        NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0,
 524        NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8,
 525        NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10,
 526        NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18,
 527        NI_GPCT_STOP_MODE_MASK = 0x60,
 528        NI_GPCT_STOP_ON_GATE_BITS = 0x00,
 529        NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20,
 530        NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40,
 531        NI_GPCT_LOAD_B_SELECT_BIT = 0x80,
 532        NI_GPCT_OUTPUT_MODE_MASK = 0x300,
 533        NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100,
 534        NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200,
 535        NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300,
 536        NI_GPCT_HARDWARE_DISARM_MASK = 0xc00,
 537        NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000,
 538        NI_GPCT_DISARM_AT_TC_BITS = 0x400,
 539        NI_GPCT_DISARM_AT_GATE_BITS = 0x800,
 540        NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00,
 541        NI_GPCT_LOADING_ON_TC_BIT = 0x1000,
 542        NI_GPCT_LOADING_ON_GATE_BIT = 0x4000,
 543        NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT,
 544        NI_GPCT_COUNTING_MODE_NORMAL_BITS =
 545                0x0 << NI_GPCT_COUNTING_MODE_SHIFT,
 546        NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS =
 547                0x1 << NI_GPCT_COUNTING_MODE_SHIFT,
 548        NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS =
 549                0x2 << NI_GPCT_COUNTING_MODE_SHIFT,
 550        NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS =
 551                0x3 << NI_GPCT_COUNTING_MODE_SHIFT,
 552        NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS =
 553                0x4 << NI_GPCT_COUNTING_MODE_SHIFT,
 554        NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS =
 555                0x6 << NI_GPCT_COUNTING_MODE_SHIFT,
 556        NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 557        NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS =
 558                0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 559        NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS =
 560                0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 561        NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS =
 562                0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 563        NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS =
 564                0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 565        NI_GPCT_INDEX_ENABLE_BIT = 0x400000,
 566        NI_GPCT_COUNTING_DIRECTION_MASK =
 567                0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 568        NI_GPCT_COUNTING_DIRECTION_DOWN_BITS =
 569                0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 570        NI_GPCT_COUNTING_DIRECTION_UP_BITS =
 571                0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 572        NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS =
 573                0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 574        NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS =
 575                0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 576        NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000,
 577        NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0,
 578        NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000,
 579        NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000,
 580        NI_GPCT_OR_GATE_BIT = 0x10000000,
 581        NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000
 582};
 583
 584/* Bits for setting a clock source with
 585 * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */
 586enum ni_gpct_clock_source_bits {
 587        NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f,
 588        NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0,
 589        NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1,
 590        NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2,
 591        NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3,
 592        NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4,
 593        NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5,
 594        NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6,      /* NI 660x-specific */
 595        NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7,
 596        NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8,
 597        NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9,
 598        NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000,
 599        NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0,
 600        NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000, /* divide source by 2 */
 601        NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000, /* divide source by 8 */
 602        NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000
 603};
 604static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n)
 605{
 606        /* NI 660x-specific */
 607        return 0x10 + n;
 608}
 609static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n)
 610{
 611        return 0x18 + n;
 612}
 613static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n)
 614{
 615        /* no pfi on NI 660x */
 616        return 0x20 + n;
 617}
 618
 619/* Possibilities for setting a gate source with
 620INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
 621May be bitwise-or'd with CR_EDGE or CR_INVERT. */
 622enum ni_gpct_gate_select {
 623        /* m-series gates */
 624        NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0,
 625        NI_GPCT_AI_START2_GATE_SELECT = 0x12,
 626        NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13,
 627        NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14,
 628        NI_GPCT_AI_START1_GATE_SELECT = 0x1c,
 629        NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d,
 630        NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e,
 631        NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f,
 632        /* more gates for 660x */
 633        NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100,
 634        NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101,
 635        /* more gates for 660x "second gate" */
 636        NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201,
 637        NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e,
 638        /* m-series "second gate" sources are unknown,
 639           we should add them here with an offset of 0x300 when known. */
 640        NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
 641};
 642static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n)
 643{
 644        return 0x102 + n;
 645}
 646static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n)
 647{
 648        return NI_USUAL_RTSI_SELECT(n);
 649}
 650static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n)
 651{
 652        return NI_USUAL_PFI_SELECT(n);
 653}
 654static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n)
 655{
 656        return 0x202 + n;
 657}
 658
 659/* Possibilities for setting a source with
 660INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */
 661enum ni_gpct_other_index {
 662        NI_GPCT_SOURCE_ENCODER_A,
 663        NI_GPCT_SOURCE_ENCODER_B,
 664        NI_GPCT_SOURCE_ENCODER_Z
 665};
 666enum ni_gpct_other_select {
 667        /* m-series gates */
 668        /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */
 669        NI_GPCT_DISABLED_OTHER_SELECT = 0x8000,
 670};
 671static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n)
 672{
 673        return NI_USUAL_PFI_SELECT(n);
 674}
 675
 676/* start sources for ni general-purpose counters for use with
 677INSN_CONFIG_ARM */
 678enum ni_gpct_arm_source {
 679        NI_GPCT_ARM_IMMEDIATE = 0x0,
 680        NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1,     /* Start both the counter and
 681                                                   the adjacent paired counter
 682                                                   simultaneously */
 683        /* NI doesn't document bits for selecting hardware arm triggers.  If
 684         * the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least
 685         * significant bits (3 bits for 660x or 5 bits for m-series) through to
 686         * the hardware.  This will at least allow someone to figure out what
 687         * the bits do later. */
 688        NI_GPCT_ARM_UNKNOWN = 0x1000,
 689};
 690
 691/* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */
 692enum ni_gpct_filter_select {
 693        NI_GPCT_FILTER_OFF = 0x0,
 694        NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1,
 695        NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2,
 696        NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3,
 697        NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4,
 698        NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5,
 699        NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6
 700};
 701
 702/* PFI digital filtering options for ni m-series for use with
 703 * INSN_CONFIG_FILTER. */
 704enum ni_pfi_filter_select {
 705        NI_PFI_FILTER_OFF = 0x0,
 706        NI_PFI_FILTER_125ns = 0x1,
 707        NI_PFI_FILTER_6425ns = 0x2,
 708        NI_PFI_FILTER_2550us = 0x3
 709};
 710
 711/* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */
 712enum ni_mio_clock_source {
 713        NI_MIO_INTERNAL_CLOCK = 0,
 714        NI_MIO_RTSI_CLOCK = 1,  /* doesn't work for m-series, use
 715                                   NI_MIO_PLL_RTSI_CLOCK() */
 716        /* the NI_MIO_PLL_* sources are m-series only */
 717        NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2,
 718        NI_MIO_PLL_PXI10_CLOCK = 3,
 719        NI_MIO_PLL_RTSI0_CLOCK = 4
 720};
 721static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel)
 722{
 723        return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel;
 724}
 725
 726/* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING.
 727 The numbers assigned are not arbitrary, they correspond to the bits required
 728 to program the board. */
 729enum ni_rtsi_routing {
 730        NI_RTSI_OUTPUT_ADR_START1 = 0,
 731        NI_RTSI_OUTPUT_ADR_START2 = 1,
 732        NI_RTSI_OUTPUT_SCLKG = 2,
 733        NI_RTSI_OUTPUT_DACUPDN = 3,
 734        NI_RTSI_OUTPUT_DA_START1 = 4,
 735        NI_RTSI_OUTPUT_G_SRC0 = 5,
 736        NI_RTSI_OUTPUT_G_GATE0 = 6,
 737        NI_RTSI_OUTPUT_RGOUT0 = 7,
 738        NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
 739        NI_RTSI_OUTPUT_RTSI_OSC = 12    /* pre-m-series always have RTSI clock
 740                                           on line 7 */
 741};
 742static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n)
 743{
 744        return NI_RTSI_OUTPUT_RTSI_BRD_0 + n;
 745}
 746
 747/* Signals which can be routed to an NI PFI pin on an m-series board with
 748 * INSN_CONFIG_SET_ROUTING.  These numbers are also returned by
 749 * INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing
 750 * cannot be changed.  The numbers assigned are not arbitrary, they correspond
 751 * to the bits required to program the board. */
 752enum ni_pfi_routing {
 753        NI_PFI_OUTPUT_PFI_DEFAULT = 0,
 754        NI_PFI_OUTPUT_AI_START1 = 1,
 755        NI_PFI_OUTPUT_AI_START2 = 2,
 756        NI_PFI_OUTPUT_AI_CONVERT = 3,
 757        NI_PFI_OUTPUT_G_SRC1 = 4,
 758        NI_PFI_OUTPUT_G_GATE1 = 5,
 759        NI_PFI_OUTPUT_AO_UPDATE_N = 6,
 760        NI_PFI_OUTPUT_AO_START1 = 7,
 761        NI_PFI_OUTPUT_AI_START_PULSE = 8,
 762        NI_PFI_OUTPUT_G_SRC0 = 9,
 763        NI_PFI_OUTPUT_G_GATE0 = 10,
 764        NI_PFI_OUTPUT_EXT_STROBE = 11,
 765        NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12,
 766        NI_PFI_OUTPUT_GOUT0 = 13,
 767        NI_PFI_OUTPUT_GOUT1 = 14,
 768        NI_PFI_OUTPUT_FREQ_OUT = 15,
 769        NI_PFI_OUTPUT_PFI_DO = 16,
 770        NI_PFI_OUTPUT_I_ATRIG = 17,
 771        NI_PFI_OUTPUT_RTSI0 = 18,
 772        NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26,
 773        NI_PFI_OUTPUT_SCXI_TRIG1 = 27,
 774        NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28,
 775        NI_PFI_OUTPUT_CDI_SAMPLE = 29,
 776        NI_PFI_OUTPUT_CDO_UPDATE = 30
 777};
 778static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel)
 779{
 780        return NI_PFI_OUTPUT_RTSI0 + rtsi_channel;
 781}
 782
 783/* Signals which can be routed to output on a NI PFI pin on a 660x board
 784 with INSN_CONFIG_SET_ROUTING.  The numbers assigned are
 785 not arbitrary, they correspond to the bits required
 786 to program the board.  Lines 0 to 7 can only be set to
 787 NI_660X_PFI_OUTPUT_DIO.  Lines 32 to 39 can only be set to
 788 NI_660X_PFI_OUTPUT_COUNTER. */
 789enum ni_660x_pfi_routing {
 790        NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */
 791        NI_660X_PFI_OUTPUT_DIO = 2,     /* static digital output */
 792};
 793
 794/* NI External Trigger lines.  These values are not arbitrary, but are related
 795 * to the bits required to program the board (offset by 1 for historical
 796 * reasons). */
 797static inline unsigned NI_EXT_PFI(unsigned pfi_channel)
 798{
 799        return NI_USUAL_PFI_SELECT(pfi_channel) - 1;
 800}
 801static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel)
 802{
 803        return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1;
 804}
 805
 806/* status bits for INSN_CONFIG_GET_COUNTER_STATUS */
 807enum comedi_counter_status_flags {
 808        COMEDI_COUNTER_ARMED = 0x1,
 809        COMEDI_COUNTER_COUNTING = 0x2,
 810        COMEDI_COUNTER_TERMINAL_COUNT = 0x4,
 811};
 812
 813/* Clock sources for CDIO subdevice on NI m-series boards.  Used as the
 814 * scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd
 815 * with CR_INVERT to change polarity. */
 816enum ni_m_series_cdio_scan_begin_src {
 817        NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0,
 818        NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18,
 819        NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19,
 820        NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20,
 821        NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28,
 822        NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29,
 823        NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30,
 824        NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31,
 825        NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32,
 826        NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33
 827};
 828static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
 829{
 830        return NI_USUAL_PFI_SELECT(pfi_channel);
 831}
 832static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
 833{
 834        return NI_USUAL_RTSI_SELECT(rtsi_channel);
 835}
 836
 837/* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI
 838 * boards.  These scan begin sources can also be bitwise-or'd with CR_INVERT to
 839 * change polarity. */
 840static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
 841{
 842        return NI_USUAL_PFI_SELECT(pfi_channel);
 843}
 844static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
 845{
 846        return NI_USUAL_RTSI_SELECT(rtsi_channel);
 847}
 848
 849/* Bits for setting a clock source with
 850 * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */
 851enum ni_freq_out_clock_source_bits {
 852        NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */
 853        NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC        /* 100 KHz */
 854};
 855
 856/* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
 857 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
 858        enum amplc_dio_clock_source {
 859                AMPLC_DIO_CLK_CLKN,     /* per channel external clock
 860                                           input/output pin (pin is only an
 861                                           input when clock source set to this
 862                                           value, otherwise it is an output) */
 863                AMPLC_DIO_CLK_10MHZ,    /* 10 MHz internal clock */
 864                AMPLC_DIO_CLK_1MHZ,     /* 1 MHz internal clock */
 865                AMPLC_DIO_CLK_100KHZ,   /* 100 kHz internal clock */
 866                AMPLC_DIO_CLK_10KHZ,    /* 10 kHz internal clock */
 867                AMPLC_DIO_CLK_1KHZ,     /* 1 kHz internal clock */
 868                AMPLC_DIO_CLK_OUTNM1,   /* output of preceding counter channel
 869                                           (for channel 0, preceding counter
 870                                           channel is channel 2 on preceding
 871                                           counter subdevice, for first counter
 872                                           subdevice, preceding counter
 873                                           subdevice is the last counter
 874                                           subdevice) */
 875                AMPLC_DIO_CLK_EXT       /* per chip external input pin */
 876        };
 877
 878/* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for
 879 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
 880        enum amplc_dio_gate_source {
 881                AMPLC_DIO_GAT_VCC,      /* internal high logic level */
 882                AMPLC_DIO_GAT_GND,      /* internal low logic level */
 883                AMPLC_DIO_GAT_GATN,     /* per channel external gate input */
 884                AMPLC_DIO_GAT_NOUTNM2,  /* negated output of counter channel
 885                                           minus 2 (for channels 0 or 1,
 886                                           channel minus 2 is channel 1 or 2 on
 887                                           the preceding counter subdevice, for
 888                                           the first counter subdevice the
 889                                           preceding counter subdevice is the
 890                                           last counter subdevice) */
 891                AMPLC_DIO_GAT_RESERVED4,
 892                AMPLC_DIO_GAT_RESERVED5,
 893                AMPLC_DIO_GAT_RESERVED6,
 894                AMPLC_DIO_GAT_RESERVED7
 895        };
 896
 897#ifdef __cplusplus
 898}
 899#endif
 900
 901#endif /* _COMEDI_H */
 902