linux/drivers/net/pci-skeleton.c
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   1/*
   2
   3        drivers/net/pci-skeleton.c
   4
   5        Maintained by Jeff Garzik <jgarzik@pobox.com>
   6
   7        Original code came from 8139too.c, which in turns was based
   8        originally on Donald Becker's rtl8139.c driver, versions 1.11
   9        and older.  This driver was originally based on rtl8139.c
  10        version 1.07.  Header of rtl8139.c version 1.11:
  11
  12        -----<snip>-----
  13
  14                Written 1997-2000 by Donald Becker.
  15                This software may be used and distributed according to the
  16                terms of the GNU General Public License (GPL), incorporated
  17                herein by reference.  Drivers based on or derived from this
  18                code fall under the GPL and must retain the authorship,
  19                copyright and license notice.  This file is not a complete
  20                program and may only be used when the entire operating
  21                system is licensed under the GPL.
  22
  23                This driver is for boards based on the RTL8129 and RTL8139
  24                PCI ethernet chips.
  25
  26                The author may be reached as becker@scyld.com, or C/O Scyld
  27                Computing Corporation 410 Severn Ave., Suite 210 Annapolis
  28                MD 21403
  29
  30                Support and updates available at
  31                http://www.scyld.com/network/rtl8139.html
  32
  33                Twister-tuning table provided by Kinston
  34                <shangh@realtek.com.tw>.
  35
  36        -----<snip>-----
  37
  38        This software may be used and distributed according to the terms
  39        of the GNU General Public License, incorporated herein by reference.
  40
  41
  42-----------------------------------------------------------------------------
  43
  44                                Theory of Operation
  45
  46I. Board Compatibility
  47
  48This device driver is designed for the RealTek RTL8139 series, the RealTek
  49Fast Ethernet controllers for PCI and CardBus.  This chip is used on many
  50low-end boards, sometimes with its markings changed.
  51
  52
  53II. Board-specific settings
  54
  55PCI bus devices are configured by the system at boot time, so no jumpers
  56need to be set on the board.  The system BIOS will assign the
  57PCI INTA signal to a (preferably otherwise unused) system IRQ line.
  58
  59III. Driver operation
  60
  61IIIa. Rx Ring buffers
  62
  63The receive unit uses a single linear ring buffer rather than the more
  64common (and more efficient) descriptor-based architecture.  Incoming frames
  65are sequentially stored into the Rx region, and the host copies them into
  66skbuffs.
  67
  68Comment: While it is theoretically possible to process many frames in place,
  69any delay in Rx processing would cause us to drop frames.  More importantly,
  70the Linux protocol stack is not designed to operate in this manner.
  71
  72IIIb. Tx operation
  73
  74The RTL8139 uses a fixed set of four Tx descriptors in register space.
  75In a stunningly bad design choice, Tx frames must be 32 bit aligned.  Linux
  76aligns the IP header on word boundaries, and 14 byte ethernet header means
  77that almost all frames will need to be copied to an alignment buffer.
  78
  79IVb. References
  80
  81http://www.realtek.com.tw/cn/cn.html
  82http://www.scyld.com/expert/NWay.html
  83
  84IVc. Errata
  85
  86*/
  87
  88#include <linux/module.h>
  89#include <linux/kernel.h>
  90#include <linux/pci.h>
  91#include <linux/init.h>
  92#include <linux/ioport.h>
  93#include <linux/netdevice.h>
  94#include <linux/etherdevice.h>
  95#include <linux/delay.h>
  96#include <linux/ethtool.h>
  97#include <linux/mii.h>
  98#include <linux/crc32.h>
  99#include <asm/io.h>
 100
 101#define NETDRV_VERSION          "1.0.1"
 102#define MODNAME                 "netdrv"
 103#define NETDRV_DRIVER_LOAD_MSG  "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
 104#define PFX                     MODNAME ": "
 105
 106static char version[] __devinitdata =
 107KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n"
 108KERN_INFO "  Support available from http://foo.com/bar/baz.html\n";
 109
 110/* define to 1 to enable PIO instead of MMIO */
 111#undef USE_IO_OPS
 112
 113/* define to 1 to enable copious debugging info */
 114#undef NETDRV_DEBUG
 115
 116/* define to 1 to disable lightweight runtime debugging checks */
 117#undef NETDRV_NDEBUG
 118
 119
 120#ifdef NETDRV_DEBUG
 121/* note: prints function name for you */
 122#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
 123#else
 124#  define DPRINTK(fmt, args...)
 125#endif
 126
 127#ifdef NETDRV_NDEBUG
 128#  define assert(expr) do {} while (0)
 129#else
 130#  define assert(expr) \
 131        if(!(expr)) {                                   \
 132        printk( "Assertion failed! %s,%s,%s,line=%d\n", \
 133        #expr,__FILE__,__func__,__LINE__);              \
 134        }
 135#endif
 136
 137
 138/* A few user-configurable values. */
 139/* media options */
 140static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
 141
 142/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
 143static int max_interrupt_work = 20;
 144
 145/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
 146   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */
 147static int multicast_filter_limit = 32;
 148
 149/* Size of the in-memory receive ring. */
 150#define RX_BUF_LEN_IDX  2       /* 0==8K, 1==16K, 2==32K, 3==64K */
 151#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
 152#define RX_BUF_PAD 16
 153#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
 154#define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
 155
 156/* Number of Tx descriptor registers. */
 157#define NUM_TX_DESC     4
 158
 159/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
 160#define MAX_ETH_FRAME_SIZE      1536
 161
 162/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
 163#define TX_BUF_SIZE     MAX_ETH_FRAME_SIZE
 164#define TX_BUF_TOT_LEN  (TX_BUF_SIZE * NUM_TX_DESC)
 165
 166/* PCI Tuning Parameters
 167   Threshold is bytes transferred to chip before transmission starts. */
 168#define TX_FIFO_THRESH 256      /* In bytes, rounded down to 32 byte units. */
 169
 170/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */
 171#define RX_FIFO_THRESH  6       /* Rx buffer level before first PCI xfer.  */
 172#define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
 173#define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
 174
 175
 176/* Operational parameters that usually are not changed. */
 177/* Time in jiffies before concluding the transmitter is hung. */
 178#define TX_TIMEOUT  (6*HZ)
 179
 180
 181enum {
 182        HAS_CHIP_XCVR = 0x020000,
 183        HAS_LNK_CHNG = 0x040000,
 184};
 185
 186#define NETDRV_MIN_IO_SIZE 0x80
 187#define RTL8139B_IO_SIZE 256
 188
 189#define NETDRV_CAPS     HAS_CHIP_XCVR|HAS_LNK_CHNG
 190
 191typedef enum {
 192        RTL8139 = 0,
 193        NETDRV_CB,
 194        SMC1211TX,
 195        /*MPX5030,*/
 196        DELTA8139,
 197        ADDTRON8139,
 198} board_t;
 199
 200
 201/* indexed by board_t, above */
 202static struct {
 203        const char *name;
 204} board_info[] __devinitdata = {
 205        { "RealTek RTL8139 Fast Ethernet" },
 206        { "RealTek RTL8139B PCI/CardBus" },
 207        { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
 208/*      { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
 209        { "Delta Electronics 8139 10/100BaseTX" },
 210        { "Addtron Technolgy 8139 10/100BaseTX" },
 211};
 212
 213
 214static struct pci_device_id netdrv_pci_tbl[] = {
 215        {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 216        {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
 217        {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
 218/*      {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
 219        {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
 220        {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
 221        {0,}
 222};
 223MODULE_DEVICE_TABLE (pci, netdrv_pci_tbl);
 224
 225
 226/* The rest of these values should never change. */
 227
 228/* Symbolic offsets to registers. */
 229enum NETDRV_registers {
 230        MAC0 = 0,               /* Ethernet hardware address. */
 231        MAR0 = 8,               /* Multicast filter. */
 232        TxStatus0 = 0x10,       /* Transmit status (Four 32bit registers). */
 233        TxAddr0 = 0x20,         /* Tx descriptors (also four 32bit). */
 234        RxBuf = 0x30,
 235        RxEarlyCnt = 0x34,
 236        RxEarlyStatus = 0x36,
 237        ChipCmd = 0x37,
 238        RxBufPtr = 0x38,
 239        RxBufAddr = 0x3A,
 240        IntrMask = 0x3C,
 241        IntrStatus = 0x3E,
 242        TxConfig = 0x40,
 243        ChipVersion = 0x43,
 244        RxConfig = 0x44,
 245        Timer = 0x48,           /* A general-purpose counter. */
 246        RxMissed = 0x4C,        /* 24 bits valid, write clears. */
 247        Cfg9346 = 0x50,
 248        Config0 = 0x51,
 249        Config1 = 0x52,
 250        FlashReg = 0x54,
 251        MediaStatus = 0x58,
 252        Config3 = 0x59,
 253        Config4 = 0x5A,         /* absent on RTL-8139A */
 254        HltClk = 0x5B,
 255        MultiIntr = 0x5C,
 256        TxSummary = 0x60,
 257        BasicModeCtrl = 0x62,
 258        BasicModeStatus = 0x64,
 259        NWayAdvert = 0x66,
 260        NWayLPAR = 0x68,
 261        NWayExpansion = 0x6A,
 262        /* Undocumented registers, but required for proper operation. */
 263        FIFOTMS = 0x70,         /* FIFO Control and test. */
 264        CSCR = 0x74,            /* Chip Status and Configuration Register. */
 265        PARA78 = 0x78,
 266        PARA7c = 0x7c,          /* Magic transceiver parameter register. */
 267        Config5 = 0xD8,         /* absent on RTL-8139A */
 268};
 269
 270enum ClearBitMasks {
 271        MultiIntrClear = 0xF000,
 272        ChipCmdClear = 0xE2,
 273        Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
 274};
 275
 276enum ChipCmdBits {
 277        CmdReset = 0x10,
 278        CmdRxEnb = 0x08,
 279        CmdTxEnb = 0x04,
 280        RxBufEmpty = 0x01,
 281};
 282
 283/* Interrupt register bits, using my own meaningful names. */
 284enum IntrStatusBits {
 285        PCIErr = 0x8000,
 286        PCSTimeout = 0x4000,
 287        RxFIFOOver = 0x40,
 288        RxUnderrun = 0x20,
 289        RxOverflow = 0x10,
 290        TxErr = 0x08,
 291        TxOK = 0x04,
 292        RxErr = 0x02,
 293        RxOK = 0x01,
 294};
 295enum TxStatusBits {
 296        TxHostOwns = 0x2000,
 297        TxUnderrun = 0x4000,
 298        TxStatOK = 0x8000,
 299        TxOutOfWindow = 0x20000000,
 300        TxAborted = 0x40000000,
 301        TxCarrierLost = 0x80000000,
 302};
 303enum RxStatusBits {
 304        RxMulticast = 0x8000,
 305        RxPhysical = 0x4000,
 306        RxBroadcast = 0x2000,
 307        RxBadSymbol = 0x0020,
 308        RxRunt = 0x0010,
 309        RxTooLong = 0x0008,
 310        RxCRCErr = 0x0004,
 311        RxBadAlign = 0x0002,
 312        RxStatusOK = 0x0001,
 313};
 314
 315/* Bits in RxConfig. */
 316enum rx_mode_bits {
 317        AcceptErr = 0x20,
 318        AcceptRunt = 0x10,
 319        AcceptBroadcast = 0x08,
 320        AcceptMulticast = 0x04,
 321        AcceptMyPhys = 0x02,
 322        AcceptAllPhys = 0x01,
 323};
 324
 325/* Bits in TxConfig. */
 326enum tx_config_bits {
 327        TxIFG1 = (1 << 25),     /* Interframe Gap Time */
 328        TxIFG0 = (1 << 24),     /* Enabling these bits violates IEEE 802.3 */
 329        TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
 330        TxCRC = (1 << 16),      /* DISABLE appending CRC to end of Tx packets */
 331        TxClearAbt = (1 << 0),  /* Clear abort (WO) */
 332        TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
 333
 334        TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
 335};
 336
 337/* Bits in Config1 */
 338enum Config1Bits {
 339        Cfg1_PM_Enable = 0x01,
 340        Cfg1_VPD_Enable = 0x02,
 341        Cfg1_PIO = 0x04,
 342        Cfg1_MMIO = 0x08,
 343        Cfg1_LWAKE = 0x10,
 344        Cfg1_Driver_Load = 0x20,
 345        Cfg1_LED0 = 0x40,
 346        Cfg1_LED1 = 0x80,
 347};
 348
 349enum RxConfigBits {
 350        /* Early Rx threshold, none or X/16 */
 351        RxCfgEarlyRxNone = 0,
 352        RxCfgEarlyRxShift = 24,
 353
 354        /* rx fifo threshold */
 355        RxCfgFIFOShift = 13,
 356        RxCfgFIFONone = (7 << RxCfgFIFOShift),
 357
 358        /* Max DMA burst */
 359        RxCfgDMAShift = 8,
 360        RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
 361
 362        /* rx ring buffer length */
 363        RxCfgRcv8K = 0,
 364        RxCfgRcv16K = (1 << 11),
 365        RxCfgRcv32K = (1 << 12),
 366        RxCfgRcv64K = (1 << 11) | (1 << 12),
 367
 368        /* Disable packet wrap at end of Rx buffer */
 369        RxNoWrap = (1 << 7),
 370};
 371
 372
 373/* Twister tuning parameters from RealTek.
 374   Completely undocumented, but required to tune bad links. */
 375enum CSCRBits {
 376        CSCR_LinkOKBit = 0x0400,
 377        CSCR_LinkChangeBit = 0x0800,
 378        CSCR_LinkStatusBits = 0x0f000,
 379        CSCR_LinkDownOffCmd = 0x003c0,
 380        CSCR_LinkDownCmd = 0x0f3c0,
 381};
 382
 383
 384enum Cfg9346Bits {
 385        Cfg9346_Lock = 0x00,
 386        Cfg9346_Unlock = 0xC0,
 387};
 388
 389
 390#define PARA78_default  0x78fa8388
 391#define PARA7c_default  0xcb38de43      /* param[0][3] */
 392#define PARA7c_xxx              0xcb38de43
 393static const unsigned long param[4][4] = {
 394        {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
 395        {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
 396        {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
 397        {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
 398};
 399
 400struct ring_info {
 401        struct sk_buff *skb;
 402        dma_addr_t mapping;
 403};
 404
 405
 406typedef enum {
 407        CH_8139 = 0,
 408        CH_8139_K,
 409        CH_8139A,
 410        CH_8139B,
 411        CH_8130,
 412        CH_8139C,
 413} chip_t;
 414
 415
 416/* directly indexed by chip_t, above */
 417static const struct {
 418        const char *name;
 419        u8 version; /* from RTL8139C docs */
 420        u32 RxConfigMask; /* should clear the bits supported by this chip */
 421} rtl_chip_info[] = {
 422        { "RTL-8139",
 423          0x40,
 424          0xf0fe0040, /* XXX copied from RTL8139A, verify */
 425        },
 426
 427        { "RTL-8139 rev K",
 428          0x60,
 429          0xf0fe0040,
 430        },
 431
 432        { "RTL-8139A",
 433          0x70,
 434          0xf0fe0040,
 435        },
 436
 437        { "RTL-8139B",
 438          0x78,
 439          0xf0fc0040
 440        },
 441
 442        { "RTL-8130",
 443          0x7C,
 444          0xf0fe0040, /* XXX copied from RTL8139A, verify */
 445        },
 446
 447        { "RTL-8139C",
 448          0x74,
 449          0xf0fc0040, /* XXX copied from RTL8139B, verify */
 450        },
 451
 452};
 453
 454
 455struct netdrv_private {
 456        board_t board;
 457        void *mmio_addr;
 458        int drv_flags;
 459        struct pci_dev *pci_dev;
 460        struct timer_list timer;        /* Media selection timer. */
 461        unsigned char *rx_ring;
 462        unsigned int cur_rx;    /* Index into the Rx buffer of next Rx pkt. */
 463        unsigned int tx_flag;
 464        atomic_t cur_tx;
 465        atomic_t dirty_tx;
 466        /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 467        struct ring_info tx_info[NUM_TX_DESC];
 468        unsigned char *tx_buf[NUM_TX_DESC];     /* Tx bounce buffers */
 469        unsigned char *tx_bufs; /* Tx bounce buffer region. */
 470        dma_addr_t rx_ring_dma;
 471        dma_addr_t tx_bufs_dma;
 472        char phys[4];           /* MII device addresses. */
 473        char twistie, twist_row, twist_col;     /* Twister tune state. */
 474        unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 475        unsigned int duplex_lock:1;
 476        unsigned int default_port:4;    /* Last dev->if_port value. */
 477        unsigned int media2:4;  /* Secondary monitored media port. */
 478        unsigned int medialock:1;       /* Don't sense media type. */
 479        unsigned int mediasense:1;      /* Media sensing in progress. */
 480        spinlock_t lock;
 481        chip_t chipset;
 482};
 483
 484MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
 485MODULE_DESCRIPTION ("Skeleton for a PCI Fast Ethernet driver");
 486MODULE_LICENSE("GPL");
 487module_param(multicast_filter_limit, int, 0);
 488module_param(max_interrupt_work, int, 0);
 489module_param_array(media, int, NULL, 0);
 490MODULE_PARM_DESC (multicast_filter_limit, "pci-skeleton maximum number of filtered multicast addresses");
 491MODULE_PARM_DESC (max_interrupt_work, "pci-skeleton maximum events handled per interrupt");
 492MODULE_PARM_DESC (media, "pci-skeleton: Bits 0-3: media type, bit 17: full duplex");
 493
 494static int read_eeprom (void *ioaddr, int location, int addr_len);
 495static int netdrv_open (struct net_device *dev);
 496static int mdio_read (struct net_device *dev, int phy_id, int location);
 497static void mdio_write (struct net_device *dev, int phy_id, int location,
 498                        int val);
 499static void netdrv_timer (unsigned long data);
 500static void netdrv_tx_timeout (struct net_device *dev);
 501static void netdrv_init_ring (struct net_device *dev);
 502static int netdrv_start_xmit (struct sk_buff *skb,
 503                               struct net_device *dev);
 504static irqreturn_t netdrv_interrupt (int irq, void *dev_instance);
 505static int netdrv_close (struct net_device *dev);
 506static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
 507static void netdrv_set_rx_mode (struct net_device *dev);
 508static void netdrv_hw_start (struct net_device *dev);
 509
 510
 511#ifdef USE_IO_OPS
 512
 513#define NETDRV_R8(reg)          inb (((unsigned long)ioaddr) + (reg))
 514#define NETDRV_R16(reg)         inw (((unsigned long)ioaddr) + (reg))
 515#define NETDRV_R32(reg)         ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
 516#define NETDRV_W8(reg, val8)    outb ((val8), ((unsigned long)ioaddr) + (reg))
 517#define NETDRV_W16(reg, val16)  outw ((val16), ((unsigned long)ioaddr) + (reg))
 518#define NETDRV_W32(reg, val32)  outl ((val32), ((unsigned long)ioaddr) + (reg))
 519#define NETDRV_W8_F             NETDRV_W8
 520#define NETDRV_W16_F            NETDRV_W16
 521#define NETDRV_W32_F            NETDRV_W32
 522#undef readb
 523#undef readw
 524#undef readl
 525#undef writeb
 526#undef writew
 527#undef writel
 528#define readb(addr) inb((unsigned long)(addr))
 529#define readw(addr) inw((unsigned long)(addr))
 530#define readl(addr) inl((unsigned long)(addr))
 531#define writeb(val,addr) outb((val),(unsigned long)(addr))
 532#define writew(val,addr) outw((val),(unsigned long)(addr))
 533#define writel(val,addr) outl((val),(unsigned long)(addr))
 534
 535#else
 536
 537/* write MMIO register, with flush */
 538/* Flush avoids rtl8139 bug w/ posted MMIO writes */
 539#define NETDRV_W8_F(reg, val8)  do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
 540#define NETDRV_W16_F(reg, val16)        do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
 541#define NETDRV_W32_F(reg, val32)        do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
 542
 543
 544#ifdef MMIO_FLUSH_AUDIT_COMPLETE
 545
 546/* write MMIO register */
 547#define NETDRV_W8(reg, val8)    writeb ((val8), ioaddr + (reg))
 548#define NETDRV_W16(reg, val16)  writew ((val16), ioaddr + (reg))
 549#define NETDRV_W32(reg, val32)  writel ((val32), ioaddr + (reg))
 550
 551#else
 552
 553/* write MMIO register, then flush */
 554#define NETDRV_W8               NETDRV_W8_F
 555#define NETDRV_W16              NETDRV_W16_F
 556#define NETDRV_W32              NETDRV_W32_F
 557
 558#endif /* MMIO_FLUSH_AUDIT_COMPLETE */
 559
 560/* read MMIO register */
 561#define NETDRV_R8(reg)          readb (ioaddr + (reg))
 562#define NETDRV_R16(reg)         readw (ioaddr + (reg))
 563#define NETDRV_R32(reg)         ((unsigned long) readl (ioaddr + (reg)))
 564
 565#endif /* USE_IO_OPS */
 566
 567
 568static const u16 netdrv_intr_mask =
 569        PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
 570        TxErr | TxOK | RxErr | RxOK;
 571
 572static const unsigned int netdrv_rx_config =
 573          RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
 574          (RX_FIFO_THRESH << RxCfgFIFOShift) |
 575          (RX_DMA_BURST << RxCfgDMAShift);
 576
 577
 578static int __devinit netdrv_init_board (struct pci_dev *pdev,
 579                                         struct net_device **dev_out,
 580                                         void **ioaddr_out)
 581{
 582        void *ioaddr = NULL;
 583        struct net_device *dev;
 584        struct netdrv_private *tp;
 585        int rc, i;
 586        u32 pio_start, pio_end, pio_flags, pio_len;
 587        unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
 588        u32 tmp;
 589
 590        DPRINTK ("ENTER\n");
 591
 592        assert (pdev != NULL);
 593        assert (ioaddr_out != NULL);
 594
 595        *ioaddr_out = NULL;
 596        *dev_out = NULL;
 597
 598        /* dev zeroed in alloc_etherdev */
 599        dev = alloc_etherdev (sizeof (*tp));
 600        if (dev == NULL) {
 601                dev_err(&pdev->dev, "unable to alloc new ethernet\n");
 602                DPRINTK ("EXIT, returning -ENOMEM\n");
 603                return -ENOMEM;
 604        }
 605        SET_NETDEV_DEV(dev, &pdev->dev);
 606        tp = netdev_priv(dev);
 607
 608        /* enable device (incl. PCI PM wakeup), and bus-mastering */
 609        rc = pci_enable_device (pdev);
 610        if (rc)
 611                goto err_out;
 612
 613        pio_start = pci_resource_start (pdev, 0);
 614        pio_end = pci_resource_end (pdev, 0);
 615        pio_flags = pci_resource_flags (pdev, 0);
 616        pio_len = pci_resource_len (pdev, 0);
 617
 618        mmio_start = pci_resource_start (pdev, 1);
 619        mmio_end = pci_resource_end (pdev, 1);
 620        mmio_flags = pci_resource_flags (pdev, 1);
 621        mmio_len = pci_resource_len (pdev, 1);
 622
 623        /* set this immediately, we need to know before
 624         * we talk to the chip directly */
 625        DPRINTK("PIO region size == 0x%02X\n", pio_len);
 626        DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
 627
 628        /* make sure PCI base addr 0 is PIO */
 629        if (!(pio_flags & IORESOURCE_IO)) {
 630                dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
 631                rc = -ENODEV;
 632                goto err_out;
 633        }
 634
 635        /* make sure PCI base addr 1 is MMIO */
 636        if (!(mmio_flags & IORESOURCE_MEM)) {
 637                dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
 638                rc = -ENODEV;
 639                goto err_out;
 640        }
 641
 642        /* check for weird/broken PCI region reporting */
 643        if ((pio_len < NETDRV_MIN_IO_SIZE) ||
 644            (mmio_len < NETDRV_MIN_IO_SIZE)) {
 645                dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
 646                rc = -ENODEV;
 647                goto err_out;
 648        }
 649
 650        rc = pci_request_regions (pdev, MODNAME);
 651        if (rc)
 652                goto err_out;
 653
 654        pci_set_master (pdev);
 655
 656#ifdef USE_IO_OPS
 657        ioaddr = (void *) pio_start;
 658#else
 659        /* ioremap MMIO region */
 660        ioaddr = ioremap (mmio_start, mmio_len);
 661        if (ioaddr == NULL) {
 662                dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
 663                rc = -EIO;
 664                goto err_out_free_res;
 665        }
 666#endif /* USE_IO_OPS */
 667
 668        /* Soft reset the chip. */
 669        NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
 670
 671        /* Check that the chip has finished the reset. */
 672        for (i = 1000; i > 0; i--)
 673                if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
 674                        break;
 675                else
 676                        udelay (10);
 677
 678        /* Bring the chip out of low-power mode. */
 679        /* <insert device-specific code here> */
 680
 681#ifndef USE_IO_OPS
 682        /* sanity checks -- ensure PIO and MMIO registers agree */
 683        assert (inb (pio_start+Config0) == readb (ioaddr+Config0));
 684        assert (inb (pio_start+Config1) == readb (ioaddr+Config1));
 685        assert (inb (pio_start+TxConfig) == readb (ioaddr+TxConfig));
 686        assert (inb (pio_start+RxConfig) == readb (ioaddr+RxConfig));
 687#endif /* !USE_IO_OPS */
 688
 689        /* identify chip attached to board */
 690        tmp = NETDRV_R8 (ChipVersion);
 691        for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--)
 692                if (tmp == rtl_chip_info[i].version) {
 693                        tp->chipset = i;
 694                        goto match;
 695                }
 696
 697        /* if unknown chip, assume array element #0, original RTL-8139 in this case */
 698        dev_printk (KERN_DEBUG, &pdev->dev,
 699                "unknown chip version, assuming RTL-8139\n");
 700        dev_printk (KERN_DEBUG, &pdev->dev, "TxConfig = 0x%lx\n",
 701                NETDRV_R32 (TxConfig));
 702        tp->chipset = 0;
 703
 704match:
 705        DPRINTK ("chipset id (%d) == index %d, '%s'\n",
 706                tmp,
 707                tp->chipset,
 708                rtl_chip_info[tp->chipset].name);
 709
 710        rc = register_netdev (dev);
 711        if (rc)
 712                goto err_out_unmap;
 713
 714        DPRINTK ("EXIT, returning 0\n");
 715        *ioaddr_out = ioaddr;
 716        *dev_out = dev;
 717        return 0;
 718
 719err_out_unmap:
 720#ifndef USE_IO_OPS
 721        iounmap(ioaddr);
 722err_out_free_res:
 723#endif
 724        pci_release_regions (pdev);
 725err_out:
 726        free_netdev (dev);
 727        DPRINTK ("EXIT, returning %d\n", rc);
 728        return rc;
 729}
 730
 731
 732static int __devinit netdrv_init_one (struct pci_dev *pdev,
 733                                       const struct pci_device_id *ent)
 734{
 735        struct net_device *dev = NULL;
 736        struct netdrv_private *tp;
 737        int i, addr_len, option;
 738        void *ioaddr = NULL;
 739        static int board_idx = -1;
 740
 741/* when built into the kernel, we only print version if device is found */
 742#ifndef MODULE
 743        static int printed_version;
 744        if (!printed_version++)
 745                printk(version);
 746#endif
 747
 748        DPRINTK ("ENTER\n");
 749
 750        assert (pdev != NULL);
 751        assert (ent != NULL);
 752
 753        board_idx++;
 754
 755        i = netdrv_init_board (pdev, &dev, &ioaddr);
 756        if (i < 0) {
 757                DPRINTK ("EXIT, returning %d\n", i);
 758                return i;
 759        }
 760
 761        tp = netdev_priv(dev);
 762
 763        assert (ioaddr != NULL);
 764        assert (dev != NULL);
 765        assert (tp != NULL);
 766
 767        addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
 768        for (i = 0; i < 3; i++)
 769                ((u16 *) (dev->dev_addr))[i] =
 770                    le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
 771
 772        /* The Rtl8139-specific entries in the device structure. */
 773        dev->open = netdrv_open;
 774        dev->hard_start_xmit = netdrv_start_xmit;
 775        dev->stop = netdrv_close;
 776        dev->set_multicast_list = netdrv_set_rx_mode;
 777        dev->do_ioctl = netdrv_ioctl;
 778        dev->tx_timeout = netdrv_tx_timeout;
 779        dev->watchdog_timeo = TX_TIMEOUT;
 780
 781        dev->irq = pdev->irq;
 782        dev->base_addr = (unsigned long) ioaddr;
 783
 784        /* netdev_priv()/tp zeroed and aligned in alloc_etherdev */
 785        tp = netdev_priv(dev);
 786
 787        /* note: tp->chipset set in netdrv_init_board */
 788        tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 789                        PCI_COMMAND_MASTER | NETDRV_CAPS;
 790        tp->pci_dev = pdev;
 791        tp->board = ent->driver_data;
 792        tp->mmio_addr = ioaddr;
 793        spin_lock_init(&tp->lock);
 794
 795        pci_set_drvdata(pdev, dev);
 796
 797        tp->phys[0] = 32;
 798
 799        printk (KERN_INFO "%s: %s at 0x%lx, %pM IRQ %d\n",
 800                dev->name,
 801                board_info[ent->driver_data].name,
 802                dev->base_addr,
 803                dev->dev_addr,
 804                dev->irq);
 805
 806        printk (KERN_DEBUG "%s:  Identified 8139 chip type '%s'\n",
 807                dev->name, rtl_chip_info[tp->chipset].name);
 808
 809        /* Put the chip into low-power mode. */
 810        NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
 811
 812        /* The lower four bits are the media type. */
 813        option = (board_idx > 7) ? 0 : media[board_idx];
 814        if (option > 0) {
 815                tp->full_duplex = (option & 0x200) ? 1 : 0;
 816                tp->default_port = option & 15;
 817                if (tp->default_port)
 818                        tp->medialock = 1;
 819        }
 820
 821        if (tp->full_duplex) {
 822                printk (KERN_INFO
 823                        "%s: Media type forced to Full Duplex.\n",
 824                        dev->name);
 825                mdio_write (dev, tp->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
 826                tp->duplex_lock = 1;
 827        }
 828
 829        DPRINTK ("EXIT - returning 0\n");
 830        return 0;
 831}
 832
 833
 834static void __devexit netdrv_remove_one (struct pci_dev *pdev)
 835{
 836        struct net_device *dev = pci_get_drvdata (pdev);
 837        struct netdrv_private *np;
 838
 839        DPRINTK ("ENTER\n");
 840
 841        assert (dev != NULL);
 842
 843        np = netdev_priv(dev);
 844        assert (np != NULL);
 845
 846        unregister_netdev (dev);
 847
 848#ifndef USE_IO_OPS
 849        iounmap (np->mmio_addr);
 850#endif /* !USE_IO_OPS */
 851
 852        pci_release_regions (pdev);
 853
 854        free_netdev (dev);
 855
 856        pci_set_drvdata (pdev, NULL);
 857
 858        pci_disable_device (pdev);
 859
 860        DPRINTK ("EXIT\n");
 861}
 862
 863
 864/* Serial EEPROM section. */
 865
 866/*  EEPROM_Ctrl bits. */
 867#define EE_SHIFT_CLK    0x04    /* EEPROM shift clock. */
 868#define EE_CS                   0x08    /* EEPROM chip select. */
 869#define EE_DATA_WRITE   0x02    /* EEPROM chip data in. */
 870#define EE_WRITE_0              0x00
 871#define EE_WRITE_1              0x02
 872#define EE_DATA_READ    0x01    /* EEPROM chip data out. */
 873#define EE_ENB                  (0x80 | EE_CS)
 874
 875/* Delay between EEPROM clock transitions.
 876   No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
 877 */
 878
 879#define eeprom_delay()  readl(ee_addr)
 880
 881/* The EEPROM commands include the alway-set leading bit. */
 882#define EE_WRITE_CMD    (5)
 883#define EE_READ_CMD             (6)
 884#define EE_ERASE_CMD    (7)
 885
 886static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
 887{
 888        int i;
 889        unsigned retval = 0;
 890        void *ee_addr = ioaddr + Cfg9346;
 891        int read_cmd = location | (EE_READ_CMD << addr_len);
 892
 893        DPRINTK ("ENTER\n");
 894
 895        writeb (EE_ENB & ~EE_CS, ee_addr);
 896        writeb (EE_ENB, ee_addr);
 897        eeprom_delay ();
 898
 899        /* Shift the read command bits out. */
 900        for (i = 4 + addr_len; i >= 0; i--) {
 901                int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 902                writeb (EE_ENB | dataval, ee_addr);
 903                eeprom_delay ();
 904                writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
 905                eeprom_delay ();
 906        }
 907        writeb (EE_ENB, ee_addr);
 908        eeprom_delay ();
 909
 910        for (i = 16; i > 0; i--) {
 911                writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
 912                eeprom_delay ();
 913                retval =
 914                    (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
 915                                     0);
 916                writeb (EE_ENB, ee_addr);
 917                eeprom_delay ();
 918        }
 919
 920        /* Terminate the EEPROM access. */
 921        writeb (~EE_CS, ee_addr);
 922        eeprom_delay ();
 923
 924        DPRINTK ("EXIT - returning %d\n", retval);
 925        return retval;
 926}
 927
 928/* MII serial management: mostly bogus for now. */
 929/* Read and write the MII management registers using software-generated
 930   serial MDIO protocol.
 931   The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
 932   met by back-to-back PCI I/O cycles, but we insert a delay to avoid
 933   "overclocking" issues. */
 934#define MDIO_DIR                0x80
 935#define MDIO_DATA_OUT   0x04
 936#define MDIO_DATA_IN    0x02
 937#define MDIO_CLK                0x01
 938#define MDIO_WRITE0 (MDIO_DIR)
 939#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
 940
 941#define mdio_delay()    readb(mdio_addr)
 942
 943
 944static char mii_2_8139_map[8] = {
 945        BasicModeCtrl,
 946        BasicModeStatus,
 947        0,
 948        0,
 949        NWayAdvert,
 950        NWayLPAR,
 951        NWayExpansion,
 952        0
 953};
 954
 955
 956/* Syncronize the MII management interface by shifting 32 one bits out. */
 957static void mdio_sync (void *mdio_addr)
 958{
 959        int i;
 960
 961        DPRINTK ("ENTER\n");
 962
 963        for (i = 32; i >= 0; i--) {
 964                writeb (MDIO_WRITE1, mdio_addr);
 965                mdio_delay ();
 966                writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
 967                mdio_delay ();
 968        }
 969
 970        DPRINTK ("EXIT\n");
 971}
 972
 973
 974static int mdio_read (struct net_device *dev, int phy_id, int location)
 975{
 976        struct netdrv_private *tp = netdev_priv(dev);
 977        void *mdio_addr = tp->mmio_addr + Config4;
 978        int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
 979        int retval = 0;
 980        int i;
 981
 982        DPRINTK ("ENTER\n");
 983
 984        if (phy_id > 31) {      /* Really a 8139.  Use internal registers. */
 985                DPRINTK ("EXIT after directly using 8139 internal regs\n");
 986                return location < 8 && mii_2_8139_map[location] ?
 987                    readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
 988        }
 989        mdio_sync (mdio_addr);
 990        /* Shift the read command bits out. */
 991        for (i = 15; i >= 0; i--) {
 992                int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
 993
 994                writeb (MDIO_DIR | dataval, mdio_addr);
 995                mdio_delay ();
 996                writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
 997                mdio_delay ();
 998        }
 999
1000        /* Read the two transition, 16 data, and wire-idle bits. */

1001        for (i = 19; i > 0; i--) {
1002                writeb (0, mdio_addr);
1003                mdio_delay ();
1004                retval =
1005                    (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1
1006                                     : 0);
1007                writeb (MDIO_CLK, mdio_addr);
1008                mdio_delay ();
1009        }
1010
1011        DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1012        return (retval >> 1) & 0xffff;
1013}
1014
1015
1016static void mdio_write (struct net_device *dev, int phy_id, int location,
1017                        int value)
1018{
1019        struct netdrv_private *tp = netdev_priv(dev);
1020        void *mdio_addr = tp->mmio_addr + Config4;
1021        int mii_cmd =
1022            (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1023        int i;
1024
1025        DPRINTK ("ENTER\n");
1026
1027        if (phy_id > 31) {      /* Really a 8139.  Use internal registers. */
1028                if (location < 8 && mii_2_8139_map[location]) {
1029                        writew (value,
1030                                tp->mmio_addr + mii_2_8139_map[location]);
1031                        readw (tp->mmio_addr + mii_2_8139_map[location]);
1032                }
1033                DPRINTK ("EXIT after directly using 8139 internal regs\n");
1034                return;
1035        }
1036        mdio_sync (mdio_addr);
1037
1038        /* Shift the command bits out. */
1039        for (i = 31; i >= 0; i--) {
1040                int dataval =
1041                    (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1042                writeb (dataval, mdio_addr);
1043                mdio_delay ();
1044                writeb (dataval | MDIO_CLK, mdio_addr);
1045                mdio_delay ();
1046        }
1047
1048        /* Clear out extra bits. */
1049        for (i = 2; i > 0; i--) {
1050                writeb (0, mdio_addr);
1051                mdio_delay ();
1052                writeb (MDIO_CLK, mdio_addr);
1053                mdio_delay ();
1054        }
1055
1056        DPRINTK ("EXIT\n");
1057}
1058
1059
1060static int netdrv_open (struct net_device *dev)
1061{
1062        struct netdrv_private *tp = netdev_priv(dev);
1063        int retval;
1064#ifdef NETDRV_DEBUG
1065        void *ioaddr = tp->mmio_addr;
1066#endif
1067
1068        DPRINTK ("ENTER\n");
1069
1070        retval = request_irq (dev->irq, netdrv_interrupt, IRQF_SHARED, dev->name, dev);
1071        if (retval) {
1072                DPRINTK ("EXIT, returning %d\n", retval);
1073                return retval;
1074        }
1075
1076        tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1077                                           &tp->tx_bufs_dma);
1078        tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1079                                           &tp->rx_ring_dma);
1080        if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1081                free_irq(dev->irq, dev);
1082
1083                if (tp->tx_bufs)
1084                        pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1085                                            tp->tx_bufs, tp->tx_bufs_dma);
1086                if (tp->rx_ring)
1087                        pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1088                                            tp->rx_ring, tp->rx_ring_dma);
1089
1090                DPRINTK ("EXIT, returning -ENOMEM\n");
1091                return -ENOMEM;
1092
1093        }
1094
1095        tp->full_duplex = tp->duplex_lock;
1096        tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1097
1098        netdrv_init_ring (dev);
1099        netdrv_hw_start (dev);
1100
1101        DPRINTK ("%s: netdrv_open() ioaddr %#lx IRQ %d"
1102                        " GP Pins %2.2x %s-duplex.\n",
1103                        dev->name, pci_resource_start (tp->pci_dev, 1),
1104                        dev->irq, NETDRV_R8 (MediaStatus),
1105                        tp->full_duplex ? "full" : "half");
1106
1107        /* Set the timer to switch to check for link beat and perhaps switch
1108           to an alternate media type. */
1109        init_timer (&tp->timer);
1110        tp->timer.expires = jiffies + 3 * HZ;
1111        tp->timer.data = (unsigned long) dev;
1112        tp->timer.function = &netdrv_timer;
1113        add_timer (&tp->timer);
1114
1115        DPRINTK ("EXIT, returning 0\n");
1116        return 0;
1117}
1118
1119
1120/* Start the hardware at open or resume. */
1121static void netdrv_hw_start (struct net_device *dev)
1122{
1123        struct netdrv_private *tp = netdev_priv(dev);
1124        void *ioaddr = tp->mmio_addr;
1125        u32 i;
1126
1127        DPRINTK ("ENTER\n");
1128
1129        /* Soft reset the chip. */
1130        NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
1131        udelay (100);
1132
1133        /* Check that the chip has finished the reset. */
1134        for (i = 1000; i > 0; i--)
1135                if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
1136                        break;
1137
1138        /* Restore our idea of the MAC address. */
1139        NETDRV_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1140        NETDRV_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1141
1142        /* Must enable Tx/Rx before setting transfer thresholds! */
1143        NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1144                           CmdRxEnb | CmdTxEnb);
1145
1146        i = netdrv_rx_config |
1147            (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1148        NETDRV_W32_F (RxConfig, i);
1149
1150        /* Check this value: the documentation for IFG contradicts ifself. */
1151        NETDRV_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1152
1153        /* unlock Config[01234] and BMCR register writes */
1154        NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
1155        udelay (10);
1156
1157        tp->cur_rx = 0;
1158
1159        /* Lock Config[01234] and BMCR register writes */
1160        NETDRV_W8_F (Cfg9346, Cfg9346_Lock);
1161        udelay (10);
1162
1163        /* init Rx ring buffer DMA address */
1164        NETDRV_W32_F (RxBuf, tp->rx_ring_dma);
1165
1166        /* init Tx buffer DMA addresses */
1167        for (i = 0; i < NUM_TX_DESC; i++)
1168                NETDRV_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1169
1170        NETDRV_W32_F (RxMissed, 0);
1171
1172        netdrv_set_rx_mode (dev);
1173
1174        /* no early-rx interrupts */
1175        NETDRV_W16 (MultiIntr, NETDRV_R16 (MultiIntr) & MultiIntrClear);
1176
1177        /* make sure RxTx has started */
1178        NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1179                           CmdRxEnb | CmdTxEnb);
1180
1181        /* Enable all known interrupts by setting the interrupt mask. */
1182        NETDRV_W16_F (IntrMask, netdrv_intr_mask);
1183
1184        netif_start_queue (dev);
1185
1186        DPRINTK ("EXIT\n");
1187}
1188
1189
1190/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1191static void netdrv_init_ring (struct net_device *dev)
1192{
1193        struct netdrv_private *tp = netdev_priv(dev);
1194        int i;
1195
1196        DPRINTK ("ENTER\n");
1197
1198        tp->cur_rx = 0;
1199        atomic_set (&tp->cur_tx, 0);
1200        atomic_set (&tp->dirty_tx, 0);
1201
1202        for (i = 0; i < NUM_TX_DESC; i++) {
1203                tp->tx_info[i].skb = NULL;
1204                tp->tx_info[i].mapping = 0;
1205                tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1206        }
1207
1208        DPRINTK ("EXIT\n");
1209}
1210
1211
1212static void netdrv_timer (unsigned long data)
1213{
1214        struct net_device *dev = (struct net_device *) data;
1215        struct netdrv_private *tp = netdev_priv(dev);
1216        void *ioaddr = tp->mmio_addr;
1217        int next_tick = 60 * HZ;
1218        int mii_lpa;
1219
1220        mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1221
1222        if (!tp->duplex_lock && mii_lpa != 0xffff) {
1223                int duplex = (mii_lpa & LPA_100FULL)
1224                    || (mii_lpa & 0x01C0) == 0x0040;
1225                if (tp->full_duplex != duplex) {
1226                        tp->full_duplex = duplex;
1227                        printk (KERN_INFO
1228                                "%s: Setting %s-duplex based on MII #%d link"
1229                                " partner ability of %4.4x.\n", dev->name,
1230                                tp->full_duplex ? "full" : "half",
1231                                tp->phys[0], mii_lpa);
1232                        NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1233                        NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1234                        NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1235                }
1236        }
1237
1238        DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1239                 dev->name, NETDRV_R16 (NWayLPAR));
1240        DPRINTK ("%s:  Other registers are IntMask %4.4x IntStatus %4.4x"
1241                 " RxStatus %4.4x.\n", dev->name,
1242                 NETDRV_R16 (IntrMask),
1243                 NETDRV_R16 (IntrStatus),
1244                 NETDRV_R32 (RxEarlyStatus));
1245        DPRINTK ("%s:  Chip config %2.2x %2.2x.\n",
1246                 dev->name, NETDRV_R8 (Config0),
1247                 NETDRV_R8 (Config1));
1248
1249        tp->timer.expires = jiffies + next_tick;
1250        add_timer (&tp->timer);
1251}
1252
1253
1254static void netdrv_tx_clear (struct net_device *dev)
1255{
1256        int i;
1257        struct netdrv_private *tp = netdev_priv(dev);
1258
1259        atomic_set (&tp->cur_tx, 0);
1260        atomic_set (&tp->dirty_tx, 0);
1261
1262        /* Dump the unsent Tx packets. */
1263        for (i = 0; i < NUM_TX_DESC; i++) {
1264                struct ring_info *rp = &tp->tx_info[i];
1265                if (rp->mapping != 0) {
1266                        pci_unmap_single (tp->pci_dev, rp->mapping,
1267                                          rp->skb->len, PCI_DMA_TODEVICE);
1268                        rp->mapping = 0;
1269                }
1270                if (rp->skb) {
1271                        dev_kfree_skb (rp->skb);
1272                        rp->skb = NULL;
1273                        dev->stats.tx_dropped++;
1274                }
1275        }
1276}
1277
1278
1279static void netdrv_tx_timeout (struct net_device *dev)
1280{
1281        struct netdrv_private *tp = netdev_priv(dev);
1282        void *ioaddr = tp->mmio_addr;
1283        int i;
1284        u8 tmp8;
1285        unsigned long flags;
1286
1287        DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1288                 "media %2.2x.\n", dev->name,
1289                 NETDRV_R8 (ChipCmd),
1290                 NETDRV_R16 (IntrStatus),
1291                 NETDRV_R8 (MediaStatus));
1292
1293        /* disable Tx ASAP, if not already */
1294        tmp8 = NETDRV_R8 (ChipCmd);
1295        if (tmp8 & CmdTxEnb)
1296                NETDRV_W8 (ChipCmd, tmp8 & ~CmdTxEnb);
1297
1298        /* Disable interrupts by clearing the interrupt mask. */
1299        NETDRV_W16 (IntrMask, 0x0000);
1300
1301        /* Emit info to figure out what went wrong. */
1302        printk (KERN_DEBUG "%s: Tx queue start entry %d  dirty entry %d.\n",
1303                dev->name, atomic_read (&tp->cur_tx),
1304                atomic_read (&tp->dirty_tx));
1305        for (i = 0; i < NUM_TX_DESC; i++)
1306                printk (KERN_DEBUG "%s:  Tx descriptor %d is %8.8lx.%s\n",
1307                        dev->name, i, NETDRV_R32 (TxStatus0 + (i * 4)),
1308                        i == atomic_read (&tp->dirty_tx) % NUM_TX_DESC ?
1309                                " (queue head)" : "");
1310
1311        /* Stop a shared interrupt from scavenging while we are. */
1312        spin_lock_irqsave (&tp->lock, flags);
1313
1314        netdrv_tx_clear (dev);
1315
1316        spin_unlock_irqrestore (&tp->lock, flags);
1317
1318        /* ...and finally, reset everything */
1319        netdrv_hw_start (dev);
1320
1321        netif_wake_queue (dev);
1322}
1323
1324
1325
1326static int netdrv_start_xmit (struct sk_buff *skb, struct net_device *dev)
1327{
1328        struct netdrv_private *tp = netdev_priv(dev);
1329        void *ioaddr = tp->mmio_addr;
1330        int entry;
1331
1332        /* Calculate the next Tx descriptor entry. */
1333        entry = atomic_read (&tp->cur_tx) % NUM_TX_DESC;
1334
1335        assert (tp->tx_info[entry].skb == NULL);
1336        assert (tp->tx_info[entry].mapping == 0);
1337
1338        tp->tx_info[entry].skb = skb;
1339        /* tp->tx_info[entry].mapping = 0; */
1340        skb_copy_from_linear_data(skb, tp->tx_buf[entry], skb->len);
1341
1342        /* Note: the chip doesn't have auto-pad! */
1343        NETDRV_W32 (TxStatus0 + (entry * sizeof(u32)),
1344                 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1345
1346        dev->trans_start = jiffies;
1347        atomic_inc (&tp->cur_tx);
1348        if ((atomic_read (&tp->cur_tx) - atomic_read (&tp->dirty_tx)) >= NUM_TX_DESC)
1349                netif_stop_queue (dev);
1350
1351        DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1352                 dev->name, skb->data, skb->len, entry);
1353
1354        return 0;
1355}
1356
1357
1358static void netdrv_tx_interrupt (struct net_device *dev,
1359                                  struct netdrv_private *tp,
1360                                  void *ioaddr)
1361{
1362        int cur_tx, dirty_tx, tx_left;
1363
1364        assert (dev != NULL);
1365        assert (tp != NULL);
1366        assert (ioaddr != NULL);
1367
1368        dirty_tx = atomic_read (&tp->dirty_tx);
1369
1370        cur_tx = atomic_read (&tp->cur_tx);
1371        tx_left = cur_tx - dirty_tx;
1372        while (tx_left > 0) {
1373                int entry = dirty_tx % NUM_TX_DESC;
1374                int txstatus;
1375
1376                txstatus = NETDRV_R32 (TxStatus0 + (entry * sizeof (u32)));
1377
1378                if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1379                        break;  /* It still hasn't been Txed */
1380
1381                /* Note: TxCarrierLost is always asserted at 100mbps. */
1382                if (txstatus & (TxOutOfWindow | TxAborted)) {
1383                        /* There was an major error, log it. */
1384                        DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1385                                 dev->name, txstatus);
1386                        dev->stats.tx_errors++;
1387                        if (txstatus & TxAborted) {
1388                                dev->stats.tx_aborted_errors++;
1389                                NETDRV_W32 (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1390                        }
1391                        if (txstatus & TxCarrierLost)
1392                                dev->stats.tx_carrier_errors++;
1393                        if (txstatus & TxOutOfWindow)
1394                                dev->stats.tx_window_errors++;
1395                } else {
1396                        if (txstatus & TxUnderrun) {
1397                                /* Add 64 to the Tx FIFO threshold. */
1398                                if (tp->tx_flag < 0x00300000)
1399                                        tp->tx_flag += 0x00020000;
1400                                dev->stats.tx_fifo_errors++;
1401                        }
1402                        dev->stats.collisions += (txstatus >> 24) & 15;
1403                        dev->stats.tx_bytes += txstatus & 0x7ff;
1404                        dev->stats.tx_packets++;
1405                }
1406
1407                /* Free the original skb. */
1408                if (tp->tx_info[entry].mapping != 0) {
1409                        pci_unmap_single(tp->pci_dev,
1410                                         tp->tx_info[entry].mapping,
1411                                         tp->tx_info[entry].skb->len,
1412                                         PCI_DMA_TODEVICE);
1413                        tp->tx_info[entry].mapping = 0;
1414                }
1415                dev_kfree_skb_irq (tp->tx_info[entry].skb);
1416                tp->tx_info[entry].skb = NULL;
1417                dirty_tx++;
1418                if (dirty_tx < 0) { /* handle signed int overflow */
1419                        atomic_sub (cur_tx, &tp->cur_tx); /* XXX racy? */
1420                        dirty_tx = cur_tx - tx_left + 1;
1421                }
1422                if (netif_queue_stopped (dev))
1423                        netif_wake_queue (dev);
1424
1425                cur_tx = atomic_read (&tp->cur_tx);
1426                tx_left = cur_tx - dirty_tx;
1427
1428        }
1429
1430#ifndef NETDRV_NDEBUG
1431        if (atomic_read (&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1432                printk (KERN_ERR
1433                  "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
1434                     dev->name, dirty_tx, atomic_read (&tp->cur_tx));
1435                dirty_tx += NUM_TX_DESC;
1436        }
1437#endif /* NETDRV_NDEBUG */
1438
1439        atomic_set (&tp->dirty_tx, dirty_tx);
1440}
1441
1442
1443/* TODO: clean this up!  Rx reset need not be this intensive */
1444static void netdrv_rx_err (u32 rx_status, struct net_device *dev,
1445                            struct netdrv_private *tp, void *ioaddr)
1446{
1447        u8 tmp8;
1448        int tmp_work = 1000;
1449
1450        DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1451                 dev->name, rx_status);
1452        if (rx_status & RxTooLong) {
1453                DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1454                         dev->name, rx_status);
1455                /* A.C.: The chip hangs here. */
1456        }
1457        dev->stats.rx_errors++;
1458        if (rx_status & (RxBadSymbol | RxBadAlign))
1459                dev->stats.rx_frame_errors++;
1460        if (rx_status & (RxRunt | RxTooLong))
1461                dev->stats.rx_length_errors++;
1462        if (rx_status & RxCRCErr)
1463                dev->stats.rx_crc_errors++;
1464        /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1465        tp->cur_rx = 0;
1466
1467        /* disable receive */
1468        tmp8 = NETDRV_R8 (ChipCmd) & ChipCmdClear;
1469        NETDRV_W8_F (ChipCmd, tmp8 | CmdTxEnb);
1470
1471        /* A.C.: Reset the multicast list. */
1472        netdrv_set_rx_mode (dev);
1473
1474        /* XXX potentially temporary hack to
1475         * restart hung receiver */
1476        while (--tmp_work > 0) {
1477                tmp8 = NETDRV_R8 (ChipCmd);
1478                if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1479                        break;
1480                NETDRV_W8_F (ChipCmd,
1481                          (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1482        }
1483
1484        /* G.S.: Re-enable receiver */
1485        /* XXX temporary hack to work around receiver hang */
1486        netdrv_set_rx_mode (dev);
1487
1488        if (tmp_work <= 0)
1489                printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1490}
1491
1492
1493/* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1494   field alignments and semantics. */
1495static void netdrv_rx_interrupt (struct net_device *dev,
1496                                  struct netdrv_private *tp, void *ioaddr)
1497{
1498        unsigned char *rx_ring;
1499        u16 cur_rx;
1500
1501        assert (dev != NULL);
1502        assert (tp != NULL);
1503        assert (ioaddr != NULL);
1504
1505        rx_ring = tp->rx_ring;
1506        cur_rx = tp->cur_rx;
1507
1508        DPRINTK ("%s: In netdrv_rx(), current %4.4x BufAddr %4.4x,"
1509                 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1510                 NETDRV_R16 (RxBufAddr),
1511                 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1512
1513        while ((NETDRV_R8 (ChipCmd) & RxBufEmpty) == 0) {
1514                int ring_offset = cur_rx % RX_BUF_LEN;
1515                u32 rx_status;
1516                unsigned int rx_size;
1517                unsigned int pkt_size;
1518                struct sk_buff *skb;
1519
1520                /* read size+status of next frame from DMA ring buffer */
1521                rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1522                rx_size = rx_status >> 16;
1523                pkt_size = rx_size - 4;
1524
1525                DPRINTK ("%s:  netdrv_rx() status %4.4x, size %4.4x,"
1526                         " cur %4.4x.\n", dev->name, rx_status,
1527                         rx_size, cur_rx);
1528#if defined(NETDRV_DEBUG) && (NETDRV_DEBUG > 2)
1529                {
1530                        int i;
1531                        DPRINTK ("%s: Frame contents ", dev->name);
1532                        for (i = 0; i < 70; i++)
1533                                printk (" %2.2x",
1534                                        rx_ring[ring_offset + i]);
1535                        printk (".\n");
1536                }
1537#endif
1538
1539                /* If Rx err or invalid rx_size/rx_status received
1540                 * (which happens if we get lost in the ring),
1541                 * Rx process gets reset, so we abort any further
1542                 * Rx processing.
1543                 */
1544                if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1545                    (!(rx_status & RxStatusOK))) {
1546                        netdrv_rx_err (rx_status, dev, tp, ioaddr);
1547                        return;
1548                }
1549
1550                /* Malloc up new buffer, compatible with net-2e. */
1551                /* Omit the four octet CRC from the length. */
1552
1553                /* TODO: consider allocating skb's outside of
1554                 * interrupt context, both to speed interrupt processing,
1555                 * and also to reduce the chances of having to
1556                 * drop packets here under memory pressure.
1557                 */
1558
1559                skb = dev_alloc_skb (pkt_size + 2);
1560                if (skb) {
1561                        skb_reserve (skb, 2);   /* 16 byte align the IP fields. */
1562
1563                        skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
1564                        skb_put (skb, pkt_size);
1565
1566                        skb->protocol = eth_type_trans (skb, dev);
1567                        netif_rx (skb);
1568                        dev->stats.rx_bytes += pkt_size;
1569                        dev->stats.rx_packets++;
1570                } else {
1571                        printk (KERN_WARNING
1572                                "%s: Memory squeeze, dropping packet.\n",
1573                                dev->name);
1574                        dev->stats.rx_dropped++;
1575                }
1576
1577                cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1578                NETDRV_W16_F (RxBufPtr, cur_rx - 16);
1579        }
1580
1581        DPRINTK ("%s: Done netdrv_rx(), current %4.4x BufAddr %4.4x,"
1582                 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1583                 NETDRV_R16 (RxBufAddr),
1584                 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1585
1586        tp->cur_rx = cur_rx;
1587}
1588
1589
1590static void netdrv_weird_interrupt (struct net_device *dev,
1591                                     struct netdrv_private *tp,
1592                                     void *ioaddr,
1593                                     int status, int link_changed)
1594{
1595        printk (KERN_DEBUG "%s: Abnormal interrupt, status %8.8x.\n",
1596                dev->name, status);
1597
1598        assert (dev != NULL);
1599        assert (tp != NULL);
1600        assert (ioaddr != NULL);
1601
1602        /* Update the error count. */
1603        dev->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1604        NETDRV_W32 (RxMissed, 0);
1605
1606        if ((status & RxUnderrun) && link_changed &&
1607            (tp->drv_flags & HAS_LNK_CHNG)) {
1608                /* Really link-change on new chips. */
1609                int lpar = NETDRV_R16 (NWayLPAR);
1610                int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
1611                                || tp->duplex_lock;
1612                if (tp->full_duplex != duplex) {
1613                        tp->full_duplex = duplex;
1614                        NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1615                        NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1616                        NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1617                }
1618                status &= ~RxUnderrun;
1619        }
1620
1621        /* XXX along with netdrv_rx_err, are we double-counting errors? */
1622        if (status &
1623            (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1624                dev->stats.rx_errors++;
1625
1626        if (status & (PCSTimeout))
1627                dev->stats.rx_length_errors++;
1628        if (status & (RxUnderrun | RxFIFOOver))
1629                dev->stats.rx_fifo_errors++;
1630        if (status & RxOverflow) {
1631                dev->stats.rx_over_errors++;
1632                tp->cur_rx = NETDRV_R16 (RxBufAddr) % RX_BUF_LEN;
1633                NETDRV_W16_F (RxBufPtr, tp->cur_rx - 16);
1634        }
1635        if (status & PCIErr) {
1636                u16 pci_cmd_status;
1637                pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1638
1639                printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
1640                        dev->name, pci_cmd_status);
1641        }
1642}
1643
1644
1645/* The interrupt handler does all of the Rx thread work and cleans up
1646   after the Tx thread. */
1647static irqreturn_t netdrv_interrupt (int irq, void *dev_instance)
1648{
1649        struct net_device *dev = (struct net_device *) dev_instance;
1650        struct netdrv_private *tp = netdev_priv(dev);
1651        int boguscnt = max_interrupt_work;
1652        void *ioaddr = tp->mmio_addr;
1653        int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1654        int handled = 0;
1655
1656        spin_lock (&tp->lock);
1657
1658        do {
1659                status = NETDRV_R16 (IntrStatus);
1660
1661                /* h/w no longer present (hotplug?) or major error, bail */
1662                if (status == 0xFFFF)
1663                        break;
1664
1665                handled = 1;
1666                /* Acknowledge all of the current interrupt sources ASAP */
1667                NETDRV_W16_F (IntrStatus, status);
1668
1669                DPRINTK ("%s: interrupt  status=%#4.4x new intstat=%#4.4x.\n",
1670                                dev->name, status,
1671                                NETDRV_R16 (IntrStatus));
1672
1673                if ((status &
1674                     (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1675                      RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1676                        break;
1677
1678                /* Check uncommon events with one test. */
1679                if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1680                              RxFIFOOver | TxErr | RxErr))
1681                        netdrv_weird_interrupt (dev, tp, ioaddr,
1682                                                 status, link_changed);
1683
1684                if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver))     /* Rx interrupt */
1685                        netdrv_rx_interrupt (dev, tp, ioaddr);
1686
1687                if (status & (TxOK | TxErr))
1688                        netdrv_tx_interrupt (dev, tp, ioaddr);
1689
1690                boguscnt--;
1691        } while (boguscnt > 0);
1692
1693        if (boguscnt <= 0) {
1694                printk (KERN_WARNING
1695                        "%s: Too much work at interrupt, "
1696                        "IntrStatus=0x%4.4x.\n", dev->name,
1697                        status);
1698
1699                /* Clear all interrupt sources. */
1700                NETDRV_W16 (IntrStatus, 0xffff);
1701        }
1702
1703        spin_unlock (&tp->lock);
1704
1705        DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
1706                 dev->name, NETDRV_R16 (IntrStatus));
1707        return IRQ_RETVAL(handled);
1708}
1709
1710
1711static int netdrv_close (struct net_device *dev)
1712{
1713        struct netdrv_private *tp = netdev_priv(dev);
1714        void *ioaddr = tp->mmio_addr;
1715        unsigned long flags;
1716
1717        DPRINTK ("ENTER\n");
1718
1719        netif_stop_queue (dev);
1720
1721        DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
1722                        dev->name, NETDRV_R16 (IntrStatus));
1723
1724        del_timer_sync (&tp->timer);
1725
1726        spin_lock_irqsave (&tp->lock, flags);
1727
1728        /* Stop the chip's Tx and Rx DMA processes. */
1729        NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1730
1731        /* Disable interrupts by clearing the interrupt mask. */
1732        NETDRV_W16 (IntrMask, 0x0000);
1733
1734        /* Update the error counts. */
1735        dev->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1736        NETDRV_W32 (RxMissed, 0);
1737
1738        spin_unlock_irqrestore (&tp->lock, flags);
1739
1740        free_irq (dev->irq, dev);
1741
1742        netdrv_tx_clear (dev);
1743
1744        pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1745                            tp->rx_ring, tp->rx_ring_dma);
1746        pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1747                            tp->tx_bufs, tp->tx_bufs_dma);
1748        tp->rx_ring = NULL;
1749        tp->tx_bufs = NULL;
1750
1751        /* Green! Put the chip in low-power mode. */
1752        NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1753        NETDRV_W8 (Config1, 0x03);
1754        NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1755
1756        DPRINTK ("EXIT\n");
1757        return 0;
1758}
1759
1760
1761static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1762{
1763        struct netdrv_private *tp = netdev_priv(dev);
1764        struct mii_ioctl_data *data = if_mii(rq);
1765        unsigned long flags;
1766        int rc = 0;
1767
1768        DPRINTK ("ENTER\n");
1769
1770        switch (cmd) {
1771        case SIOCGMIIPHY:               /* Get address of MII PHY in use. */
1772                data->phy_id = tp->phys[0] & 0x3f;
1773                /* Fall Through */
1774
1775        case SIOCGMIIREG:               /* Read MII PHY register. */
1776                spin_lock_irqsave (&tp->lock, flags);
1777                data->val_out = mdio_read (dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1778                spin_unlock_irqrestore (&tp->lock, flags);
1779                break;
1780
1781        case SIOCSMIIREG:               /* Write MII PHY register. */
1782                if (!capable (CAP_NET_ADMIN)) {
1783                        rc = -EPERM;
1784                        break;
1785                }
1786
1787                spin_lock_irqsave (&tp->lock, flags);
1788                mdio_write (dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1789                spin_unlock_irqrestore (&tp->lock, flags);
1790                break;
1791
1792        default:
1793                rc = -EOPNOTSUPP;
1794                break;
1795        }
1796
1797        DPRINTK ("EXIT, returning %d\n", rc);
1798        return rc;
1799}
1800
1801/* Set or clear the multicast filter for this adaptor.
1802   This routine is not state sensitive and need not be SMP locked. */
1803
1804static void netdrv_set_rx_mode (struct net_device *dev)
1805{
1806        struct netdrv_private *tp = netdev_priv(dev);
1807        void *ioaddr = tp->mmio_addr;
1808        u32 mc_filter[2];       /* Multicast hash filter */
1809        int i, rx_mode;
1810        u32 tmp;
1811
1812        DPRINTK ("ENTER\n");
1813
1814        DPRINTK ("%s:   netdrv_set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1815                        dev->name, dev->flags, NETDRV_R32 (RxConfig));
1816
1817        /* Note: do not reorder, GCC is clever about common statements. */
1818        if (dev->flags & IFF_PROMISC) {
1819                rx_mode =
1820                    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1821                    AcceptAllPhys;
1822                mc_filter[1] = mc_filter[0] = 0xffffffff;
1823        } else if ((dev->mc_count > multicast_filter_limit)
1824                   || (dev->flags & IFF_ALLMULTI)) {
1825                /* Too many to filter perfectly -- accept all multicasts. */
1826                rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1827                mc_filter[1] = mc_filter[0] = 0xffffffff;
1828        } else {
1829                struct dev_mc_list *mclist;
1830                rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1831                mc_filter[1] = mc_filter[0] = 0;
1832                for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1833                     i++, mclist = mclist->next) {
1834                        int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1835
1836                        mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1837                }
1838        }
1839
1840        /* if called from irq handler, lock already acquired */
1841        if (!in_irq ())
1842                spin_lock_irq (&tp->lock);
1843
1844        /* We can safely update without stopping the chip. */
1845        tmp = netdrv_rx_config | rx_mode |
1846                (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1847        NETDRV_W32_F (RxConfig, tmp);
1848        NETDRV_W32_F (MAR0 + 0, mc_filter[0]);
1849        NETDRV_W32_F (MAR0 + 4, mc_filter[1]);
1850
1851        if (!in_irq ())
1852                spin_unlock_irq (&tp->lock);
1853
1854        DPRINTK ("EXIT\n");
1855}
1856
1857
1858#ifdef CONFIG_PM
1859
1860static int netdrv_suspend (struct pci_dev *pdev, pm_message_t state)
1861{
1862        struct net_device *dev = pci_get_drvdata (pdev);
1863        struct netdrv_private *tp = netdev_priv(dev);
1864        void *ioaddr = tp->mmio_addr;
1865        unsigned long flags;
1866
1867        if (!netif_running(dev))
1868                return 0;
1869        netif_device_detach (dev);
1870
1871        spin_lock_irqsave (&tp->lock, flags);
1872
1873        /* Disable interrupts, stop Tx and Rx. */
1874        NETDRV_W16 (IntrMask, 0x0000);
1875        NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1876
1877        /* Update the error counts. */
1878        dev->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1879        NETDRV_W32 (RxMissed, 0);
1880
1881        spin_unlock_irqrestore (&tp->lock, flags);
1882
1883        pci_save_state (pdev);
1884        pci_set_power_state (pdev, PCI_D3hot);
1885
1886        return 0;
1887}
1888
1889
1890static int netdrv_resume (struct pci_dev *pdev)
1891{
1892        struct net_device *dev = pci_get_drvdata (pdev);
1893        /*struct netdrv_private *tp = netdev_priv(dev);*/
1894
1895        if (!netif_running(dev))
1896                return 0;
1897        pci_set_power_state (pdev, PCI_D0);
1898        pci_restore_state (pdev);
1899        netif_device_attach (dev);
1900        netdrv_hw_start (dev);
1901
1902        return 0;
1903}
1904
1905#endif /* CONFIG_PM */
1906
1907
1908static struct pci_driver netdrv_pci_driver = {
1909        .name           = MODNAME,
1910        .id_table       = netdrv_pci_tbl,
1911        .probe          = netdrv_init_one,
1912        .remove         = __devexit_p(netdrv_remove_one),
1913#ifdef CONFIG_PM
1914        .suspend        = netdrv_suspend,
1915        .resume         = netdrv_resume,
1916#endif /* CONFIG_PM */
1917};
1918
1919
1920static int __init netdrv_init_module (void)
1921{
1922/* when a module, this is printed whether or not devices are found in probe */
1923#ifdef MODULE
1924        printk(version);
1925#endif
1926        return pci_register_driver(&netdrv_pci_driver);
1927}
1928
1929
1930static void __exit netdrv_cleanup_module (void)
1931{
1932        pci_unregister_driver (&netdrv_pci_driver);
1933}
1934
1935
1936module_init(netdrv_init_module);
1937module_exit(netdrv_cleanup_module);
1938
The original LXR software by the LXR community, this experimental version by lxr@linux.no.
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