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29#include <linux/init.h>
30#include <linux/spinlock.h>
31#include <linux/errno.h>
32#include <linux/list.h>
33#include <linux/clk.h>
34#include <linux/delay.h>
35#include <linux/io.h>
36#include <linux/module.h>
37#include <mach/hardware.h>
38#include <mach/dmtimer.h>
39#include <mach/irqs.h>
40
41
42#define _OMAP_TIMER_ID_OFFSET 0x00
43#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
44#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
45#define _OMAP_TIMER_STAT_OFFSET 0x18
46#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
47#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
48#define _OMAP_TIMER_CTRL_OFFSET 0x24
49#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
50#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
51#define OMAP_TIMER_CTRL_PT (1 << 12)
52#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
53#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
54#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
55#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
56#define OMAP_TIMER_CTRL_CE (1 << 6)
57#define OMAP_TIMER_CTRL_PRE (1 << 5)
58#define OMAP_TIMER_CTRL_PTV_SHIFT 2
59#define OMAP_TIMER_CTRL_POSTED (1 << 2)
60#define OMAP_TIMER_CTRL_AR (1 << 1)
61#define OMAP_TIMER_CTRL_ST (1 << 0)
62#define _OMAP_TIMER_COUNTER_OFFSET 0x28
63#define _OMAP_TIMER_LOAD_OFFSET 0x2c
64#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
65#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
66#define WP_NONE 0
67#define WP_TCLR (1 << 0)
68#define WP_TCRR (1 << 1)
69#define WP_TLDR (1 << 2)
70#define WP_TTGR (1 << 3)
71#define WP_TMAR (1 << 4)
72#define WP_TPIR (1 << 5)
73#define WP_TNIR (1 << 6)
74#define WP_TCVR (1 << 7)
75#define WP_TOCR (1 << 8)
76#define WP_TOWR (1 << 9)
77#define _OMAP_TIMER_MATCH_OFFSET 0x38
78#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
79#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
80#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44
81#define _OMAP_TIMER_TICK_POS_OFFSET 0x48
82#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c
83#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50
84#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54
85#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58
86
87
88#define WPSHIFT 16
89
90#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
91 | (WP_NONE << WPSHIFT))
92
93#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
94 | (WP_NONE << WPSHIFT))
95
96#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
97 | (WP_NONE << WPSHIFT))
98
99#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
100 | (WP_NONE << WPSHIFT))
101
102#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
103 | (WP_NONE << WPSHIFT))
104
105#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
106 | (WP_NONE << WPSHIFT))
107
108#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
109 | (WP_TCLR << WPSHIFT))
110
111#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
112 | (WP_TCRR << WPSHIFT))
113
114#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
115 | (WP_TLDR << WPSHIFT))
116
117#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
118 | (WP_TTGR << WPSHIFT))
119
120#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
121 | (WP_NONE << WPSHIFT))
122
123#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
124 | (WP_TMAR << WPSHIFT))
125
126#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
127 | (WP_NONE << WPSHIFT))
128
129#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
130 | (WP_NONE << WPSHIFT))
131
132#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
133 | (WP_NONE << WPSHIFT))
134
135#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
136 | (WP_TPIR << WPSHIFT))
137
138#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
139 | (WP_TNIR << WPSHIFT))
140
141#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
142 | (WP_TCVR << WPSHIFT))
143
144#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
145 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
146
147#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
148 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
149
150struct omap_dm_timer {
151 unsigned long phys_base;
152 int irq;
153#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
154 struct clk *iclk, *fclk;
155#endif
156 void __iomem *io_base;
157 unsigned reserved:1;
158 unsigned enabled:1;
159 unsigned posted:1;
160};
161
162#ifdef CONFIG_ARCH_OMAP1
163
164#define omap_dm_clk_enable(x)
165#define omap_dm_clk_disable(x)
166#define omap2_dm_timers NULL
167#define omap2_dm_source_names NULL
168#define omap2_dm_source_clocks NULL
169#define omap3_dm_timers NULL
170#define omap3_dm_source_names NULL
171#define omap3_dm_source_clocks NULL
172
173static struct omap_dm_timer omap1_dm_timers[] = {
174 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
175 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
176 { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
177 { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
178 { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
179 { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
180 { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 },
181 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
182};
183
184static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
185
186#elif defined(CONFIG_ARCH_OMAP2)
187
188#define omap_dm_clk_enable(x) clk_enable(x)
189#define omap_dm_clk_disable(x) clk_disable(x)
190#define omap1_dm_timers NULL
191#define omap3_dm_timers NULL
192#define omap3_dm_source_names NULL
193#define omap3_dm_source_clocks NULL
194
195static struct omap_dm_timer omap2_dm_timers[] = {
196 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
197 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
198 { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
199 { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
200 { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
201 { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
202 { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
203 { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
204 { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
205 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
206 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
207 { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
208};
209
210static const char *omap2_dm_source_names[] __initdata = {
211 "sys_ck",
212 "func_32k_ck",
213 "alt_ck",
214 NULL
215};
216
217static struct clk **omap2_dm_source_clocks[3];
218static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
219
220#elif defined(CONFIG_ARCH_OMAP3)
221
222#define omap_dm_clk_enable(x) clk_enable(x)
223#define omap_dm_clk_disable(x) clk_disable(x)
224#define omap1_dm_timers NULL
225#define omap2_dm_timers NULL
226#define omap2_dm_source_names NULL
227#define omap2_dm_source_clocks NULL
228
229static struct omap_dm_timer omap3_dm_timers[] = {
230 { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
231 { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
232 { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 },
233 { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 },
234 { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 },
235 { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 },
236 { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 },
237 { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 },
238 { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
239 { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
240 { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
241 { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ },
242};
243
244static const char *omap3_dm_source_names[] __initdata = {
245 "sys_ck",
246 "omap_32k_fck",
247 NULL
248};
249
250static struct clk **omap3_dm_source_clocks[2];
251static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
252
253#else
254
255#error OMAP architecture not supported!
256
257#endif
258
259static struct omap_dm_timer *dm_timers;
260static char **dm_source_names;
261static struct clk **dm_source_clocks;
262
263static spinlock_t dm_timer_lock;
264
265
266
267
268
269
270static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
271{
272 if (timer->posted)
273 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
274 & (reg >> WPSHIFT))
275 cpu_relax();
276 return readl(timer->io_base + (reg & 0xff));
277}
278
279
280
281
282
283
284
285static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
286 u32 value)
287{
288 if (timer->posted)
289 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
290 & (reg >> WPSHIFT))
291 cpu_relax();
292 writel(value, timer->io_base + (reg & 0xff));
293}
294
295static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
296{
297 int c;
298
299 c = 0;
300 while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
301 c++;
302 if (c > 100000) {
303 printk(KERN_ERR "Timer failed to reset\n");
304 return;
305 }
306 }
307}
308
309static void omap_dm_timer_reset(struct omap_dm_timer *timer)
310{
311 u32 l;
312
313 if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
314 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
315 omap_dm_timer_wait_for_reset(timer);
316 }
317 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
318
319 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
320 l |= 0x02 << 3;
321 l |= 0x2 << 8;
322
323
324
325
326 if (cpu_class_is_omap2())
327 l |= 1 << 2;
328 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
329
330
331 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
332 OMAP_TIMER_CTRL_POSTED);
333 timer->posted = 1;
334}
335
336static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
337{
338 omap_dm_timer_enable(timer);
339 omap_dm_timer_reset(timer);
340}
341
342struct omap_dm_timer *omap_dm_timer_request(void)
343{
344 struct omap_dm_timer *timer = NULL;
345 unsigned long flags;
346 int i;
347
348 spin_lock_irqsave(&dm_timer_lock, flags);
349 for (i = 0; i < dm_timer_count; i++) {
350 if (dm_timers[i].reserved)
351 continue;
352
353 timer = &dm_timers[i];
354 timer->reserved = 1;
355 break;
356 }
357 spin_unlock_irqrestore(&dm_timer_lock, flags);
358
359 if (timer != NULL)
360 omap_dm_timer_prepare(timer);
361
362 return timer;
363}
364EXPORT_SYMBOL_GPL(omap_dm_timer_request);
365
366struct omap_dm_timer *omap_dm_timer_request_specific(int id)
367{
368 struct omap_dm_timer *timer;
369 unsigned long flags;
370
371 spin_lock_irqsave(&dm_timer_lock, flags);
372 if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
373 spin_unlock_irqrestore(&dm_timer_lock, flags);
374 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
375 __FILE__, __LINE__, __func__, id);
376 dump_stack();
377 return NULL;
378 }
379
380 timer = &dm_timers[id-1];
381 timer->reserved = 1;
382 spin_unlock_irqrestore(&dm_timer_lock, flags);
383
384 omap_dm_timer_prepare(timer);
385
386 return timer;
387}
388EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
389
390void omap_dm_timer_free(struct omap_dm_timer *timer)
391{
392 omap_dm_timer_enable(timer);
393 omap_dm_timer_reset(timer);
394 omap_dm_timer_disable(timer);
395
396 WARN_ON(!timer->reserved);
397 timer->reserved = 0;
398}
399EXPORT_SYMBOL_GPL(omap_dm_timer_free);
400
401void omap_dm_timer_enable(struct omap_dm_timer *timer)
402{
403 if (timer->enabled)
404 return;
405
406 omap_dm_clk_enable(timer->fclk);
407 omap_dm_clk_enable(timer->iclk);
408
409 timer->enabled = 1;
410}
411EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
412
413void omap_dm_timer_disable(struct omap_dm_timer *timer)
414{
415 if (!timer->enabled)
416 return;
417
418 omap_dm_clk_disable(timer->iclk);
419 omap_dm_clk_disable(timer->fclk);
420
421 timer->enabled = 0;
422}
423EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
424
425int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
426{
427 return timer->irq;
428}
429EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
430
431#if defined(CONFIG_ARCH_OMAP1)
432
433
434
435
436
437__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
438{
439 int i;
440
441
442 if (!(inputmask & (1 << 1)))
443 return inputmask;
444
445
446 for (i = 0; i < dm_timer_count; i++) {
447 u32 l;
448
449 l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
450 if (l & OMAP_TIMER_CTRL_ST) {
451 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
452 inputmask &= ~(1 << 1);
453 else
454 inputmask &= ~(1 << 2);
455 }
456 }
457
458 return inputmask;
459}
460EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
461
462#elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3)
463
464struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
465{
466 return timer->fclk;
467}
468EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
469
470__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
471{
472 BUG();
473
474 return 0;
475}
476EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
477
478#endif
479
480void omap_dm_timer_trigger(struct omap_dm_timer *timer)
481{
482 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
483}
484EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
485
486void omap_dm_timer_start(struct omap_dm_timer *timer)
487{
488 u32 l;
489
490 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
491 if (!(l & OMAP_TIMER_CTRL_ST)) {
492 l |= OMAP_TIMER_CTRL_ST;
493 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
494 }
495}
496EXPORT_SYMBOL_GPL(omap_dm_timer_start);
497
498void omap_dm_timer_stop(struct omap_dm_timer *timer)
499{
500 u32 l;
501
502 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
503 if (l & OMAP_TIMER_CTRL_ST) {
504 l &= ~0x1;
505 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
506 }
507}
508EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
509
510#ifdef CONFIG_ARCH_OMAP1
511
512int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
513{
514 int n = (timer - dm_timers) << 1;
515 u32 l;
516
517 l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
518 l |= source << n;
519 omap_writel(l, MOD_CONF_CTRL_1);
520
521 return 0;
522}
523EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
524
525#else
526
527int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
528{
529 int ret = -EINVAL;
530
531 if (source < 0 || source >= 3)
532 return -EINVAL;
533
534 clk_disable(timer->fclk);
535 ret = clk_set_parent(timer->fclk, dm_source_clocks[source]);
536 clk_enable(timer->fclk);
537
538
539
540
541
542 __delay(150000);
543
544 return ret;
545}
546EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
547
548#endif
549
550void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
551 unsigned int load)
552{
553 u32 l;
554
555 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
556 if (autoreload)
557 l |= OMAP_TIMER_CTRL_AR;
558 else
559 l &= ~OMAP_TIMER_CTRL_AR;
560 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
561 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
562
563 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
564}
565EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
566
567
568void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
569 unsigned int load)
570{
571 u32 l;
572
573 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
574 if (autoreload) {
575 l |= OMAP_TIMER_CTRL_AR;
576 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
577 } else {
578 l &= ~OMAP_TIMER_CTRL_AR;
579 }
580 l |= OMAP_TIMER_CTRL_ST;
581
582 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
583 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
584}
585EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
586
587void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
588 unsigned int match)
589{
590 u32 l;
591
592 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
593 if (enable)
594 l |= OMAP_TIMER_CTRL_CE;
595 else
596 l &= ~OMAP_TIMER_CTRL_CE;
597 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
598 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
599}
600EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
601
602void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
603 int toggle, int trigger)
604{
605 u32 l;
606
607 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
608 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
609 OMAP_TIMER_CTRL_PT | (0x03 << 10));
610 if (def_on)
611 l |= OMAP_TIMER_CTRL_SCPWM;
612 if (toggle)
613 l |= OMAP_TIMER_CTRL_PT;
614 l |= trigger << 10;
615 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
616}
617EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
618
619void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
620{
621 u32 l;
622
623 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
624 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
625 if (prescaler >= 0x00 && prescaler <= 0x07) {
626 l |= OMAP_TIMER_CTRL_PRE;
627 l |= prescaler << 2;
628 }
629 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
630}
631EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
632
633void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
634 unsigned int value)
635{
636 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
637 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
638}
639EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
640
641unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
642{
643 unsigned int l;
644
645 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
646
647 return l;
648}
649EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
650
651void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
652{
653 omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
654}
655EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
656
657unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
658{
659 unsigned int l;
660
661 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
662
663 return l;
664}
665EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
666
667void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
668{
669 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
670}
671EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
672
673int omap_dm_timers_active(void)
674{
675 int i;
676
677 for (i = 0; i < dm_timer_count; i++) {
678 struct omap_dm_timer *timer;
679
680 timer = &dm_timers[i];
681
682 if (!timer->enabled)
683 continue;
684
685 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
686 OMAP_TIMER_CTRL_ST) {
687 return 1;
688 }
689 }
690 return 0;
691}
692EXPORT_SYMBOL_GPL(omap_dm_timers_active);
693
694int __init omap_dm_timer_init(void)
695{
696 struct omap_dm_timer *timer;
697 int i;
698
699 if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
700 return -ENODEV;
701
702 spin_lock_init(&dm_timer_lock);
703
704 if (cpu_class_is_omap1())
705 dm_timers = omap1_dm_timers;
706 else if (cpu_is_omap24xx()) {
707 dm_timers = omap2_dm_timers;
708 dm_source_names = (char **)omap2_dm_source_names;
709 dm_source_clocks = (struct clk **)omap2_dm_source_clocks;
710 } else if (cpu_is_omap34xx()) {
711 dm_timers = omap3_dm_timers;
712 dm_source_names = (char **)omap3_dm_source_names;
713 dm_source_clocks = (struct clk **)omap3_dm_source_clocks;
714 }
715
716 if (cpu_class_is_omap2())
717 for (i = 0; dm_source_names[i] != NULL; i++)
718 dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
719
720 if (cpu_is_omap243x())
721 dm_timers[0].phys_base = 0x49018000;
722
723 for (i = 0; i < dm_timer_count; i++) {
724 timer = &dm_timers[i];
725 timer->io_base = IO_ADDRESS(timer->phys_base);
726#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
727 if (cpu_class_is_omap2()) {
728 char clk_name[16];
729 sprintf(clk_name, "gpt%d_ick", i + 1);
730 timer->iclk = clk_get(NULL, clk_name);
731 sprintf(clk_name, "gpt%d_fck", i + 1);
732 timer->fclk = clk_get(NULL, clk_name);
733 }
734#endif
735 }
736
737 return 0;
738}
739
