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10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/interrupt.h>
13#include <linux/input.h>
14#include <linux/mtd/physmap.h>
15#include <linux/mtd/nand.h>
16#include <linux/i2c.h>
17#include <linux/smc91x.h>
18#include <linux/delay.h>
19#include <linux/clk.h>
20#include <linux/gpio.h>
21#include <linux/spi/spi.h>
22#include <linux/spi/spi_gpio.h>
23#include <video/sh_mobile_lcdc.h>
24#include <media/sh_mobile_ceu.h>
25#include <media/ov772x.h>
26#include <media/tw9910.h>
27#include <asm/clock.h>
28#include <asm/machvec.h>
29#include <asm/io.h>
30#include <asm/sh_keysc.h>
31#include <mach/migor.h>
32#include <cpu/sh7722.h>
33
34
35
36
37
38
39
40
41
42static struct smc91x_platdata smc91x_info = {
43 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
44};
45
46static struct resource smc91x_eth_resources[] = {
47 [0] = {
48 .name = "SMC91C111" ,
49 .start = 0x10000300,
50 .end = 0x1000030f,
51 .flags = IORESOURCE_MEM,
52 },
53 [1] = {
54 .start = 32,
55 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
56 },
57};
58
59static struct platform_device smc91x_eth_device = {
60 .name = "smc91x",
61 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
62 .resource = smc91x_eth_resources,
63 .dev = {
64 .platform_data = &smc91x_info,
65 },
66};
67
68static struct sh_keysc_info sh_keysc_info = {
69 .mode = SH_KEYSC_MODE_2,
70 .scan_timing = 3,
71 .delay = 5,
72 .keycodes = {
73 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
74 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
75 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
76 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
77 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
78 },
79};
80
81static struct resource sh_keysc_resources[] = {
82 [0] = {
83 .start = 0x044b0000,
84 .end = 0x044b000f,
85 .flags = IORESOURCE_MEM,
86 },
87 [1] = {
88 .start = 79,
89 .flags = IORESOURCE_IRQ,
90 },
91};
92
93static struct platform_device sh_keysc_device = {
94 .name = "sh_keysc",
95 .id = 0,
96 .num_resources = ARRAY_SIZE(sh_keysc_resources),
97 .resource = sh_keysc_resources,
98 .dev = {
99 .platform_data = &sh_keysc_info,
100 },
101};
102
103static struct mtd_partition migor_nor_flash_partitions[] =
104{
105 {
106 .name = "uboot",
107 .offset = 0,
108 .size = (1 * 1024 * 1024),
109 .mask_flags = MTD_WRITEABLE,
110 },
111 {
112 .name = "rootfs",
113 .offset = MTDPART_OFS_APPEND,
114 .size = (15 * 1024 * 1024),
115 },
116 {
117 .name = "other",
118 .offset = MTDPART_OFS_APPEND,
119 .size = MTDPART_SIZ_FULL,
120 },
121};
122
123static struct physmap_flash_data migor_nor_flash_data = {
124 .width = 2,
125 .parts = migor_nor_flash_partitions,
126 .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
127};
128
129static struct resource migor_nor_flash_resources[] = {
130 [0] = {
131 .name = "NOR Flash",
132 .start = 0x00000000,
133 .end = 0x03ffffff,
134 .flags = IORESOURCE_MEM,
135 }
136};
137
138static struct platform_device migor_nor_flash_device = {
139 .name = "physmap-flash",
140 .resource = migor_nor_flash_resources,
141 .num_resources = ARRAY_SIZE(migor_nor_flash_resources),
142 .dev = {
143 .platform_data = &migor_nor_flash_data,
144 },
145};
146
147static struct mtd_partition migor_nand_flash_partitions[] = {
148 {
149 .name = "nanddata1",
150 .offset = 0x0,
151 .size = 512 * 1024 * 1024,
152 },
153 {
154 .name = "nanddata2",
155 .offset = MTDPART_OFS_APPEND,
156 .size = 512 * 1024 * 1024,
157 },
158};
159
160static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
161 unsigned int ctrl)
162{
163 struct nand_chip *chip = mtd->priv;
164
165 if (cmd == NAND_CMD_NONE)
166 return;
167
168 if (ctrl & NAND_CLE)
169 writeb(cmd, chip->IO_ADDR_W + 0x00400000);
170 else if (ctrl & NAND_ALE)
171 writeb(cmd, chip->IO_ADDR_W + 0x00800000);
172 else
173 writeb(cmd, chip->IO_ADDR_W);
174}
175
176static int migor_nand_flash_ready(struct mtd_info *mtd)
177{
178 return gpio_get_value(GPIO_PTA1);
179}
180
181struct platform_nand_data migor_nand_flash_data = {
182 .chip = {
183 .nr_chips = 1,
184 .partitions = migor_nand_flash_partitions,
185 .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
186 .chip_delay = 20,
187 .part_probe_types = (const char *[]) { "cmdlinepart", NULL },
188 },
189 .ctrl = {
190 .dev_ready = migor_nand_flash_ready,
191 .cmd_ctrl = migor_nand_flash_cmd_ctl,
192 },
193};
194
195static struct resource migor_nand_flash_resources[] = {
196 [0] = {
197 .name = "NAND Flash",
198 .start = 0x18000000,
199 .end = 0x18ffffff,
200 .flags = IORESOURCE_MEM,
201 },
202};
203
204static struct platform_device migor_nand_flash_device = {
205 .name = "gen_nand",
206 .resource = migor_nand_flash_resources,
207 .num_resources = ARRAY_SIZE(migor_nand_flash_resources),
208 .dev = {
209 .platform_data = &migor_nand_flash_data,
210 }
211};
212
213static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
214#ifdef CONFIG_SH_MIGOR_RTA_WVGA
215 .clock_source = LCDC_CLK_BUS,
216 .ch[0] = {
217 .chan = LCDC_CHAN_MAINLCD,
218 .bpp = 16,
219 .interface_type = RGB16,
220 .clock_divider = 2,
221 .lcd_cfg = {
222 .name = "LB070WV1",
223 .xres = 800,
224 .yres = 480,
225 .left_margin = 64,
226 .right_margin = 16,
227 .hsync_len = 120,
228 .upper_margin = 1,
229 .lower_margin = 17,
230 .vsync_len = 2,
231 .sync = 0,
232 },
233 .lcd_size_cfg = {
234 .width = 152,
235 .height = 91,
236 },
237 }
238#endif
239#ifdef CONFIG_SH_MIGOR_QVGA
240 .clock_source = LCDC_CLK_PERIPHERAL,
241 .ch[0] = {
242 .chan = LCDC_CHAN_MAINLCD,
243 .bpp = 16,
244 .interface_type = SYS16A,
245 .clock_divider = 10,
246 .lcd_cfg = {
247 .name = "PH240320T",
248 .xres = 320,
249 .yres = 240,
250 .left_margin = 0,
251 .right_margin = 16,
252 .hsync_len = 8,
253 .upper_margin = 1,
254 .lower_margin = 17,
255 .vsync_len = 2,
256 .sync = FB_SYNC_HOR_HIGH_ACT,
257 },
258 .lcd_size_cfg = {
259 .width = 49,
260 .height = 37,
261 },
262 .board_cfg = {
263 .setup_sys = migor_lcd_qvga_setup,
264 },
265 .sys_bus_cfg = {
266 .ldmt2r = 0x06000a09,
267 .ldmt3r = 0x180e3418,
268
269 .deferred_io_msec = 1000,
270 },
271 }
272#endif
273};
274
275static struct resource migor_lcdc_resources[] = {
276 [0] = {
277 .name = "LCDC",
278 .start = 0xfe940000,
279 .end = 0xfe941fff,
280 .flags = IORESOURCE_MEM,
281 },
282 [1] = {
283 .start = 28,
284 .flags = IORESOURCE_IRQ,
285 },
286};
287
288static struct platform_device migor_lcdc_device = {
289 .name = "sh_mobile_lcdc_fb",
290 .num_resources = ARRAY_SIZE(migor_lcdc_resources),
291 .resource = migor_lcdc_resources,
292 .dev = {
293 .platform_data = &sh_mobile_lcdc_info,
294 },
295};
296
297static struct clk *camera_clk;
298static DEFINE_MUTEX(camera_lock);
299
300static void camera_power_on(int is_tw)
301{
302 mutex_lock(&camera_lock);
303
304
305
306
307 camera_clk = clk_get(NULL, "video_clk");
308 clk_set_rate(camera_clk, 10000000);
309 clk_enable(camera_clk);
310
311
312 mdelay(10);
313 if (is_tw) {
314 gpio_set_value(GPIO_PTT2, 0);
315 gpio_set_value(GPIO_PTT0, 0);
316 } else {
317 gpio_set_value(GPIO_PTT0, 1);
318 }
319 gpio_set_value(GPIO_PTT3, 0);
320 mdelay(10);
321 gpio_set_value(GPIO_PTT3, 1);
322 mdelay(10);
323}
324
325static void camera_power_off(void)
326{
327 clk_disable(camera_clk);
328 clk_put(camera_clk);
329
330 gpio_set_value(GPIO_PTT3, 0);
331 mutex_unlock(&camera_lock);
332}
333
334static int ov7725_power(struct device *dev, int mode)
335{
336 if (mode)
337 camera_power_on(0);
338 else
339 camera_power_off();
340
341 return 0;
342}
343
344static int tw9910_power(struct device *dev, int mode)
345{
346 if (mode)
347 camera_power_on(1);
348 else
349 camera_power_off();
350
351 return 0;
352}
353
354static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
355 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
356};
357
358static struct resource migor_ceu_resources[] = {
359 [0] = {
360 .name = "CEU",
361 .start = 0xfe910000,
362 .end = 0xfe91009f,
363 .flags = IORESOURCE_MEM,
364 },
365 [1] = {
366 .start = 52,
367 .flags = IORESOURCE_IRQ,
368 },
369 [2] = {
370
371 },
372};
373
374static struct platform_device migor_ceu_device = {
375 .name = "sh_mobile_ceu",
376 .id = 0,
377 .num_resources = ARRAY_SIZE(migor_ceu_resources),
378 .resource = migor_ceu_resources,
379 .dev = {
380 .platform_data = &sh_mobile_ceu_info,
381 },
382};
383
384static struct ov772x_camera_info ov7725_info = {
385 .buswidth = SOCAM_DATAWIDTH_8,
386 .link = {
387 .power = ov7725_power,
388 },
389};
390
391static struct tw9910_video_info tw9910_info = {
392 .buswidth = SOCAM_DATAWIDTH_8,
393 .mpout = TW9910_MPO_FIELD,
394 .link = {
395 .power = tw9910_power,
396 }
397};
398
399struct spi_gpio_platform_data sdcard_cn9_platform_data = {
400 .sck = GPIO_PTD0,
401 .mosi = GPIO_PTD1,
402 .miso = GPIO_PTD2,
403 .num_chipselect = 1,
404};
405
406static struct platform_device sdcard_cn9_device = {
407 .name = "spi_gpio",
408 .dev = {
409 .platform_data = &sdcard_cn9_platform_data,
410 },
411};
412
413static struct platform_device *migor_devices[] __initdata = {
414 &smc91x_eth_device,
415 &sh_keysc_device,
416 &migor_lcdc_device,
417 &migor_ceu_device,
418 &migor_nor_flash_device,
419 &migor_nand_flash_device,
420 &sdcard_cn9_device,
421};
422
423static struct i2c_board_info migor_i2c_devices[] = {
424 {
425 I2C_BOARD_INFO("rs5c372b", 0x32),
426 },
427 {
428 I2C_BOARD_INFO("migor_ts", 0x51),
429 .irq = 38,
430 },
431 {
432 I2C_BOARD_INFO("ov772x", 0x21),
433 .platform_data = &ov7725_info,
434 },
435 {
436 I2C_BOARD_INFO("tw9910", 0x45),
437 .platform_data = &tw9910_info,
438 },
439};
440
441static struct spi_board_info migor_spi_devices[] = {
442 {
443 .modalias = "mmc_spi",
444 .max_speed_hz = 5000000,
445 .chip_select = 0,
446 .controller_data = (void *) GPIO_PTD5,
447 },
448};
449
450static int __init migor_devices_setup(void)
451{
452
453#ifdef CONFIG_PM
454
455 gpio_request(GPIO_FN_STATUS0, NULL);
456
457
458 gpio_request(GPIO_FN_PDSTATUS, NULL);
459#else
460
461 gpio_request(GPIO_PTJ7, NULL);
462 gpio_direction_output(GPIO_PTJ7, 1);
463 gpio_export(GPIO_PTJ7, 0);
464
465
466 gpio_request(GPIO_PTJ5, NULL);
467 gpio_direction_output(GPIO_PTJ5, 1);
468 gpio_export(GPIO_PTJ5, 0);
469#endif
470
471
472 gpio_request(GPIO_FN_IRQ0, NULL);
473 ctrl_outl(0x00003400, BSC_CS4BCR);
474 ctrl_outl(0x00110080, BSC_CS4WCR);
475
476
477 gpio_request(GPIO_FN_KEYOUT0, NULL);
478 gpio_request(GPIO_FN_KEYOUT1, NULL);
479 gpio_request(GPIO_FN_KEYOUT2, NULL);
480 gpio_request(GPIO_FN_KEYOUT3, NULL);
481 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
482 gpio_request(GPIO_FN_KEYIN1, NULL);
483 gpio_request(GPIO_FN_KEYIN2, NULL);
484 gpio_request(GPIO_FN_KEYIN3, NULL);
485 gpio_request(GPIO_FN_KEYIN4, NULL);
486 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
487
488
489 gpio_request(GPIO_FN_CS6A_CE2B, NULL);
490 ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
491 gpio_request(GPIO_PTA1, NULL);
492 gpio_direction_input(GPIO_PTA1);
493
494
495 gpio_request(GPIO_FN_IRQ6, NULL);
496
497
498#ifdef CONFIG_SH_MIGOR_QVGA
499 gpio_request(GPIO_FN_LCDD17, NULL);
500 gpio_request(GPIO_FN_LCDD16, NULL);
501 gpio_request(GPIO_FN_LCDD15, NULL);
502 gpio_request(GPIO_FN_LCDD14, NULL);
503 gpio_request(GPIO_FN_LCDD13, NULL);
504 gpio_request(GPIO_FN_LCDD12, NULL);
505 gpio_request(GPIO_FN_LCDD11, NULL);
506 gpio_request(GPIO_FN_LCDD10, NULL);
507 gpio_request(GPIO_FN_LCDD8, NULL);
508 gpio_request(GPIO_FN_LCDD7, NULL);
509 gpio_request(GPIO_FN_LCDD6, NULL);
510 gpio_request(GPIO_FN_LCDD5, NULL);
511 gpio_request(GPIO_FN_LCDD4, NULL);
512 gpio_request(GPIO_FN_LCDD3, NULL);
513 gpio_request(GPIO_FN_LCDD2, NULL);
514 gpio_request(GPIO_FN_LCDD1, NULL);
515 gpio_request(GPIO_FN_LCDRS, NULL);
516 gpio_request(GPIO_FN_LCDCS, NULL);
517 gpio_request(GPIO_FN_LCDRD, NULL);
518 gpio_request(GPIO_FN_LCDWR, NULL);
519 gpio_request(GPIO_PTH2, NULL);
520 gpio_direction_output(GPIO_PTH2, 1);
521#endif
522#ifdef CONFIG_SH_MIGOR_RTA_WVGA
523 gpio_request(GPIO_FN_LCDD15, NULL);
524 gpio_request(GPIO_FN_LCDD14, NULL);
525 gpio_request(GPIO_FN_LCDD13, NULL);
526 gpio_request(GPIO_FN_LCDD12, NULL);
527 gpio_request(GPIO_FN_LCDD11, NULL);
528 gpio_request(GPIO_FN_LCDD10, NULL);
529 gpio_request(GPIO_FN_LCDD9, NULL);
530 gpio_request(GPIO_FN_LCDD8, NULL);
531 gpio_request(GPIO_FN_LCDD7, NULL);
532 gpio_request(GPIO_FN_LCDD6, NULL);
533 gpio_request(GPIO_FN_LCDD5, NULL);
534 gpio_request(GPIO_FN_LCDD4, NULL);
535 gpio_request(GPIO_FN_LCDD3, NULL);
536 gpio_request(GPIO_FN_LCDD2, NULL);
537 gpio_request(GPIO_FN_LCDD1, NULL);
538 gpio_request(GPIO_FN_LCDD0, NULL);
539 gpio_request(GPIO_FN_LCDLCLK, NULL);
540 gpio_request(GPIO_FN_LCDDCK, NULL);
541 gpio_request(GPIO_FN_LCDVEPWC, NULL);
542 gpio_request(GPIO_FN_LCDVCPWC, NULL);
543 gpio_request(GPIO_FN_LCDVSYN, NULL);
544 gpio_request(GPIO_FN_LCDHSYN, NULL);
545 gpio_request(GPIO_FN_LCDDISP, NULL);
546 gpio_request(GPIO_FN_LCDDON, NULL);
547#endif
548
549
550 gpio_request(GPIO_FN_VIO_CLK2, NULL);
551 gpio_request(GPIO_FN_VIO_VD2, NULL);
552 gpio_request(GPIO_FN_VIO_HD2, NULL);
553 gpio_request(GPIO_FN_VIO_FLD, NULL);
554 gpio_request(GPIO_FN_VIO_CKO, NULL);
555 gpio_request(GPIO_FN_VIO_D15, NULL);
556 gpio_request(GPIO_FN_VIO_D14, NULL);
557 gpio_request(GPIO_FN_VIO_D13, NULL);
558 gpio_request(GPIO_FN_VIO_D12, NULL);
559 gpio_request(GPIO_FN_VIO_D11, NULL);
560 gpio_request(GPIO_FN_VIO_D10, NULL);
561 gpio_request(GPIO_FN_VIO_D9, NULL);
562 gpio_request(GPIO_FN_VIO_D8, NULL);
563
564 gpio_request(GPIO_PTT3, NULL);
565 gpio_direction_output(GPIO_PTT3, 0);
566 gpio_request(GPIO_PTT2, NULL);
567 gpio_direction_output(GPIO_PTT2, 1);
568 gpio_request(GPIO_PTT0, NULL);
569#ifdef CONFIG_SH_MIGOR_RTA_WVGA
570 gpio_direction_output(GPIO_PTT0, 0);
571#else
572 gpio_direction_output(GPIO_PTT0, 1);
573#endif
574 ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB);
575
576 platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
577
578 i2c_register_board_info(0, migor_i2c_devices,
579 ARRAY_SIZE(migor_i2c_devices));
580
581 spi_register_board_info(migor_spi_devices,
582 ARRAY_SIZE(migor_spi_devices));
583
584 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
585}
586__initcall(migor_devices_setup);
587
