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13#include <linux/module.h>
14#include <linux/moduleparam.h>
15
16#include <linux/kernel.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/vmalloc.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/dma-mapping.h>
29#include <linux/bitops.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <linux/delay.h>
33#include <asm/byteorder.h>
34#include <asm/page.h>
35#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
38#include <linux/if_vlan.h>
39#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
40#define BCM_VLAN 1
41#endif
42#include <net/ip.h>
43#include <net/tcp.h>
44#include <net/checksum.h>
45#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
48#include <linux/cache.h>
49#include <linux/firmware.h>
50#include <linux/log2.h>
51
52#include "bnx2.h"
53#include "bnx2_fw.h"
54
55#define DRV_MODULE_NAME "bnx2"
56#define PFX DRV_MODULE_NAME ": "
57#define DRV_MODULE_VERSION "2.0.1"
58#define DRV_MODULE_RELDATE "May 6, 2009"
59#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-4.6.16.fw"
60#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-4.6.16.fw"
61#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-4.6.17.fw"
62#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-4.6.15.fw"
63
64#define RUN_AT(x) (jiffies + (x))
65
66
67#define TX_TIMEOUT (5*HZ)
68
69static char version[] __devinitdata =
70 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
71
72MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
73MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
74MODULE_LICENSE("GPL");
75MODULE_VERSION(DRV_MODULE_VERSION);
76MODULE_FIRMWARE(FW_MIPS_FILE_06);
77MODULE_FIRMWARE(FW_RV2P_FILE_06);
78MODULE_FIRMWARE(FW_MIPS_FILE_09);
79MODULE_FIRMWARE(FW_RV2P_FILE_09);
80
81static int disable_msi = 0;
82
83module_param(disable_msi, int, 0);
84MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
85
86typedef enum {
87 BCM5706 = 0,
88 NC370T,
89 NC370I,
90 BCM5706S,
91 NC370F,
92 BCM5708,
93 BCM5708S,
94 BCM5709,
95 BCM5709S,
96 BCM5716,
97 BCM5716S,
98} board_t;
99
100
101static struct {
102 char *name;
103} board_info[] __devinitdata = {
104 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
105 { "HP NC370T Multifunction Gigabit Server Adapter" },
106 { "HP NC370i Multifunction Gigabit Server Adapter" },
107 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
108 { "HP NC370F Multifunction Gigabit Server Adapter" },
109 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
110 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
111 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
112 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
113 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
114 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
115 };
116
117static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
119 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
121 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
127 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
136 { PCI_VENDOR_ID_BROADCOM, 0x163b,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
138 { PCI_VENDOR_ID_BROADCOM, 0x163c,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
140 { 0, }
141};
142
143static struct flash_spec flash_table[] =
144{
145#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
146#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
147
148 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
149 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
150 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
151 "EEPROM - slow"},
152
153 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
154 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
155 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
156 "Entry 0001"},
157
158
159 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
160 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
161 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
162 "Non-buffered flash (128kB)"},
163
164
165 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
167 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
168 "Non-buffered flash (256kB)"},
169
170 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
171 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
172 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
173 "Entry 0100"},
174
175 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
176 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
177 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
178 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
179
180 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
181 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
182 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
183 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
184
185
186 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
187 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
188 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
189 "Non-buffered flash (64kB)"},
190
191 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
192 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
193 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
194 "EEPROM - fast"},
195
196 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
197 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
198 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
199 "Entry 1001"},
200
201 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
202 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
203 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
204 "Entry 1010"},
205
206 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
207 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
208 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
209 "Buffered flash (128kB)"},
210
211 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
212 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
214 "Entry 1100"},
215
216 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
217 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
218 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
219 "Entry 1101"},
220
221 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
222 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
223 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
224 "Entry 1110 (Atmel)"},
225
226 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
227 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
228 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
229 "Buffered flash (256kB)"},
230};
231
232static struct flash_spec flash_5709 = {
233 .flags = BNX2_NV_BUFFERED,
234 .page_bits = BCM5709_FLASH_PAGE_BITS,
235 .page_size = BCM5709_FLASH_PAGE_SIZE,
236 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
237 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
238 .name = "5709 Buffered flash (256kB)",
239};
240
241MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
242
243static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
244{
245 u32 diff;
246
247 smp_mb();
248
249
250
251
252 diff = txr->tx_prod - txr->tx_cons;
253 if (unlikely(diff >= TX_DESC_CNT)) {
254 diff &= 0xffff;
255 if (diff == TX_DESC_CNT)
256 diff = MAX_TX_DESC_CNT;
257 }
258 return (bp->tx_ring_size - diff);
259}
260
261static u32
262bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
263{
264 u32 val;
265
266 spin_lock_bh(&bp->indirect_lock);
267 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
268 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
269 spin_unlock_bh(&bp->indirect_lock);
270 return val;
271}
272
273static void
274bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
275{
276 spin_lock_bh(&bp->indirect_lock);
277 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
278 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
279 spin_unlock_bh(&bp->indirect_lock);
280}
281
282static void
283bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
284{
285 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
286}
287
288static u32
289bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
290{
291 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
292}
293
294static void
295bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
296{
297 offset += cid_addr;
298 spin_lock_bh(&bp->indirect_lock);
299 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
300 int i;
301
302 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
303 REG_WR(bp, BNX2_CTX_CTX_CTRL,
304 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
305 for (i = 0; i < 5; i++) {
306 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
307 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
308 break;
309 udelay(5);
310 }
311 } else {
312 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
313 REG_WR(bp, BNX2_CTX_DATA, val);
314 }
315 spin_unlock_bh(&bp->indirect_lock);
316}
317
318static int
319bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
320{
321 u32 val1;
322 int i, ret;
323
324 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
325 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
326 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
327
328 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
329 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
330
331 udelay(40);
332 }
333
334 val1 = (bp->phy_addr << 21) | (reg << 16) |
335 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
336 BNX2_EMAC_MDIO_COMM_START_BUSY;
337 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
338
339 for (i = 0; i < 50; i++) {
340 udelay(10);
341
342 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
343 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
344 udelay(5);
345
346 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
347 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
348
349 break;
350 }
351 }
352
353 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
354 *val = 0x0;
355 ret = -EBUSY;
356 }
357 else {
358 *val = val1;
359 ret = 0;
360 }
361
362 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
363 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
364 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
365
366 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
367 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
368
369 udelay(40);
370 }
371
372 return ret;
373}
374
375static int
376bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
377{
378 u32 val1;
379 int i, ret;
380
381 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
382 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
383 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
384
385 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
386 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
387
388 udelay(40);
389 }
390
391 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
392 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
393 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
394 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
395
396 for (i = 0; i < 50; i++) {
397 udelay(10);
398
399 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
400 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
401 udelay(5);
402 break;
403 }
404 }
405
406 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
407 ret = -EBUSY;
408 else
409 ret = 0;
410
411 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
412 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
413 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
414
415 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
416 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
417
418 udelay(40);
419 }
420
421 return ret;
422}
423
424static void
425bnx2_disable_int(struct bnx2 *bp)
426{
427 int i;
428 struct bnx2_napi *bnapi;
429
430 for (i = 0; i < bp->irq_nvecs; i++) {
431 bnapi = &bp->bnx2_napi[i];
432 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
433 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
434 }
435 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
436}
437
438static void
439bnx2_enable_int(struct bnx2 *bp)
440{
441 int i;
442 struct bnx2_napi *bnapi;
443
444 for (i = 0; i < bp->irq_nvecs; i++) {
445 bnapi = &bp->bnx2_napi[i];
446
447 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
448 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
449 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
450 bnapi->last_status_idx);
451
452 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
453 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
454 bnapi->last_status_idx);
455 }
456 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
457}
458
459static void
460bnx2_disable_int_sync(struct bnx2 *bp)
461{
462 int i;
463
464 atomic_inc(&bp->intr_sem);
465 bnx2_disable_int(bp);
466 for (i = 0; i < bp->irq_nvecs; i++)
467 synchronize_irq(bp->irq_tbl[i].vector);
468}
469
470static void
471bnx2_napi_disable(struct bnx2 *bp)
472{
473 int i;
474
475 for (i = 0; i < bp->irq_nvecs; i++)
476 napi_disable(&bp->bnx2_napi[i].napi);
477}
478
479static void
480bnx2_napi_enable(struct bnx2 *bp)
481{
482 int i;
483
484 for (i = 0; i < bp->irq_nvecs; i++)
485 napi_enable(&bp->bnx2_napi[i].napi);
486}
487
488static void
489bnx2_netif_stop(struct bnx2 *bp)
490{
491 bnx2_disable_int_sync(bp);
492 if (netif_running(bp->dev)) {
493 bnx2_napi_disable(bp);
494 netif_tx_disable(bp->dev);
495 bp->dev->trans_start = jiffies;
496 }
497}
498
499static void
500bnx2_netif_start(struct bnx2 *bp)
501{
502 if (atomic_dec_and_test(&bp->intr_sem)) {
503 if (netif_running(bp->dev)) {
504 netif_tx_wake_all_queues(bp->dev);
505 bnx2_napi_enable(bp);
506 bnx2_enable_int(bp);
507 }
508 }
509}
510
511static void
512bnx2_free_tx_mem(struct bnx2 *bp)
513{
514 int i;
515
516 for (i = 0; i < bp->num_tx_rings; i++) {
517 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
518 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
519
520 if (txr->tx_desc_ring) {
521 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
522 txr->tx_desc_ring,
523 txr->tx_desc_mapping);
524 txr->tx_desc_ring = NULL;
525 }
526 kfree(txr->tx_buf_ring);
527 txr->tx_buf_ring = NULL;
528 }
529}
530
531static void
532bnx2_free_rx_mem(struct bnx2 *bp)
533{
534 int i;
535
536 for (i = 0; i < bp->num_rx_rings; i++) {
537 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
538 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
539 int j;
540
541 for (j = 0; j < bp->rx_max_ring; j++) {
542 if (rxr->rx_desc_ring[j])
543 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
544 rxr->rx_desc_ring[j],
545 rxr->rx_desc_mapping[j]);
546 rxr->rx_desc_ring[j] = NULL;
547 }
548 if (rxr->rx_buf_ring)
549 vfree(rxr->rx_buf_ring);
550 rxr->rx_buf_ring = NULL;
551
552 for (j = 0; j < bp->rx_max_pg_ring; j++) {
553 if (rxr->rx_pg_desc_ring[j])
554 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
555 rxr->rx_pg_desc_ring[j],
556 rxr->rx_pg_desc_mapping[j]);
557 rxr->rx_pg_desc_ring[j] = NULL;
558 }
559 if (rxr->rx_pg_ring)
560 vfree(rxr->rx_pg_ring);
561 rxr->rx_pg_ring = NULL;
562 }
563}
564
565static int
566bnx2_alloc_tx_mem(struct bnx2 *bp)
567{
568 int i;
569
570 for (i = 0; i < bp->num_tx_rings; i++) {
571 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
572 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
573
574 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
575 if (txr->tx_buf_ring == NULL)
576 return -ENOMEM;
577
578 txr->tx_desc_ring =
579 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
580 &txr->tx_desc_mapping);
581 if (txr->tx_desc_ring == NULL)
582 return -ENOMEM;
583 }
584 return 0;
585}
586
587static int
588bnx2_alloc_rx_mem(struct bnx2 *bp)
589{
590 int i;
591
592 for (i = 0; i < bp->num_rx_rings; i++) {
593 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
594 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
595 int j;
596
597 rxr->rx_buf_ring =
598 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
599 if (rxr->rx_buf_ring == NULL)
600 return -ENOMEM;
601
602 memset(rxr->rx_buf_ring, 0,
603 SW_RXBD_RING_SIZE * bp->rx_max_ring);
604
605 for (j = 0; j < bp->rx_max_ring; j++) {
606 rxr->rx_desc_ring[j] =
607 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
608 &rxr->rx_desc_mapping[j]);
609 if (rxr->rx_desc_ring[j] == NULL)
610 return -ENOMEM;
611
612 }
613
614 if (bp->rx_pg_ring_size) {
615 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
616 bp->rx_max_pg_ring);
617 if (rxr->rx_pg_ring == NULL)
618 return -ENOMEM;
619
620 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
621 bp->rx_max_pg_ring);
622 }
623
624 for (j = 0; j < bp->rx_max_pg_ring; j++) {
625 rxr->rx_pg_desc_ring[j] =
626 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
627 &rxr->rx_pg_desc_mapping[j]);
628 if (rxr->rx_pg_desc_ring[j] == NULL)
629 return -ENOMEM;
630
631 }
632 }
633 return 0;
634}
635
636static void
637bnx2_free_mem(struct bnx2 *bp)
638{
639 int i;
640 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
641
642 bnx2_free_tx_mem(bp);
643 bnx2_free_rx_mem(bp);
644
645 for (i = 0; i < bp->ctx_pages; i++) {
646 if (bp->ctx_blk[i]) {
647 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
648 bp->ctx_blk[i],
649 bp->ctx_blk_mapping[i]);
650 bp->ctx_blk[i] = NULL;
651 }
652 }
653 if (bnapi->status_blk.msi) {
654 pci_free_consistent(bp->pdev, bp->status_stats_size,
655 bnapi->status_blk.msi,
656 bp->status_blk_mapping);
657 bnapi->status_blk.msi = NULL;
658 bp->stats_blk = NULL;
659 }
660}
661
662static int
663bnx2_alloc_mem(struct bnx2 *bp)
664{
665 int i, status_blk_size, err;
666 struct bnx2_napi *bnapi;
667 void *status_blk;
668
669
670 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
671 if (bp->flags & BNX2_FLAG_MSIX_CAP)
672 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
673 BNX2_SBLK_MSIX_ALIGN_SIZE);
674 bp->status_stats_size = status_blk_size +
675 sizeof(struct statistics_block);
676
677 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
678 &bp->status_blk_mapping);
679 if (status_blk == NULL)
680 goto alloc_mem_err;
681
682 memset(status_blk, 0, bp->status_stats_size);
683
684 bnapi = &bp->bnx2_napi[0];
685 bnapi->status_blk.msi = status_blk;
686 bnapi->hw_tx_cons_ptr =
687 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
688 bnapi->hw_rx_cons_ptr =
689 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
690 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
691 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
692 struct status_block_msix *sblk;
693
694 bnapi = &bp->bnx2_napi[i];
695
696 sblk = (void *) (status_blk +
697 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
698 bnapi->status_blk.msix = sblk;
699 bnapi->hw_tx_cons_ptr =
700 &sblk->status_tx_quick_consumer_index;
701 bnapi->hw_rx_cons_ptr =
702 &sblk->status_rx_quick_consumer_index;
703 bnapi->int_num = i << 24;
704 }
705 }
706
707 bp->stats_blk = status_blk + status_blk_size;
708
709 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
710
711 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
712 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
713 if (bp->ctx_pages == 0)
714 bp->ctx_pages = 1;
715 for (i = 0; i < bp->ctx_pages; i++) {
716 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
717 BCM_PAGE_SIZE,
718 &bp->ctx_blk_mapping[i]);
719 if (bp->ctx_blk[i] == NULL)
720 goto alloc_mem_err;
721 }
722 }
723
724 err = bnx2_alloc_rx_mem(bp);
725 if (err)
726 goto alloc_mem_err;
727
728 err = bnx2_alloc_tx_mem(bp);
729 if (err)
730 goto alloc_mem_err;
731
732 return 0;
733
734alloc_mem_err:
735 bnx2_free_mem(bp);
736 return -ENOMEM;
737}
738
739static void
740bnx2_report_fw_link(struct bnx2 *bp)
741{
742 u32 fw_link_status = 0;
743
744 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
745 return;
746
747 if (bp->link_up) {
748 u32 bmsr;
749
750 switch (bp->line_speed) {
751 case SPEED_10:
752 if (bp->duplex == DUPLEX_HALF)
753 fw_link_status = BNX2_LINK_STATUS_10HALF;
754 else
755 fw_link_status = BNX2_LINK_STATUS_10FULL;
756 break;
757 case SPEED_100:
758 if (bp->duplex == DUPLEX_HALF)
759 fw_link_status = BNX2_LINK_STATUS_100HALF;
760 else
761 fw_link_status = BNX2_LINK_STATUS_100FULL;
762 break;
763 case SPEED_1000:
764 if (bp->duplex == DUPLEX_HALF)
765 fw_link_status = BNX2_LINK_STATUS_1000HALF;
766 else
767 fw_link_status = BNX2_LINK_STATUS_1000FULL;
768 break;
769 case SPEED_2500:
770 if (bp->duplex == DUPLEX_HALF)
771 fw_link_status = BNX2_LINK_STATUS_2500HALF;
772 else
773 fw_link_status = BNX2_LINK_STATUS_2500FULL;
774 break;
775 }
776
777 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
778
779 if (bp->autoneg) {
780 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
781
782 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
783 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
784
785 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
786 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
787 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
788 else
789 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
790 }
791 }
792 else
793 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
794
795 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
796}
797
798static char *
799bnx2_xceiver_str(struct bnx2 *bp)
800{
801 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
802 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
803 "Copper"));
804}
805
806static void
807bnx2_report_link(struct bnx2 *bp)
808{
809 if (bp->link_up) {
810 netif_carrier_on(bp->dev);
811 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
812 bnx2_xceiver_str(bp));
813
814 printk("%d Mbps ", bp->line_speed);
815
816 if (bp->duplex == DUPLEX_FULL)
817 printk("full duplex");
818 else
819 printk("half duplex");
820
821 if (bp->flow_ctrl) {
822 if (bp->flow_ctrl & FLOW_CTRL_RX) {
823 printk(", receive ");
824 if (bp->flow_ctrl & FLOW_CTRL_TX)
825 printk("& transmit ");
826 }
827 else {
828 printk(", transmit ");
829 }
830 printk("flow control ON");
831 }
832 printk("\n");
833 }
834 else {
835 netif_carrier_off(bp->dev);
836 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
837 bnx2_xceiver_str(bp));
838 }
839
840 bnx2_report_fw_link(bp);
841}
842
843static void
844bnx2_resolve_flow_ctrl(struct bnx2 *bp)
845{
846 u32 local_adv, remote_adv;
847
848 bp->flow_ctrl = 0;
849 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
850 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
851
852 if (bp->duplex == DUPLEX_FULL) {
853 bp->flow_ctrl = bp->req_flow_ctrl;
854 }
855 return;
856 }
857
858 if (bp->duplex != DUPLEX_FULL) {
859 return;
860 }
861
862 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
863 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
864 u32 val;
865
866 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
867 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
868 bp->flow_ctrl |= FLOW_CTRL_TX;
869 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
870 bp->flow_ctrl |= FLOW_CTRL_RX;
871 return;
872 }
873
874 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
875 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
876
877 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
878 u32 new_local_adv = 0;
879 u32 new_remote_adv = 0;
880
881 if (local_adv & ADVERTISE_1000XPAUSE)
882 new_local_adv |= ADVERTISE_PAUSE_CAP;
883 if (local_adv & ADVERTISE_1000XPSE_ASYM)
884 new_local_adv |= ADVERTISE_PAUSE_ASYM;
885 if (remote_adv & ADVERTISE_1000XPAUSE)
886 new_remote_adv |= ADVERTISE_PAUSE_CAP;
887 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
888 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
889
890 local_adv = new_local_adv;
891 remote_adv = new_remote_adv;
892 }
893
894
895 if (local_adv & ADVERTISE_PAUSE_CAP) {
896 if(local_adv & ADVERTISE_PAUSE_ASYM) {
897 if (remote_adv & ADVERTISE_PAUSE_CAP) {
898 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
899 }
900 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
901 bp->flow_ctrl = FLOW_CTRL_RX;
902 }
903 }
904 else {
905 if (remote_adv & ADVERTISE_PAUSE_CAP) {
906 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
907 }
908 }
909 }
910 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
911 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
912 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
913
914 bp->flow_ctrl = FLOW_CTRL_TX;
915 }
916 }
917}
918
919static int
920bnx2_5709s_linkup(struct bnx2 *bp)
921{
922 u32 val, speed;
923
924 bp->link_up = 1;
925
926 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
927 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
928 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
929
930 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
931 bp->line_speed = bp->req_line_speed;
932 bp->duplex = bp->req_duplex;
933 return 0;
934 }
935 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
936 switch (speed) {
937 case MII_BNX2_GP_TOP_AN_SPEED_10:
938 bp->line_speed = SPEED_10;
939 break;
940 case MII_BNX2_GP_TOP_AN_SPEED_100:
941 bp->line_speed = SPEED_100;
942 break;
943 case MII_BNX2_GP_TOP_AN_SPEED_1G:
944 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
945 bp->line_speed = SPEED_1000;
946 break;
947 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
948 bp->line_speed = SPEED_2500;
949 break;
950 }
951 if (val & MII_BNX2_GP_TOP_AN_FD)
952 bp->duplex = DUPLEX_FULL;
953 else
954 bp->duplex = DUPLEX_HALF;
955 return 0;
956}
957
958static int
959bnx2_5708s_linkup(struct bnx2 *bp)
960{
961 u32 val;
962
963 bp->link_up = 1;
964 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
965 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
966 case BCM5708S_1000X_STAT1_SPEED_10:
967 bp->line_speed = SPEED_10;
968 break;
969 case BCM5708S_1000X_STAT1_SPEED_100:
970 bp->line_speed = SPEED_100;
971 break;
972 case BCM5708S_1000X_STAT1_SPEED_1G:
973 bp->line_speed = SPEED_1000;
974 break;
975 case BCM5708S_1000X_STAT1_SPEED_2G5:
976 bp->line_speed = SPEED_2500;
977 break;
978 }
979 if (val & BCM5708S_1000X_STAT1_FD)
980 bp->duplex = DUPLEX_FULL;
981 else
982 bp->duplex = DUPLEX_HALF;
983
984 return 0;
985}
986
987static int
988bnx2_5706s_linkup(struct bnx2 *bp)
989{
990 u32 bmcr, local_adv, remote_adv, common;
991
992 bp->link_up = 1;
993 bp->line_speed = SPEED_1000;
994
995 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
996 if (bmcr & BMCR_FULLDPLX) {
997 bp->duplex = DUPLEX_FULL;
998 }
999 else {
1000 bp->duplex = DUPLEX_HALF;
1001 }
1002
1003 if (!(bmcr & BMCR_ANENABLE)) {
1004 return 0;
1005 }
1006
1007 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1008 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1009
1010 common = local_adv & remote_adv;
1011 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1012
1013 if (common & ADVERTISE_1000XFULL) {
1014 bp->duplex = DUPLEX_FULL;
1015 }
1016 else {
1017 bp->duplex = DUPLEX_HALF;
1018 }
1019 }
1020
1021 return 0;
1022}
1023
1024static int
1025bnx2_copper_linkup(struct bnx2 *bp)
1026{
1027 u32 bmcr;
1028
1029 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1030 if (bmcr & BMCR_ANENABLE) {
1031 u32 local_adv, remote_adv, common;
1032
1033 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1034 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1035
1036 common = local_adv & (remote_adv >> 2);
1037 if (common & ADVERTISE_1000FULL) {
1038 bp->line_speed = SPEED_1000;
1039 bp->duplex = DUPLEX_FULL;
1040 }
1041 else if (common & ADVERTISE_1000HALF) {
1042 bp->line_speed = SPEED_1000;
1043 bp->duplex = DUPLEX_HALF;
1044 }
1045 else {
1046 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1047 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1048
1049 common = local_adv & remote_adv;
1050 if (common & ADVERTISE_100FULL) {
1051 bp->line_speed = SPEED_100;
1052 bp->duplex = DUPLEX_FULL;
1053 }
1054 else if (common & ADVERTISE_100HALF) {
1055 bp->line_speed = SPEED_100;
1056 bp->duplex = DUPLEX_HALF;
1057 }
1058 else if (common & ADVERTISE_10FULL) {
1059 bp->line_speed = SPEED_10;
1060 bp->duplex = DUPLEX_FULL;
1061 }
1062 else if (common & ADVERTISE_10HALF) {
1063 bp->line_speed = SPEED_10;
1064 bp->duplex = DUPLEX_HALF;
1065 }
1066 else {
1067 bp->line_speed = 0;
1068 bp->link_up = 0;
1069 }
1070 }
1071 }
1072 else {
1073 if (bmcr & BMCR_SPEED100) {
1074 bp->line_speed = SPEED_100;
1075 }
1076 else {
1077 bp->line_speed = SPEED_10;
1078 }
1079 if (bmcr & BMCR_FULLDPLX) {
1080 bp->duplex = DUPLEX_FULL;
1081 }
1082 else {
1083 bp->duplex = DUPLEX_HALF;
1084 }
1085 }
1086
1087 return 0;
1088}
1089
1090static void
1091bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1092{
1093 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1094
1095 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1096 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1097 val |= 0x02 << 8;
1098
1099 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1100 u32 lo_water, hi_water;
1101
1102 if (bp->flow_ctrl & FLOW_CTRL_TX)
1103 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1104 else
1105 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1106 if (lo_water >= bp->rx_ring_size)
1107 lo_water = 0;
1108
1109 hi_water = bp->rx_ring_size / 4;
1110
1111 if (hi_water <= lo_water)
1112 lo_water = 0;
1113
1114 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1115 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1116
1117 if (hi_water > 0xf)
1118 hi_water = 0xf;
1119 else if (hi_water == 0)
1120 lo_water = 0;
1121 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1122 }
1123 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1124}
1125
1126static void
1127bnx2_init_all_rx_contexts(struct bnx2 *bp)
1128{
1129 int i;
1130 u32 cid;
1131
1132 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1133 if (i == 1)
1134 cid = RX_RSS_CID;
1135 bnx2_init_rx_context(bp, cid);
1136 }
1137}
1138
1139static void
1140bnx2_set_mac_link(struct bnx2 *bp)
1141{
1142 u32 val;
1143
1144 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1145 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1146 (bp->duplex == DUPLEX_HALF)) {
1147 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1148 }
1149
1150
1151 val = REG_RD(bp, BNX2_EMAC_MODE);
1152
1153 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1154 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1155 BNX2_EMAC_MODE_25G_MODE);
1156
1157 if (bp->link_up) {
1158 switch (bp->line_speed) {
1159 case SPEED_10:
1160 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1161 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1162 break;
1163 }
1164
1165 case SPEED_100:
1166 val |= BNX2_EMAC_MODE_PORT_MII;
1167 break;
1168 case SPEED_2500:
1169 val |= BNX2_EMAC_MODE_25G_MODE;
1170
1171 case SPEED_1000:
1172 val |= BNX2_EMAC_MODE_PORT_GMII;
1173 break;
1174 }
1175 }
1176 else {
1177 val |= BNX2_EMAC_MODE_PORT_GMII;
1178 }
1179
1180
1181 if (bp->duplex == DUPLEX_HALF)
1182 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1183 REG_WR(bp, BNX2_EMAC_MODE, val);
1184
1185
1186 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1187
1188 if (bp->flow_ctrl & FLOW_CTRL_RX)
1189 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1190 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1191
1192
1193 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1194 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1195
1196 if (bp->flow_ctrl & FLOW_CTRL_TX)
1197 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1198 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1199
1200
1201 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1202
1203 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1204 bnx2_init_all_rx_contexts(bp);
1205}
1206
1207static void
1208bnx2_enable_bmsr1(struct bnx2 *bp)
1209{
1210 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1211 (CHIP_NUM(bp) == CHIP_NUM_5709))
1212 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1213 MII_BNX2_BLK_ADDR_GP_STATUS);
1214}
1215
1216static void
1217bnx2_disable_bmsr1(struct bnx2 *bp)
1218{
1219 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1220 (CHIP_NUM(bp) == CHIP_NUM_5709))
1221 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1222 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1223}
1224
1225static int
1226bnx2_test_and_enable_2g5(struct bnx2 *bp)
1227{
1228 u32 up1;
1229 int ret = 1;
1230
1231 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1232 return 0;
1233
1234 if (bp->autoneg & AUTONEG_SPEED)
1235 bp->advertising |= ADVERTISED_2500baseX_Full;
1236
1237 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1238 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1239
1240 bnx2_read_phy(bp, bp->mii_up1, &up1);
1241 if (!(up1 & BCM5708S_UP1_2G5)) {
1242 up1 |= BCM5708S_UP1_2G5;
1243 bnx2_write_phy(bp, bp->mii_up1, up1);
1244 ret = 0;
1245 }
1246
1247 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1248 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1249 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1250
1251 return ret;
1252}
1253
1254static int
1255bnx2_test_and_disable_2g5(struct bnx2 *bp)
1256{
1257 u32 up1;
1258 int ret = 0;
1259
1260 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1261 return 0;
1262
1263 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1264 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1265
1266 bnx2_read_phy(bp, bp->mii_up1, &up1);
1267 if (up1 & BCM5708S_UP1_2G5) {
1268 up1 &= ~BCM5708S_UP1_2G5;
1269 bnx2_write_phy(bp, bp->mii_up1, up1);
1270 ret = 1;
1271 }
1272
1273 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1274 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1275 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1276
1277 return ret;
1278}
1279
1280static void
1281bnx2_enable_forced_2g5(struct bnx2 *bp)
1282{
1283 u32 bmcr;
1284
1285 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1286 return;
1287
1288 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1289 u32 val;
1290
1291 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1292 MII_BNX2_BLK_ADDR_SERDES_DIG);
1293 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1294 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1295 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1296 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1297
1298 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1299 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1300 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1301
1302 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1303 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1304 bmcr |= BCM5708S_BMCR_FORCE_2500;
1305 }
1306
1307 if (bp->autoneg & AUTONEG_SPEED) {
1308 bmcr &= ~BMCR_ANENABLE;
1309 if (bp->req_duplex == DUPLEX_FULL)
1310 bmcr |= BMCR_FULLDPLX;
1311 }
1312 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1313}
1314
1315static void
1316bnx2_disable_forced_2g5(struct bnx2 *bp)
1317{
1318 u32 bmcr;
1319
1320 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1321 return;
1322
1323 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1324 u32 val;
1325
1326 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1327 MII_BNX2_BLK_ADDR_SERDES_DIG);
1328 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1329 val &= ~MII_BNX2_SD_MISC1_FORCE;
1330 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1331
1332 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1333 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1334 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1335
1336 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1337 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1338 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1339 }
1340
1341 if (bp->autoneg & AUTONEG_SPEED)
1342 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1343 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1344}
1345
1346static void
1347bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1348{
1349 u32 val;
1350
1351 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1352 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1353 if (start)
1354 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1355 else
1356 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1357}
1358
1359static int
1360bnx2_set_link(struct bnx2 *bp)
1361{
1362 u32 bmsr;
1363 u8 link_up;
1364
1365 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1366 bp->link_up = 1;
1367 return 0;
1368 }
1369
1370 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1371 return 0;
1372
1373 link_up = bp->link_up;
1374
1375 bnx2_enable_bmsr1(bp);
1376 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1377 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1378 bnx2_disable_bmsr1(bp);
1379
1380 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1381 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1382 u32 val, an_dbg;
1383
1384 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1385 bnx2_5706s_force_link_dn(bp, 0);
1386 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1387 }
1388 val = REG_RD(bp, BNX2_EMAC_STATUS);
1389
1390 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1391 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1392 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1393
1394 if ((val & BNX2_EMAC_STATUS_LINK) &&
1395 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1396 bmsr |= BMSR_LSTATUS;
1397 else
1398 bmsr &= ~BMSR_LSTATUS;
1399 }
1400
1401 if (bmsr & BMSR_LSTATUS) {
1402 bp->link_up = 1;
1403
1404 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1405 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1406 bnx2_5706s_linkup(bp);
1407 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1408 bnx2_5708s_linkup(bp);
1409 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1410 bnx2_5709s_linkup(bp);
1411 }
1412 else {
1413 bnx2_copper_linkup(bp);
1414 }
1415 bnx2_resolve_flow_ctrl(bp);
1416 }
1417 else {
1418 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1419 (bp->autoneg & AUTONEG_SPEED))
1420 bnx2_disable_forced_2g5(bp);
1421
1422 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1423 u32 bmcr;
1424
1425 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1426 bmcr |= BMCR_ANENABLE;
1427 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1428
1429 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1430 }
1431 bp->link_up = 0;
1432 }
1433
1434 if (bp->link_up != link_up) {
1435 bnx2_report_link(bp);
1436 }
1437
1438 bnx2_set_mac_link(bp);
1439
1440 return 0;
1441}
1442
1443static int
1444bnx2_reset_phy(struct bnx2 *bp)
1445{
1446 int i;
1447 u32 reg;
1448
1449 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1450
1451#define PHY_RESET_MAX_WAIT 100
1452 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1453 udelay(10);
1454
1455 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1456 if (!(reg & BMCR_RESET)) {
1457 udelay(20);
1458 break;
1459 }
1460 }
1461 if (i == PHY_RESET_MAX_WAIT) {
1462 return -EBUSY;
1463 }
1464 return 0;
1465}
1466
1467static u32
1468bnx2_phy_get_pause_adv(struct bnx2 *bp)
1469{
1470 u32 adv = 0;
1471
1472 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1473 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1474
1475 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1476 adv = ADVERTISE_1000XPAUSE;
1477 }
1478 else {
1479 adv = ADVERTISE_PAUSE_CAP;
1480 }
1481 }
1482 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1483 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1484 adv = ADVERTISE_1000XPSE_ASYM;
1485 }
1486 else {
1487 adv = ADVERTISE_PAUSE_ASYM;
1488 }
1489 }
1490 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1491 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1492 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1493 }
1494 else {
1495 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1496 }
1497 }
1498 return adv;
1499}
1500
1501static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1502
1503static int
1504bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1505__releases(&bp->phy_lock)
1506__acquires(&bp->phy_lock)
1507{
1508 u32 speed_arg = 0, pause_adv;
1509
1510 pause_adv = bnx2_phy_get_pause_adv(bp);
1511
1512 if (bp->autoneg & AUTONEG_SPEED) {
1513 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1514 if (bp->advertising & ADVERTISED_10baseT_Half)
1515 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1516 if (bp->advertising & ADVERTISED_10baseT_Full)
1517 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1518 if (bp->advertising & ADVERTISED_100baseT_Half)
1519 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1520 if (bp->advertising & ADVERTISED_100baseT_Full)
1521 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1522 if (bp->advertising & ADVERTISED_1000baseT_Full)
1523 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1524 if (bp->advertising & ADVERTISED_2500baseX_Full)
1525 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1526 } else {
1527 if (bp->req_line_speed == SPEED_2500)
1528 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1529 else if (bp->req_line_speed == SPEED_1000)
1530 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1531 else if (bp->req_line_speed == SPEED_100) {
1532 if (bp->req_duplex == DUPLEX_FULL)
1533 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1534 else
1535 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1536 } else if (bp->req_line_speed == SPEED_10) {
1537 if (bp->req_duplex == DUPLEX_FULL)
1538 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1539 else
1540 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1541 }
1542 }
1543
1544 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1545 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1546 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1547 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1548
1549 if (port == PORT_TP)
1550 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1551 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1552
1553 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1554
1555 spin_unlock_bh(&bp->phy_lock);
1556 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1557 spin_lock_bh(&bp->phy_lock);
1558
1559 return 0;
1560}
1561
1562static int
1563bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1564__releases(&bp->phy_lock)
1565__acquires(&bp->phy_lock)
1566{
1567 u32 adv, bmcr;
1568 u32 new_adv = 0;
1569
1570 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1571 return (bnx2_setup_remote_phy(bp, port));
1572
1573 if (!(bp->autoneg & AUTONEG_SPEED)) {
1574 u32 new_bmcr;
1575 int force_link_down = 0;
1576
1577 if (bp->req_line_speed == SPEED_2500) {
1578 if (!bnx2_test_and_enable_2g5(bp))
1579 force_link_down = 1;
1580 } else if (bp->req_line_speed == SPEED_1000) {
1581 if (bnx2_test_and_disable_2g5(bp))
1582 force_link_down = 1;
1583 }
1584 bnx2_read_phy(bp, bp->mii_adv, &adv);
1585 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1586
1587 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1588 new_bmcr = bmcr & ~BMCR_ANENABLE;
1589 new_bmcr |= BMCR_SPEED1000;
1590
1591 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1592 if (bp->req_line_speed == SPEED_2500)
1593 bnx2_enable_forced_2g5(bp);
1594 else if (bp->req_line_speed == SPEED_1000) {
1595 bnx2_disable_forced_2g5(bp);
1596 new_bmcr &= ~0x2000;
1597 }
1598
1599 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1600 if (bp->req_line_speed == SPEED_2500)
1601 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1602 else
1603 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1604 }
1605
1606 if (bp->req_duplex == DUPLEX_FULL) {
1607 adv |= ADVERTISE_1000XFULL;
1608 new_bmcr |= BMCR_FULLDPLX;
1609 }
1610 else {
1611 adv |= ADVERTISE_1000XHALF;
1612 new_bmcr &= ~BMCR_FULLDPLX;
1613 }
1614 if ((new_bmcr != bmcr) || (force_link_down)) {
1615
1616 if (bp->link_up) {
1617 bnx2_write_phy(bp, bp->mii_adv, adv &
1618 ~(ADVERTISE_1000XFULL |
1619 ADVERTISE_1000XHALF));
1620 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1621 BMCR_ANRESTART | BMCR_ANENABLE);
1622
1623 bp->link_up = 0;
1624 netif_carrier_off(bp->dev);
1625 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1626 bnx2_report_link(bp);
1627 }
1628 bnx2_write_phy(bp, bp->mii_adv, adv);
1629 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1630 } else {
1631 bnx2_resolve_flow_ctrl(bp);
1632 bnx2_set_mac_link(bp);
1633 }
1634 return 0;
1635 }
1636
1637 bnx2_test_and_enable_2g5(bp);
1638
1639 if (bp->advertising & ADVERTISED_1000baseT_Full)
1640 new_adv |= ADVERTISE_1000XFULL;
1641
1642 new_adv |= bnx2_phy_get_pause_adv(bp);
1643
1644 bnx2_read_phy(bp, bp->mii_adv, &adv);
1645 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1646
1647 bp->serdes_an_pending = 0;
1648 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1649
1650 if (bp->link_up) {
1651 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1652 spin_unlock_bh(&bp->phy_lock);
1653 msleep(20);
1654 spin_lock_bh(&bp->phy_lock);
1655 }
1656
1657 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1658 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1659 BMCR_ANENABLE);
1660
1661
1662
1663
1664
1665
1666
1667
1668 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1669 bp->serdes_an_pending = 1;
1670 mod_timer(&bp->timer, jiffies + bp->current_interval);
1671 } else {
1672 bnx2_resolve_flow_ctrl(bp);
1673 bnx2_set_mac_link(bp);
1674 }
1675
1676 return 0;
1677}
1678
1679#define ETHTOOL_ALL_FIBRE_SPEED \
1680 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1681 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1682 (ADVERTISED_1000baseT_Full)
1683
1684#define ETHTOOL_ALL_COPPER_SPEED \
1685 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1686 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1687 ADVERTISED_1000baseT_Full)
1688
1689#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1690 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1691
1692#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1693
1694static void
1695bnx2_set_default_remote_link(struct bnx2 *bp)
1696{
1697 u32 link;
1698
1699 if (bp->phy_port == PORT_TP)
1700 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1701 else
1702 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1703
1704 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1705 bp->req_line_speed = 0;
1706 bp->autoneg |= AUTONEG_SPEED;
1707 bp->advertising = ADVERTISED_Autoneg;
1708 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1709 bp->advertising |= ADVERTISED_10baseT_Half;
1710 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1711 bp->advertising |= ADVERTISED_10baseT_Full;
1712 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1713 bp->advertising |= ADVERTISED_100baseT_Half;
1714 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1715 bp->advertising |= ADVERTISED_100baseT_Full;
1716 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1717 bp->advertising |= ADVERTISED_1000baseT_Full;
1718 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1719 bp->advertising |= ADVERTISED_2500baseX_Full;
1720 } else {
1721 bp->autoneg = 0;
1722 bp->advertising = 0;
1723 bp->req_duplex = DUPLEX_FULL;
1724 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1725 bp->req_line_speed = SPEED_10;
1726 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1727 bp->req_duplex = DUPLEX_HALF;
1728 }
1729 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1730 bp->req_line_speed = SPEED_100;
1731 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1732 bp->req_duplex = DUPLEX_HALF;
1733 }
1734 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1735 bp->req_line_speed = SPEED_1000;
1736 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1737 bp->req_line_speed = SPEED_2500;
1738 }
1739}
1740
1741static void
1742bnx2_set_default_link(struct bnx2 *bp)
1743{
1744 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1745 bnx2_set_default_remote_link(bp);
1746 return;
1747 }
1748
1749 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1750 bp->req_line_speed = 0;
1751 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1752 u32 reg;
1753
1754 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1755
1756 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1757 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1758 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1759 bp->autoneg = 0;
1760 bp->req_line_speed = bp->line_speed = SPEED_1000;
1761 bp->req_duplex = DUPLEX_FULL;
1762 }
1763 } else
1764 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1765}
1766
1767static void
1768bnx2_send_heart_beat(struct bnx2 *bp)
1769{
1770 u32 msg;
1771 u32 addr;
1772
1773 spin_lock(&bp->indirect_lock);
1774 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1775 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1776 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1777 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1778 spin_unlock(&bp->indirect_lock);
1779}
1780
1781static void
1782bnx2_remote_phy_event(struct bnx2 *bp)
1783{
1784 u32 msg;
1785 u8 link_up = bp->link_up;
1786 u8 old_port;
1787
1788 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1789
1790 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1791 bnx2_send_heart_beat(bp);
1792
1793 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1794
1795 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1796 bp->link_up = 0;
1797 else {
1798 u32 speed;
1799
1800 bp->link_up = 1;
1801 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1802 bp->duplex = DUPLEX_FULL;
1803 switch (speed) {
1804 case BNX2_LINK_STATUS_10HALF:
1805 bp->duplex = DUPLEX_HALF;
1806 case BNX2_LINK_STATUS_10FULL:
1807 bp->line_speed = SPEED_10;
1808 break;
1809 case BNX2_LINK_STATUS_100HALF:
1810 bp->duplex = DUPLEX_HALF;
1811 case BNX2_LINK_STATUS_100BASE_T4:
1812 case BNX2_LINK_STATUS_100FULL:
1813 bp->line_speed = SPEED_100;
1814 break;
1815 case BNX2_LINK_STATUS_1000HALF:
1816 bp->duplex = DUPLEX_HALF;
1817 case BNX2_LINK_STATUS_1000FULL:
1818 bp->line_speed = SPEED_1000;
1819 break;
1820 case BNX2_LINK_STATUS_2500HALF:
1821 bp->duplex = DUPLEX_HALF;
1822 case BNX2_LINK_STATUS_2500FULL:
1823 bp->line_speed = SPEED_2500;
1824 break;
1825 default:
1826 bp->line_speed = 0;
1827 break;
1828 }
1829
1830 bp->flow_ctrl = 0;
1831 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1832 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1833 if (bp->duplex == DUPLEX_FULL)
1834 bp->flow_ctrl = bp->req_flow_ctrl;
1835 } else {
1836 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1837 bp->flow_ctrl |= FLOW_CTRL_TX;
1838 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1839 bp->flow_ctrl |= FLOW_CTRL_RX;
1840 }
1841
1842 old_port = bp->phy_port;
1843 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1844 bp->phy_port = PORT_FIBRE;
1845 else
1846 bp->phy_port = PORT_TP;
1847
1848 if (old_port != bp->phy_port)
1849 bnx2_set_default_link(bp);
1850
1851 }
1852 if (bp->link_up != link_up)
1853 bnx2_report_link(bp);
1854
1855 bnx2_set_mac_link(bp);
1856}
1857
1858static int
1859bnx2_set_remote_link(struct bnx2 *bp)
1860{
1861 u32 evt_code;
1862
1863 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1864 switch (evt_code) {
1865 case BNX2_FW_EVT_CODE_LINK_EVENT:
1866 bnx2_remote_phy_event(bp);
1867 break;
1868 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1869 default:
1870 bnx2_send_heart_beat(bp);
1871 break;
1872 }
1873 return 0;
1874}
1875
1876static int
1877bnx2_setup_copper_phy(struct bnx2 *bp)
1878__releases(&bp->phy_lock)
1879__acquires(&bp->phy_lock)
1880{
1881 u32 bmcr;
1882 u32 new_bmcr;
1883
1884 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1885
1886 if (bp->autoneg & AUTONEG_SPEED) {
1887 u32 adv_reg, adv1000_reg;
1888 u32 new_adv_reg = 0;
1889 u32 new_adv1000_reg = 0;
1890
1891 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1892 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1893 ADVERTISE_PAUSE_ASYM);
1894
1895 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1896 adv1000_reg &= PHY_ALL_1000_SPEED;
1897
1898 if (bp->advertising & ADVERTISED_10baseT_Half)
1899 new_adv_reg |= ADVERTISE_10HALF;
1900 if (bp->advertising & ADVERTISED_10baseT_Full)
1901 new_adv_reg |= ADVERTISE_10FULL;
1902 if (bp->advertising & ADVERTISED_100baseT_Half)
1903 new_adv_reg |= ADVERTISE_100HALF;
1904 if (bp->advertising & ADVERTISED_100baseT_Full)
1905 new_adv_reg |= ADVERTISE_100FULL;
1906 if (bp->advertising & ADVERTISED_1000baseT_Full)
1907 new_adv1000_reg |= ADVERTISE_1000FULL;
1908
1909 new_adv_reg |= ADVERTISE_CSMA;
1910
1911 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1912
1913 if ((adv1000_reg != new_adv1000_reg) ||
1914 (adv_reg != new_adv_reg) ||
1915 ((bmcr & BMCR_ANENABLE) == 0)) {
1916
1917 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1918 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1919 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1920 BMCR_ANENABLE);
1921 }
1922 else if (bp->link_up) {
1923
1924
1925
1926 bnx2_resolve_flow_ctrl(bp);
1927 bnx2_set_mac_link(bp);
1928 }
1929 return 0;
1930 }
1931
1932 new_bmcr = 0;
1933 if (bp->req_line_speed == SPEED_100) {
1934 new_bmcr |= BMCR_SPEED100;
1935 }
1936 if (bp->req_duplex == DUPLEX_FULL) {
1937 new_bmcr |= BMCR_FULLDPLX;
1938 }
1939 if (new_bmcr != bmcr) {
1940 u32 bmsr;
1941
1942 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1943 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1944
1945 if (bmsr & BMSR_LSTATUS) {
1946
1947 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1948 spin_unlock_bh(&bp->phy_lock);
1949 msleep(50);
1950 spin_lock_bh(&bp->phy_lock);
1951
1952 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1953 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1954 }
1955
1956 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1957
1958
1959
1960
1961
1962 if (bmsr & BMSR_LSTATUS) {
1963 bp->line_speed = bp->req_line_speed;
1964 bp->duplex = bp->req_duplex;
1965 bnx2_resolve_flow_ctrl(bp);
1966 bnx2_set_mac_link(bp);
1967 }
1968 } else {
1969 bnx2_resolve_flow_ctrl(bp);
1970 bnx2_set_mac_link(bp);
1971 }
1972 return 0;
1973}
1974
1975static int
1976bnx2_setup_phy(struct bnx2 *bp, u8 port)
1977__releases(&bp->phy_lock)
1978__acquires(&bp->phy_lock)
1979{
1980 if (bp->loopback == MAC_LOOPBACK)
1981 return 0;
1982
1983 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1984 return (bnx2_setup_serdes_phy(bp, port));
1985 }
1986 else {
1987 return (bnx2_setup_copper_phy(bp));
1988 }
1989}
1990
1991static int
1992bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1993{
1994 u32 val;
1995
1996 bp->mii_bmcr = MII_BMCR + 0x10;
1997 bp->mii_bmsr = MII_BMSR + 0x10;
1998 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1999 bp->mii_adv = MII_ADVERTISE + 0x10;
2000 bp->mii_lpa = MII_LPA + 0x10;
2001 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2002
2003 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2004 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2005
2006 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2007 if (reset_phy)
2008 bnx2_reset_phy(bp);
2009
2010 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2011
2012 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2013 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2014 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2015 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2016
2017 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2018 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2019 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2020 val |= BCM5708S_UP1_2G5;
2021 else
2022 val &= ~BCM5708S_UP1_2G5;
2023 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2024
2025 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2026 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2027 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2028 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2029
2030 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2031
2032 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2033 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2034 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2035
2036 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2037
2038 return 0;
2039}
2040
2041static int
2042bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2043{
2044 u32 val;
2045
2046 if (reset_phy)
2047 bnx2_reset_phy(bp);
2048
2049 bp->mii_up1 = BCM5708S_UP1;
2050
2051 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2052 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2053 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2054
2055 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2056 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2057 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2058
2059 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2060 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2061 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2062
2063 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2064 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2065 val |= BCM5708S_UP1_2G5;
2066 bnx2_write_phy(bp, BCM5708S_UP1, val);
2067 }
2068
2069 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2070 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2071 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2072
2073 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2074 BCM5708S_BLK_ADDR_TX_MISC);
2075 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2076 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2077 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2078 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2079 }
2080
2081 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2082 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2083
2084 if (val) {
2085 u32 is_backplane;
2086
2087 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2088 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2089 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2090 BCM5708S_BLK_ADDR_TX_MISC);
2091 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2092 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2093 BCM5708S_BLK_ADDR_DIG);
2094 }
2095 }
2096 return 0;
2097}
2098
2099static int
2100bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2101{
2102 if (reset_phy)
2103 bnx2_reset_phy(bp);
2104
2105 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2106
2107 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2108 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2109
2110 if (bp->dev->mtu > 1500) {
2111 u32 val;
2112
2113
2114 bnx2_write_phy(bp, 0x18, 0x7);
2115 bnx2_read_phy(bp, 0x18, &val);
2116 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2117
2118 bnx2_write_phy(bp, 0x1c, 0x6c00);
2119 bnx2_read_phy(bp, 0x1c, &val);
2120 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2121 }
2122 else {
2123 u32 val;
2124
2125 bnx2_write_phy(bp, 0x18, 0x7);
2126 bnx2_read_phy(bp, 0x18, &val);
2127 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2128
2129 bnx2_write_phy(bp, 0x1c, 0x6c00);
2130 bnx2_read_phy(bp, 0x1c, &val);
2131 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2132 }
2133
2134 return 0;
2135}
2136
2137static int
2138bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2139{
2140 u32 val;
2141
2142 if (reset_phy)
2143 bnx2_reset_phy(bp);
2144
2145 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2146 bnx2_write_phy(bp, 0x18, 0x0c00);
2147 bnx2_write_phy(bp, 0x17, 0x000a);
2148 bnx2_write_phy(bp, 0x15, 0x310b);
2149 bnx2_write_phy(bp, 0x17, 0x201f);
2150 bnx2_write_phy(bp, 0x15, 0x9506);
2151 bnx2_write_phy(bp, 0x17, 0x401f);
2152 bnx2_write_phy(bp, 0x15, 0x14e2);
2153 bnx2_write_phy(bp, 0x18, 0x0400);
2154 }
2155
2156 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2157 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2158 MII_BNX2_DSP_EXPAND_REG | 0x8);
2159 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2160 val &= ~(1 << 8);
2161 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2162 }
2163
2164 if (bp->dev->mtu > 1500) {
2165
2166 bnx2_write_phy(bp, 0x18, 0x7);
2167 bnx2_read_phy(bp, 0x18, &val);
2168 bnx2_write_phy(bp, 0x18, val | 0x4000);
2169
2170 bnx2_read_phy(bp, 0x10, &val);
2171 bnx2_write_phy(bp, 0x10, val | 0x1);
2172 }
2173 else {
2174 bnx2_write_phy(bp, 0x18, 0x7);
2175 bnx2_read_phy(bp, 0x18, &val);
2176 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2177
2178 bnx2_read_phy(bp, 0x10, &val);
2179 bnx2_write_phy(bp, 0x10, val & ~0x1);
2180 }
2181
2182
2183 bnx2_write_phy(bp, 0x18, 0x7007);
2184 bnx2_read_phy(bp, 0x18, &val);
2185 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2186 return 0;
2187}
2188
2189
2190static int
2191bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2192__releases(&bp->phy_lock)
2193__acquires(&bp->phy_lock)
2194{
2195 u32 val;
2196 int rc = 0;
2197
2198 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2199 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2200
2201 bp->mii_bmcr = MII_BMCR;
2202 bp->mii_bmsr = MII_BMSR;
2203 bp->mii_bmsr1 = MII_BMSR;
2204 bp->mii_adv = MII_ADVERTISE;
2205 bp->mii_lpa = MII_LPA;
2206
2207 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2208
2209 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2210 goto setup_phy;
2211
2212 bnx2_read_phy(bp, MII_PHYSID1, &val);
2213 bp->phy_id = val << 16;
2214 bnx2_read_phy(bp, MII_PHYSID2, &val);
2215 bp->phy_id |= val & 0xffff;
2216
2217 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2218 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2219 rc = bnx2_init_5706s_phy(bp, reset_phy);
2220 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2221 rc = bnx2_init_5708s_phy(bp, reset_phy);
2222 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2223 rc = bnx2_init_5709s_phy(bp, reset_phy);
2224 }
2225 else {
2226 rc = bnx2_init_copper_phy(bp, reset_phy);
2227 }
2228
2229setup_phy:
2230 if (!rc)
2231 rc = bnx2_setup_phy(bp, bp->phy_port);
2232
2233 return rc;
2234}
2235
2236static int
2237bnx2_set_mac_loopback(struct bnx2 *bp)
2238{
2239 u32 mac_mode;
2240
2241 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2242 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2243 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2244 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2245 bp->link_up = 1;
2246 return 0;
2247}
2248
2249static int bnx2_test_link(struct bnx2 *);
2250
2251static int
2252bnx2_set_phy_loopback(struct bnx2 *bp)
2253{
2254 u32 mac_mode;
2255 int rc, i;
2256
2257 spin_lock_bh(&bp->phy_lock);
2258 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2259 BMCR_SPEED1000);
2260 spin_unlock_bh(&bp->phy_lock);
2261 if (rc)
2262 return rc;
2263
2264 for (i = 0; i < 10; i++) {
2265 if (bnx2_test_link(bp) == 0)
2266 break;
2267 msleep(100);
2268 }
2269
2270 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2271 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2272 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2273 BNX2_EMAC_MODE_25G_MODE);
2274
2275 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2276 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2277 bp->link_up = 1;
2278 return 0;
2279}
2280
2281static int
2282bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2283{
2284 int i;
2285 u32 val;
2286
2287 bp->fw_wr_seq++;
2288 msg_data |= bp->fw_wr_seq;
2289
2290 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2291
2292 if (!ack)
2293 return 0;
2294
2295
2296 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2297 msleep(10);
2298
2299 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2300
2301 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2302 break;
2303 }
2304 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2305 return 0;
2306
2307
2308 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2309 if (!silent)
2310 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2311 "%x\n", msg_data);
2312
2313 msg_data &= ~BNX2_DRV_MSG_CODE;
2314 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2315
2316 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2317
2318 return -EBUSY;
2319 }
2320
2321 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2322 return -EIO;
2323
2324 return 0;
2325}
2326
2327static int
2328bnx2_init_5709_context(struct bnx2 *bp)
2329{
2330 int i, ret = 0;
2331 u32 val;
2332
2333 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2334 val |= (BCM_PAGE_BITS - 8) << 16;
2335 REG_WR(bp, BNX2_CTX_COMMAND, val);
2336 for (i = 0; i < 10; i++) {
2337 val = REG_RD(bp, BNX2_CTX_COMMAND);
2338 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2339 break;
2340 udelay(2);
2341 }
2342 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2343 return -EBUSY;
2344
2345 for (i = 0; i < bp->ctx_pages; i++) {
2346 int j;
2347
2348 if (bp->ctx_blk[i])
2349 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2350 else
2351 return -ENOMEM;
2352
2353 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2354 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2355 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2356 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2357 (u64) bp->ctx_blk_mapping[i] >> 32);
2358 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2359 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2360 for (j = 0; j < 10; j++) {
2361
2362 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2363 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2364 break;
2365 udelay(5);
2366 }
2367 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2368 ret = -EBUSY;
2369 break;
2370 }
2371 }
2372 return ret;
2373}
2374
2375static void
2376bnx2_init_context(struct bnx2 *bp)
2377{
2378 u32 vcid;
2379
2380 vcid = 96;
2381 while (vcid) {
2382 u32 vcid_addr, pcid_addr, offset;
2383 int i;
2384
2385 vcid--;
2386
2387 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2388 u32 new_vcid;
2389
2390 vcid_addr = GET_PCID_ADDR(vcid);
2391 if (vcid & 0x8) {
2392 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2393 }
2394 else {
2395 new_vcid = vcid;
2396 }
2397 pcid_addr = GET_PCID_ADDR(new_vcid);
2398 }
2399 else {
2400 vcid_addr = GET_CID_ADDR(vcid);
2401 pcid_addr = vcid_addr;
2402 }
2403
2404 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2405 vcid_addr += (i << PHY_CTX_SHIFT);
2406 pcid_addr += (i << PHY_CTX_SHIFT);
2407
2408 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2409 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2410
2411
2412 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2413 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2414 }
2415 }
2416}
2417
2418static int
2419bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2420{
2421 u16 *good_mbuf;
2422 u32 good_mbuf_cnt;
2423 u32 val;
2424
2425 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2426 if (good_mbuf == NULL) {
2427 printk(KERN_ERR PFX "Failed to allocate memory in "
2428 "bnx2_alloc_bad_rbuf\n");
2429 return -ENOMEM;
2430 }
2431
2432 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2433 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2434
2435 good_mbuf_cnt = 0;
2436
2437
2438 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2439 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2440 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2441 BNX2_RBUF_COMMAND_ALLOC_REQ);
2442
2443 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2444
2445 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2446
2447
2448 if (!(val & (1 << 9))) {
2449 good_mbuf[good_mbuf_cnt] = (u16) val;
2450 good_mbuf_cnt++;
2451 }
2452
2453 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2454 }
2455
2456
2457
2458 while (good_mbuf_cnt) {
2459 good_mbuf_cnt--;
2460
2461 val = good_mbuf[good_mbuf_cnt];
2462 val = (val << 9) | val | 1;
2463
2464 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2465 }
2466 kfree(good_mbuf);
2467 return 0;
2468}
2469
2470static void
2471bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2472{
2473 u32 val;
2474
2475 val = (mac_addr[0] << 8) | mac_addr[1];
2476
2477 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2478
2479 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2480 (mac_addr[4] << 8) | mac_addr[5];
2481
2482 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2483}
2484
2485static inline int
2486bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2487{
2488 dma_addr_t mapping;
2489 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2490 struct rx_bd *rxbd =
2491 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2492 struct page *page = alloc_page(GFP_ATOMIC);
2493
2494 if (!page)
2495 return -ENOMEM;
2496 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2497 PCI_DMA_FROMDEVICE);
2498 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2499 __free_page(page);
2500 return -EIO;
2501 }
2502
2503 rx_pg->page = page;
2504 pci_unmap_addr_set(rx_pg, mapping, mapping);
2505 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2506 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2507 return 0;
2508}
2509
2510static void
2511bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2512{
2513 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2514 struct page *page = rx_pg->page;
2515
2516 if (!page)
2517 return;
2518
2519 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2520 PCI_DMA_FROMDEVICE);
2521
2522 __free_page(page);
2523 rx_pg->page = NULL;
2524}
2525
2526static inline int
2527bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2528{
2529 struct sk_buff *skb;
2530 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2531 dma_addr_t mapping;
2532 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2533 unsigned long align;
2534
2535 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2536 if (skb == NULL) {
2537 return -ENOMEM;
2538 }
2539
2540 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2541 skb_reserve(skb, BNX2_RX_ALIGN - align);
2542
2543 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2544 PCI_DMA_FROMDEVICE);
2545 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2546 dev_kfree_skb(skb);
2547 return -EIO;
2548 }
2549
2550 rx_buf->skb = skb;
2551 pci_unmap_addr_set(rx_buf, mapping, mapping);
2552
2553 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2554 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2555
2556 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2557
2558 return 0;
2559}
2560
2561static int
2562bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2563{
2564 struct status_block *sblk = bnapi->status_blk.msi;
2565 u32 new_link_state, old_link_state;
2566 int is_set = 1;
2567
2568 new_link_state = sblk->status_attn_bits & event;
2569 old_link_state = sblk->status_attn_bits_ack & event;
2570 if (new_link_state != old_link_state) {
2571 if (new_link_state)
2572 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2573 else
2574 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2575 } else
2576 is_set = 0;
2577
2578 return is_set;
2579}
2580
2581static void
2582bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2583{
2584 spin_lock(&bp->phy_lock);
2585
2586 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2587 bnx2_set_link(bp);
2588 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2589 bnx2_set_remote_link(bp);
2590
2591 spin_unlock(&bp->phy_lock);
2592
2593}
2594
2595static inline u16
2596bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2597{
2598 u16 cons;
2599
2600
2601 barrier();
2602 cons = *bnapi->hw_tx_cons_ptr;
2603 barrier();
2604 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2605 cons++;
2606 return cons;
2607}
2608
2609static int
2610bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2611{
2612 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2613 u16 hw_cons, sw_cons, sw_ring_cons;
2614 int tx_pkt = 0, index;
2615 struct netdev_queue *txq;
2616
2617 index = (bnapi - bp->bnx2_napi);
2618 txq = netdev_get_tx_queue(bp->dev, index);
2619
2620 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2621 sw_cons = txr->tx_cons;
2622
2623 while (sw_cons != hw_cons) {
2624 struct sw_tx_bd *tx_buf;
2625 struct sk_buff *skb;
2626 int i, last;
2627
2628 sw_ring_cons = TX_RING_IDX(sw_cons);
2629
2630 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2631 skb = tx_buf->skb;
2632
2633
2634 if (skb_is_gso(skb)) {
2635 u16 last_idx, last_ring_idx;
2636
2637 last_idx = sw_cons +
2638 skb_shinfo(skb)->nr_frags + 1;
2639 last_ring_idx = sw_ring_cons +
2640 skb_shinfo(skb)->nr_frags + 1;
2641 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2642 last_idx++;
2643 }
2644 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2645 break;
2646 }
2647 }
2648
2649 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
2650
2651 tx_buf->skb = NULL;
2652 last = skb_shinfo(skb)->nr_frags;
2653
2654 for (i = 0; i < last; i++) {
2655 sw_cons = NEXT_TX_BD(sw_cons);
2656 }
2657
2658 sw_cons = NEXT_TX_BD(sw_cons);
2659
2660 dev_kfree_skb(skb);
2661 tx_pkt++;
2662 if (tx_pkt == budget)
2663 break;
2664
2665 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2666 }
2667
2668 txr->hw_tx_cons = hw_cons;
2669 txr->tx_cons = sw_cons;
2670
2671
2672
2673
2674
2675
2676 smp_mb();
2677
2678 if (unlikely(netif_tx_queue_stopped(txq)) &&
2679 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2680 __netif_tx_lock(txq, smp_processor_id());
2681 if ((netif_tx_queue_stopped(txq)) &&
2682 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2683 netif_tx_wake_queue(txq);
2684 __netif_tx_unlock(txq);
2685 }
2686
2687 return tx_pkt;
2688}
2689
2690static void
2691bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2692 struct sk_buff *skb, int count)
2693{
2694 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2695 struct rx_bd *cons_bd, *prod_bd;
2696 int i;
2697 u16 hw_prod, prod;
2698 u16 cons = rxr->rx_pg_cons;
2699
2700 cons_rx_pg = &rxr->rx_pg_ring[cons];
2701
2702
2703
2704
2705
2706 if (skb) {
2707 struct page *page;
2708 struct skb_shared_info *shinfo;
2709
2710 shinfo = skb_shinfo(skb);
2711 shinfo->nr_frags--;
2712 page = shinfo->frags[shinfo->nr_frags].page;
2713 shinfo->frags[shinfo->nr_frags].page = NULL;
2714
2715 cons_rx_pg->page = page;
2716 dev_kfree_skb(skb);
2717 }
2718
2719 hw_prod = rxr->rx_pg_prod;
2720
2721 for (i = 0; i < count; i++) {
2722 prod = RX_PG_RING_IDX(hw_prod);
2723
2724 prod_rx_pg = &rxr->rx_pg_ring[prod];
2725 cons_rx_pg = &rxr->rx_pg_ring[cons];
2726 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2727 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2728
2729 if (prod != cons) {
2730 prod_rx_pg->page = cons_rx_pg->page;
2731 cons_rx_pg->page = NULL;
2732 pci_unmap_addr_set(prod_rx_pg, mapping,
2733 pci_unmap_addr(cons_rx_pg, mapping));
2734
2735 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2736 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2737
2738 }
2739 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2740 hw_prod = NEXT_RX_BD(hw_prod);
2741 }
2742 rxr->rx_pg_prod = hw_prod;
2743 rxr->rx_pg_cons = cons;
2744}
2745
2746static inline void
2747bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2748 struct sk_buff *skb, u16 cons, u16 prod)
2749{
2750 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2751 struct rx_bd *cons_bd, *prod_bd;
2752
2753 cons_rx_buf = &rxr->rx_buf_ring[cons];
2754 prod_rx_buf = &rxr->rx_buf_ring[prod];
2755
2756 pci_dma_sync_single_for_device(bp->pdev,
2757 pci_unmap_addr(cons_rx_buf, mapping),
2758 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2759
2760 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2761
2762 prod_rx_buf->skb = skb;
2763
2764 if (cons == prod)
2765 return;
2766
2767 pci_unmap_addr_set(prod_rx_buf, mapping,
2768 pci_unmap_addr(cons_rx_buf, mapping));
2769
2770 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2771 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2772 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2773 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2774}
2775
2776static int
2777bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2778 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2779 u32 ring_idx)
2780{
2781 int err;
2782 u16 prod = ring_idx & 0xffff;
2783
2784 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2785 if (unlikely(err)) {
2786 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2787 if (hdr_len) {
2788 unsigned int raw_len = len + 4;
2789 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2790
2791 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2792 }
2793 return err;
2794 }
2795
2796 skb_reserve(skb, BNX2_RX_OFFSET);
2797 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2798 PCI_DMA_FROMDEVICE);
2799
2800 if (hdr_len == 0) {
2801 skb_put(skb, len);
2802 return 0;
2803 } else {
2804 unsigned int i, frag_len, frag_size, pages;
2805 struct sw_pg *rx_pg;
2806 u16 pg_cons = rxr->rx_pg_cons;
2807 u16 pg_prod = rxr->rx_pg_prod;
2808
2809 frag_size = len + 4 - hdr_len;
2810 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2811 skb_put(skb, hdr_len);
2812
2813 for (i = 0; i < pages; i++) {
2814 dma_addr_t mapping_old;
2815
2816 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2817 if (unlikely(frag_len <= 4)) {
2818 unsigned int tail = 4 - frag_len;
2819
2820 rxr->rx_pg_cons = pg_cons;
2821 rxr->rx_pg_prod = pg_prod;
2822 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2823 pages - i);
2824 skb->len -= tail;
2825 if (i == 0) {
2826 skb->tail -= tail;
2827 } else {
2828 skb_frag_t *frag =
2829 &skb_shinfo(skb)->frags[i - 1];
2830 frag->size -= tail;
2831 skb->data_len -= tail;
2832 skb->truesize -= tail;
2833 }
2834 return 0;
2835 }
2836 rx_pg = &rxr->rx_pg_ring[pg_cons];
2837
2838
2839
2840
2841 mapping_old = pci_unmap_addr(rx_pg, mapping);
2842 if (i == pages - 1)
2843 frag_len -= 4;
2844
2845 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2846 rx_pg->page = NULL;
2847
2848 err = bnx2_alloc_rx_page(bp, rxr,
2849 RX_PG_RING_IDX(pg_prod));
2850 if (unlikely(err)) {
2851 rxr->rx_pg_cons = pg_cons;
2852 rxr->rx_pg_prod = pg_prod;
2853 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
2854 pages - i);
2855 return err;
2856 }
2857
2858 pci_unmap_page(bp->pdev, mapping_old,
2859 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2860
2861 frag_size -= frag_len;
2862 skb->data_len += frag_len;
2863 skb->truesize += frag_len;
2864 skb->len += frag_len;
2865
2866 pg_prod = NEXT_RX_BD(pg_prod);
2867 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2868 }
2869 rxr->rx_pg_prod = pg_prod;
2870 rxr->rx_pg_cons = pg_cons;
2871 }
2872 return 0;
2873}
2874
2875static inline u16
2876bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2877{
2878 u16 cons;
2879
2880
2881 barrier();
2882 cons = *bnapi->hw_rx_cons_ptr;
2883 barrier();
2884 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2885 cons++;
2886 return cons;
2887}
2888
2889static int
2890bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2891{
2892 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2893 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2894 struct l2_fhdr *rx_hdr;
2895 int rx_pkt = 0, pg_ring_used = 0;
2896
2897 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2898 sw_cons = rxr->rx_cons;
2899 sw_prod = rxr->rx_prod;
2900
2901
2902
2903
2904 rmb();
2905 while (sw_cons != hw_cons) {
2906 unsigned int len, hdr_len;
2907 u32 status;
2908 struct sw_bd *rx_buf;
2909 struct sk_buff *skb;
2910 dma_addr_t dma_addr;
2911 u16 vtag = 0;
2912 int hw_vlan __maybe_unused = 0;
2913
2914 sw_ring_cons = RX_RING_IDX(sw_cons);
2915 sw_ring_prod = RX_RING_IDX(sw_prod);
2916
2917 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
2918 skb = rx_buf->skb;
2919
2920 rx_buf->skb = NULL;
2921
2922 dma_addr = pci_unmap_addr(rx_buf, mapping);
2923
2924 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2925 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2926 PCI_DMA_FROMDEVICE);
2927
2928 rx_hdr = (struct l2_fhdr *) skb->data;
2929 len = rx_hdr->l2_fhdr_pkt_len;
2930 status = rx_hdr->l2_fhdr_status;
2931
2932 hdr_len = 0;
2933 if (status & L2_FHDR_STATUS_SPLIT) {
2934 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2935 pg_ring_used = 1;
2936 } else if (len > bp->rx_jumbo_thresh) {
2937 hdr_len = bp->rx_jumbo_thresh;
2938 pg_ring_used = 1;
2939 }
2940
2941 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
2942 L2_FHDR_ERRORS_PHY_DECODE |
2943 L2_FHDR_ERRORS_ALIGNMENT |
2944 L2_FHDR_ERRORS_TOO_SHORT |
2945 L2_FHDR_ERRORS_GIANT_FRAME))) {
2946
2947 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2948 sw_ring_prod);
2949 if (pg_ring_used) {
2950 int pages;
2951
2952 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
2953
2954 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2955 }
2956 goto next_rx;
2957 }
2958
2959 len -= 4;
2960
2961 if (len <= bp->rx_copy_thresh) {
2962 struct sk_buff *new_skb;
2963
2964 new_skb = netdev_alloc_skb(bp->dev, len + 6);
2965 if (new_skb == NULL) {
2966 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2967 sw_ring_prod);
2968 goto next_rx;
2969 }
2970
2971
2972 skb_copy_from_linear_data_offset(skb,
2973 BNX2_RX_OFFSET - 6,
2974 new_skb->data, len + 6);
2975 skb_reserve(new_skb, 6);
2976 skb_put(new_skb, len);
2977
2978 bnx2_reuse_rx_skb(bp, rxr, skb,
2979 sw_ring_cons, sw_ring_prod);
2980
2981 skb = new_skb;
2982 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
2983 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2984 goto next_rx;
2985
2986 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2987 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2988 vtag = rx_hdr->l2_fhdr_vlan_tag;
2989#ifdef BCM_VLAN
2990 if (bp->vlgrp)
2991 hw_vlan = 1;
2992 else
2993#endif
2994 {
2995 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2996 __skb_push(skb, 4);
2997
2998 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2999 ve->h_vlan_proto = htons(ETH_P_8021Q);
3000 ve->h_vlan_TCI = htons(vtag);
3001 len += 4;
3002 }
3003 }
3004
3005 skb->protocol = eth_type_trans(skb, bp->dev);
3006
3007 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3008 (ntohs(skb->protocol) != 0x8100)) {
3009
3010 dev_kfree_skb(skb);
3011 goto next_rx;
3012
3013 }
3014
3015 skb->ip_summed = CHECKSUM_NONE;
3016 if (bp->rx_csum &&
3017 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3018 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3019
3020 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3021 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3022 skb->ip_summed = CHECKSUM_UNNECESSARY;
3023 }
3024
3025 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3026
3027#ifdef BCM_VLAN
3028 if (hw_vlan)
3029 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3030 else
3031#endif
3032 netif_receive_skb(skb);
3033
3034 rx_pkt++;
3035
3036next_rx:
3037 sw_cons = NEXT_RX_BD(sw_cons);
3038 sw_prod = NEXT_RX_BD(sw_prod);
3039
3040 if ((rx_pkt == budget))
3041 break;
3042
3043
3044 if (sw_cons == hw_cons) {
3045 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3046 rmb();
3047 }
3048 }
3049 rxr->rx_cons = sw_cons;
3050 rxr->rx_prod = sw_prod;
3051
3052 if (pg_ring_used)
3053 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3054
3055 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3056
3057 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3058
3059 mmiowb();
3060
3061 return rx_pkt;
3062
3063}
3064
3065
3066
3067
3068static irqreturn_t
3069bnx2_msi(int irq, void *dev_instance)
3070{
3071 struct bnx2_napi *bnapi = dev_instance;
3072 struct bnx2 *bp = bnapi->bp;
3073
3074 prefetch(bnapi->status_blk.msi);
3075 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3076 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3077 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3078
3079
3080 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3081 return IRQ_HANDLED;
3082
3083 napi_schedule(&bnapi->napi);
3084
3085 return IRQ_HANDLED;
3086}
3087
3088static irqreturn_t
3089bnx2_msi_1shot(int irq, void *dev_instance)
3090{
3091 struct bnx2_napi *bnapi = dev_instance;
3092 struct bnx2 *bp = bnapi->bp;
3093
3094 prefetch(bnapi->status_blk.msi);
3095
3096
3097 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3098 return IRQ_HANDLED;
3099
3100 napi_schedule(&bnapi->napi);
3101
3102 return IRQ_HANDLED;
3103}
3104
3105static irqreturn_t
3106bnx2_interrupt(int irq, void *dev_instance)
3107{
3108 struct bnx2_napi *bnapi = dev_instance;
3109 struct bnx2 *bp = bnapi->bp;
3110 struct status_block *sblk = bnapi->status_blk.msi;
3111
3112
3113
3114
3115
3116
3117
3118 if ((sblk->status_idx == bnapi->last_status_idx) &&
3119 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3120 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3121 return IRQ_NONE;
3122
3123 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3124 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3125 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3126
3127
3128
3129
3130 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3131
3132
3133 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3134 return IRQ_HANDLED;
3135
3136 if (napi_schedule_prep(&bnapi->napi)) {
3137 bnapi->last_status_idx = sblk->status_idx;
3138 __napi_schedule(&bnapi->napi);
3139 }
3140
3141 return IRQ_HANDLED;
3142}
3143
3144static inline int
3145bnx2_has_fast_work(struct bnx2_napi *bnapi)
3146{
3147 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3148 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3149
3150 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3151 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3152 return 1;
3153 return 0;
3154}
3155
3156#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3157 STATUS_ATTN_BITS_TIMER_ABORT)
3158
3159static inline int
3160bnx2_has_work(struct bnx2_napi *bnapi)
3161{
3162 struct status_block *sblk = bnapi->status_blk.msi;
3163
3164 if (bnx2_has_fast_work(bnapi))
3165 return 1;
3166
3167 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3168 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3169 return 1;
3170
3171 return 0;
3172}
3173
3174static void
3175bnx2_chk_missed_msi(struct bnx2 *bp)
3176{
3177 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3178 u32 msi_ctrl;
3179
3180 if (bnx2_has_work(bnapi)) {
3181 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3182 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3183 return;
3184
3185 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3186 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3187 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3188 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3189 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3190 }
3191 }
3192
3193 bp->idle_chk_status_idx = bnapi->last_status_idx;
3194}
3195
3196static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3197{
3198 struct status_block *sblk = bnapi->status_blk.msi;
3199 u32 status_attn_bits = sblk->status_attn_bits;
3200 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3201
3202 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3203 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3204
3205 bnx2_phy_int(bp, bnapi);
3206
3207
3208
3209
3210 REG_WR(bp, BNX2_HC_COMMAND,
3211 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3212 REG_RD(bp, BNX2_HC_COMMAND);
3213 }
3214}
3215
3216static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3217 int work_done, int budget)
3218{
3219 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3220 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3221
3222 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3223 bnx2_tx_int(bp, bnapi, 0);
3224
3225 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3226 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3227
3228 return work_done;
3229}
3230
3231static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3232{
3233 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3234 struct bnx2 *bp = bnapi->bp;
3235 int work_done = 0;
3236 struct status_block_msix *sblk = bnapi->status_blk.msix;
3237
3238 while (1) {
3239 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3240 if (unlikely(work_done >= budget))
3241 break;
3242
3243 bnapi->last_status_idx = sblk->status_idx;
3244
3245 rmb();
3246 if (likely(!bnx2_has_fast_work(bnapi))) {
3247
3248 napi_complete(napi);
3249 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3250 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3251 bnapi->last_status_idx);
3252 break;
3253 }
3254 }
3255 return work_done;
3256}
3257
3258static int bnx2_poll(struct napi_struct *napi, int budget)
3259{
3260 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3261 struct bnx2 *bp = bnapi->bp;
3262 int work_done = 0;
3263 struct status_block *sblk = bnapi->status_blk.msi;
3264
3265 while (1) {
3266 bnx2_poll_link(bp, bnapi);
3267
3268 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3269
3270
3271
3272
3273
3274 bnapi->last_status_idx = sblk->status_idx;
3275
3276 if (unlikely(work_done >= budget))
3277 break;
3278
3279 rmb();
3280 if (likely(!bnx2_has_work(bnapi))) {
3281 napi_complete(napi);
3282 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3283 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3284 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3285 bnapi->last_status_idx);
3286 break;
3287 }
3288 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3289 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3290 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3291 bnapi->last_status_idx);
3292
3293 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3294 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3295 bnapi->last_status_idx);
3296 break;
3297 }
3298 }
3299
3300 return work_done;
3301}
3302
3303
3304
3305
3306static void
3307bnx2_set_rx_mode(struct net_device *dev)
3308{
3309 struct bnx2 *bp = netdev_priv(dev);
3310 u32 rx_mode, sort_mode;
3311 struct dev_addr_list *uc_ptr;
3312 int i;
3313
3314 if (!netif_running(dev))
3315 return;
3316
3317 spin_lock_bh(&bp->phy_lock);
3318
3319 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3320 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3321 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3322#ifdef BCM_VLAN
3323 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3324 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3325#else
3326 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3327 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3328#endif
3329 if (dev->flags & IFF_PROMISC) {
3330
3331 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3332 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3333 BNX2_RPM_SORT_USER0_PROM_VLAN;
3334 }
3335 else if (dev->flags & IFF_ALLMULTI) {
3336 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3337 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3338 0xffffffff);
3339 }
3340 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3341 }
3342 else {
3343
3344 struct dev_mc_list *mclist;
3345 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3346 u32 regidx;
3347 u32 bit;
3348 u32 crc;
3349
3350 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3351
3352 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3353 i++, mclist = mclist->next) {
3354
3355 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3356 bit = crc & 0xff;
3357 regidx = (bit & 0xe0) >> 5;
3358 bit &= 0x1f;
3359 mc_filter[regidx] |= (1 << bit);
3360 }
3361
3362 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3363 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3364 mc_filter[i]);
3365 }
3366
3367 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3368 }
3369
3370 uc_ptr = NULL;
3371 if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3372 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3373 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3374 BNX2_RPM_SORT_USER0_PROM_VLAN;
3375 } else if (!(dev->flags & IFF_PROMISC)) {
3376 uc_ptr = dev->uc_list;
3377
3378
3379 for (i = 0; i < dev->uc_count; i++) {
3380 bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3381 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3382 sort_mode |= (1 <<
3383 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3384 uc_ptr = uc_ptr->next;
3385 }
3386
3387 }
3388
3389 if (rx_mode != bp->rx_mode) {
3390 bp->rx_mode = rx_mode;
3391 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3392 }
3393
3394 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3395 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3396 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3397
3398 spin_unlock_bh(&bp->phy_lock);
3399}
3400
3401static int __devinit
3402check_fw_section(const struct firmware *fw,
3403 const struct bnx2_fw_file_section *section,
3404 u32 alignment, bool non_empty)
3405{
3406 u32 offset = be32_to_cpu(section->offset);
3407 u32 len = be32_to_cpu(section->len);
3408
3409 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3410 return -EINVAL;
3411 if ((non_empty && len == 0) || len > fw->size - offset ||
3412 len & (alignment - 1))
3413 return -EINVAL;
3414 return 0;
3415}
3416
3417static int __devinit
3418check_mips_fw_entry(const struct firmware *fw,
3419 const struct bnx2_mips_fw_file_entry *entry)
3420{
3421 if (check_fw_section(fw, &entry->text, 4, true) ||
3422 check_fw_section(fw, &entry->data, 4, false) ||
3423 check_fw_section(fw, &entry->rodata, 4, false))
3424 return -EINVAL;
3425 return 0;
3426}
3427
3428static int __devinit
3429bnx2_request_firmware(struct bnx2 *bp)
3430{
3431 const char *mips_fw_file, *rv2p_fw_file;
3432 const struct bnx2_mips_fw_file *mips_fw;
3433 const struct bnx2_rv2p_fw_file *rv2p_fw;
3434 int rc;
3435
3436 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3437 mips_fw_file = FW_MIPS_FILE_09;
3438 rv2p_fw_file = FW_RV2P_FILE_09;
3439 } else {
3440 mips_fw_file = FW_MIPS_FILE_06;
3441 rv2p_fw_file = FW_RV2P_FILE_06;
3442 }
3443
3444 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3445 if (rc) {
3446 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3447 mips_fw_file);
3448 return rc;
3449 }
3450
3451 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3452 if (rc) {
3453 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3454 rv2p_fw_file);
3455 return rc;
3456 }
3457 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3458 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3459 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3460 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3461 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3462 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3463 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3464 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3465 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3466 mips_fw_file);
3467 return -EINVAL;
3468 }
3469 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3470 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3471 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3472 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3473 rv2p_fw_file);
3474 return -EINVAL;
3475 }
3476
3477 return 0;
3478}
3479
3480static u32
3481rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3482{
3483 switch (idx) {
3484 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3485 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3486 rv2p_code |= RV2P_BD_PAGE_SIZE;
3487 break;
3488 }
3489 return rv2p_code;
3490}
3491
3492static int
3493load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3494 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3495{
3496 u32 rv2p_code_len, file_offset;
3497 __be32 *rv2p_code;
3498 int i;
3499 u32 val, cmd, addr;
3500
3501 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3502 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3503
3504 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3505
3506 if (rv2p_proc == RV2P_PROC1) {
3507 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3508 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3509 } else {
3510 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3511 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3512 }
3513
3514 for (i = 0; i < rv2p_code_len; i += 8) {
3515 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3516 rv2p_code++;
3517 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3518 rv2p_code++;
3519
3520 val = (i / 8) | cmd;
3521 REG_WR(bp, addr, val);
3522 }
3523
3524 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3525 for (i = 0; i < 8; i++) {
3526 u32 loc, code;
3527
3528 loc = be32_to_cpu(fw_entry->fixup[i]);
3529 if (loc && ((loc * 4) < rv2p_code_len)) {
3530 code = be32_to_cpu(*(rv2p_code + loc - 1));
3531 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3532 code = be32_to_cpu(*(rv2p_code + loc));
3533 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3534 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3535
3536 val = (loc / 2) | cmd;
3537 REG_WR(bp, addr, val);
3538 }
3539 }
3540
3541
3542 if (rv2p_proc == RV2P_PROC1) {
3543 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3544 }
3545 else {
3546 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3547 }
3548
3549 return 0;
3550}
3551
3552static int
3553load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3554 const struct bnx2_mips_fw_file_entry *fw_entry)
3555{
3556 u32 addr, len, file_offset;
3557 __be32 *data;
3558 u32 offset;
3559 u32 val;
3560
3561
3562 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3563 val |= cpu_reg->mode_value_halt;
3564 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3565 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3566
3567
3568 addr = be32_to_cpu(fw_entry->text.addr);
3569 len = be32_to_cpu(fw_entry->text.len);
3570 file_offset = be32_to_cpu(fw_entry->text.offset);
3571 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3572
3573 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3574 if (len) {
3575 int j;
3576
3577 for (j = 0; j < (len / 4); j++, offset += 4)
3578 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3579 }
3580
3581
3582 addr = be32_to_cpu(fw_entry->data.addr);
3583 len = be32_to_cpu(fw_entry->data.len);
3584 file_offset = be32_to_cpu(fw_entry->data.offset);
3585 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3586
3587 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3588 if (len) {
3589 int j;
3590
3591 for (j = 0; j < (len / 4); j++, offset += 4)
3592 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3593 }
3594
3595
3596 addr = be32_to_cpu(fw_entry->rodata.addr);
3597 len = be32_to_cpu(fw_entry->rodata.len);
3598 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3599 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3600
3601 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3602 if (len) {
3603 int j;
3604
3605 for (j = 0; j < (len / 4); j++, offset += 4)
3606 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3607 }
3608
3609
3610 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3611
3612 val = be32_to_cpu(fw_entry->start_addr);
3613 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3614
3615
3616 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3617 val &= ~cpu_reg->mode_value_halt;
3618 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3619 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3620
3621 return 0;
3622}
3623
3624static int
3625bnx2_init_cpus(struct bnx2 *bp)
3626{
3627 const struct bnx2_mips_fw_file *mips_fw =
3628 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3629 const struct bnx2_rv2p_fw_file *rv2p_fw =
3630 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3631 int rc;
3632
3633
3634 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3635 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3636
3637
3638 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3639 if (rc)
3640 goto init_cpu_err;
3641
3642
3643 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3644 if (rc)
3645 goto init_cpu_err;
3646
3647
3648 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3649 if (rc)
3650 goto init_cpu_err;
3651
3652
3653 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3654 if (rc)
3655 goto init_cpu_err;
3656
3657
3658 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3659
3660init_cpu_err:
3661 return rc;
3662}
3663
3664static int
3665bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3666{
3667 u16 pmcsr;
3668
3669 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3670
3671 switch (state) {
3672 case PCI_D0: {
3673 u32 val;
3674
3675 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3676 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3677 PCI_PM_CTRL_PME_STATUS);
3678
3679 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3680
3681 msleep(20);
3682
3683 val = REG_RD(bp, BNX2_EMAC_MODE);
3684 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3685 val &= ~BNX2_EMAC_MODE_MPKT;
3686 REG_WR(bp, BNX2_EMAC_MODE, val);
3687
3688 val = REG_RD(bp, BNX2_RPM_CONFIG);
3689 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3690 REG_WR(bp, BNX2_RPM_CONFIG, val);
3691 break;
3692 }
3693 case PCI_D3hot: {
3694 int i;
3695 u32 val, wol_msg;
3696
3697 if (bp->wol) {
3698 u32 advertising;
3699 u8 autoneg;
3700
3701 autoneg = bp->autoneg;
3702 advertising = bp->advertising;
3703
3704 if (bp->phy_port == PORT_TP) {
3705 bp->autoneg = AUTONEG_SPEED;
3706 bp->advertising = ADVERTISED_10baseT_Half |
3707 ADVERTISED_10baseT_Full |
3708 ADVERTISED_100baseT_Half |
3709 ADVERTISED_100baseT_Full |
3710 ADVERTISED_Autoneg;
3711 }
3712
3713 spin_lock_bh(&bp->phy_lock);
3714 bnx2_setup_phy(bp, bp->phy_port);
3715 spin_unlock_bh(&bp->phy_lock);
3716
3717 bp->autoneg = autoneg;
3718 bp->advertising = advertising;
3719
3720 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3721
3722 val = REG_RD(bp, BNX2_EMAC_MODE);
3723
3724
3725 val &= ~BNX2_EMAC_MODE_PORT;
3726 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3727 BNX2_EMAC_MODE_ACPI_RCVD |
3728 BNX2_EMAC_MODE_MPKT;
3729 if (bp->phy_port == PORT_TP)
3730 val |= BNX2_EMAC_MODE_PORT_MII;
3731 else {
3732 val |= BNX2_EMAC_MODE_PORT_GMII;
3733 if (bp->line_speed == SPEED_2500)
3734 val |= BNX2_EMAC_MODE_25G_MODE;
3735 }
3736
3737 REG_WR(bp, BNX2_EMAC_MODE, val);
3738
3739
3740 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3741 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3742 0xffffffff);
3743 }
3744 REG_WR(bp, BNX2_EMAC_RX_MODE,
3745 BNX2_EMAC_RX_MODE_SORT_MODE);
3746
3747 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3748 BNX2_RPM_SORT_USER0_MC_EN;
3749 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3750 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3751 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3752 BNX2_RPM_SORT_USER0_ENA);
3753
3754
3755 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3756 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3757 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3758 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3759
3760 val = REG_RD(bp, BNX2_RPM_CONFIG);
3761 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3762 REG_WR(bp, BNX2_RPM_CONFIG, val);
3763
3764 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3765 }
3766 else {
3767 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3768 }
3769
3770 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3771 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3772 1, 0);
3773
3774 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3775 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3776 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3777
3778 if (bp->wol)
3779 pmcsr |= 3;
3780 }
3781 else {
3782 pmcsr |= 3;
3783 }
3784 if (bp->wol) {
3785 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3786 }
3787 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3788 pmcsr);
3789
3790
3791
3792
3793 udelay(50);
3794 break;
3795 }
3796 default:
3797 return -EINVAL;
3798 }
3799 return 0;
3800}
3801
3802static int
3803bnx2_acquire_nvram_lock(struct bnx2 *bp)
3804{
3805 u32 val;
3806 int j;
3807
3808
3809 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3810 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3811 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3812 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3813 break;
3814
3815 udelay(5);
3816 }
3817
3818 if (j >= NVRAM_TIMEOUT_COUNT)
3819 return -EBUSY;
3820
3821 return 0;
3822}
3823
3824static int
3825bnx2_release_nvram_lock(struct bnx2 *bp)
3826{
3827 int j;
3828 u32 val;
3829
3830
3831 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3832
3833 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3834 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3835 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3836 break;
3837
3838 udelay(5);
3839 }
3840
3841 if (j >= NVRAM_TIMEOUT_COUNT)
3842 return -EBUSY;
3843
3844 return 0;
3845}
3846
3847
3848static int
3849bnx2_enable_nvram_write(struct bnx2 *bp)
3850{
3851 u32 val;
3852
3853 val = REG_RD(bp, BNX2_MISC_CFG);
3854 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3855
3856 if (bp->flash_info->flags & BNX2_NV_WREN) {
3857 int j;
3858
3859 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3860 REG_WR(bp, BNX2_NVM_COMMAND,
3861 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3862
3863 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3864 udelay(5);
3865
3866 val = REG_RD(bp, BNX2_NVM_COMMAND);
3867 if (val & BNX2_NVM_COMMAND_DONE)
3868 break;
3869 }
3870
3871 if (j >= NVRAM_TIMEOUT_COUNT)
3872 return -EBUSY;
3873 }
3874 return 0;
3875}
3876
3877static void
3878bnx2_disable_nvram_write(struct bnx2 *bp)
3879{
3880 u32 val;
3881
3882 val = REG_RD(bp, BNX2_MISC_CFG);
3883 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3884}
3885
3886
3887static void
3888bnx2_enable_nvram_access(struct bnx2 *bp)
3889{
3890 u32 val;
3891
3892 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3893
3894 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3895 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3896}
3897
3898static void
3899bnx2_disable_nvram_access(struct bnx2 *bp)
3900{
3901 u32 val;
3902
3903 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3904
3905 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3906 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3907 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3908}
3909
3910static int
3911bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3912{
3913 u32 cmd;
3914 int j;
3915
3916 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3917
3918 return 0;
3919
3920
3921 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3922 BNX2_NVM_COMMAND_DOIT;
3923
3924
3925 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3926
3927
3928 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3929
3930
3931 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3932
3933
3934 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3935 u32 val;
3936
3937 udelay(5);
3938
3939 val = REG_RD(bp, BNX2_NVM_COMMAND);
3940 if (val & BNX2_NVM_COMMAND_DONE)
3941 break;
3942 }
3943
3944 if (j >= NVRAM_TIMEOUT_COUNT)
3945 return -EBUSY;
3946
3947 return 0;
3948}
3949
3950static int
3951bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3952{
3953 u32 cmd;
3954 int j;
3955
3956
3957 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3958
3959
3960 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3961 offset = ((offset / bp->flash_info->page_size) <<
3962 bp->flash_info->page_bits) +
3963 (offset % bp->flash_info->page_size);
3964 }
3965
3966
3967 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3968
3969
3970 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3971
3972
3973 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3974
3975
3976 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3977 u32 val;
3978
3979 udelay(5);
3980
3981 val = REG_RD(bp, BNX2_NVM_COMMAND);
3982 if (val & BNX2_NVM_COMMAND_DONE) {
3983 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3984 memcpy(ret_val, &v, 4);
3985 break;
3986 }
3987 }
3988 if (j >= NVRAM_TIMEOUT_COUNT)
3989 return -EBUSY;
3990
3991 return 0;
3992}
3993
3994
3995static int
3996bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3997{
3998 u32 cmd;
3999 __be32 val32;
4000 int j;
4001
4002
4003 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4004
4005
4006 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4007 offset = ((offset / bp->flash_info->page_size) <<
4008 bp->flash_info->page_bits) +
4009 (offset % bp->flash_info->page_size);
4010 }
4011
4012
4013 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4014
4015 memcpy(&val32, val, 4);
4016
4017
4018 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4019
4020
4021 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4022
4023
4024 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4025
4026
4027 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4028 udelay(5);
4029
4030 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4031 break;
4032 }
4033 if (j >= NVRAM_TIMEOUT_COUNT)
4034 return -EBUSY;
4035
4036 return 0;
4037}
4038
4039static int
4040bnx2_init_nvram(struct bnx2 *bp)
4041{
4042 u32 val;
4043 int j, entry_count, rc = 0;
4044 struct flash_spec *flash;
4045
4046 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4047 bp->flash_info = &flash_5709;
4048 goto get_flash_size;
4049 }
4050
4051
4052 val = REG_RD(bp, BNX2_NVM_CFG1);
4053
4054 entry_count = ARRAY_SIZE(flash_table);
4055
4056 if (val & 0x40000000) {
4057
4058
4059 for (j = 0, flash = &flash_table[0]; j < entry_count;
4060 j++, flash++) {
4061 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4062 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4063 bp->flash_info = flash;
4064 break;
4065 }
4066 }
4067 }
4068 else {
4069 u32 mask;
4070
4071
4072 if (val & (1 << 23))
4073 mask = FLASH_BACKUP_STRAP_MASK;
4074 else
4075 mask = FLASH_STRAP_MASK;
4076
4077 for (j = 0, flash = &flash_table[0]; j < entry_count;
4078 j++, flash++) {
4079
4080 if ((val & mask) == (flash->strapping & mask)) {
4081 bp->flash_info = flash;
4082
4083
4084 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4085 return rc;
4086
4087
4088 bnx2_enable_nvram_access(bp);
4089
4090
4091 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4092 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4093 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4094 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4095
4096
4097 bnx2_disable_nvram_access(bp);
4098 bnx2_release_nvram_lock(bp);
4099
4100 break;
4101 }
4102 }
4103 }
4104
4105 if (j == entry_count) {
4106 bp->flash_info = NULL;
4107 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
4108 return -ENODEV;
4109 }
4110
4111get_flash_size:
4112 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4113 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4114 if (val)
4115 bp->flash_size = val;
4116 else
4117 bp->flash_size = bp->flash_info->total_size;
4118
4119 return rc;
4120}
4121
4122static int
4123bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4124 int buf_size)
4125{
4126 int rc = 0;
4127 u32 cmd_flags, offset32, len32, extra;
4128
4129 if (buf_size == 0)
4130 return 0;
4131
4132
4133 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4134 return rc;
4135
4136
4137 bnx2_enable_nvram_access(bp);
4138
4139 len32 = buf_size;
4140 offset32 = offset;
4141 extra = 0;
4142
4143 cmd_flags = 0;
4144
4145 if (offset32 & 3) {
4146 u8 buf[4];
4147 u32 pre_len;
4148
4149 offset32 &= ~3;
4150 pre_len = 4 - (offset & 3);
4151
4152 if (pre_len >= len32) {
4153 pre_len = len32;
4154 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4155 BNX2_NVM_COMMAND_LAST;
4156 }
4157 else {
4158 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4159 }
4160
4161 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4162
4163 if (rc)
4164 return rc;
4165
4166 memcpy(ret_buf, buf + (offset & 3), pre_len);
4167
4168 offset32 += 4;
4169 ret_buf += pre_len;
4170 len32 -= pre_len;
4171 }
4172 if (len32 & 3) {
4173 extra = 4 - (len32 & 3);
4174 len32 = (len32 + 4) & ~3;
4175 }
4176
4177 if (len32 == 4) {
4178 u8 buf[4];
4179
4180 if (cmd_flags)
4181 cmd_flags = BNX2_NVM_COMMAND_LAST;
4182 else
4183 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4184 BNX2_NVM_COMMAND_LAST;
4185
4186 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4187
4188 memcpy(ret_buf, buf, 4 - extra);
4189 }
4190 else if (len32 > 0) {
4191 u8 buf[4];
4192
4193
4194 if (cmd_flags)
4195 cmd_flags = 0;
4196 else
4197 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4198
4199 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4200
4201
4202 offset32 += 4;
4203 ret_buf += 4;
4204 len32 -= 4;
4205
4206 while (len32 > 4 && rc == 0) {
4207 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4208
4209
4210 offset32 += 4;
4211 ret_buf += 4;
4212 len32 -= 4;
4213 }
4214
4215 if (rc)
4216 return rc;
4217
4218 cmd_flags = BNX2_NVM_COMMAND_LAST;
4219 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4220
4221 memcpy(ret_buf, buf, 4 - extra);
4222 }
4223
4224
4225 bnx2_disable_nvram_access(bp);
4226
4227 bnx2_release_nvram_lock(bp);
4228
4229 return rc;
4230}
4231
4232static int
4233bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4234 int buf_size)
4235{
4236 u32 written, offset32, len32;
4237 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4238 int rc = 0;
4239 int align_start, align_end;
4240
4241 buf = data_buf;
4242 offset32 = offset;
4243 len32 = buf_size;
4244 align_start = align_end = 0;
4245
4246 if ((align_start = (offset32 & 3))) {
4247 offset32 &= ~3;
4248 len32 += align_start;
4249 if (len32 < 4)
4250 len32 = 4;
4251 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4252 return rc;
4253 }
4254
4255 if (len32 & 3) {
4256 align_end = 4 - (len32 & 3);
4257 len32 += align_end;
4258 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4259 return rc;
4260 }
4261
4262 if (align_start || align_end) {
4263 align_buf = kmalloc(len32, GFP_KERNEL);
4264 if (align_buf == NULL)
4265 return -ENOMEM;
4266 if (align_start) {
4267 memcpy(align_buf, start, 4);
4268 }
4269 if (align_end) {
4270 memcpy(align_buf + len32 - 4, end, 4);
4271 }
4272 memcpy(align_buf + align_start, data_buf, buf_size);
4273 buf = align_buf;
4274 }
4275
4276 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4277 flash_buffer = kmalloc(264, GFP_KERNEL);
4278 if (flash_buffer == NULL) {
4279 rc = -ENOMEM;
4280 goto nvram_write_end;
4281 }
4282 }
4283
4284 written = 0;
4285 while ((written < len32) && (rc == 0)) {
4286 u32 page_start, page_end, data_start, data_end;
4287 u32 addr, cmd_flags;
4288 int i;
4289
4290
4291 page_start = offset32 + written;
4292 page_start -= (page_start % bp->flash_info->page_size);
4293
4294 page_end = page_start + bp->flash_info->page_size;
4295
4296 data_start = (written == 0) ? offset32 : page_start;
4297
4298 data_end = (page_end > offset32 + len32) ?
4299 (offset32 + len32) : page_end;
4300
4301
4302 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4303 goto nvram_write_end;
4304
4305
4306 bnx2_enable_nvram_access(bp);
4307
4308 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4309 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4310 int j;
4311
4312
4313
4314 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4315 if (j == (bp->flash_info->page_size - 4)) {
4316 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4317 }
4318 rc = bnx2_nvram_read_dword(bp,
4319 page_start + j,
4320 &flash_buffer[j],
4321 cmd_flags);
4322
4323 if (rc)
4324 goto nvram_write_end;
4325
4326 cmd_flags = 0;
4327 }
4328 }
4329
4330
4331 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4332 goto nvram_write_end;
4333
4334
4335
4336 i = 0;
4337 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4338
4339 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4340 goto nvram_write_end;
4341
4342
4343 bnx2_enable_nvram_write(bp);
4344
4345 for (addr = page_start; addr < data_start;
4346 addr += 4, i += 4) {
4347
4348 rc = bnx2_nvram_write_dword(bp, addr,
4349 &flash_buffer[i], cmd_flags);
4350
4351 if (rc != 0)
4352 goto nvram_write_end;
4353
4354 cmd_flags = 0;
4355 }
4356 }
4357
4358
4359 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4360 if ((addr == page_end - 4) ||
4361 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4362 (addr == data_end - 4))) {
4363
4364 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4365 }
4366 rc = bnx2_nvram_write_dword(bp, addr, buf,
4367 cmd_flags);
4368
4369 if (rc != 0)
4370 goto nvram_write_end;
4371
4372 cmd_flags = 0;
4373 buf += 4;
4374 }
4375
4376
4377
4378 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4379 for (addr = data_end; addr < page_end;
4380 addr += 4, i += 4) {
4381
4382 if (addr == page_end-4) {
4383 cmd_flags = BNX2_NVM_COMMAND_LAST;
4384 }
4385 rc = bnx2_nvram_write_dword(bp, addr,
4386 &flash_buffer[i], cmd_flags);
4387
4388 if (rc != 0)
4389 goto nvram_write_end;
4390
4391 cmd_flags = 0;
4392 }
4393 }
4394
4395
4396 bnx2_disable_nvram_write(bp);
4397
4398
4399 bnx2_disable_nvram_access(bp);
4400 bnx2_release_nvram_lock(bp);
4401
4402
4403 written += data_end - data_start;
4404 }
4405
4406nvram_write_end:
4407 kfree(flash_buffer);
4408 kfree(align_buf);
4409 return rc;
4410}
4411
4412static void
4413bnx2_init_fw_cap(struct bnx2 *bp)
4414{
4415 u32 val, sig = 0;
4416
4417 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4418 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4419
4420 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4421 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4422
4423 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4424 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4425 return;
4426
4427 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4428 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4429 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4430 }
4431
4432 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4433 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4434 u32 link;
4435
4436 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4437
4438 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4439 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4440 bp->phy_port = PORT_FIBRE;
4441 else
4442 bp->phy_port = PORT_TP;
4443
4444 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4445 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4446 }
4447
4448 if (netif_running(bp->dev) && sig)
4449 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4450}
4451
4452static void
4453bnx2_setup_msix_tbl(struct bnx2 *bp)
4454{
4455 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4456
4457 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4458 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4459}
4460
4461static int
4462bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4463{
4464 u32 val;
4465 int i, rc = 0;
4466 u8 old_port;
4467
4468
4469
4470 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4471 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4472 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4473 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4474 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4475 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4476 udelay(5);
4477
4478
4479 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4480
4481
4482
4483 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4484 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4485
4486
4487
4488 val = REG_RD(bp, BNX2_MISC_ID);
4489
4490 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4491 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4492 REG_RD(bp, BNX2_MISC_COMMAND);
4493 udelay(5);
4494
4495 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4496 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4497
4498 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4499
4500 } else {
4501 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4502 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4503 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4504
4505
4506 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4507
4508
4509
4510
4511
4512 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4513 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4514 msleep(20);
4515
4516
4517 for (i = 0; i < 10; i++) {
4518 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4519 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4520 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4521 break;
4522 udelay(10);
4523 }
4524
4525 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4526 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4527 printk(KERN_ERR PFX "Chip reset did not complete\n");
4528 return -EBUSY;
4529 }
4530 }
4531
4532
4533 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4534 if (val != 0x01020304) {
4535 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4536 return -ENODEV;
4537 }
4538
4539
4540 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4541 if (rc)
4542 return rc;
4543
4544 spin_lock_bh(&bp->phy_lock);
4545 old_port = bp->phy_port;
4546 bnx2_init_fw_cap(bp);
4547 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4548 old_port != bp->phy_port)
4549 bnx2_set_default_remote_link(bp);
4550 spin_unlock_bh(&bp->phy_lock);
4551
4552 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4553
4554
4555 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4556
4557
4558 rc = bnx2_alloc_bad_rbuf(bp);
4559 }
4560
4561 if (bp->flags & BNX2_FLAG_USING_MSIX)
4562 bnx2_setup_msix_tbl(bp);
4563
4564 return rc;
4565}
4566
4567static int
4568bnx2_init_chip(struct bnx2 *bp)
4569{
4570 u32 val, mtu;
4571 int rc, i;
4572
4573
4574 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4575
4576 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4577 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4578#ifdef __BIG_ENDIAN
4579 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4580#endif
4581 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4582 DMA_READ_CHANS << 12 |
4583 DMA_WRITE_CHANS << 16;
4584
4585 val |= (0x2 << 20) | (1 << 11);
4586
4587 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4588 val |= (1 << 23);
4589
4590 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4591 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4592 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4593
4594 REG_WR(bp, BNX2_DMA_CONFIG, val);
4595
4596 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4597 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4598 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4599 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4600 }
4601
4602 if (bp->flags & BNX2_FLAG_PCIX) {
4603 u16 val16;
4604
4605 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4606 &val16);
4607 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4608 val16 & ~PCI_X_CMD_ERO);
4609 }
4610
4611 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4612 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4613 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4614 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4615
4616
4617
4618 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4619 rc = bnx2_init_5709_context(bp);
4620 if (rc)
4621 return rc;
4622 } else
4623 bnx2_init_context(bp);
4624
4625 if ((rc = bnx2_init_cpus(bp)) != 0)
4626 return rc;
4627
4628 bnx2_init_nvram(bp);
4629
4630 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4631
4632 val = REG_RD(bp, BNX2_MQ_CONFIG);
4633 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4634 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4635 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4636 val |= BNX2_MQ_CONFIG_HALT_DIS;
4637
4638 REG_WR(bp, BNX2_MQ_CONFIG, val);
4639
4640 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4641 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4642 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4643
4644 val = (BCM_PAGE_BITS - 8) << 24;
4645 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4646
4647
4648 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4649 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4650 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4651 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4652
4653 val = bp->mac_addr[0] +
4654 (bp->mac_addr[1] << 8) +
4655 (bp->mac_addr[2] << 16) +
4656 bp->mac_addr[3] +
4657 (bp->mac_addr[4] << 8) +
4658 (bp->mac_addr[5] << 16);
4659 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4660
4661
4662 mtu = bp->dev->mtu;
4663 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4664 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4665 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4666 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4667
4668 if (mtu < 1500)
4669 mtu = 1500;
4670
4671 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4672 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4673 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4674
4675 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4676 bp->bnx2_napi[i].last_status_idx = 0;
4677
4678 bp->idle_chk_status_idx = 0xffff;
4679
4680 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4681
4682
4683 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4684
4685 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4686 (u64) bp->status_blk_mapping & 0xffffffff);
4687 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4688
4689 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4690 (u64) bp->stats_blk_mapping & 0xffffffff);
4691 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4692 (u64) bp->stats_blk_mapping >> 32);
4693
4694 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4695 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4696
4697 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4698 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4699
4700 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4701 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4702
4703 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4704
4705 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4706
4707 REG_WR(bp, BNX2_HC_COM_TICKS,
4708 (bp->com_ticks_int << 16) | bp->com_ticks);
4709
4710 REG_WR(bp, BNX2_HC_CMD_TICKS,
4711 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4712
4713 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4714 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4715 else
4716 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4717 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);
4718
4719 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4720 val = BNX2_HC_CONFIG_COLLECT_STATS;
4721 else {
4722 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4723 BNX2_HC_CONFIG_COLLECT_STATS;
4724 }
4725
4726 if (bp->irq_nvecs > 1) {
4727 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4728 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4729
4730 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4731 }
4732
4733 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4734 val |= BNX2_HC_CONFIG_ONE_SHOT;
4735
4736 REG_WR(bp, BNX2_HC_CONFIG, val);
4737
4738 for (i = 1; i < bp->irq_nvecs; i++) {
4739 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4740 BNX2_HC_SB_CONFIG_1;
4741
4742 REG_WR(bp, base,
4743 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4744 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4745 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4746
4747 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4748 (bp->tx_quick_cons_trip_int << 16) |
4749 bp->tx_quick_cons_trip);
4750
4751 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4752 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4753
4754 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4755 (bp->rx_quick_cons_trip_int << 16) |
4756 bp->rx_quick_cons_trip);
4757
4758 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4759 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4760 }
4761
4762
4763 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4764
4765 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4766
4767
4768 bnx2_set_rx_mode(bp->dev);
4769
4770 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4771 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4772 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4773 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4774 }
4775 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4776 1, 0);
4777
4778 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4779 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4780
4781 udelay(20);
4782
4783 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4784
4785 return rc;
4786}
4787
4788static void
4789bnx2_clear_ring_states(struct bnx2 *bp)
4790{
4791 struct bnx2_napi *bnapi;
4792 struct bnx2_tx_ring_info *txr;
4793 struct bnx2_rx_ring_info *rxr;
4794 int i;
4795
4796 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4797 bnapi = &bp->bnx2_napi[i];
4798 txr = &bnapi->tx_ring;
4799 rxr = &bnapi->rx_ring;
4800
4801 txr->tx_cons = 0;
4802 txr->hw_tx_cons = 0;
4803 rxr->rx_prod_bseq = 0;
4804 rxr->rx_prod = 0;
4805 rxr->rx_cons = 0;
4806 rxr->rx_pg_prod = 0;
4807 rxr->rx_pg_cons = 0;
4808 }
4809}
4810
4811static void
4812bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
4813{
4814 u32 val, offset0, offset1, offset2, offset3;
4815 u32 cid_addr = GET_CID_ADDR(cid);
4816
4817 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4818 offset0 = BNX2_L2CTX_TYPE_XI;
4819 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4820 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4821 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4822 } else {
4823 offset0 = BNX2_L2CTX_TYPE;
4824 offset1 = BNX2_L2CTX_CMD_TYPE;
4825 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4826 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4827 }
4828 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4829 bnx2_ctx_wr(bp, cid_addr, offset0, val);
4830
4831 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4832 bnx2_ctx_wr(bp, cid_addr, offset1, val);
4833
4834 val = (u64) txr->tx_desc_mapping >> 32;
4835 bnx2_ctx_wr(bp, cid_addr, offset2, val);
4836
4837 val = (u64) txr->tx_desc_mapping & 0xffffffff;
4838 bnx2_ctx_wr(bp, cid_addr, offset3, val);
4839}
4840
4841static void
4842bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
4843{
4844 struct tx_bd *txbd;
4845 u32 cid = TX_CID;
4846 struct bnx2_napi *bnapi;
4847 struct bnx2_tx_ring_info *txr;
4848
4849 bnapi = &bp->bnx2_napi[ring_num];
4850 txr = &bnapi->tx_ring;
4851
4852 if (ring_num == 0)
4853 cid = TX_CID;
4854 else
4855 cid = TX_TSS_CID + ring_num - 1;
4856
4857 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4858
4859 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
4860
4861 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4862 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
4863
4864 txr->tx_prod = 0;
4865 txr->tx_prod_bseq = 0;
4866
4867 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4868 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4869
4870 bnx2_init_tx_context(bp, cid, txr);
4871}
4872
4873static void
4874bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4875 int num_rings)
4876{
4877 int i;
4878 struct rx_bd *rxbd;
4879
4880 for (i = 0; i < num_rings; i++) {
4881 int j;
4882
4883 rxbd = &rx_ring[i][0];
4884 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4885 rxbd->rx_bd_len = buf_size;
4886 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4887 }
4888 if (i == (num_rings - 1))
4889 j = 0;
4890 else
4891 j = i + 1;
4892 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4893 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4894 }
4895}
4896
4897static void
4898bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
4899{
4900 int i;
4901 u16 prod, ring_prod;
4902 u32 cid, rx_cid_addr, val;
4903 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4904 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4905
4906 if (ring_num == 0)
4907 cid = RX_CID;
4908 else
4909 cid = RX_RSS_CID + ring_num - 1;
4910
4911 rx_cid_addr = GET_CID_ADDR(cid);
4912
4913 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
4914 bp->rx_buf_use_size, bp->rx_max_ring);
4915
4916 bnx2_init_rx_context(bp, cid);
4917
4918 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4919 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4920 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4921 }
4922
4923 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4924 if (bp->rx_pg_ring_size) {
4925 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4926 rxr->rx_pg_desc_mapping,
4927 PAGE_SIZE, bp->rx_max_pg_ring);
4928 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4929 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4930 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4931 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
4932
4933 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
4934 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4935
4936 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
4937 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4938
4939 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4940 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4941 }
4942
4943 val = (u64) rxr->rx_desc_mapping[0] >> 32;
4944 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4945
4946 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
4947 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4948
4949 ring_prod = prod = rxr->rx_pg_prod;
4950 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4951 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
4952 break;
4953 prod = NEXT_RX_BD(prod);
4954 ring_prod = RX_PG_RING_IDX(prod);
4955 }
4956 rxr->rx_pg_prod = prod;
4957
4958 ring_prod = prod = rxr->rx_prod;
4959 for (i = 0; i < bp->rx_ring_size; i++) {
4960 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
4961 break;
4962 prod = NEXT_RX_BD(prod);
4963 ring_prod = RX_RING_IDX(prod);
4964 }
4965 rxr->rx_prod = prod;
4966
4967 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4968 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4969 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
4970
4971 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4972 REG_WR16(bp, rxr->rx_bidx_addr, prod);
4973
4974 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
4975}
4976
4977static void
4978bnx2_init_all_rings(struct bnx2 *bp)
4979{
4980 int i;
4981 u32 val;
4982
4983 bnx2_clear_ring_states(bp);
4984
4985 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4986 for (i = 0; i < bp->num_tx_rings; i++)
4987 bnx2_init_tx_ring(bp, i);
4988
4989 if (bp->num_tx_rings > 1)
4990 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4991 (TX_TSS_CID << 7));
4992
4993 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4994 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4995
4996 for (i = 0; i < bp->num_rx_rings; i++)
4997 bnx2_init_rx_ring(bp, i);
4998
4999 if (bp->num_rx_rings > 1) {
5000 u32 tbl_32;
5001 u8 *tbl = (u8 *) &tbl_32;
5002
5003 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5004 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5005
5006 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5007 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5008 if ((i % 4) == 3)
5009 bnx2_reg_wr_ind(bp,
5010 BNX2_RXP_SCRATCH_RSS_TBL + i,
5011 cpu_to_be32(tbl_32));
5012 }
5013
5014 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5015 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5016
5017 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5018
5019 }
5020}
5021
5022static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5023{
5024 u32 max, num_rings = 1;
5025
5026 while (ring_size > MAX_RX_DESC_CNT) {
5027 ring_size -= MAX_RX_DESC_CNT;
5028 num_rings++;
5029 }
5030
5031 max = max_size;
5032 while ((max & num_rings) == 0)
5033 max >>= 1;
5034
5035 if (num_rings != max)
5036 max <<= 1;
5037
5038 return max;
5039}
5040
5041static void
5042bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5043{
5044 u32 rx_size, rx_space, jumbo_size;
5045
5046
5047 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5048
5049 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5050 sizeof(struct skb_shared_info);
5051
5052 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5053 bp->rx_pg_ring_size = 0;
5054 bp->rx_max_pg_ring = 0;
5055 bp->rx_max_pg_ring_idx = 0;
5056 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5057 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5058
5059 jumbo_size = size * pages;
5060 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5061 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5062
5063 bp->rx_pg_ring_size = jumbo_size;
5064 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5065 MAX_RX_PG_RINGS);
5066 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5067 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5068 bp->rx_copy_thresh = 0;
5069 }
5070
5071 bp->rx_buf_use_size = rx_size;
5072
5073 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5074 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5075 bp->rx_ring_size = size;
5076 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5077 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5078}
5079
5080static void
5081bnx2_free_tx_skbs(struct bnx2 *bp)
5082{
5083 int i;
5084
5085 for (i = 0; i < bp->num_tx_rings; i++) {
5086 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5087 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5088 int j;
5089
5090 if (txr->tx_buf_ring == NULL)
5091 continue;
5092
5093 for (j = 0; j < TX_DESC_CNT; ) {
5094 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5095 struct sk_buff *skb = tx_buf->skb;
5096
5097 if (skb == NULL) {
5098 j++;
5099 continue;
5100 }
5101
5102 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5103
5104 tx_buf->skb = NULL;
5105
5106 j += skb_shinfo(skb)->nr_frags + 1;
5107 dev_kfree_skb(skb);
5108 }
5109 }
5110}
5111
5112static void
5113bnx2_free_rx_skbs(struct bnx2 *bp)
5114{
5115 int i;
5116
5117 for (i = 0; i < bp->num_rx_rings; i++) {
5118 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5119 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5120 int j;
5121
5122 if (rxr->rx_buf_ring == NULL)
5123 return;
5124
5125 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5126 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5127 struct sk_buff *skb = rx_buf->skb;
5128
5129 if (skb == NULL)
5130 continue;
5131
5132 pci_unmap_single(bp->pdev,
5133 pci_unmap_addr(rx_buf, mapping),
5134 bp->rx_buf_use_size,
5135 PCI_DMA_FROMDEVICE);
5136
5137 rx_buf->skb = NULL;
5138
5139 dev_kfree_skb(skb);
5140 }
5141 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5142 bnx2_free_rx_page(bp, rxr, j);
5143 }
5144}
5145
5146static void
5147bnx2_free_skbs(struct bnx2 *bp)
5148{
5149 bnx2_free_tx_skbs(bp);
5150 bnx2_free_rx_skbs(bp);
5151}
5152
5153static int
5154bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5155{
5156 int rc;
5157
5158 rc = bnx2_reset_chip(bp, reset_code);
5159 bnx2_free_skbs(bp);
5160 if (rc)
5161 return rc;
5162
5163 if ((rc = bnx2_init_chip(bp)) != 0)
5164 return rc;
5165
5166 bnx2_init_all_rings(bp);
5167 return 0;
5168}
5169
5170static int
5171bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5172{
5173 int rc;
5174
5175 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5176 return rc;
5177
5178 spin_lock_bh(&bp->phy_lock);
5179 bnx2_init_phy(bp, reset_phy);
5180 bnx2_set_link(bp);
5181 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5182 bnx2_remote_phy_event(bp);
5183 spin_unlock_bh(&bp->phy_lock);
5184 return 0;
5185}
5186
5187static int
5188bnx2_shutdown_chip(struct bnx2 *bp)
5189{
5190 u32 reset_code;
5191
5192 if (bp->flags & BNX2_FLAG_NO_WOL)
5193 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5194 else if (bp->wol)
5195 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5196 else
5197 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5198
5199 return bnx2_reset_chip(bp, reset_code);
5200}
5201
5202static int
5203bnx2_test_registers(struct bnx2 *bp)
5204{
5205 int ret;
5206 int i, is_5709;
5207 static const struct {
5208 u16 offset;
5209 u16 flags;
5210#define BNX2_FL_NOT_5709 1
5211 u32 rw_mask;
5212 u32 ro_mask;
5213 } reg_tbl[] = {
5214 { 0x006c, 0, 0x00000000, 0x0000003f },
5215 { 0x0090, 0, 0xffffffff, 0x00000000 },
5216 { 0x0094, 0, 0x00000000, 0x00000000 },
5217
5218 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5219 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5220 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5221 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5222 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5223 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5224 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5225 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5226 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5227
5228 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5229 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5230 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5231 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5232 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5233 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5234
5235 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5236 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5237 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5238
5239 { 0x1000, 0, 0x00000000, 0x00000001 },
5240 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5241
5242 { 0x1408, 0, 0x01c00800, 0x00000000 },
5243 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5244 { 0x14a8, 0, 0x00000000, 0x000001ff },
5245 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5246 { 0x14b0, 0, 0x00000002, 0x00000001 },
5247 { 0x14b8, 0, 0x00000000, 0x00000000 },
5248 { 0x14c0, 0, 0x00000000, 0x00000009 },
5249 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5250 { 0x14cc, 0, 0x00000000, 0x00000001 },
5251 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5252
5253 { 0x1800, 0, 0x00000000, 0x00000001 },
5254 { 0x1804, 0, 0x00000000, 0x00000003 },
5255
5256 { 0x2800, 0, 0x00000000, 0x00000001 },
5257 { 0x2804, 0, 0x00000000, 0x00003f01 },
5258 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5259 { 0x2810, 0, 0xffff0000, 0x00000000 },
5260 { 0x2814, 0, 0xffff0000, 0x00000000 },
5261 { 0x2818, 0, 0xffff0000, 0x00000000 },
5262 { 0x281c, 0, 0xffff0000, 0x00000000 },
5263 { 0x2834, 0, 0xffffffff, 0x00000000 },
5264 { 0x2840, 0, 0x00000000, 0xffffffff },
5265 { 0x2844, 0, 0x00000000, 0xffffffff },
5266 { 0x2848, 0, 0xffffffff, 0x00000000 },
5267 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5268
5269 { 0x2c00, 0, 0x00000000, 0x00000011 },
5270 { 0x2c04, 0, 0x00000000, 0x00030007 },
5271
5272 { 0x3c00, 0, 0x00000000, 0x00000001 },
5273 { 0x3c04, 0, 0x00000000, 0x00070000 },
5274 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5275 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5276 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5277 { 0x3c14, 0, 0x00000000, 0xffffffff },
5278 { 0x3c18, 0, 0x00000000, 0xffffffff },
5279 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5280 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5281
5282 { 0x5004, 0, 0x00000000, 0x0000007f },
5283 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5284
5285 { 0x5c00, 0, 0x00000000, 0x00000001 },
5286 { 0x5c04, 0, 0x00000000, 0x0003000f },
5287 { 0x5c08, 0, 0x00000003, 0x00000000 },
5288 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5289 { 0x5c10, 0, 0x00000000, 0xffffffff },
5290 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5291 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5292 { 0x5c88, 0, 0x00000000, 0x00077373 },
5293 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5294
5295 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5296 { 0x680c, 0, 0xffffffff, 0x00000000 },
5297 { 0x6810, 0, 0xffffffff, 0x00000000 },
5298 { 0x6814, 0, 0xffffffff, 0x00000000 },
5299 { 0x6818, 0, 0xffffffff, 0x00000000 },
5300 { 0x681c, 0, 0xffffffff, 0x00000000 },
5301 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5302 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5303 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5304 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5305 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5306 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5307 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5308 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5309 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5310 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5311 { 0x684c, 0, 0xffffffff, 0x00000000 },
5312 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5313 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5314 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5315 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5316 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5317 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5318
5319 { 0xffff, 0, 0x00000000, 0x00000000 },
5320 };
5321
5322 ret = 0;
5323 is_5709 = 0;
5324 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5325 is_5709 = 1;
5326
5327 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5328 u32 offset, rw_mask, ro_mask, save_val, val;
5329 u16 flags = reg_tbl[i].flags;
5330
5331 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5332 continue;
5333
5334 offset = (u32) reg_tbl[i].offset;
5335 rw_mask = reg_tbl[i].rw_mask;
5336 ro_mask = reg_tbl[i].ro_mask;
5337
5338 save_val = readl(bp->regview + offset);
5339
5340 writel(0, bp->regview + offset);
5341
5342 val = readl(bp->regview + offset);
5343 if ((val & rw_mask) != 0) {
5344 goto reg_test_err;
5345 }
5346
5347 if ((val & ro_mask) != (save_val & ro_mask)) {
5348 goto reg_test_err;
5349 }
5350
5351 writel(0xffffffff, bp->regview + offset);
5352
5353 val = readl(bp->regview + offset);
5354 if ((val & r
