LXR linux/drivers/staging/meilhaus/me4600

   1/**
   2 * @file me4600_ai.c
   3 *
   4 * @brief ME-4000 analog input subdevice instance.
   5 * @note Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
   6 * @author Guenter Gebhardt
   7 * @author Krzysztof Gantzke    (k.gantzke@meilhaus.de)
   8 */
   9
  10/*
  11 * Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
  12 *
  13 * This file is free software; you can redistribute it and/or modify
  14 * it under the terms of the GNU General Public License as published by
  15 * the Free Software Foundation; either version 2 of the License, or
  16 * (at your option) any later version.
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 * GNU General Public License for more details.
  22 *
  23 * You should have received a copy of the GNU General Public License
  24 * along with this program; if not, write to the Free Software
  25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26 */
  27
  28#ifndef __KERNEL__
  29# define __KERNEL__
  30#endif
  31
  32/*
  33 * Includes
  34 */
  35#include <linux/module.h>
  36
  37#include <linux/slab.h>
  38#include <linux/spinlock.h>
  39#include <asm/io.h>
  40#include <asm/uaccess.h>
  41#include <linux/types.h>
  42#include <linux/interrupt.h>
  43#include <linux/delay.h>
  44
  45#include "medefines.h"
  46#include "meinternal.h"
  47#include "meerror.h"
  48#include "medebug.h"
  49#include "meids.h"
  50
  51#include "me4600_reg.h"
  52#include "me4600_ai_reg.h"
  53#include "me4600_ai.h"
  54
  55/*
  56 * Declarations (local)
  57 */
  58
  59static void me4600_ai_destructor(struct me_subdevice *subdevice);
  60static int me4600_ai_io_reset_subdevice(me_subdevice_t * subdevice,
  61                                        struct file *filep, int flags);
  62
  63static int me4600_ai_io_single_config(me_subdevice_t * subdevice,
  64                                      struct file *filep,
  65                                      int channel,
  66                                      int single_config,
  67                                      int ref,
  68                                      int trig_chan,
  69                                      int trig_type, int trig_edge, int flags);
  70
  71static int me4600_ai_io_single_read(me_subdevice_t * subdevice,
  72                                    struct file *filep,
  73                                    int channel,
  74                                    int *value, int time_out, int flags);
  75
  76static int me4600_ai_io_stream_config(me_subdevice_t * subdevice,
  77                                      struct file *filep,
  78                                      meIOStreamConfig_t * config_list,
  79                                      int count,
  80                                      meIOStreamTrigger_t * trigger,
  81                                      int fifo_irq_threshold, int flags);
  82static int me4600_ai_io_stream_read(me_subdevice_t * subdevice,
  83                                    struct file *filep,
  84                                    int read_mode,
  85                                    int *values, int *count, int flags);
  86static int me4600_ai_io_stream_new_values(me_subdevice_t * subdevice,
  87                                          struct file *filep,
  88                                          int time_out, int *count, int flags);
  89static int inline me4600_ai_io_stream_read_get_value(me4600_ai_subdevice_t *
  90                                                     instance, int *values,
  91                                                     const int count,
  92                                                     const int flags);
  93
  94static int me4600_ai_io_stream_start(me_subdevice_t * subdevice,
  95                                     struct file *filep,
  96                                     int start_mode, int time_out, int flags);
  97static int me4600_ai_io_stream_stop(me_subdevice_t * subdevice,
  98                                    struct file *filep,
  99                                    int stop_mode, int flags);
 100static int me4600_ai_io_stream_status(me_subdevice_t * subdevice,
 101                                      struct file *filep,
 102                                      int wait,
 103                                      int *status, int *values, int flags);
 104
 105static int me4600_ai_query_range_by_min_max(me_subdevice_t * subdevice,
 106                                            int unit,
 107                                            int *min,
 108                                            int *max, int *maxdata, int *range);
 109static int me4600_ai_query_number_ranges(me_subdevice_t * subdevice,
 110                                         int unit, int *count);
 111static int me4600_ai_query_range_info(me_subdevice_t * subdevice,
 112                                      int range,
 113                                      int *unit,
 114                                      int *min, int *max, int *maxdata);
 115static int me4600_ai_query_timer(me_subdevice_t * subdevice,
 116                                 int timer,
 117                                 int *base_frequency,
 118                                 long long *min_ticks, long long *max_ticks);
 119static int me4600_ai_query_number_channels(me_subdevice_t * subdevice,
 120                                           int *number);
 121static int me4600_ai_query_subdevice_type(me_subdevice_t * subdevice,
 122                                          int *type, int *subtype);
 123static int me4600_ai_query_subdevice_caps(me_subdevice_t * subdevice,
 124                                          int *caps);
 125static int me4600_ai_query_subdevice_caps_args(struct me_subdevice *subdevice,
 126                                               int cap, int *args, int count);
 127
 128#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
 129static irqreturn_t me4600_ai_isr(int irq, void *dev_id);
 130#else
 131static irqreturn_t me4600_ai_isr(int irq, void *dev_id, struct pt_regs *regs);
 132#endif
 133
 134static int ai_mux_toggler(me4600_ai_subdevice_t * subdevice);
 135
 136/** Immidiate stop.
 137* Reset all IRQ's sources. (block laches)
 138* Preserve FIFO
 139*/
 140static int ai_stop_immediately(me4600_ai_subdevice_t * instance);
 141
 142/** Immidiate stop.
 143* Reset all IRQ's sources. (block laches)
 144* Reset data FIFO
 145*/
 146void inline ai_stop_isr(me4600_ai_subdevice_t * instance);
 147
 148/** Interrupt logics.
 149* Read datas
 150* Reset latches
 151*/
 152void ai_limited_isr(me4600_ai_subdevice_t * instance, const uint32_t irq_status,
 153                    const uint32_t ctrl_status);
 154void ai_infinite_isr(me4600_ai_subdevice_t * instance,
 155                     const uint32_t irq_status, const uint32_t ctrl_status);
 156
 157/** Last chunck of datas. We must reschedule sample counter.
 158* Leaving SC_RELOAD doesn't do any harm, but in some bad case can make extra interrupts.
 159* When threshold is wrongly set some IRQ are lost.(!!!)
 160*/
 161void inline ai_reschedule_SC(me4600_ai_subdevice_t * instance);
 162
 163/** Read datas from FIFO and copy them to buffer */
 164static int inline ai_read_data(me4600_ai_subdevice_t * instance,
 165                               const int count);
 166
 167/** Copy rest of data from fifo to circular buffer.*/
 168static int inline ai_read_data_pooling(me4600_ai_subdevice_t * instance);
 169
 170/** Set ISM to next state for infinite data aqusation mode*/
 171void inline ai_infinite_ISM(me4600_ai_subdevice_t * instance);
 172
 173/** Set ISM to next state for define amount of data aqusation mode*/
 174void inline ai_limited_ISM(me4600_ai_subdevice_t * instance,
 175                           uint32_t irq_status);
 176
 177/** Set ISM to next stage for limited mode */
 178void inline ai_data_acquisition_logic(me4600_ai_subdevice_t * instance);
 179
 180#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
 181static void me4600_ai_work_control_task(void *subdevice);
 182#else
 183static void me4600_ai_work_control_task(struct work_struct *work);
 184#endif
 185
 186/* Definitions
 187 */
 188
 189me4600_ai_subdevice_t *me4600_ai_constructor(uint32_t reg_base,
 190                                             unsigned int channels,
 191                                             unsigned int ranges,
 192                                             int isolated,
 193                                             int sh,
 194                                             int irq,
 195                                             spinlock_t * ctrl_reg_lock,
 196                                             struct workqueue_struct *me4600_wq)
 197{
 198        me4600_ai_subdevice_t *subdevice;
 199        int err;
 200        unsigned int i;
 201
 202        PDEBUG("executed. idx=0\n");
 203
 204        // Allocate memory for subdevice instance.
 205        subdevice = kmalloc(sizeof(me4600_ai_subdevice_t), GFP_KERNEL);
 206
 207        if (!subdevice) {
 208                PERROR("Cannot get memory for subdevice instance.\n");
 209                return NULL;
 210        }
 211
 212        memset(subdevice, 0, sizeof(me4600_ai_subdevice_t));
 213
 214        // Initialize subdevice base class.
 215        err = me_subdevice_init(&subdevice->base);
 216
 217        if (err) {
 218                PERROR("Cannot initialize subdevice base class instance.\n");
 219                kfree(subdevice);
 220                return NULL;
 221        }
 222        // Initialize spin locks.
 223        spin_lock_init(&subdevice->subdevice_lock);
 224
 225        subdevice->ctrl_reg_lock = ctrl_reg_lock;
 226
 227        // Initialize circular buffer.
 228        subdevice->circ_buf.mask = ME4600_AI_CIRC_BUF_COUNT - 1;
 229
 230        subdevice->circ_buf.buf =
 231            (void *)__get_free_pages(GFP_KERNEL, ME4600_AI_CIRC_BUF_SIZE_ORDER);
 232        PDEBUG("circ_buf = %p size=%ld\n", subdevice->circ_buf.buf,
 233               ME4600_AI_CIRC_BUF_SIZE);
 234
 235        if (!subdevice->circ_buf.buf) {
 236                PERROR("Cannot get circular buffer.\n");
 237                me_subdevice_deinit((me_subdevice_t *) subdevice);
 238                kfree(subdevice);
 239                return NULL;
 240        }
 241
 242        memset(subdevice->circ_buf.buf, 0, ME4600_AI_CIRC_BUF_SIZE);
 243        subdevice->circ_buf.head = 0;
 244        subdevice->circ_buf.tail = 0;
 245        subdevice->status = ai_status_none;
 246
 247        // Initialize wait queue.
 248        init_waitqueue_head(&subdevice->wait_queue);
 249
 250        // Save the number of channels.
 251        subdevice->channels = channels;
 252
 253        /* Initialize the single config entries to reset values */
 254        for (i = 0; i < channels; i++) {
 255                subdevice->single_config[i].status = ME_SINGLE_CHANNEL_NOT_CONFIGURED;  //not configured
 256        }
 257
 258        // Save if isolated device.
 259        subdevice->isolated = isolated;
 260
 261        // Save if sample and hold is available.
 262        subdevice->sh = sh;
 263
 264        // Set stream config to not configured state.
 265        subdevice->fifo_irq_threshold = 0;
 266        subdevice->data_required = 0;
 267        subdevice->chan_list_len = 0;
 268
 269        // Initialize registers addresses.
 270        subdevice->ctrl_reg = reg_base + ME4600_AI_CTRL_REG;
 271        subdevice->status_reg = reg_base + ME4600_AI_STATUS_REG;
 272        subdevice->channel_list_reg = reg_base + ME4600_AI_CHANNEL_LIST_REG;
 273        subdevice->data_reg = reg_base + ME4600_AI_DATA_REG;
 274        subdevice->chan_timer_reg = reg_base + ME4600_AI_CHAN_TIMER_REG;
 275        subdevice->chan_pre_timer_reg = reg_base + ME4600_AI_CHAN_PRE_TIMER_REG;
 276        subdevice->scan_timer_low_reg = reg_base + ME4600_AI_SCAN_TIMER_LOW_REG;
 277        subdevice->scan_timer_high_reg =
 278            reg_base + ME4600_AI_SCAN_TIMER_HIGH_REG;
 279        subdevice->scan_pre_timer_low_reg =
 280            reg_base + ME4600_AI_SCAN_PRE_TIMER_LOW_REG;
 281        subdevice->scan_pre_timer_high_reg =
 282            reg_base + ME4600_AI_SCAN_PRE_TIMER_HIGH_REG;
 283        subdevice->start_reg = reg_base + ME4600_AI_START_REG;
 284        subdevice->irq_status_reg = reg_base + ME4600_IRQ_STATUS_REG;
 285        subdevice->sample_counter_reg = reg_base + ME4600_AI_SAMPLE_COUNTER_REG;
 286#ifdef MEDEBUG_DEBUG_REG
 287        subdevice->reg_base = reg_base;
 288#endif
 289
 290        // Initialize ranges.
 291        subdevice->ranges_len = ranges;
 292        subdevice->ranges[0].min = -10E6;
 293        subdevice->ranges[0].max = 9999694;
 294
 295        subdevice->ranges[1].min = 0;
 296        subdevice->ranges[1].max = 9999847;
 297
 298        subdevice->ranges[2].min = -25E5;
 299        subdevice->ranges[2].max = 2499923;
 300
 301        subdevice->ranges[3].min = 0;
 302        subdevice->ranges[3].max = 2499961;
 303
 304        // We have to switch the mux in order to get it work correctly.
 305        ai_mux_toggler(subdevice);
 306
 307        // Register interrupt service routine.
 308        subdevice->irq = irq;
 309        if (request_irq(subdevice->irq, me4600_ai_isr,
 310#ifdef IRQF_DISABLED
 311                        IRQF_DISABLED | IRQF_SHARED,
 312#else
 313                        SA_INTERRUPT | SA_SHIRQ,
 314#endif
 315                        ME4600_NAME, subdevice)) {
 316                PERROR("Cannot register interrupt service routine.\n");
 317                me_subdevice_deinit((me_subdevice_t *) subdevice);
 318                free_pages((unsigned long)subdevice->circ_buf.buf,
 319                           ME4600_AI_CIRC_BUF_SIZE_ORDER);
 320                subdevice->circ_buf.buf = NULL;
 321                kfree(subdevice);
 322                return NULL;
 323        }
 324        PINFO("Registered irq=%d.\n", subdevice->irq);
 325
 326        // Override base class methods.
 327        subdevice->base.me_subdevice_destructor = me4600_ai_destructor;
 328        subdevice->base.me_subdevice_io_reset_subdevice =
 329            me4600_ai_io_reset_subdevice;
 330        subdevice->base.me_subdevice_io_single_config =
 331            me4600_ai_io_single_config;
 332        subdevice->base.me_subdevice_io_single_read = me4600_ai_io_single_read;
 333        subdevice->base.me_subdevice_io_stream_config =
 334            me4600_ai_io_stream_config;
 335        subdevice->base.me_subdevice_io_stream_new_values =
 336            me4600_ai_io_stream_new_values;
 337        subdevice->base.me_subdevice_io_stream_read = me4600_ai_io_stream_read;
 338        subdevice->base.me_subdevice_io_stream_start =
 339            me4600_ai_io_stream_start;
 340        subdevice->base.me_subdevice_io_stream_status =
 341            me4600_ai_io_stream_status;
 342        subdevice->base.me_subdevice_io_stream_stop = me4600_ai_io_stream_stop;
 343        subdevice->base.me_subdevice_query_number_channels =
 344            me4600_ai_query_number_channels;
 345        subdevice->base.me_subdevice_query_subdevice_type =
 346            me4600_ai_query_subdevice_type;
 347        subdevice->base.me_subdevice_query_subdevice_caps =
 348            me4600_ai_query_subdevice_caps;
 349        subdevice->base.me_subdevice_query_subdevice_caps_args =
 350            me4600_ai_query_subdevice_caps_args;
 351        subdevice->base.me_subdevice_query_range_by_min_max =
 352            me4600_ai_query_range_by_min_max;
 353        subdevice->base.me_subdevice_query_number_ranges =
 354            me4600_ai_query_number_ranges;
 355        subdevice->base.me_subdevice_query_range_info =
 356            me4600_ai_query_range_info;
 357        subdevice->base.me_subdevice_query_timer = me4600_ai_query_timer;
 358
 359        // Prepare work queue.
 360        subdevice->me4600_workqueue = me4600_wq;
 361
 362/* workqueue API changed in kernel 2.6.20 */
 363#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) )
 364        INIT_WORK(&subdevice->ai_control_task, me4600_ai_work_control_task,
 365                  (void *)subdevice);
 366#else
 367        INIT_DELAYED_WORK(&subdevice->ai_control_task,
 368                          me4600_ai_work_control_task);
 369#endif
 370
 371        return subdevice;
 372}
 373
 374static void me4600_ai_destructor(struct me_subdevice *subdevice)
 375{
 376        me4600_ai_subdevice_t *instance;
 377
 378        instance = (me4600_ai_subdevice_t *) subdevice;
 379
 380        PDEBUG("executed. idx=0\n");
 381
 382        instance->ai_control_task_flag = 0;
 383        // Reset subdevice to asure clean exit.
 384        me4600_ai_io_reset_subdevice(subdevice, NULL,
 385                                     ME_IO_RESET_SUBDEVICE_NO_FLAGS);
 386
 387        // Remove any tasks from work queue. This is paranoic because it was done allready in reset().
 388        if (!cancel_delayed_work(&instance->ai_control_task)) { //Wait 2 ticks to be sure that control task is removed from queue.
 389                set_current_state(TASK_INTERRUPTIBLE);
 390                schedule_timeout(2);
 391        }
 392
 393        free_irq(instance->irq, instance);
 394        free_pages((unsigned long)instance->circ_buf.buf,
 395                   ME4600_AI_CIRC_BUF_SIZE_ORDER);
 396        me_subdevice_deinit(&instance->base);
 397        kfree(instance);
 398}
 399
 400static int me4600_ai_io_reset_subdevice(me_subdevice_t * subdevice,
 401                                        struct file *filep, int flags)
 402{
 403        me4600_ai_subdevice_t *instance;
 404        int err = ME_ERRNO_SUCCESS;
 405        volatile uint32_t ctrl;
 406        unsigned long status;
 407        const int timeout = HZ / 10;    //100ms
 408        int i;
 409
 410        PDEBUG("executed. idx=0\n");
 411
 412        if (flags) {
 413                PERROR("Invalid flag specified.\n");
 414                return ME_ERRNO_INVALID_FLAGS;
 415        }
 416
 417        instance = (me4600_ai_subdevice_t *) subdevice;
 418
 419        ME_SUBDEVICE_ENTER;
 420
 421        instance->ai_control_task_flag = 0;
 422        instance->status = ai_status_none;
 423
 424        for (i = 0; i <= timeout; i++) {
 425                spin_lock_irqsave(instance->ctrl_reg_lock, status);
 426                ctrl = inl(instance->ctrl_reg);
 427                //Stop DMA
 428                ctrl &= ~ME4600_AI_CTRL_RPCI_FIFO;
 429                // Stop all actions. No conditions!
 430                ctrl &= ~ME4600_AI_CTRL_BIT_STOP;
 431                ctrl |= ME4600_AI_CTRL_BIT_IMMEDIATE_STOP;
 432
 433                outl(ctrl, instance->ctrl_reg);
 434                PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
 435                           instance->reg_base,
 436                           instance->ctrl_reg - instance->reg_base, ctrl);
 437                spin_unlock_irqrestore(instance->ctrl_reg_lock, status);
 438
 439                if (!(inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM))
 440                        break;
 441
 442                set_current_state(TASK_INTERRUPTIBLE);
 443                schedule_timeout(1);
 444        }
 445
 446        if (i > timeout) {
 447                PERROR("FSM is still busy.\n");
 448                ME_SUBDEVICE_EXIT;
 449                return ME_ERRNO_INTERNAL;
 450        }
 451
 452        spin_lock_irqsave(instance->ctrl_reg_lock, status);
 453        ctrl = inl(instance->ctrl_reg);
 454        // Clear all features. Dissable interrupts.
 455        ctrl &= ~(ME4600_AI_CTRL_BIT_STOP
 456                  | ME4600_AI_CTRL_BIT_LE_IRQ
 457                  | ME4600_AI_CTRL_BIT_HF_IRQ | ME4600_AI_CTRL_BIT_SC_IRQ);
 458        ctrl |= (ME4600_AI_CTRL_BIT_IMMEDIATE_STOP
 459                 | ME4600_AI_CTRL_BIT_LE_IRQ_RESET
 460                 | ME4600_AI_CTRL_BIT_HF_IRQ_RESET
 461                 | ME4600_AI_CTRL_BIT_SC_IRQ_RESET);
 462
 463        outl(ctrl, instance->ctrl_reg);
 464        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
 465                   instance->ctrl_reg - instance->reg_base, ctrl);
 466        spin_unlock_irqrestore(instance->ctrl_reg_lock, status);
 467
 468        outl(ME4600_AI_MIN_CHAN_TICKS - 1, instance->chan_timer_reg);
 469        PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%llx\n",
 470                   instance->reg_base,
 471                   instance->chan_timer_reg - instance->reg_base,
 472                   ME4600_AI_MIN_CHAN_TICKS);
 473        outl(ME4600_AI_MIN_ACQ_TICKS - 1, instance->chan_pre_timer_reg);
 474        PDEBUG_REG("chan_pre_timer_reg outl(0x%lX+0x%lX)=0x%llx\n",
 475                   instance->reg_base,
 476                   instance->chan_pre_timer_reg - instance->reg_base,
 477                   ME4600_AI_MIN_ACQ_TICKS);
 478        outl(0, instance->scan_timer_low_reg);
 479        PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
 480                   instance->reg_base,
 481                   instance->scan_timer_low_reg - instance->reg_base, 0);
 482        outl(0, instance->scan_timer_high_reg);
 483        PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
 484                   instance->reg_base,
 485                   instance->scan_timer_high_reg - instance->reg_base, 0);
 486        outl(0, instance->scan_pre_timer_low_reg);
 487        PDEBUG_REG("scan_pre_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
 488                   instance->reg_base,
 489                   instance->scan_pre_timer_low_reg - instance->reg_base, 0);
 490        outl(0, instance->scan_pre_timer_high_reg);
 491        PDEBUG_REG("scan_pre_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
 492                   instance->reg_base,
 493                   instance->scan_pre_timer_high_reg - instance->reg_base, 0);
 494        outl(0xEFFFFFFF, instance->sample_counter_reg);
 495        PDEBUG_REG("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
 496                   instance->reg_base,
 497                   instance->sample_counter_reg - instance->reg_base,
 498                   0xEFFFFFFF);
 499
 500        instance->circ_buf.head = 0;
 501        instance->circ_buf.tail = 0;
 502
 503        instance->fifo_irq_threshold = 0;
 504        instance->data_required = 0;
 505        instance->chan_list_len = 0;
 506
 507        // Initialize the single config entries to reset values.
 508        for (i = 0; i < instance->channels; i++) {
 509                instance->single_config[i].status =
 510                    ME_SINGLE_CHANNEL_NOT_CONFIGURED;
 511        }
 512        instance->status = ai_status_none;
 513
 514        //Signal reset if user is on wait.
 515        wake_up_interruptible_all(&instance->wait_queue);
 516
 517        ME_SUBDEVICE_EXIT;
 518
 519        return err;
 520}
 521
 522static int me4600_ai_io_single_config(me_subdevice_t * subdevice,
 523                                      struct file *filep,
 524                                      int channel,
 525                                      int single_config,
 526                                      int ref,
 527                                      int trig_chan,
 528                                      int trig_type, int trig_edge, int flags)
 529{
 530        me4600_ai_subdevice_t *instance;
 531        int err = ME_ERRNO_SUCCESS;
 532        unsigned long cpu_flags;
 533        int i;
 534
 535        instance = (me4600_ai_subdevice_t *) subdevice;
 536
 537        PDEBUG("executed. idx=0\n");
 538
 539        if (flags & ~ME_IO_SINGLE_CONFIG_CONTINUE) {
 540                PERROR("Invalid flag specified.\n");
 541                return ME_ERRNO_INVALID_FLAGS;
 542        }
 543
 544        switch (trig_type) {
 545        case ME_TRIG_TYPE_SW:
 546                if (trig_edge != ME_TRIG_EDGE_NONE) {
 547                        PERROR
 548                            ("Invalid trigger edge. Software trigger has not edge.\n");
 549                        return ME_ERRNO_INVALID_TRIG_EDGE;
 550                }
 551                break;
 552
 553        case ME_TRIG_TYPE_EXT_ANALOG:
 554                if (instance->channels <= 16)   //Only versions with 32 channels have analog trigger (4670 and 4680)
 555                {
 556                        PERROR("Invalid trigger type specified.\n");
 557                        return ME_ERRNO_INVALID_TRIG_TYPE;
 558                }
 559
 560        case ME_TRIG_TYPE_EXT_DIGITAL:
 561                if ((trig_edge != ME_TRIG_EDGE_ANY)
 562                    && (trig_edge != ME_TRIG_EDGE_RISING)
 563                    && (trig_edge != ME_TRIG_EDGE_FALLING)) {
 564                        PERROR("Invalid trigger edge specified.\n");
 565                        return ME_ERRNO_INVALID_TRIG_EDGE;
 566                }
 567                break;
 568
 569        default:
 570                PERROR("Invalid trigger type specified.\n");
 571                return ME_ERRNO_INVALID_TRIG_TYPE;
 572        }
 573
 574        if (trig_chan != ME_TRIG_CHAN_DEFAULT) {
 575                PERROR("Invalid trigger channel specified.\n");
 576                return ME_ERRNO_INVALID_TRIG_CHAN;
 577        }
 578
 579        if ((single_config < 0) || (single_config >= instance->ranges_len)) {
 580                PERROR("Invalid single config specified.\n");
 581                return ME_ERRNO_INVALID_SINGLE_CONFIG;
 582        }
 583
 584        if ((ref != ME_REF_AI_GROUND) && (ref != ME_REF_AI_DIFFERENTIAL)) {
 585                PERROR("Invalid analog reference specified.\n");
 586                return ME_ERRNO_INVALID_REF;
 587        }
 588
 589        if ((single_config % 2) && (ref != ME_REF_AI_GROUND)) {
 590                PERROR("Invalid analog reference specified.\n");
 591                return ME_ERRNO_INVALID_REF;
 592        }
 593
 594        if ((ref == ME_REF_AI_DIFFERENTIAL)
 595            && ((instance->channels == 16) || (channel >= 16))) {
 596                PERROR("Invalid analog reference specified.\n");
 597                return ME_ERRNO_INVALID_REF;
 598        }
 599
 600        if (channel < 0) {
 601                PERROR("Invalid channel number specified.\n");
 602                return ME_ERRNO_INVALID_CHANNEL;
 603        }
 604
 605        if (channel >= instance->channels) {
 606                PERROR("Invalid channel number specified.\n");
 607                return ME_ERRNO_INVALID_CHANNEL;
 608        }
 609
 610        ME_SUBDEVICE_ENTER;
 611
 612        spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
 613        //Prepare data entry.
 614        // Common for all modes.
 615        instance->single_config[channel].entry =
 616            channel | ME4600_AI_LIST_LAST_ENTRY;
 617
 618        if (ref == ME_REF_AI_DIFFERENTIAL) {    // ME_REF_AI_DIFFERENTIAL
 619                instance->single_config[channel].entry |=
 620                    ME4600_AI_LIST_INPUT_DIFFERENTIAL;
 621        }
 622/*
 623                // ME4600_AI_LIST_INPUT_SINGLE_ENDED = 0x0000
 624                // 'entry |= ME4600_AI_LIST_INPUT_SINGLE_ENDED' <== Do nothing. Removed.
 625                else
 626                {// ME_REF_AI_GROUND
 627                        instance->single_config[channel].entry |= ME4600_AI_LIST_INPUT_SINGLE_ENDED;
 628                }
 629*/
 630        switch (single_config) {
 631        case 0:         //-10V..10V
 632/*
 633                                        // ME4600_AI_LIST_RANGE_BIPOLAR_10 = 0x0000
 634                                        // 'entry |= ME4600_AI_LIST_RANGE_BIPOLAR_10' <== Do nothing. Removed.
 635                                        instance->single_config[channel].entry |= ME4600_AI_LIST_RANGE_BIPOLAR_10;
 636*/ break;
 637
 638        case 1:         //0V..10V
 639                instance->single_config[channel].entry |=
 640                    ME4600_AI_LIST_RANGE_UNIPOLAR_10;
 641                break;
 642
 643        case 2:         //-2.5V..2.5V
 644                instance->single_config[channel].entry |=
 645                    ME4600_AI_LIST_RANGE_BIPOLAR_2_5;
 646                break;
 647
 648        case 3:         //0V..2.5V
 649                instance->single_config[channel].entry |=
 650                    ME4600_AI_LIST_RANGE_UNIPOLAR_2_5;
 651                break;
 652        }
 653
 654        // Prepare control register.
 655        // Common for all modes.
 656        instance->single_config[channel].ctrl =
 657            ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO;
 658
 659        switch (trig_type) {
 660        case ME_TRIG_TYPE_SW:
 661                // Nothing to set.
 662                break;
 663
 664        case ME_TRIG_TYPE_EXT_ANALOG:
 665                instance->single_config[channel].ctrl |=
 666                    ME4600_AI_CTRL_BIT_EX_TRIG_ANALOG;
 667
 668        case ME_TRIG_TYPE_EXT_DIGITAL:
 669                instance->single_config[channel].ctrl |=
 670                    ME4600_AI_CTRL_BIT_EX_TRIG;
 671                break;
 672        }
 673
 674        switch (trig_edge) {
 675        case ME_TRIG_EDGE_RISING:
 676                // Nothing to set.
 677                break;
 678
 679        case ME_TRIG_EDGE_ANY:
 680                instance->single_config[channel].ctrl |=
 681                    ME4600_AI_CTRL_BIT_EX_TRIG_BOTH;
 682
 683        case ME_TRIG_EDGE_FALLING:
 684                instance->single_config[channel].ctrl |=
 685                    ME4600_AI_CTRL_BIT_EX_TRIG_FALLING;
 686                break;
 687        }
 688
 689        // Enable this channel
 690        instance->single_config[channel].status = ME_SINGLE_CHANNEL_CONFIGURED;
 691
 692        // Copy this settings to other outputs.
 693        if (flags == ME_IO_SINGLE_CONFIG_CONTINUE) {
 694                for (i = channel + 1; i < instance->channels; i++) {
 695                        instance->single_config[i].ctrl =
 696                            instance->single_config[channel].ctrl;
 697                        instance->single_config[i].entry =
 698                            instance->single_config[channel].entry;
 699                        instance->single_config[i].status =
 700                            ME_SINGLE_CHANNEL_CONFIGURED;
 701                }
 702        }
 703
 704        instance->status = ai_status_single_configured;
 705        spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
 706
 707        ME_SUBDEVICE_EXIT;
 708
 709        return err;
 710}
 711
 712static int me4600_ai_io_single_read(me_subdevice_t * subdevice,
 713                                    struct file *filep,
 714                                    int channel,
 715                                    int *value, int time_out, int flags)
 716{
 717        me4600_ai_subdevice_t *instance;
 718        volatile uint32_t tmp;
 719        volatile uint32_t val;
 720        unsigned long cpu_flags;
 721        int err = ME_ERRNO_SUCCESS;
 722
 723        unsigned long j;
 724        unsigned long delay = 0;
 725
 726        PDEBUG("executed. idx=0\n");
 727
 728        instance = (me4600_ai_subdevice_t *) subdevice;
 729
 730        if (flags) {
 731                PERROR("Invalid flag specified.\n");
 732                return ME_ERRNO_INVALID_FLAGS;
 733        }
 734
 735        if (instance->status != ai_status_single_configured) {
 736                PERROR("Subdevice not configured to work in single mode!\n");
 737                return ME_ERRNO_PREVIOUS_CONFIG;
 738        }
 739
 740        if ((channel > instance->channels) || (channel < 0)) {
 741                PERROR("Invalid channel specified.\n");
 742                return ME_ERRNO_INVALID_CHANNEL;
 743        }
 744
 745        if (time_out < 0) {
 746                PERROR("Invalid timeout specified.\n");
 747                return ME_ERRNO_INVALID_TIMEOUT;
 748        }
 749
 750        if (instance->single_config[channel].status !=
 751            ME_SINGLE_CHANNEL_CONFIGURED) {
 752                PERROR("Channel is not configured to work in single mode!\n");
 753                return ME_ERRNO_PREVIOUS_CONFIG;
 754        }
 755
 756        if (inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM) {
 757                PERROR("Subdevice is busy.\n");
 758                return ME_ERRNO_SUBDEVICE_BUSY;
 759        }
 760
 761        ME_SUBDEVICE_ENTER;
 762
 763        // Cancel control task
 764        PDEBUG("Cancel control task.\n");
 765        instance->ai_control_task_flag = 0;
 766        cancel_delayed_work(&instance->ai_control_task);
 767
 768        if (time_out) {
 769                delay = (time_out * HZ) / 1000;
 770
 771                if (delay == 0)
 772                        delay = 1;
 773        }
 774
 775        spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
 776
 777        // Mark that StreamConfig is removed.
 778        instance->chan_list_len = 0;
 779
 780        spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
 781        /// @note Imprtant: Preserve EXT IRQ settings.
 782        tmp = inl(instance->ctrl_reg);
 783        // Clear FIFOs and dissable interrupts
 784        tmp &=
 785            ~(ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO);
 786
 787        tmp &=
 788            ~(ME4600_AI_CTRL_BIT_SC_IRQ | ME4600_AI_CTRL_BIT_HF_IRQ |
 789              ME4600_AI_CTRL_BIT_LE_IRQ);
 790        tmp |=
 791            ME4600_AI_CTRL_BIT_SC_IRQ_RESET | ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
 792            ME4600_AI_CTRL_BIT_LE_IRQ_RESET;
 793
 794        tmp |= ME4600_AI_CTRL_BIT_IMMEDIATE_STOP;
 795        outl(tmp, instance->ctrl_reg);
 796        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
 797                   instance->ctrl_reg - instance->reg_base, tmp);
 798
 799        outl(0, instance->scan_pre_timer_low_reg);
 800        PDEBUG_REG("scan_pre_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
 801                   instance->reg_base,
 802                   instance->scan_pre_timer_low_reg - instance->reg_base, 0);
 803        outl(0, instance->scan_pre_timer_high_reg);
 804        PDEBUG_REG("scan_pre_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
 805                   instance->reg_base,
 806                   instance->scan_pre_timer_high_reg - instance->reg_base, 0);
 807        outl(0, instance->scan_timer_low_reg);
 808        PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
 809                   instance->reg_base,
 810                   instance->scan_timer_low_reg - instance->reg_base, 0);
 811        outl(0, instance->scan_timer_high_reg);
 812        PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
 813                   instance->reg_base,
 814                   instance->scan_timer_high_reg - instance->reg_base, 0);
 815        outl(65, instance->chan_timer_reg);
 816        PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
 817                   instance->reg_base,
 818                   instance->chan_timer_reg - instance->reg_base, 65);
 819        outl(65, instance->chan_pre_timer_reg);
 820        PDEBUG_REG("chan_pre_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
 821                   instance->reg_base,
 822                   instance->chan_pre_timer_reg - instance->reg_base, 65);
 823
 824        //Reactive FIFOs. Enable work.
 825        tmp |= ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO;
 826        outl(tmp, instance->ctrl_reg);
 827        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
 828                   instance->ctrl_reg - instance->reg_base, tmp);
 829
 830        outl(instance->single_config[channel].entry,
 831             instance->channel_list_reg);
 832        PDEBUG_REG("channel_list_reg outl(0x%lX+0x%lX)=0x%x\n",
 833                   instance->reg_base,
 834                   instance->channel_list_reg - instance->reg_base,
 835                   instance->single_config[channel].entry);
 836
 837        // Preserve EXT IRQ settings.
 838        tmp &= (ME4600_AI_CTRL_BIT_EX_IRQ | ME4600_AI_CTRL_BIT_EX_IRQ_RESET);
 839        outl(instance->single_config[channel].ctrl | tmp, instance->ctrl_reg);
 840        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
 841                   instance->ctrl_reg - instance->reg_base,
 842                   instance->single_config[channel].ctrl | tmp);
 843
 844        spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
 845
 846        if (!(instance->single_config[channel].ctrl & ME4600_AI_CTRL_BIT_EX_TRIG)) {    // Software start
 847                inl(instance->start_reg);
 848                PDEBUG_REG("start_reg inl(0x%lX+0x%lX)\n", instance->reg_base,
 849                           instance->start_reg - instance->reg_base);
 850
 851                delay = 2;
 852        }
 853
 854        j = jiffies;
 855
 856        while (!(inl(instance->status_reg) & ME4600_AI_STATUS_BIT_EF_DATA)) {
 857                if (delay && ((jiffies - j) >= delay)) {
 858                        if (!(instance->single_config[channel].ctrl & ME4600_AI_CTRL_BIT_EX_TRIG)) {    // Software start.
 859                                PERROR("Value not available after wait.\n");
 860                                err = ME_ERRNO_INTERNAL;
 861                        } else {        // External start.
 862                                PERROR("Timeout reached.\n");
 863                                err = ME_ERRNO_TIMEOUT;
 864                        }
 865                        break;
 866                }
 867                // Wait
 868                set_current_state(TASK_INTERRUPTIBLE);
 869                schedule_timeout(1);
 870
 871                if (signal_pending(current)) {
 872                        PERROR
 873                            ("Wait on external trigger interrupted by signal.\n");
 874                        err = ME_ERRNO_SIGNAL;
 875                        break;
 876                }
 877
 878                if (instance->status != ai_status_single_configured) {
 879                        PERROR("Wait interrupted by reset.\n");
 880                        err = ME_ERRNO_CANCELLED;
 881                        break;
 882                }
 883        }
 884
 885        // Read value.
 886        if (!err) {
 887                val = inl(instance->data_reg) ^ 0x8000;
 888                PDEBUG_REG("data_reg inl(0x%lX+0x%lX)=0x%x\n",
 889                           instance->reg_base,
 890                           instance->data_reg - instance->reg_base, val);
 891                *value = val & ME4600_AI_MAX_DATA;
 892        } else {
 893                *value = 0xFFFFFFFF;
 894        }
 895
 896        // Restore settings.
 897        spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
 898        tmp = inl(instance->ctrl_reg);
 899        // Clear FIFOs and dissable interrupts.
 900        tmp &=
 901            ~(ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO);
 902        tmp |= ME4600_AI_CTRL_BIT_SC_IRQ | ME4600_AI_CTRL_BIT_HF_IRQ;
 903        tmp |=
 904            ME4600_AI_CTRL_BIT_SC_IRQ_RESET | ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
 905            ME4600_AI_CTRL_BIT_LE_IRQ_RESET | ME4600_AI_CTRL_BIT_IMMEDIATE_STOP;
 906        outl(tmp, instance->ctrl_reg);
 907        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
 908                   instance->ctrl_reg - instance->reg_base, tmp);
 909        spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
 910
 911        spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
 912
 913        ME_SUBDEVICE_EXIT;
 914
 915        return err;
 916}
 917
 918static int me4600_ai_io_stream_config(me_subdevice_t * subdevice,
 919                                      struct file *filep,
 920                                      meIOStreamConfig_t * config_list,
 921                                      int count,
 922                                      meIOStreamTrigger_t * trigger,
 923                                      int fifo_irq_threshold, int flags)
 924{
 925        me4600_ai_subdevice_t *instance;
 926        int err = ME_ERRNO_SUCCESS;
 927        int i;                  // internal multipurpose variable
 928        unsigned long long data_required;
 929
 930        volatile uint32_t entry;
 931        volatile uint32_t ctrl = ME4600_AI_CTRL_BIT_IMMEDIATE_STOP;
 932        volatile uint32_t tmp;  // use when current copy of register's value needed
 933        unsigned long cpu_flags;
 934
 935        uint64_t acq_ticks;
 936        uint64_t scan_ticks;
 937        uint64_t conv_ticks;
 938        unsigned int acq_start_ticks_low = trigger->iAcqStartTicksLow;
 939        unsigned int acq_start_ticks_high = trigger->iAcqStartTicksHigh;
 940        unsigned int scan_start_ticks_low = trigger->iScanStartTicksLow;
 941        unsigned int scan_start_ticks_high = trigger->iScanStartTicksHigh;
 942        unsigned int conv_start_ticks_low = trigger->iConvStartTicksLow;
 943        unsigned int conv_start_ticks_high = trigger->iConvStartTicksHigh;
 944
 945        PDEBUG("executed. idx=0\n");
 946
 947        instance = (me4600_ai_subdevice_t *) subdevice;
 948
 949        if (flags) {
 950                PERROR("Invalid flag specified.\n");
 951                return ME_ERRNO_INVALID_FLAGS;
 952        }
 953
 954        ME_SUBDEVICE_ENTER
 955            // Convert ticks to 64 bit long values
 956            acq_ticks =
 957            (uint64_t) acq_start_ticks_low +
 958            ((uint64_t) acq_start_ticks_high << 32);
 959        scan_ticks =
 960            (uint64_t) scan_start_ticks_low +
 961            ((uint64_t) scan_start_ticks_high << 32);
 962        conv_ticks =
 963            (uint64_t) conv_start_ticks_low +
 964            ((uint64_t) conv_start_ticks_high << 32);
 965
 966        // Check settings - begin
 967        switch (trigger->iAcqStartTrigType) {
 968        case ME_TRIG_TYPE_SW:
 969        case ME_TRIG_TYPE_EXT_DIGITAL:
 970        case ME_TRIG_TYPE_EXT_ANALOG:
 971                break;
 972
 973        default:
 974                PERROR("Invalid acquisition start trigger type specified.\n");
 975                err = ME_ERRNO_INVALID_ACQ_START_TRIG_TYPE;
 976                goto ERROR;
 977                break;
 978        }
 979
 980        if ((trigger->iAcqStartTrigType == ME_TRIG_TYPE_SW)
 981            && (trigger->iAcqStartTrigEdge != ME_TRIG_EDGE_NONE)) {
 982                PERROR("Invalid acquisition start trigger edge specified.\n");
 983                err = ME_ERRNO_INVALID_ACQ_START_TRIG_EDGE;
 984                goto ERROR;
 985        }
 986
 987        if (trigger->iAcqStartTrigType != ME_TRIG_TYPE_SW) {
 988                switch (trigger->iAcqStartTrigEdge) {
 989                case ME_TRIG_EDGE_RISING:
 990                case ME_TRIG_EDGE_FALLING:
 991                case ME_TRIG_EDGE_ANY:
 992                        break;
 993
 994                default:
 995                        PERROR
 996                            ("Invalid acquisition start trigger edge specified.\n");
 997                        err = ME_ERRNO_INVALID_ACQ_START_TRIG_EDGE;
 998                        goto ERROR;
 999                        break;
1000                }

1001        }
1002
1003        if (trigger->iAcqStartTrigChan != ME_TRIG_CHAN_DEFAULT) {
1004                PERROR
1005                    ("Invalid acquisition start trigger channel specified.\n");
1006                err = ME_ERRNO_INVALID_ACQ_START_TRIG_CHAN;
1007                goto ERROR;
1008        }
1009
1010        if ((acq_ticks < ME4600_AI_MIN_ACQ_TICKS)
1011            || (acq_ticks > ME4600_AI_MAX_ACQ_TICKS)) {
1012                PERROR
1013                    ("Invalid acquisition start trigger argument specified.\n");
1014                err = ME_ERRNO_INVALID_ACQ_START_ARG;
1015                goto ERROR;
1016        }
1017
1018        switch (trigger->iScanStartTrigType) {
1019
1020        case ME_TRIG_TYPE_TIMER:
1021                if ((scan_ticks < ME4600_AI_MIN_SCAN_TICKS)
1022                    || (scan_ticks > ME4600_AI_MAX_SCAN_TICKS)
1023                    || (scan_ticks < count * conv_ticks)
1024                    ) {
1025                        PERROR("Invalid scan start argument specified.\n");
1026                        err = ME_ERRNO_INVALID_SCAN_START_ARG;
1027                        goto ERROR;
1028                }
1029                break;
1030
1031        case ME_TRIG_TYPE_EXT_DIGITAL:
1032                if (trigger->iAcqStartTrigType != ME_TRIG_TYPE_EXT_DIGITAL) {
1033                        PERROR
1034                            ("Invalid scan start trigger type specified (Acq is HW digital)\n");
1035                        err = ME_ERRNO_INVALID_SCAN_START_TRIG_TYPE;
1036                        goto ERROR;
1037                }
1038                break;
1039
1040        case ME_TRIG_TYPE_EXT_ANALOG:
1041                if (trigger->iAcqStartTrigType != ME_TRIG_TYPE_EXT_ANALOG) {
1042                        PERROR
1043                            ("Invalid scan start trigger type specified (Acq is HW analog)\n");
1044                        err = ME_ERRNO_INVALID_SCAN_START_TRIG_TYPE;
1045                        goto ERROR;
1046                }
1047                break;
1048
1049        case ME_TRIG_TYPE_FOLLOW:
1050                break;
1051
1052        default:
1053                PERROR("Invalid scan start trigger type specified.\n");
1054                err = ME_ERRNO_INVALID_SCAN_START_TRIG_TYPE;
1055                goto ERROR;
1056                break;
1057        }
1058
1059        switch (trigger->iConvStartTrigType) {
1060
1061        case ME_TRIG_TYPE_TIMER:
1062                if ((conv_ticks < ME4600_AI_MIN_CHAN_TICKS)
1063                    || (conv_ticks > ME4600_AI_MAX_CHAN_TICKS)) {
1064                        PERROR
1065                            ("Invalid conv start trigger argument specified.\n");
1066                        err = ME_ERRNO_INVALID_CONV_START_ARG;
1067                        goto ERROR;
1068                }
1069                break;
1070
1071        case ME_TRIG_TYPE_EXT_DIGITAL:
1072                if ((trigger->iScanStartTrigType != ME_TRIG_TYPE_FOLLOW)
1073                    || (trigger->iAcqStartTrigType !=
1074                        ME_TRIG_TYPE_EXT_DIGITAL)) {
1075                        PERROR("Invalid conv start trigger type specified.\n");
1076                        err = ME_ERRNO_INVALID_CONV_START_TRIG_TYPE;
1077                        goto ERROR;
1078                }
1079                break;
1080
1081        case ME_TRIG_TYPE_EXT_ANALOG:
1082                if ((trigger->iScanStartTrigType != ME_TRIG_TYPE_FOLLOW)
1083                    || (trigger->iAcqStartTrigType !=
1084                        ME_TRIG_TYPE_EXT_ANALOG)) {
1085                        PERROR("Invalid conv start trigger type specified.\n");
1086                        err = ME_ERRNO_INVALID_CONV_START_TRIG_TYPE;
1087                        goto ERROR;
1088                }
1089                break;
1090
1091        default:
1092                PERROR("Invalid conv start trigger type specified.\n");
1093                err = ME_ERRNO_INVALID_CONV_START_TRIG_TYPE;
1094                goto ERROR;
1095
1096                break;
1097        }
1098/**
1099* Aceptable settings:
1100* iScanStopTrigType             :       iAcqStopTrigType
1101*
1102* ME_TRIG_TYPE_NONE             :       ME_TRIG_TYPE_NONE       -> infinite count with manual stop
1103* ME_TRIG_TYPE_NONE             :       ME_TRIG_TYPE_COUNT      -> stop after getting iScanStopCount list of values (iScanStopCount * count)
1104* ME_TRIG_TYPE_COUNT    :       ME_TRIG_TYPE_FOLLOW     -> stop after getting iAcqStopCount values (it can stops in midle of the list)
1105*/
1106        switch (trigger->iScanStopTrigType) {
1107
1108        case ME_TRIG_TYPE_NONE:
1109                break;
1110
1111        case ME_TRIG_TYPE_COUNT:
1112                if (trigger->iScanStopCount <= 0) {
1113                        PERROR("Invalid scan stop argument specified.\n");
1114                        err = ME_ERRNO_INVALID_SCAN_STOP_ARG;
1115                        goto ERROR;
1116                }
1117                break;
1118
1119        default:
1120                PERROR("Invalid scan stop trigger type specified.\n");
1121                err = ME_ERRNO_INVALID_SCAN_STOP_TRIG_TYPE;
1122                goto ERROR;
1123                break;
1124        }
1125
1126        switch (trigger->iAcqStopTrigType) {
1127
1128        case ME_TRIG_TYPE_NONE:
1129                if (trigger->iScanStopTrigType != ME_TRIG_TYPE_NONE) {
1130                        PERROR("Invalid acq stop trigger type specified.\n");
1131                        err = ME_ERRNO_INVALID_ACQ_STOP_TRIG_TYPE;
1132                        goto ERROR;
1133                }
1134                break;
1135
1136        case ME_TRIG_TYPE_FOLLOW:
1137                if (trigger->iScanStopTrigType != ME_TRIG_TYPE_COUNT) {
1138                        PERROR("Invalid acq stop trigger type specified.\n");
1139                        err = ME_ERRNO_INVALID_ACQ_STOP_TRIG_TYPE;
1140                        goto ERROR;
1141                }
1142                break;
1143
1144        case ME_TRIG_TYPE_COUNT:
1145                if (trigger->iScanStopTrigType != ME_TRIG_TYPE_NONE) {
1146                        PERROR("Invalid acq stop trigger type specified.\n");
1147                        err = ME_ERRNO_INVALID_ACQ_STOP_TRIG_TYPE;
1148                        goto ERROR;
1149                }
1150
1151                if (trigger->iAcqStopCount <= 0) {
1152                        PERROR
1153                            ("Invalid acquisition or scan stop argument specified.\n");
1154                        err = ME_ERRNO_INVALID_ACQ_STOP_ARG;
1155                        goto ERROR;
1156                }
1157                break;
1158
1159        default:
1160                PERROR("Invalid acq stop trigger type specified.\n");
1161                err = ME_ERRNO_INVALID_ACQ_STOP_TRIG_TYPE;
1162                goto ERROR;
1163                break;
1164        }
1165
1166        if ((count <= 0) || (count > ME4600_AI_LIST_COUNT)) {
1167                PERROR("Invalid channel list count specified.\n");
1168                err = ME_ERRNO_INVALID_CONFIG_LIST_COUNT;
1169                goto ERROR;
1170        }
1171///This is general limitation
1172//      if (fifo_irq_threshold < 0 || fifo_irq_threshold >= ME4600_AI_CIRC_BUF_COUNT)
1173///This is limitation from Windows. I use it for compatibility.
1174        if (fifo_irq_threshold < 0
1175            || fifo_irq_threshold >= ME4600_AI_FIFO_COUNT) {
1176                PERROR("Invalid fifo irq threshold specified.\n");
1177                err = ME_ERRNO_INVALID_FIFO_IRQ_THRESHOLD;
1178                goto ERROR;
1179        }
1180
1181        if ((config_list[0].iRef == ME_REF_AI_DIFFERENTIAL)
1182            && (instance->channels == 16)) {
1183                PERROR
1184                    ("Differential reference is not available on this subdevice.\n");
1185                err = ME_ERRNO_INVALID_REF;
1186                goto ERROR;
1187        }
1188
1189        if (flags & ME_IO_STREAM_CONFIG_SAMPLE_AND_HOLD) {
1190                if (!instance->sh) {
1191                        PERROR
1192                            ("Sample and hold is not available for this board.\n");
1193                        err = ME_ERRNO_INVALID_FLAGS;
1194                        goto ERROR;
1195                }
1196                if (config_list[0].iRef == ME_REF_AI_DIFFERENTIAL) {
1197                        PERROR
1198                            ("Sample and hold is not available in differential mode.\n");
1199                        err = ME_ERRNO_INVALID_FLAGS;
1200                        goto ERROR;
1201                }
1202        }
1203
1204        for (i = 0; i < count; i++) {
1205                if ((config_list[i].iStreamConfig < 0)
1206                    || (config_list[i].iStreamConfig >= instance->ranges_len)) {
1207                        PERROR("Invalid stream config specified.\n");
1208                        err = ME_ERRNO_INVALID_STREAM_CONFIG;
1209                        goto ERROR;
1210                }
1211
1212                if ((config_list[i].iRef != ME_REF_AI_GROUND)
1213                    && (config_list[i].iRef != ME_REF_AI_DIFFERENTIAL)) {
1214                        PERROR("Invalid references in the list. Ref=0x%x\n",
1215                               config_list[i].iRef);
1216                        err = ME_ERRNO_INVALID_REF;
1217                        goto ERROR;
1218                }
1219
1220                if (config_list[i].iStreamConfig % 2) { // StreamConfig: 1 or 3
1221                        if (config_list[i].iRef == ME_REF_AI_DIFFERENTIAL) {
1222                                PERROR
1223                                    ("Only bipolar modes support differential measurement.\n");
1224                                err = ME_ERRNO_INVALID_REF;
1225                                goto ERROR;
1226                        }
1227                }
1228
1229                if (config_list[i].iRef != config_list[0].iRef) {
1230                        PERROR
1231                            ("Not all references in the configuration list are equal. Ref[0]=0x%x Ref[%d]=0x%x\n",
1232                             config_list[0].iRef, i, config_list[i].iRef);
1233                        err = ME_ERRNO_INVALID_REF;
1234                        goto ERROR;
1235                }
1236
1237                if ((config_list[i].iRef == ME_REF_AI_DIFFERENTIAL)
1238                    && (config_list[i].iChannel >= 16)) {
1239                        PERROR("Channel not available in differential mode.\n");
1240                        err = ME_ERRNO_INVALID_CHANNEL;
1241                        goto ERROR;
1242                }
1243
1244                if ((config_list[i].iChannel < 0)
1245                    || (config_list[i].iChannel >= instance->channels)) {
1246                        PERROR("Invalid channel number specified.\n");
1247                        err = ME_ERRNO_INVALID_CHANNEL;
1248                        goto ERROR;
1249                }
1250        }
1251
1252        // Check settings - end
1253
1254        //Cancel control task
1255        PDEBUG("Cancel control task.\n");
1256        instance->ai_control_task_flag = 0;
1257        cancel_delayed_work(&instance->ai_control_task);
1258
1259        // Work around from Keith Hartley - begin
1260        if (trigger->iScanStartTrigType == ME_TRIG_TYPE_TIMER) {
1261                if (count == 1) {
1262                        // The hardware does not work properly with a non-zero scan time
1263                        // if there is only ONE channel in the channel list. In this case
1264                        // we must set the scan time to zero and use the channel time.
1265
1266                        conv_ticks = scan_ticks;
1267                        trigger->iScanStartTrigType = ME_TRIG_TYPE_FOLLOW;
1268                } else if (scan_ticks == count * conv_ticks) {
1269                        // Another hardware problem. If the number of scan ticks is
1270                        // exactly equal to the number of channel ticks multiplied by
1271                        // the number of channels then the sampling rate is reduced
1272                        // by half.
1273                        trigger->iScanStartTrigType = ME_TRIG_TYPE_FOLLOW;
1274                }
1275        }
1276        // Work around from Keith Hartley - end
1277
1278        spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
1279
1280        if (inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM) {
1281                PERROR("Subdevice is busy.\n");
1282                spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
1283                ME_SUBDEVICE_EXIT;
1284                return ME_ERRNO_SUBDEVICE_BUSY;
1285        }
1286
1287        instance->status = ai_status_none;
1288        spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
1289        // Stop all actions. Block all interrupts. Clear (disable) FIFOs.
1290        ctrl =
1291            ME4600_AI_CTRL_BIT_LE_IRQ_RESET | ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
1292            ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
1293
1294        tmp = inl(instance->ctrl_reg);
1295        // Preserve EXT IRQ and OFFSET settings. Clean other bits.
1296        tmp &=
1297            (ME4600_AI_CTRL_BIT_EX_IRQ | ME4600_AI_CTRL_BIT_EX_IRQ_RESET |
1298             ME4600_AI_CTRL_BIT_FULLSCALE | ME4600_AI_CTRL_BIT_OFFSET);
1299
1300        // Send it to register.
1301        outl(tmp | ctrl, instance->ctrl_reg);
1302        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1303                   instance->ctrl_reg - instance->reg_base, tmp | ctrl);
1304
1305        // Enable channel fifo -> data fifo in stream_start().
1306        ctrl |= ME4600_AI_CTRL_BIT_CHANNEL_FIFO;
1307        outl(tmp | ctrl, instance->ctrl_reg);
1308        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1309                   instance->ctrl_reg - instance->reg_base, tmp | ctrl);
1310        spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1311
1312        // Write the channel list
1313        for (i = 0; i < count; i++) {
1314                entry = config_list[i].iChannel;
1315
1316                switch (config_list[i].iStreamConfig) {
1317                case 0: //BIPOLAR 10V
1318/*
1319                                // ME4600_AI_LIST_RANGE_BIPOLAR_10 = 0x0000
1320                                // 'entry |= ME4600_AI_LIST_RANGE_BIPOLAR_10' <== Do nothing. Removed.
1321                                entry |= ME4600_AI_LIST_RANGE_BIPOLAR_10;
1322*/
1323                        break;
1324                case 1: //UNIPOLAR 10V
1325                        entry |= ME4600_AI_LIST_RANGE_UNIPOLAR_10;
1326                        break;
1327                case 2: //BIPOLAR 2.5V
1328                        entry |= ME4600_AI_LIST_RANGE_BIPOLAR_2_5;
1329                        break;
1330                case 3: //UNIPOLAR 2.5V
1331                        entry |= ME4600_AI_LIST_RANGE_UNIPOLAR_2_5;
1332                        break;
1333                default:
1334                        PERROR_CRITICAL("UNCHECK ERROR in config_list!\n");
1335                        PERROR_CRITICAL
1336                            ("WRONG range\nPosition:%d Range:0x%04X\n", i,
1337                             config_list[i].iStreamConfig);
1338                        goto VERIFY_ERROR;
1339                        break;
1340                }
1341
1342                switch (config_list[i].iRef) {
1343                case ME_REF_AI_GROUND:  //SINGLE ENDED
1344/*
1345                                // ME4600_AI_LIST_INPUT_SINGLE_ENDED = 0x0000
1346                                // 'entry |= ME4600_AI_LIST_INPUT_SINGLE_ENDED' ==> Do nothing. Removed.
1347                                entry |= ME4600_AI_LIST_INPUT_SINGLE_ENDED;
1348*/ break;
1349                case ME_REF_AI_DIFFERENTIAL:    //DIFFERENTIAL
1350                        entry |= ME4600_AI_LIST_INPUT_DIFFERENTIAL;
1351                        break;
1352                default:
1353                        PERROR_CRITICAL("UNCHECK ERROR in config_list!\n");
1354                        PERROR_CRITICAL
1355                            ("WRONG reference\nPosition:%d Reference:0x%04X\n",
1356                             i, config_list[i].iRef);
1357                        goto VERIFY_ERROR;
1358                        break;
1359                }
1360
1361                //Add last entry flag
1362                if (i == (count - 1)) {
1363                        entry |= ME4600_AI_LIST_LAST_ENTRY;
1364                }
1365
1366                outl(entry, instance->channel_list_reg);
1367                PDEBUG_REG("channel_list_reg outl(0x%lX+0x%lX)=0x%x\n",
1368                           instance->reg_base,
1369                           instance->channel_list_reg - instance->reg_base,
1370                           entry);
1371        }
1372
1373        // Set triggering registers
1374        --acq_ticks;
1375        outl(acq_ticks, instance->chan_pre_timer_reg);
1376        PDEBUG_REG("chan_pre_timer_reg outl(0x%lX+0x%lX)=0x%llX\n",
1377                   instance->reg_base,
1378                   instance->chan_pre_timer_reg - instance->reg_base,
1379                   acq_ticks);
1380        outl(acq_ticks, instance->scan_pre_timer_low_reg);
1381        PDEBUG_REG("scan_pre_timer_low_reg outl(0x%lX+0x%lX)=0x%llX\n",
1382                   instance->reg_base,
1383                   instance->scan_pre_timer_low_reg - instance->reg_base,
1384                   acq_ticks & 0xFFFFFFFF);
1385        outl((acq_ticks >> 32), instance->scan_pre_timer_high_reg);
1386        PDEBUG_REG("scan_pre_timer_high_reg outl(0x%lX+0x%lX)=0x%llX\n",
1387                   instance->reg_base,
1388                   instance->scan_pre_timer_high_reg - instance->reg_base,
1389                   (acq_ticks >> 32) & 0xFFFFFFFF);
1390
1391        // Set triggers
1392        switch (trigger->iAcqStartTrigType) {
1393                // Internal
1394        case ME_TRIG_TYPE_SW:
1395                // Nothing to set.
1396                break;
1397
1398                // External
1399        case ME_TRIG_TYPE_EXT_ANALOG:
1400                ctrl |= ME4600_AI_CTRL_BIT_EX_TRIG_ANALOG;
1401        case ME_TRIG_TYPE_EXT_DIGITAL:
1402                ctrl |= ME4600_AI_CTRL_BIT_EX_TRIG;
1403
1404                // External trigger needs edge's definition
1405                switch (trigger->iAcqStartTrigEdge) {
1406                case ME_TRIG_EDGE_RISING:
1407                        // Nothing to set.
1408                        break;
1409
1410                case ME_TRIG_EDGE_FALLING:
1411                        ctrl |= ME4600_AI_CTRL_BIT_EX_TRIG_FALLING;
1412                        break;
1413
1414                case ME_TRIG_EDGE_ANY:
1415                        ctrl |=
1416                            ME4600_AI_CTRL_BIT_EX_TRIG_FALLING |
1417                            ME4600_AI_CTRL_BIT_EX_TRIG_BOTH;
1418                        break;
1419
1420                default:
1421                        PERROR_CRITICAL
1422                            ("UNCHECK TRIGGER EDGE in triggers structure!\n");
1423                        PERROR_CRITICAL
1424                            ("WRONG acquisition start trigger:0x%04X.\n",
1425                             trigger->iAcqStartTrigEdge);
1426                        err = ME_ERRNO_INVALID_ACQ_START_TRIG_EDGE;
1427                        goto VERIFY_ERROR;
1428                        break;
1429                }
1430                break;
1431
1432        default:
1433                PERROR_CRITICAL("UNCHECK TRIGGER in triggers structure!\n");
1434                PERROR_CRITICAL("WRONG acquisition start trigger:0x%04X.\n",
1435                                trigger->iAcqStartTrigType);
1436                err = ME_ERRNO_INVALID_ACQ_START_TRIG_TYPE;
1437                goto VERIFY_ERROR;
1438                break;
1439        }
1440
1441        switch (trigger->iScanStartTrigType) {
1442        case ME_TRIG_TYPE_TIMER:
1443                --scan_ticks;
1444                outl(scan_ticks, instance->scan_timer_low_reg);
1445                PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%llX\n",
1446                           instance->reg_base,
1447                           instance->scan_timer_low_reg - instance->reg_base,
1448                           scan_ticks & 0xFFFFFFFF);
1449                outl((scan_ticks >> 32), instance->scan_timer_high_reg);
1450                PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%llX\n",
1451                           instance->reg_base,
1452                           instance->scan_timer_high_reg - instance->reg_base,
1453                           (scan_ticks >> 32) & 0xFFFFFFFF);
1454
1455                if (trigger->iAcqStartTrigType == ME_TRIG_TYPE_SW) {
1456                        ctrl |= ME4600_AI_CTRL_BIT_MODE_0;
1457                } else {
1458                        ctrl |= ME4600_AI_CTRL_BIT_MODE_1;
1459                }
1460                break;
1461
1462        case ME_TRIG_TYPE_EXT_DIGITAL:
1463        case ME_TRIG_TYPE_EXT_ANALOG:
1464                outl(0, instance->scan_timer_low_reg);
1465                PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
1466                           instance->reg_base,
1467                           instance->scan_timer_low_reg - instance->reg_base,
1468                           0);
1469                outl(0, instance->scan_timer_high_reg);
1470                PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
1471                           instance->reg_base,
1472                           instance->scan_timer_high_reg - instance->reg_base,
1473                           0);
1474                ctrl |= ME4600_AI_CTRL_BIT_MODE_2;
1475                break;
1476
1477        case ME_TRIG_TYPE_FOLLOW:
1478                outl(0, instance->scan_timer_low_reg);
1479                PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
1480                           instance->reg_base,
1481                           instance->scan_timer_low_reg - instance->reg_base,
1482                           0);
1483                outl(0, instance->scan_timer_high_reg);
1484                PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
1485                           instance->reg_base,
1486                           instance->scan_timer_high_reg - instance->reg_base,
1487                           0);
1488
1489                if (trigger->iAcqStartTrigType == ME_TRIG_TYPE_SW) {
1490                        ctrl |= ME4600_AI_CTRL_BIT_MODE_0;
1491                } else {
1492                        ctrl |= ME4600_AI_CTRL_BIT_MODE_1;
1493                }
1494                break;
1495
1496        default:
1497                PERROR_CRITICAL("UNCHECK TRIGGER in triggers structure!\n");
1498                PERROR_CRITICAL("WRONG scan start trigger:0x%04X.\n",
1499                                trigger->iScanStartTrigType);
1500                err = ME_ERRNO_INVALID_SCAN_START_TRIG_TYPE;
1501                goto VERIFY_ERROR;
1502                break;
1503        }
1504
1505        switch (trigger->iConvStartTrigType) {
1506
1507        case ME_TRIG_TYPE_TIMER:
1508                --conv_ticks;
1509                outl(conv_ticks, instance->chan_timer_reg);
1510                PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%llX\n",
1511                           instance->reg_base,
1512                           instance->chan_timer_reg - instance->reg_base,
1513                           conv_ticks);
1514                break;
1515
1516        case ME_TRIG_TYPE_EXT_DIGITAL:
1517        case ME_TRIG_TYPE_EXT_ANALOG:
1518                outl(0, instance->chan_timer_reg);
1519                PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
1520                           instance->reg_base,
1521                           instance->chan_timer_reg - instance->reg_base, 0);
1522                ctrl |= ME4600_AI_CTRL_BIT_MODE_0 | ME4600_AI_CTRL_BIT_MODE_1;
1523                break;
1524
1525        default:
1526                PERROR_CRITICAL("UNCHECK TRIGGER in triggers structure!\n");
1527                PERROR_CRITICAL("WRONG conv start trigger:0x%04X.\n",
1528                                trigger->iConvStartTrigType);
1529                err = ME_ERRNO_INVALID_CONV_START_TRIG_TYPE;
1530                goto VERIFY_ERROR;
1531
1532                break;
1533        }
1534
1535        //Sample & Hold feature
1536        if (flags & ME_IO_STREAM_CONFIG_SAMPLE_AND_HOLD) {
1537                if (instance->sh) {
1538                        ctrl |= ME4600_AI_CTRL_BIT_SAMPLE_HOLD;
1539                } else {
1540                        PERROR_CRITICAL("UNCHECK S&H feature!\n");
1541                        err = ME_ERRNO_INVALID_FLAGS;
1542                        goto VERIFY_ERROR;
1543                }
1544        }
1545        //Enable IRQs sources but leave latches blocked.
1546        ctrl |= (ME4600_AI_CTRL_BIT_HF_IRQ | ME4600_AI_CTRL_BIT_SC_IRQ | ME4600_AI_CTRL_BIT_LE_IRQ);    //The last IRQ source (ME4600_AI_CTRL_BIT_LE_IRQ) is unused!
1547
1548        //Everything is good. Finalize
1549        spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
1550        tmp = inl(instance->ctrl_reg);
1551
1552        //Preserve EXT IRQ and OFFSET settings. Clean other bits.
1553        tmp &=
1554            (ME4600_AI_CTRL_BIT_EX_IRQ | ME4600_AI_CTRL_BIT_EX_IRQ_RESET |
1555             ME4600_AI_CTRL_BIT_FULLSCALE | ME4600_AI_CTRL_BIT_OFFSET);
1556
1557        // write the control word
1558        outl(ctrl | tmp, instance->ctrl_reg);
1559        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1560                   instance->ctrl_reg - instance->reg_base, ctrl | tmp);
1561        spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1562
1563        //Set the global parameters end exit.
1564        instance->chan_list_len = count;
1565        instance->fifo_irq_threshold = fifo_irq_threshold;
1566
1567        if (trigger->iAcqStopTrigType == ME_TRIG_TYPE_COUNT) {
1568                data_required =
1569                    (unsigned long long)trigger->iAcqStopCount *
1570                    (unsigned long long)count;
1571                if (data_required > UINT_MAX)
1572                        data_required = UINT_MAX;
1573                instance->data_required = (unsigned int)data_required;
1574        } else if (trigger->iScanStopTrigType == ME_TRIG_TYPE_COUNT)
1575                instance->data_required =
1576                    (unsigned long long)trigger->iScanStopCount;
1577        else
1578                instance->data_required = 0;
1579
1580        // Mark subdevice as configured to work in stream mode.
1581        instance->status = ai_status_stream_configured;
1582
1583        // Deinit single config. Set all entries to NOT_CONFIGURED.
1584        for (i = 0; i < instance->channels; i++) {
1585                instance->single_config[i].status =
1586                    ME_SINGLE_CHANNEL_NOT_CONFIGURED;
1587        }
1588
1589      VERIFY_ERROR:             // Error in code. Wrong setting check. This should never ever happend!
1590        spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
1591      ERROR:                    // Error in settings.
1592        ME_SUBDEVICE_EXIT;
1593
1594        return err;
1595}
1596
1597static int me4600_ai_io_stream_new_values(me_subdevice_t * subdevice,
1598                                          struct file *filep,
1599                                          int time_out, int *count, int flags)
1600{
1601        me4600_ai_subdevice_t *instance;
1602        int err = ME_ERRNO_SUCCESS;
1603        unsigned long t;
1604        unsigned long j;
1605        int volatile head;
1606
1607        PDEBUG("executed. idx=0\n");
1608
1609        if (flags) {
1610                PERROR("Invalid flag specified.\n");
1611                return ME_ERRNO_INVALID_FLAGS;
1612        }
1613
1614        if (time_out < 0) {
1615                PERROR("Invalid time_out specified.\n");
1616                return ME_ERRNO_INVALID_TIMEOUT;
1617        }
1618
1619        if (time_out) {
1620                t = (time_out * HZ) / 1000;
1621
1622                if (t == 0)
1623                        t = 1;
1624        } else {                // Max time.
1625                t = LONG_MAX;
1626        }
1627
1628        instance = (me4600_ai_subdevice_t *) subdevice;
1629
1630        ME_SUBDEVICE_ENTER;
1631
1632        j = jiffies;
1633
1634        while (1) {
1635                // Only runing device can generate break.
1636                head = instance->circ_buf.head;
1637                wait_event_interruptible_timeout(instance->wait_queue,
1638                                                 ((head !=
1639                                                   instance->circ_buf.head)
1640                                                  ||
1641                                                  ((instance->status <=
1642                                                    ai_status_stream_run_wait)
1643                                                   && (instance->status >=
1644                                                       ai_status_stream_end_wait))),
1645                                                 t);
1646
1647                if (head != instance->circ_buf.head) {  // New data in buffer.
1648                        break;
1649                } else if (instance->status == ai_status_stream_end) {  // End of work.
1650                        break;
1651                } else if (instance->status == ai_status_stream_fifo_error) {
1652                        err = ME_ERRNO_FIFO_BUFFER_OVERFLOW;
1653                        break;
1654                } else if (instance->status == ai_status_stream_buffer_error) {
1655                        err = ME_ERRNO_RING_BUFFER_OVERFLOW;
1656                        break;
1657                } else if (instance->status == ai_status_stream_error) {
1658                        err = ME_ERRNO_INTERNAL;
1659                        break;
1660                } else if ((jiffies - j) >= t) {
1661                        PERROR("Wait on values timed out.\n");
1662                        err = ME_ERRNO_TIMEOUT;
1663                        break;
1664                } else if (signal_pending(current)) {
1665                        PERROR("Wait on values interrupted from signal.\n");
1666                        err = ME_ERRNO_SIGNAL;
1667                        break;
1668                }
1669                // Correct timeout.
1670                t -= jiffies - j;
1671        }
1672
1673        *count = me_circ_buf_values(&instance->circ_buf);
1674
1675        ME_SUBDEVICE_EXIT;
1676
1677        return err;
1678}
1679
1680static int inline me4600_ai_io_stream_read_get_value(me4600_ai_subdevice_t *
1681                                                     instance, int *values,
1682                                                     const int count,
1683                                                     const int flags)
1684{
1685        int n;
1686        int i;
1687        uint32_t value;
1688
1689        ///Checking how many datas can be copied.
1690        n = me_circ_buf_values(&instance->circ_buf);
1691        if (n <= 0)
1692                return 0;
1693
1694        if (n > count)
1695                n = count;
1696
1697        if (flags & ME_IO_STREAM_READ_FRAMES) {
1698                if (n < instance->chan_list_len)        //Not enough data!
1699                        return 0;
1700                n -= n % instance->chan_list_len;
1701        }
1702
1703        for (i = 0; i < n; i++) {
1704                value = *(instance->circ_buf.buf + instance->circ_buf.tail);
1705                if (put_user(value, values + i)) {
1706                        PERROR("Cannot copy new values to user.\n");
1707                        return -ME_ERRNO_INTERNAL;
1708                }
1709                instance->circ_buf.tail++;
1710                instance->circ_buf.tail &= instance->circ_buf.mask;
1711        }
1712        return n;
1713}
1714
1715static int me4600_ai_io_stream_read(me_subdevice_t * subdevice,
1716                                    struct file *filep,
1717                                    int read_mode,
1718                                    int *values, int *count, int flags)
1719{
1720        me4600_ai_subdevice_t *instance;
1721        int err = ME_ERRNO_SUCCESS;
1722        int ret;
1723
1724        int c = *count;
1725        int min = c;
1726
1727        PDEBUG("executed. idx=0\n");
1728
1729        if (flags & ~ME_IO_STREAM_READ_FRAMES) {
1730                PERROR("Invalid flag specified.\n");
1731                return ME_ERRNO_INVALID_FLAGS;
1732        }
1733
1734        if (!values || !count) {
1735                PERROR("Request has invalid pointer.\n");
1736                return ME_ERRNO_INVALID_POINTER;
1737        }
1738
1739        if (c < 0) {
1740                PERROR("Request has invalid value's counter.\n");
1741                return ME_ERRNO_INVALID_VALUE_COUNT;
1742        }
1743
1744        if ((read_mode != ME_READ_MODE_BLOCKING)
1745            && (read_mode != ME_READ_MODE_NONBLOCKING)) {
1746                PERROR("Invalid read mode specified.\n");
1747                return ME_ERRNO_INVALID_READ_MODE;
1748        }
1749
1750        if (c == 0) {           //You get what you want! Nothing more or less.
1751                return ME_ERRNO_SUCCESS;
1752        }
1753
1754        instance = (me4600_ai_subdevice_t *) subdevice;
1755        ME_SUBDEVICE_ENTER;
1756
1757        //Check if subdevice is configured.
1758        if (instance->chan_list_len <= 0) {
1759                PERROR("Subdevice wasn't configured.\n");
1760                ME_SUBDEVICE_EXIT;
1761                return ME_ERRNO_PREVIOUS_CONFIG;
1762        }
1763
1764        if (flags & ME_IO_STREAM_READ_FRAMES) {
1765                if (c < instance->chan_list_len) {      //Not enough data requested.
1766                        PERROR
1767                            ("When using FRAME_READ mode minimal size is defined by channel list.\n");
1768                        ME_SUBDEVICE_EXIT;
1769                        return ME_ERRNO_INVALID_VALUE_COUNT;
1770                }
1771        }
1772
1773        if (c > (ME4600_AI_CIRC_BUF_COUNT - instance->chan_list_len)) { // To return acceptable amount of data when user pass too big value.
1774                min = ME4600_AI_CIRC_BUF_COUNT - instance->chan_list_len;
1775        }
1776
1777        if (flags & ME_IO_STREAM_READ_FRAMES) {
1778                //Wait for whole list.
1779                if (read_mode == ME_READ_MODE_BLOCKING) {
1780                        min = c - (c % instance->chan_list_len);
1781                }
1782
1783                if (read_mode == ME_READ_MODE_NONBLOCKING) {
1784                        min = instance->chan_list_len;
1785                }
1786        }
1787
1788        if ((inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM)) {   //Working
1789                //If blocking mode -> wait for data.
1790                if ((me_circ_buf_values(&instance->circ_buf) < min)
1791                    && (read_mode == ME_READ_MODE_BLOCKING)) {
1792                        wait_event_interruptible(instance->wait_queue,
1793                                                 ((me_circ_buf_values
1794                                                   (&instance->circ_buf) >= min)
1795                                                  || !(inl(instance->status_reg)
1796                                                       &
1797                                                       ME4600_AI_STATUS_BIT_FSM)));
1798
1799                        if (signal_pending(current)) {
1800                                PERROR
1801                                    ("Wait on values interrupted from signal.\n");
1802                                err = ME_ERRNO_SIGNAL;
1803                        }
1804                }
1805        }
1806
1807        ret = me4600_ai_io_stream_read_get_value(instance, values, c, flags);
1808        if (ret < 0) {
1809                err = -ret;
1810                *count = 0;
1811        } else if (ret == 0) {
1812                *count = 0;
1813                if (instance->status == ai_status_stream_fifo_error) {
1814                        err = ME_ERRNO_FIFO_BUFFER_OVERFLOW;
1815                        instance->status = ai_status_stream_end;
1816                } else if (instance->status == ai_status_stream_buffer_error) {
1817                        err = ME_ERRNO_RING_BUFFER_OVERFLOW;
1818                        instance->status = ai_status_stream_end;
1819                } else if (instance->status == ai_status_stream_end) {
1820                        err = ME_ERRNO_SUBDEVICE_NOT_RUNNING;
1821                } else if (instance->status == ai_status_stream_error) {
1822                        err = ME_ERRNO_INTERNAL;
1823                } else if (instance->status == ai_status_none) {
1824                        PDEBUG("Stream canceled.\n");
1825                        err = ME_ERRNO_INTERNAL;
1826                }
1827        } else {
1828                *count = ret;
1829        }
1830
1831        ME_SUBDEVICE_EXIT;
1832
1833        return err;
1834}
1835
1836/** @brief Stop aqusation. Preserve FIFOs.
1837*
1838* @param instance The subdevice instance (pointer).
1839*/
1840
1841static int ai_stop_immediately(me4600_ai_subdevice_t * instance)
1842{
1843        unsigned long cpu_flags = 0;
1844        volatile uint32_t ctrl;
1845        const int timeout = HZ / 10;    //100ms
1846        int i;
1847
1848        for (i = 0; i <= timeout; i++) {
1849                spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
1850                ctrl = inl(instance->ctrl_reg);
1851                ctrl &= ~ME4600_AI_CTRL_BIT_STOP;
1852                ctrl |=
1853                    (ME4600_AI_CTRL_BIT_IMMEDIATE_STOP |
1854                     ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
1855                     ME4600_AI_CTRL_BIT_SC_IRQ_RESET);
1856                outl(ctrl, instance->ctrl_reg);
1857                PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
1858                           instance->reg_base,
1859                           instance->ctrl_reg - instance->reg_base, ctrl);
1860                spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1861
1862                if (!(inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM)) {  // Exit.
1863                        break;
1864                }
1865
1866                PINFO("Wait for stop: %d\n", i + 1);
1867                //Still working!
1868                set_current_state(TASK_INTERRUPTIBLE);
1869                schedule_timeout(1);
1870        }
1871
1872        if (i > timeout) {
1873                PERROR_CRITICAL("FSM IS BUSY!\n");
1874                return ME_ERRNO_INTERNAL;
1875        }
1876
1877        return ME_ERRNO_SUCCESS;
1878}
1879
1880static int me4600_ai_io_stream_start(me_subdevice_t * subdevice,
1881                                     struct file *filep,
1882                                     int start_mode, int time_out, int flags)
1883{
1884        me4600_ai_subdevice_t *instance;
1885        int err = ME_ERRNO_SUCCESS;
1886        unsigned long cpu_flags = 0;
1887        unsigned long ref;
1888        unsigned long delay = 0;
1889
1890        volatile uint32_t tmp;
1891
1892        PDEBUG("executed. idx=0\n");
1893
1894        instance = (me4600_ai_subdevice_t *) subdevice;
1895
1896        if (flags) {
1897                PERROR("Invalid flag specified.\n");
1898                return ME_ERRNO_INVALID_FLAGS;
1899        }
1900
1901        if ((start_mode != ME_START_MODE_BLOCKING)
1902            && (start_mode != ME_START_MODE_NONBLOCKING)) {
1903                PERROR("Invalid start mode specified.\n");
1904                return ME_ERRNO_INVALID_START_MODE;
1905        }
1906
1907        if (time_out < 0) {
1908                PERROR("Invalid timeout specified.\n");
1909                return ME_ERRNO_INVALID_TIMEOUT;
1910        }
1911
1912        if (time_out) {
1913                delay = (time_out * HZ) / 1000;
1914
1915                if (delay == 0)
1916                        delay = 1;
1917        }
1918
1919        ME_SUBDEVICE_ENTER
1920            spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
1921
1922        tmp = inl(instance->ctrl_reg);
1923
1924        if ((tmp & ME4600_AI_STATUS_BIT_FSM)) {
1925                PERROR("Conversion is already running.\n");
1926                spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1927                err = ME_ERRNO_SUBDEVICE_BUSY;
1928                goto ERROR;
1929        }
1930
1931        if (instance->chan_list_len == 0) {     //Not configured!
1932                PERROR("Subdevice is not configured to work in stream mode!\n");
1933                spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1934                err = ME_ERRNO_PREVIOUS_CONFIG;
1935                goto ERROR;
1936        }
1937
1938        if (!(tmp & (ME4600_AI_CTRL_BIT_MODE_0 | ME4600_AI_CTRL_BIT_MODE_1 | ME4600_AI_CTRL_BIT_MODE_2))) {     //Mode 0 = single work => no stream config
1939                PERROR("Subdevice is configured to work in single mode.\n");
1940                spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1941                err = ME_ERRNO_PREVIOUS_CONFIG;
1942                goto ERROR;
1943        }
1944        //Reset stop bits.
1945        tmp |= ME4600_AI_CTRL_BIT_IMMEDIATE_STOP | ME4600_AI_CTRL_BIT_STOP;
1946        outl(tmp, instance->ctrl_reg);
1947        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1948                   instance->ctrl_reg - instance->reg_base, tmp);
1949
1950        //Start datas' FIFO.
1951        tmp |= ME4600_AI_CTRL_BIT_DATA_FIFO;
1952        //Free stop bits.
1953        tmp &= ~(ME4600_AI_CTRL_BIT_IMMEDIATE_STOP | ME4600_AI_CTRL_BIT_STOP);
1954        outl(tmp, instance->ctrl_reg);
1955        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1956                   instance->ctrl_reg - instance->reg_base, tmp);
1957        spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1958
1959        //Cancel control task
1960        PDEBUG("Cancel control task.\n");
1961        instance->ai_control_task_flag = 0;
1962        cancel_delayed_work(&instance->ai_control_task);
1963
1964        //Set the starting values.
1965        instance->ISM.global_read = 0;
1966        instance->ISM.read = 0;
1967        //Clear circular buffer
1968        instance->circ_buf.head = 0;
1969        instance->circ_buf.tail = 0;
1970
1971        //Set everything.
1972        ai_data_acquisition_logic(instance);
1973
1974        //Set status to 'wait for start'
1975        instance->status = ai_status_stream_run_wait;
1976
1977        // Set control task's timeout
1978        instance->timeout.delay = delay;
1979        instance->timeout.start_time = jiffies;
1980
1981        //Lets go! Start work
1982        inl(instance->start_reg);
1983        PDEBUG_REG("start_reg inl(0x%lX+0x%lX)\n", instance->reg_base,
1984                   instance->start_reg - instance->reg_base);
1985
1986        // Schedule control task
1987        instance->ai_control_task_flag = 1;
1988        queue_delayed_work(instance->me4600_workqueue,
1989                           &instance->ai_control_task, 1);
1990
1991        PDEVELOP("Delay:%ld\n", delay);
1992
1993        if (start_mode == ME_START_MODE_BLOCKING) {     //Wait for start.
1994                ref = jiffies;
1995                //Only runing process will interrupt this call. Events are signaled when status change. Extra timeout add for safe reason.
1996                wait_event_interruptible_timeout(instance->wait_queue,
1997                                                 (instance->status !=
1998                                                  ai_status_stream_run_wait),
1999                                                 (delay) ? delay +
2000                                                 1 : LONG_MAX);

2001
2002                if ((instance->status != ai_status_stream_run)
2003                    && (instance->status != ai_status_stream_end)) {
2004                        PDEBUG("Starting stream canceled. %d\n",
2005                               instance->status);
2006                        err = ME_ERRNO_CANCELLED;
2007                }
2008
2009                if (signal_pending(current)) {
2010                        PERROR("Wait on start of state machine interrupted.\n");
2011                        instance->status = ai_status_none;
2012                        ai_stop_isr(instance);
2013                        err = ME_ERRNO_SIGNAL;
2014                } else if ((delay) && ((jiffies - ref) > delay)) {
2015                        if (instance->status != ai_status_stream_run) {
2016                                if (instance->status == ai_status_stream_end) {
2017                                        PDEBUG("Timeout reached.\n");
2018                                } else if ((jiffies - ref) > delay + 1) {
2019                                        PERROR
2020                                            ("Timeout reached. Not handled by control task!\n");
2021                                        ai_stop_isr(instance);
2022                                        instance->status =
2023                                            ai_status_stream_error;
2024                                } else {
2025                                        PERROR
2026                                            ("Timeout reached. Signal come but status is strange: %d\n",
2027                                             instance->status);
2028                                        ai_stop_isr(instance);
2029                                        instance->status =
2030                                            ai_status_stream_error;
2031                                }
2032
2033                                instance->ai_control_task_flag = 0;
2034                                cancel_delayed_work(&instance->ai_control_task);
2035                                err = ME_ERRNO_TIMEOUT;
2036                        }
2037                }
2038        }
2039#ifdef MEDEBUG_INFO
2040        tmp = inl(instance->ctrl_reg);
2041        PDEBUG_REG("ctrl_reg inl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
2042                   instance->ctrl_reg - instance->reg_base, tmp);
2043
2044        PINFO("STATUS_BIT_FSM=%s.\n",
2045              (tmp & ME4600_AI_STATUS_BIT_FSM) ? "on" : "off");
2046        PINFO("CTRL_BIT_HF_IRQ=%s.\n",
2047              (tmp & ME4600_AI_CTRL_BIT_HF_IRQ) ? "enable" : "disable");
2048        PINFO("CTRL_BIT_HF_IRQ_RESET=%s.\n",
2049              (tmp & ME4600_AI_CTRL_BIT_HF_IRQ_RESET) ? "reset" : "work");
2050        PINFO("CTRL_BIT_SC_IRQ=%s.\n",
2051              (tmp & ME4600_AI_CTRL_BIT_SC_IRQ) ? "enable" : "disable");
2052        PINFO("CTRL_BIT_SC_RELOAD=%s.\n",
2053              (tmp & ME4600_AI_CTRL_BIT_SC_RELOAD) ? "on" : "off");
2054        PINFO("CTRL_BIT_SC_IRQ_RESET=%s.\n",
2055              (tmp & ME4600_AI_CTRL_BIT_SC_IRQ_RESET) ? "reset" : "work");
2056#endif
2057
2058      ERROR:
2059        ME_SUBDEVICE_EXIT;
2060
2061        return err;
2062}
2063
2064static int me4600_ai_io_stream_status(me_subdevice_t * subdevice,
2065                                      struct file *filep,
2066                                      int wait,
2067                                      int *status, int *values, int flags)
2068{
2069        me4600_ai_subdevice_t *instance;
2070        int err = ME_ERRNO_SUCCESS;
2071
2072        PDEBUG("executed. idx=0\n");
2073
2074        instance = (me4600_ai_subdevice_t *) subdevice;
2075
2076        if (flags) {
2077                PERROR("Invalid flag specified.\n");
2078                return ME_ERRNO_INVALID_FLAGS;
2079        }
2080
2081        ME_SUBDEVICE_ENTER;
2082
2083        switch (instance->status) {
2084        case ai_status_single_configured:
2085        case ai_status_stream_configured:
2086        case ai_status_stream_end:
2087        case ai_status_stream_fifo_error:
2088        case ai_status_stream_buffer_error:
2089        case ai_status_stream_error:
2090                *status = ME_STATUS_IDLE;
2091                break;
2092
2093        case ai_status_stream_run_wait:
2094        case ai_status_stream_run:
2095        case ai_status_stream_end_wait:
2096                *status = ME_STATUS_BUSY;
2097                break;
2098
2099        case ai_status_none:
2100        default:
2101                *status =
2102                    (inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM) ?
2103                    ME_STATUS_BUSY : ME_STATUS_IDLE;
2104                break;
2105        }
2106
2107        if ((wait == ME_WAIT_IDLE) && (*status == ME_STATUS_BUSY)) {
2108                // Only runing process will interrupt this call. Events are signaled when status change. Extra timeout add for safe reason.
2109                wait_event_interruptible_timeout(instance->wait_queue,
2110                                                 ((instance->status !=
2111                                                   ai_status_stream_run_wait)
2112                                                  && (instance->status !=
2113                                                      ai_status_stream_run)
2114                                                  && (instance->status !=
2115                                                      ai_status_stream_end_wait)),
2116                                                 LONG_MAX);
2117
2118                if (instance->status != ai_status_stream_end) {
2119                        PDEBUG("Wait for IDLE canceled. %d\n",
2120                               instance->status);
2121                        err = ME_ERRNO_CANCELLED;
2122                }
2123
2124                if (signal_pending(current)) {
2125                        PERROR("Wait for IDLE interrupted.\n");
2126                        instance->status = ai_status_none;
2127                        ai_stop_isr(instance);
2128                        err = ME_ERRNO_SIGNAL;
2129                }
2130
2131                *status = ME_STATUS_IDLE;
2132        }
2133
2134        *values = me_circ_buf_values(&instance->circ_buf);
2135        PDEBUG("me_circ_buf_values(&instance->circ_buf)=%d.\n", *values);
2136
2137        ME_SUBDEVICE_EXIT;
2138
2139        return err;
2140}
2141
2142static int me4600_ai_io_stream_stop(me_subdevice_t * subdevice,
2143                                    struct file *filep,
2144                                    int stop_mode, int flags)
2145{
2146/**
2147 @note Stop is implemented only in blocking mode.
2148 @note Function return when state machine is stoped.
2149*/
2150        me4600_ai_subdevice_t *instance;
2151        unsigned long cpu_flags;
2152        uint32_t ctrl;
2153        int ret;
2154
2155        PDEBUG("executed. idx=0\n");
2156
2157        if (flags) {
2158                PERROR("Invalid flag specified.\n");
2159                return ME_ERRNO_INVALID_FLAGS;
2160        }
2161
2162        if ((stop_mode != ME_STOP_MODE_IMMEDIATE)
2163            && (stop_mode != ME_STOP_MODE_LAST_VALUE)) {
2164                PERROR("Invalid stop mode specified.\n");
2165                return ME_ERRNO_INVALID_STOP_MODE;
2166        }
2167
2168        instance = (me4600_ai_subdevice_t *) subdevice;
2169
2170        ME_SUBDEVICE_ENTER;
2171
2172        // Mark as stopping. => Software stop.
2173        instance->status = ai_status_stream_end_wait;
2174
2175        if (stop_mode == ME_STOP_MODE_IMMEDIATE) {
2176                ret = ai_stop_immediately(instance);
2177
2178                if (ret) {
2179                        PERROR("FSM is still busy.\n");
2180                        ME_SUBDEVICE_EXIT;
2181                        return ME_ERRNO_SUBDEVICE_BUSY;
2182                }
2183                instance->ai_control_task_flag = 0;
2184
2185        } else if (stop_mode == ME_STOP_MODE_LAST_VALUE) {
2186                // Set stop bit in registry.
2187                spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
2188                ctrl = inl(instance->ctrl_reg);
2189                ctrl |= ME4600_AI_CTRL_BIT_STOP;
2190                outl(ctrl, instance->ctrl_reg);
2191                PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
2192                           instance->reg_base,
2193                           instance->ctrl_reg - instance->reg_base, ctrl);
2194                spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
2195
2196                // Only runing process will interrupt this call. Events are signaled when status change.
2197                wait_event_interruptible_timeout(instance->wait_queue,
2198                                                 (instance->status !=
2199                                                  ai_status_stream_end_wait),
2200                                                 LONG_MAX);
2201
2202                if (instance->status != ai_status_stream_end) {
2203                        PDEBUG("Stopping stream canceled.\n");
2204                        ret = ME_ERRNO_CANCELLED;
2205                }
2206
2207                if (signal_pending(current)) {
2208                        PERROR("Stopping stream interrupted.\n");
2209                        instance->status = ai_status_none;
2210                        ret = ME_ERRNO_SIGNAL;
2211                }
2212                // End of work.
2213                ai_stop_immediately(instance);
2214
2215        }
2216
2217        ret = ai_read_data_pooling(instance);
2218        if (ret > 0) {          // Everything fine. More datas put to software buffer.
2219                instance->status = ai_status_stream_end;
2220                ret = ME_ERRNO_SUCCESS;
2221                // Signal that we put last data to software buffer.
2222                wake_up_interruptible_all(&instance->wait_queue);
2223        } else if (ret == 0) {  // Everything fine. No more datas in FIFO.
2224                instance->status = ai_status_stream_end;
2225                ret = ME_ERRNO_SUCCESS;
2226        } else if (ret == -ME_ERRNO_RING_BUFFER_OVERFLOW) {     // Stop is unsuccessful, buffer is overflow.
2227                instance->status = ai_status_stream_buffer_error;
2228                ret = ME_ERRNO_SUCCESS;
2229        } else {                // Stop is unsuccessful
2230                instance->status = ai_status_stream_end;
2231                ret = -ret;
2232        }
2233
2234        ME_SUBDEVICE_EXIT;
2235
2236        return ret;
2237}
2238
2239static int me4600_ai_query_range_by_min_max(me_subdevice_t * subdevice,
2240                                            int unit,
2241                                            int *min,
2242                                            int *max, int *maxdata, int *range)
2243{
2244        me4600_ai_subdevice_t *instance;
2245        int i;
2246        int r = -1;
2247        int diff = 21E6;
2248
2249        PDEBUG("executed. idx=0\n");
2250
2251        instance = (me4600_ai_subdevice_t *) subdevice;
2252
2253        if ((*max - *min) < 0) {
2254                PERROR("Invalid minimum and maximum values specified.\n");
2255                return ME_ERRNO_INVALID_MIN_MAX;
2256        }
2257
2258        if ((unit == ME_UNIT_VOLT) || (unit == ME_UNIT_ANY)) {
2259                for (i = 0; i < instance->ranges_len; i++) {
2260                        if ((instance->ranges[i].min <= *min)
2261                            && ((instance->ranges[i].max + 1000) >= *max)) {
2262                                if ((instance->ranges[i].max -
2263                                     instance->ranges[i].min) - (*max - *min) <
2264                                    diff) {
2265                                        r = i;
2266                                        diff =
2267                                            (instance->ranges[i].max -
2268                                             instance->ranges[i].min) - (*max -
2269                                                                         *min);
2270                                }
2271                        }
2272                }
2273
2274                if (r < 0) {
2275                        PERROR("No matching range found.\n");
2276                        return ME_ERRNO_NO_RANGE;
2277                } else {
2278                        *min = instance->ranges[r].min;
2279                        *max = instance->ranges[r].max;
2280                        *maxdata = ME4600_AI_MAX_DATA;
2281                        *range = r;
2282                }
2283        } else {
2284                PERROR("Invalid physical unit specified.\n");
2285                return ME_ERRNO_INVALID_UNIT;
2286        }
2287
2288        return ME_ERRNO_SUCCESS;
2289}
2290
2291static int me4600_ai_query_number_ranges(me_subdevice_t * subdevice,
2292                                         int unit, int *count)
2293{
2294        me4600_ai_subdevice_t *instance;
2295
2296        PDEBUG("executed. idx=0\n");
2297
2298        instance = (me4600_ai_subdevice_t *) subdevice;
2299
2300        if ((unit == ME_UNIT_VOLT) || (unit == ME_UNIT_ANY)) {
2301                *count = instance->ranges_len;
2302        } else {
2303                *count = 0;
2304        }
2305
2306        return ME_ERRNO_SUCCESS;
2307}
2308
2309static int me4600_ai_query_range_info(me_subdevice_t * subdevice,
2310                                      int range,
2311                                      int *unit,
2312                                      int *min, int *max, int *maxdata)
2313{
2314        me4600_ai_subdevice_t *instance;
2315
2316        PDEBUG("executed. idx=0\n");
2317
2318        instance = (me4600_ai_subdevice_t *) subdevice;
2319
2320        if ((range < instance->ranges_len) && (range >= 0)) {
2321                *unit = ME_UNIT_VOLT;
2322                *min = instance->ranges[range].min;
2323                *max = instance->ranges[range].max;
2324                *maxdata = ME4600_AI_MAX_DATA;
2325        } else {
2326                PERROR("Invalid range number specified.\n");
2327                return ME_ERRNO_INVALID_RANGE;
2328        }
2329
2330        return ME_ERRNO_SUCCESS;
2331}
2332
2333static int me4600_ai_query_timer(me_subdevice_t * subdevice,
2334                                 int timer,
2335                                 int *base_frequency,
2336                                 long long *min_ticks, long long *max_ticks)
2337{
2338        me4600_ai_subdevice_t *instance;
2339
2340        PDEBUG("executed. idx=0\n");
2341
2342        instance = (me4600_ai_subdevice_t *) subdevice;
2343
2344        switch (timer) {
2345
2346        case ME_TIMER_ACQ_START:
2347                *base_frequency = ME4600_AI_BASE_FREQUENCY;
2348                *min_ticks = ME4600_AI_MIN_ACQ_TICKS;
2349                *max_ticks = ME4600_AI_MAX_ACQ_TICKS;
2350                break;
2351
2352        case ME_TIMER_SCAN_START:
2353                *base_frequency = ME4600_AI_BASE_FREQUENCY;
2354                *min_ticks = ME4600_AI_MIN_SCAN_TICKS;
2355                *max_ticks = ME4600_AI_MAX_SCAN_TICKS;
2356                break;
2357
2358        case ME_TIMER_CONV_START:
2359                *base_frequency = ME4600_AI_BASE_FREQUENCY;
2360                *min_ticks = ME4600_AI_MIN_CHAN_TICKS;
2361                *max_ticks = ME4600_AI_MAX_CHAN_TICKS;
2362                break;
2363
2364        default:
2365                PERROR("Invalid timer specified.(0x%04x)\n", timer);
2366
2367                return ME_ERRNO_INVALID_TIMER;
2368        }
2369
2370        return ME_ERRNO_SUCCESS;
2371}
2372
2373static int me4600_ai_query_number_channels(me_subdevice_t * subdevice,
2374                                           int *number)
2375{
2376        me4600_ai_subdevice_t *instance;
2377
2378        PDEBUG("executed. idx=0\n");
2379
2380        instance = (me4600_ai_subdevice_t *) subdevice;
2381        *number = instance->channels;
2382
2383        return ME_ERRNO_SUCCESS;
2384}
2385
2386static int me4600_ai_query_subdevice_type(me_subdevice_t * subdevice,
2387                                          int *type, int *subtype)
2388{
2389        PDEBUG("executed. idx=0\n");
2390
2391        *type = ME_TYPE_AI;
2392        *subtype = ME_SUBTYPE_STREAMING;
2393
2394        return ME_ERRNO_SUCCESS;
2395}
2396
2397static int me4600_ai_query_subdevice_caps(me_subdevice_t * subdevice, int *caps)
2398{
2399        PDEBUG("executed. idx=0\n");
2400
2401        *caps =
2402            ME_CAPS_AI_TRIG_SYNCHRONOUS | ME_CAPS_AI_FIFO |
2403            ME_CAPS_AI_FIFO_THRESHOLD;
2404
2405        return ME_ERRNO_SUCCESS;
2406}
2407
2408static int me4600_ai_query_subdevice_caps_args(struct me_subdevice *subdevice,
2409                                               int cap, int *args, int count)
2410{
2411        me4600_ai_subdevice_t *instance;
2412        int err = ME_ERRNO_SUCCESS;
2413
2414        instance = (me4600_ai_subdevice_t *) subdevice;
2415
2416        PDEBUG("executed. idx=0\n");
2417
2418        if (count != 1) {
2419                PERROR("Invalid capability argument count.\n");
2420                return ME_ERRNO_INVALID_CAP_ARG_COUNT;
2421        }
2422
2423        switch (cap) {
2424        case ME_CAP_AI_FIFO_SIZE:
2425                args[0] = ME4600_AI_FIFO_COUNT;
2426                break;
2427
2428        case ME_CAP_AI_BUFFER_SIZE:
2429                args[0] =
2430                    (instance->circ_buf.buf) ? ME4600_AI_CIRC_BUF_COUNT : 0;
2431                break;
2432
2433        default:
2434                PERROR("Invalid capability.\n");
2435                err = ME_ERRNO_INVALID_CAP;
2436                args[0] = 0;
2437        }
2438
2439        return err;
2440}
2441
2442void ai_limited_isr(me4600_ai_subdevice_t * instance, const uint32_t irq_status,
2443                    const uint32_t ctrl_status)
2444{
2445        int to_read;
2446
2447        if (!instance->fifo_irq_threshold) {    //No threshold provided. SC ends work. HF need reseting.
2448                if (irq_status & ME4600_IRQ_STATUS_BIT_SC) {
2449                        if (ai_read_data(instance, instance->ISM.next) != instance->ISM.next) { //ERROR!
2450                                PERROR
2451                                    ("Limited amounts aqusition with TH=0: Circular buffer full!\n");
2452                                instance->status =
2453                                    ai_status_stream_buffer_error;
2454                        } else {
2455                                instance->status = ai_status_stream_end;
2456                        }
2457                        //End of work.
2458                        ai_stop_isr(instance);
2459                } else if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF) {
2460                        instance->ISM.global_read += ME4600_AI_FIFO_HALF;
2461
2462                        if (ai_read_data(instance, ME4600_AI_FIFO_HALF) != ME4600_AI_FIFO_HALF) {       //ERROR!
2463                                PERROR
2464                                    ("Limited amounts aqusition with TH = 0: Circular buffer full!\n");
2465                                //End of work.
2466                                ai_stop_isr(instance);
2467                                instance->status =
2468                                    ai_status_stream_buffer_error;
2469                        } else {
2470                                //Continue.
2471                                ai_limited_ISM(instance, irq_status);
2472                        }
2473                }
2474                //Signal user.
2475                wake_up_interruptible_all(&instance->wait_queue);
2476        } else                  //if(instance->fifo_irq_threshold)
2477        {
2478                if (irq_status & ME4600_IRQ_STATUS_BIT_SC) {
2479                        instance->ISM.read = 0;
2480                        if ((instance->fifo_irq_threshold < ME4600_AI_FIFO_HALF)
2481                            && (!(ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA)))
2482                        {
2483                                to_read =
2484                                    ME4600_AI_FIFO_HALF -
2485                                    (ME4600_AI_FIFO_HALF %
2486                                     instance->fifo_irq_threshold);
2487                                PDEBUG
2488                                    ("Limited amounts aqusition with TH != 0: Not fast enough data aqusition! correction=%d\n",
2489                                     to_read);
2490                        } else {
2491                                to_read = instance->ISM.next;
2492                        }
2493                        instance->ISM.global_read += to_read;
2494
2495                        ai_reschedule_SC(instance);
2496
2497                        if (ai_read_data(instance, to_read) != to_read) {       //ERROR!
2498                                PERROR
2499                                    ("Limited amounts aqusition with TH != 0: Circular buffer full!\n");
2500                                //End of work.
2501                                ai_stop_isr(instance);
2502                                instance->status =
2503                                    ai_status_stream_buffer_error;
2504                        } else {
2505                                //Continue.
2506                                ai_limited_ISM(instance, irq_status);
2507                        }
2508
2509                        //Signal user.
2510                        wake_up_interruptible_all(&instance->wait_queue);
2511                } else if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF) {
2512                        instance->ISM.read += ME4600_AI_FIFO_HALF;
2513                        instance->ISM.global_read += ME4600_AI_FIFO_HALF;
2514
2515                        if (ai_read_data(instance, ME4600_AI_FIFO_HALF) != ME4600_AI_FIFO_HALF) {       //ERROR!
2516                                PERROR
2517                                    ("Limited amounts aqusition with TH != 0: Circular buffer full!\n");
2518                                ai_stop_isr(instance);
2519
2520                                instance->status =
2521                                    ai_status_stream_buffer_error;
2522                                //Signal user.
2523                                wake_up_interruptible_all(&instance->
2524                                                          wait_queue);
2525                        } else {
2526                                //Countinue.
2527                                ai_limited_ISM(instance, irq_status);
2528                        }
2529                }
2530
2531                if (instance->ISM.global_read >= instance->data_required) {     //End of work. Next paranoid pice of code: '>=' instead od '==' only to be sure.
2532                        ai_stop_isr(instance);
2533                        if (instance->status < ai_status_stream_end) {
2534                                instance->status = ai_status_stream_end;
2535                        }
2536#ifdef MEDEBUG_ERROR
2537                        if (instance->ISM.global_read > instance->data_required) {      //This is security check case. This should never ever happend!
2538                                PERROR
2539                                    ("Limited amounts aqusition: Read more data than necessary! data_required=%d < read=%d\n",
2540                                     instance->data_required,
2541                                     instance->ISM.global_read);
2542                                //Signal error (warning??).
2543                                instance->status = ai_status_stream_error;
2544                        }
2545#endif
2546                }
2547        }
2548}
2549
2550void ai_infinite_isr(me4600_ai_subdevice_t * instance,
2551                     const uint32_t irq_status, const uint32_t ctrl_status)
2552{
2553        int to_read;
2554
2555        if (irq_status & ME4600_IRQ_STATUS_BIT_SC) {    //next chunck of data -> read fifo
2556                //Set new state in ISM.
2557                if ((instance->fifo_irq_threshold < ME4600_AI_FIFO_HALF) && (!(ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA))) {  //There is more data than we ecpected. Propably we aren't fast enough. Read as many as possible.
2558                        if (instance->fifo_irq_threshold) {
2559                                to_read =
2560                                    ME4600_AI_FIFO_HALF -
2561                                    (ME4600_AI_FIFO_HALF %
2562                                     instance->fifo_irq_threshold);
2563                                if (to_read > instance->fifo_irq_threshold) {
2564                                        PDEBUG
2565                                            ("Infinite aqusition: Not fast enough data aqusition! TH != 0: correction=%d\n",
2566                                             to_read);
2567                                }
2568                        } else {        //No threshold specified.
2569                                to_read = ME4600_AI_FIFO_HALF;
2570                        }
2571                } else {
2572                        to_read = instance->ISM.next;
2573                }
2574
2575                instance->ISM.read += to_read;
2576
2577                //Get data
2578                if (ai_read_data(instance, to_read) != to_read) {       //ERROR!
2579                        PERROR("Infinite aqusition: Circular buffer full!\n");
2580                        ai_stop_isr(instance);
2581                        instance->status = ai_status_stream_buffer_error;
2582                } else {
2583                        ai_infinite_ISM(instance);
2584                        instance->ISM.global_read += instance->ISM.read;
2585                        instance->ISM.read = 0;
2586                }
2587
2588                //Signal data to user
2589                wake_up_interruptible_all(&instance->wait_queue);
2590        } else if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF) {  //fifo is half full -> read fifo       Large blocks only!
2591                instance->ISM.read += ME4600_AI_FIFO_HALF;
2592
2593                if (ai_read_data(instance, ME4600_AI_FIFO_HALF) != ME4600_AI_FIFO_HALF) {       //ERROR!
2594                        PERROR("Infinite aqusition: Circular buffer full!\n");
2595                        ai_stop_isr(instance);
2596                        instance->status = ai_status_stream_buffer_error;
2597
2598                        //Signal it.
2599                        wake_up_interruptible_all(&instance->wait_queue);
2600                } else {
2601                        ai_infinite_ISM(instance);
2602                }
2603        }
2604}
2605
2606#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
2607static irqreturn_t me4600_ai_isr(int irq, void *dev_id)
2608#else
2609static irqreturn_t me4600_ai_isr(int irq, void *dev_id, struct pt_regs *regs)
2610#endif
2611{                               /// @note This is time critical function!
2612        uint32_t irq_status;
2613        uint32_t ctrl_status;
2614        me4600_ai_subdevice_t *instance = dev_id;
2615        //int to_read;
2616
2617        PDEBUG("executed. idx=0\n");
2618
2619        if (irq != instance->irq) {
2620                PERROR("Incorrect interrupt num: %d.\n", irq);
2621                return IRQ_NONE;
2622        }
2623
2624        irq_status = inl(instance->irq_status_reg);
2625        if (!
2626            (irq_status &
2627             (ME4600_IRQ_STATUS_BIT_AI_HF | ME4600_IRQ_STATUS_BIT_SC))) {
2628#ifdef MEDEBUG_INFO
2629                if ((irq_status & (ME4600_IRQ_STATUS_BIT_AI_HF | ME4600_IRQ_STATUS_BIT_SC | ME4600_IRQ_STATUS_BIT_LE)) == ME4600_IRQ_STATUS_BIT_LE) {   //This is security check case. LE is unused. This should never ever happend.
2630                        PINFO
2631                            ("%ld Shared interrupt. %s(): irq_status_reg=LE_IRQ\n",
2632                             jiffies, __func__);
2633                } else {
2634                        PINFO
2635                            ("%ld Shared interrupt. %s(): irq_status_reg=0x%04X\n",
2636                             jiffies, __func__, irq_status);
2637                }
2638#endif
2639                return IRQ_NONE;
2640        }
2641
2642        if (!instance->circ_buf.buf) {  //Security check.
2643                PERROR_CRITICAL("CIRCULAR BUFFER NOT EXISTS!\n");
2644                ai_stop_isr(instance);
2645                return IRQ_HANDLED;
2646        }
2647        //Get the status register.
2648        ctrl_status = inl(instance->status_reg);
2649
2650#ifdef MEDEBUG_INFO
2651        if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF)
2652                PINFO("HF interrupt active\n");
2653        if (irq_status & ME4600_IRQ_STATUS_BIT_SC)
2654                PINFO("SC interrupt active\n");
2655        if (irq_status & ME4600_IRQ_STATUS_BIT_LE)
2656                PINFO("LE interrupt active\n");
2657#endif
2658
2659        //This is safety check!
2660        if ((irq_status & ME4600_IRQ_STATUS_BIT_AI_HF)
2661            && (ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA)) {
2662                PDEBUG("HF interrupt active but FIFO under half\n");
2663                //Reset HF interrupt latch.
2664                spin_lock(instance->ctrl_reg_lock);
2665                outl(ctrl_status | ME4600_AI_CTRL_BIT_HF_IRQ_RESET,
2666                     instance->ctrl_reg);
2667                PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
2668                           instance->reg_base,
2669                           instance->ctrl_reg - instance->reg_base,
2670                           ctrl_status);
2671                outl(ctrl_status, instance->ctrl_reg);
2672                PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
2673                           instance->reg_base,
2674                           instance->ctrl_reg - instance->reg_base,
2675                           ctrl_status);
2676                spin_unlock(instance->ctrl_reg_lock);
2677                return IRQ_HANDLED;
2678        }
2679#ifdef MEDEBUG_INFO
2680        PINFO("STATUS_BIT_FSM=%s.\n",
2681              (ctrl_status & ME4600_AI_STATUS_BIT_FSM) ? "on" : "off");
2682
2683        PINFO("STATUS_BIT_EF_CHANNEL=%s.\n",
2684              (ctrl_status & ME4600_AI_STATUS_BIT_EF_CHANNEL) ? "not empty" :
2685              "empty");
2686        PINFO("STATUS_BIT_HF_CHANNEL=%s.\n",
2687              (ctrl_status & ME4600_AI_STATUS_BIT_HF_CHANNEL) ? " < HF" :
2688              " > HF");
2689        PINFO("STATUS_BIT_FF_CHANNEL=%s.\n",
2690              (ctrl_status & ME4600_AI_STATUS_BIT_FF_CHANNEL) ? "not full" :
2691              "full");
2692
2693        PINFO("STATUS_BIT_EF_DATA=%s.\n",
2694              (ctrl_status & ME4600_AI_STATUS_BIT_EF_DATA) ? "not empty" :
2695              "empty");
2696        PINFO("STATUS_BIT_HF_DATA=%s.\n",
2697              (ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA) ? " < HF" : " > HF");
2698        PINFO("STATUS_BIT_FF_DATA=%s.\n",
2699              (ctrl_status & ME4600_AI_STATUS_BIT_FF_DATA) ? "not full" :
2700              "full");
2701
2702        PINFO("CTRL_BIT_HF_IRQ=%s.\n",
2703              (ctrl_status & ME4600_AI_CTRL_BIT_HF_IRQ) ? "enable" : "disable");
2704        PINFO("CTRL_BIT_HF_IRQ_RESET=%s.\n",
2705              (ctrl_status & ME4600_AI_CTRL_BIT_HF_IRQ_RESET) ? "reset" :
2706              "work");
2707        PINFO("CTRL_BIT_SC_IRQ=%s.\n",
2708              (ctrl_status & ME4600_AI_CTRL_BIT_SC_IRQ) ? "enable" : "disable");
2709        PINFO("CTRL_BIT_SC_RELOAD=%s.\n",
2710              (ctrl_status & ME4600_AI_CTRL_BIT_SC_RELOAD) ? "on" : "off");
2711        PINFO("CTRL_BIT_SC_IRQ_RESET=%s.\n",
2712              (ctrl_status & ME4600_AI_CTRL_BIT_SC_IRQ_RESET) ? "reset" :
2713              "work");
2714#endif
2715
2716        //Look for overflow error.
2717        if (!(ctrl_status & ME4600_AI_STATUS_BIT_FF_DATA)) {
2718                //FIFO is full. Read datas and reset all settings.
2719                PERROR("FIFO overflow.\n");
2720                ai_read_data(instance, ME4600_AI_FIFO_COUNT);
2721                ai_stop_isr(instance);
2722
2723                instance->status = ai_status_stream_fifo_error;
2724                //Signal it.
2725                wake_up_interruptible_all(&instance->wait_queue);
2726
2727                return IRQ_HANDLED;
2728        }
2729
2730        if (!instance->data_required) { //This is infinite aqusition.
2731#ifdef MEDEBUG_ERROR
2732                if ((irq_status &
2733                     (ME4600_IRQ_STATUS_BIT_AI_HF | ME4600_IRQ_STATUS_BIT_SC))
2734                    ==
2735                    (ME4600_IRQ_STATUS_BIT_AI_HF | ME4600_IRQ_STATUS_BIT_SC)) {
2736                        ///In infinite mode only one interrupt source should be reported!
2737                        PERROR
2738                            ("Error in ISM! Infinite aqusition: HF and SC interrupts active! threshold=%d next=%d ctrl=0x%04X irq_status_reg=0x%04X",
2739                             instance->fifo_irq_threshold, instance->ISM.next,
2740                             ctrl_status, irq_status);
2741                }
2742#endif
2743
2744                ai_infinite_isr(instance, irq_status, ctrl_status);
2745
2746#ifdef MEDEBUG_INFO
2747                ctrl_status = inl(instance->ctrl_reg);
2748#endif
2749        } else {
2750
2751                ai_limited_isr(instance, irq_status, ctrl_status);
2752                ctrl_status = inl(instance->status_reg);
2753                if (!(ctrl_status & (ME4600_AI_STATUS_BIT_HF_DATA | ME4600_AI_CTRL_BIT_HF_IRQ_RESET))) {        //HF active, but we have more than half already => HF will never come
2754                        PDEBUG
2755                            ("MISSED HF. data_required=%d ISM.read=%d ISM.global=%d ISM.next=%d\n",
2756                             instance->data_required, instance->ISM.read,
2757                             instance->ISM.global_read, instance->ISM.next);
2758                        ai_limited_isr(instance, ME4600_IRQ_STATUS_BIT_AI_HF,
2759                                       ctrl_status);
2760                }
2761        }
2762
2763#ifdef MEDEBUG_INFO
2764        PINFO("STATUS_BIT_FSM=%s.\n",
2765              (ctrl_status & ME4600_AI_STATUS_BIT_FSM) ? "on" : "off");
2766
2767        PINFO("STATUS_BIT_EF_CHANNEL=%s.\n",
2768              (ctrl_status & ME4600_AI_STATUS_BIT_EF_CHANNEL) ? "not empty" :
2769              "empty");
2770        PINFO("STATUS_BIT_HF_CHANNEL=%s.\n",
2771              (ctrl_status & ME4600_AI_STATUS_BIT_HF_CHANNEL) ? " < HF" :
2772              " > HF");
2773        PINFO("STATUS_BIT_FF_CHANNEL=%s.\n",
2774              (ctrl_status & ME4600_AI_STATUS_BIT_FF_CHANNEL) ? "not full" :
2775              "full");
2776
2777        PINFO("STATUS_BIT_EF_DATA=%s.\n",
2778              (ctrl_status & ME4600_AI_STATUS_BIT_EF_DATA) ? "not empty" :
2779              "empty");
2780        PINFO("STATUS_BIT_HF_DATA=%s.\n",
2781              (ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA) ? " < HF" : " > HF");
2782        PINFO("STATUS_BIT_FF_DATA=%s.\n",
2783              (ctrl_status & ME4600_AI_STATUS_BIT_FF_DATA) ? "not full" :
2784              "full");
2785
2786        PINFO("CTRL_BIT_HF_IRQ_RESET=%s.\n",
2787              (ctrl_status & ME4600_AI_CTRL_BIT_HF_IRQ_RESET) ? "reset" :
2788              "work");
2789        PINFO("CTRL_BIT_SC_IRQ=%s.\n",
2790              (ctrl_status & ME4600_AI_CTRL_BIT_SC_IRQ) ? "enable" : "disable");
2791        PINFO("CTRL_BIT_SC_RELOAD=%s.\n",
2792              (ctrl_status & ME4600_AI_CTRL_BIT_SC_RELOAD) ? "on" : "off");
2793        PINFO("CTRL_BIT_SC_IRQ_RESET=%s.\n",
2794              (ctrl_status & ME4600_AI_CTRL_BIT_SC_IRQ_RESET) ? "reset" :
2795              "work");
2796        PINFO("%ld END\n", jiffies);
2797#endif
2798
2799        return IRQ_HANDLED;
2800}
2801
2802/** @brief Stop aqusation of data. Reset interrupts' laches. Clear data's FIFO.
2803*
2804* @param instance The subdevice instance (pointer).
2805*/
2806void inline ai_stop_isr(me4600_ai_subdevice_t * instance)
2807{                               /// @note This is soft time critical function!
2808        register uint32_t tmp;
2809
2810        spin_lock(instance->ctrl_reg_lock);
2811        //Stop all. Reset interrupt laches. Reset data FIFO.
2812        tmp = inl(instance->ctrl_reg);
2813        tmp |=
2814            (ME4600_AI_CTRL_BIT_IMMEDIATE_STOP | ME4600_AI_CTRL_BIT_HF_IRQ_RESET
2815             | ME4600_AI_CTRL_BIT_LE_IRQ_RESET |
2816             ME4600_AI_CTRL_BIT_SC_IRQ_RESET);
2817        tmp &= ~ME4600_AI_CTRL_BIT_DATA_FIFO;
2818        outl(tmp, instance->ctrl_reg);
2819        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
2820                   instance->ctrl_reg - instance->reg_base, tmp);
2821        spin_unlock(instance->ctrl_reg_lock);
2822}
2823
2824/** @brief Copy data from fifo to circular buffer.
2825*
2826* @param instance The subdevice instance (pointer).
2827* @param count The number of requested data.
2828*
2829* @return On success: Number of copied values.
2830* @return On error: -ME_ERRNO_RING_BUFFER_OVERFLOW.
2831*/
2832static int inline ai_read_data(me4600_ai_subdevice_t * instance,
2833                               const int count)
2834{                               /// @note This is time critical function!
2835        int c = count;
2836        int empty_space;
2837        int copied = 0;
2838        int i, j;
2839
2840        empty_space = me_circ_buf_space_to_end(&instance->circ_buf);
2841        if (empty_space <= 0) {
2842                PDEBUG("Circular buffer full.\n");
2843                return -ME_ERRNO_RING_BUFFER_OVERFLOW;
2844        }
2845
2846        if (empty_space < c) {  //Copy first part. Max to end of buffer.
2847                PDEBUG
2848                    ("Try to copy %d values from FIFO to circular buffer (pass 1).\n",
2849                     empty_space);
2850                for (i = 0; i < empty_space; i++) {
2851                        *(instance->circ_buf.buf + instance->circ_buf.head) =
2852                            (inw(instance->data_reg) ^ 0x8000);
2853                        instance->circ_buf.head++;
2854                }
2855                instance->circ_buf.head &= instance->circ_buf.mask;
2856                c -= empty_space;
2857                copied = empty_space;
2858
2859                empty_space = me_circ_buf_space_to_end(&instance->circ_buf);
2860        }
2861
2862        if (empty_space > 0) {
2863                j = (empty_space < c) ? empty_space : c;
2864                PDEBUG
2865                    ("Try to copy %d values from FIFO to circular buffer (pass 2).\n",
2866                     c);
2867                for (i = 0; i < j; i++) {
2868                        *(instance->circ_buf.buf + instance->circ_buf.head) =
2869                            (inw(instance->data_reg) ^ 0x8000);
2870                        instance->circ_buf.head++;
2871                }
2872                instance->circ_buf.head &= instance->circ_buf.mask;
2873                copied += j;
2874        }
2875        return copied;
2876}
2877
2878void inline ai_infinite_ISM(me4600_ai_subdevice_t * instance)
2879{                               /// @note This is time critical function!
2880        register volatile uint32_t ctrl_set, ctrl_reset, tmp;
2881
2882        if (instance->fifo_irq_threshold < ME4600_AI_FIFO_MAX_SC) {     // Only sample counter with reloadnig is working. Reset it.
2883                PINFO
2884                    ("Only sample counter with reloadnig is working. Reset it.\n");
2885                ctrl_set = ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
2886                ctrl_reset = ~ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
2887        } else if (instance->fifo_irq_threshold == instance->ISM.read) {        //This is SC interrupt for large block. The whole section is done. Reset SC_IRQ an HF_IRQ and start everything again from beginning.
2888                PINFO
2889                    ("This is SC interrupt for large block. The whole section is done. Reset SC_IRQ an HF_IRQ and start everything again from beginning.\n");
2890                ctrl_set =
2891                    ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
2892                    ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2893                ctrl_reset =
2894                    ~(ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
2895                      ME4600_AI_CTRL_BIT_HF_IRQ_RESET);
2896        } else if (instance->fifo_irq_threshold >= (ME4600_AI_FIFO_MAX_SC + instance->ISM.read)) {      //This is HF interrupt for large block.The next interrupt should be from HF, also. Reset HF.
2897                PINFO
2898                    ("This is HF interrupt for large block.The next interrupt should be from HF, also. Reset HF.\n");
2899                ctrl_set = ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2900                ctrl_reset = ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2901        } else {                //This is HF interrupt for large block.The next interrupt should be from SC. Don't reset HF!
2902                PINFO
2903                    ("This is HF interrupt for large block.The next interrupt should be from SC. Don't reset HF!\n");
2904                ctrl_set = ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2905                ctrl_reset = 0xFFFFFFFF;
2906        }
2907
2908        //Reset interrupt latch.
2909        spin_lock(instance->ctrl_reg_lock);
2910        tmp = inl(instance->ctrl_reg);
2911        PINFO("ctrl=0x%x ctrl_set=0x%x ctrl_reset=0x%x\n", tmp, ctrl_set,
2912              ctrl_reset);
2913        tmp |= ctrl_set;
2914        outl(tmp, instance->ctrl_reg);
2915        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
2916                   instance->ctrl_reg - instance->reg_base, tmp);
2917        if (ctrl_reset != 0xFFFFFFFF) {
2918                outl(tmp & ctrl_reset, instance->ctrl_reg);
2919                PDEBUG_REG("ctrl_reset outl(0x%lX+0x%lX)=0x%x\n",
2920                           instance->reg_base,
2921                           instance->ctrl_reg - instance->reg_base,
2922                           tmp & ctrl_reset);
2923        }
2924        spin_unlock(instance->ctrl_reg_lock);
2925
2926}
2927
2928void inline ai_limited_ISM(me4600_ai_subdevice_t * instance,
2929                           uint32_t irq_status)
2930{                               /// @note This is time critical function!
2931        register volatile uint32_t ctrl_set, ctrl_reset = 0xFFFFFFFF, tmp;
2932
2933        if (!instance->fifo_irq_threshold) {    //No threshold provided. SC ends work.
2934                PINFO("No threshold provided. SC ends work.\n");
2935                ctrl_set = ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2936                if (instance->data_required > (ME4600_AI_FIFO_COUNT - 1 + instance->ISM.global_read)) { //HF need reseting.
2937                        ctrl_reset &= ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2938                }
2939        } else                  //if(instance->fifo_irq_threshold)
2940        {
2941                if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF) {
2942                        PINFO("Threshold provided. Clear HF latch.\n");
2943                        ctrl_set = ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2944
2945                        if (instance->fifo_irq_threshold >= (ME4600_AI_FIFO_MAX_SC + instance->ISM.read)) {     //This is not the last one. HF need reseting.
2946                                PINFO
2947                                    ("The next interrupt is HF. HF need be activating.\n");
2948                                ctrl_reset = ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2949                        }
2950                }
2951
2952                if (irq_status & ME4600_IRQ_STATUS_BIT_SC) {
2953                        PINFO("Threshold provided. Restart SC.\n");
2954                        ctrl_set = ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
2955                        ctrl_reset &= ~ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
2956
2957                        if (instance->fifo_irq_threshold >= ME4600_AI_FIFO_MAX_SC) {    //This is not the last one. HF need to be activating.
2958                                PINFO
2959                                    ("The next interrupt is HF. HF need to be activating.\n");
2960                                ctrl_reset &= ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2961                        }
2962                }
2963        }
2964
2965        //Reset interrupt latch.
2966        spin_lock(instance->ctrl_reg_lock);
2967        tmp = inl(instance->ctrl_reg);
2968        tmp |= ctrl_set;
2969        outl(tmp, instance->ctrl_reg);
2970        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
2971                   instance->ctrl_reg - instance->reg_base, tmp);
2972
2973        if (ctrl_reset != 0xFFFFFFFF) {
2974                outl(tmp & ctrl_reset, instance->ctrl_reg);
2975                PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
2976                           instance->reg_base,
2977                           instance->ctrl_reg - instance->reg_base,
2978                           tmp & ctrl_reset);
2979        }
2980        spin_unlock(instance->ctrl_reg_lock);
2981
2982}
2983
2984/** @brief Last chunck of datas. We must reschedule sample counter.
2985*       @note Last chunck.
2986*       Leaving SC_RELOAD doesn't do any harm, but in some bad case can make extra interrupts.
2987*       @warning When threshold is wrongly set some IRQ are lost.(!!!)
2988*/
2989void inline ai_reschedule_SC(me4600_ai_subdevice_t * instance)
2990{
2991        register uint32_t rest;
2992
2993        if (instance->data_required <= instance->ISM.global_read)
2994                return;
2995
2996        rest = instance->data_required - instance->ISM.global_read;
2997        if (rest < instance->fifo_irq_threshold) {      //End of work soon ....
2998                PDEBUG("Rescheduling SC from %d to %d.\n",
2999                       instance->fifo_irq_threshold, rest);
3000                /// @note Write new value to SC <==  DANGER! This is not safe solution! We can miss some inputs.

3001                outl(rest, instance->sample_counter_reg);
3002                PDEBUG_REG("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
3003                           instance->reg_base,
3004                           instance->sample_counter_reg - instance->reg_base,
3005                           rest);
3006                instance->fifo_irq_threshold = rest;
3007
3008                if (rest < ME4600_AI_FIFO_MAX_SC) {
3009                        instance->ISM.next = rest;
3010                } else {
3011                        instance->ISM.next = rest % ME4600_AI_FIFO_HALF;
3012                        if (instance->ISM.next + ME4600_AI_FIFO_HALF <
3013                            ME4600_AI_FIFO_MAX_SC) {
3014                                instance->ISM.next += ME4600_AI_FIFO_HALF;
3015                        }
3016                }
3017        }
3018}
3019
3020/** Start the ISM. All must be reseted before enter to this function. */
3021void inline ai_data_acquisition_logic(me4600_ai_subdevice_t * instance)
3022{
3023        register uint32_t tmp;
3024
3025        if (!instance->data_required) { //This is infinite aqusition.
3026                if (!instance->fifo_irq_threshold) {    //No threshold provided. Set SC to 0.5*FIFO. Clear the SC's latch.
3027                        //Set the sample counter
3028                        outl(ME4600_AI_FIFO_HALF, instance->sample_counter_reg);
3029                        PDEBUG_REG
3030                            ("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
3031                             instance->reg_base,
3032                             instance->sample_counter_reg - instance->reg_base,
3033                             ME4600_AI_FIFO_HALF);
3034                } else {        //Threshold provided. Set SC to treshold. Clear the SC's latch.
3035                        //Set the sample counter
3036                        outl(instance->fifo_irq_threshold,
3037                             instance->sample_counter_reg);
3038                        PDEBUG_REG
3039                            ("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
3040                             instance->reg_base,
3041                             instance->sample_counter_reg - instance->reg_base,
3042                             instance->fifo_irq_threshold);
3043                }
3044
3045                if (instance->fifo_irq_threshold < ME4600_AI_FIFO_MAX_SC) {     //Enable only sample counter's interrupt. Set reload bit. Clear the SC's latch.
3046                        spin_lock(instance->ctrl_reg_lock);
3047                        tmp = inl(instance->ctrl_reg);
3048                        tmp |= ME4600_AI_CTRL_BIT_SC_RELOAD;
3049                        tmp &= ~ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
3050                        outl(tmp, instance->ctrl_reg);
3051                        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3052                                   instance->reg_base,
3053                                   instance->ctrl_reg - instance->reg_base,
3054                                   tmp);
3055                        spin_unlock(instance->ctrl_reg_lock);
3056                        if (!instance->fifo_irq_threshold) {    //No threshold provided. Set ISM.next to 0.5*FIFO.
3057                                instance->ISM.next = ME4600_AI_FIFO_HALF;
3058                        } else {        //Threshold provided. Set ISM.next to treshold.
3059                                instance->ISM.next =
3060                                    instance->fifo_irq_threshold;
3061                        }
3062                } else {        //Enable sample counter's and HF's interrupts.
3063                        spin_lock(instance->ctrl_reg_lock);
3064                        tmp = inl(instance->ctrl_reg);
3065                        tmp |= ME4600_AI_CTRL_BIT_SC_RELOAD;
3066                        tmp &=
3067                            ~(ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
3068                              ME4600_AI_CTRL_BIT_HF_IRQ_RESET);
3069                        outl(tmp, instance->ctrl_reg);
3070                        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3071                                   instance->reg_base,
3072                                   instance->ctrl_reg - instance->reg_base,
3073                                   tmp);
3074                        spin_unlock(instance->ctrl_reg_lock);
3075
3076                        instance->ISM.next =
3077                            instance->fifo_irq_threshold % ME4600_AI_FIFO_HALF;
3078                        if (instance->ISM.next + ME4600_AI_FIFO_HALF <
3079                            ME4600_AI_FIFO_MAX_SC) {
3080                                instance->ISM.next += ME4600_AI_FIFO_HALF;
3081                        }
3082                }
3083        } else {                //This aqusition is limited to set number of data.
3084                if (instance->fifo_irq_threshold >= instance->data_required) {  //Stupid situation.
3085                        instance->fifo_irq_threshold = 0;
3086                        PDEBUG
3087                            ("Stupid situation: data_required(%d) < threshold(%d).\n",
3088                             instance->fifo_irq_threshold,
3089                             instance->data_required);
3090                }
3091
3092                if (!instance->fifo_irq_threshold) {    //No threshold provided. Easy case: HF=read and SC=end.
3093                        //Set the sample counter to data_required.
3094                        outl(instance->data_required,
3095                             instance->sample_counter_reg);
3096                        PDEBUG_REG
3097                            ("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
3098                             instance->reg_base,
3099                             instance->sample_counter_reg - instance->reg_base,
3100                             instance->data_required);
3101
3102                        //Reset the latches of sample counter and HF (if SC>FIFO).
3103                        //No SC reload!
3104                        spin_lock(instance->ctrl_reg_lock);
3105                        tmp = inl(instance->ctrl_reg);
3106                        tmp &=
3107                            ~(ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
3108                              ME4600_AI_CTRL_BIT_SC_RELOAD);
3109                        if (instance->data_required >
3110                            (ME4600_AI_FIFO_COUNT - 1)) {
3111                                tmp &= ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
3112                                instance->ISM.next =
3113                                    instance->data_required %
3114                                    ME4600_AI_FIFO_HALF;
3115                                instance->ISM.next += ME4600_AI_FIFO_HALF;
3116
3117                        } else {
3118                                instance->ISM.next = instance->data_required;
3119                        }
3120                        outl(tmp, instance->ctrl_reg);
3121                        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3122                                   instance->reg_base,
3123                                   instance->ctrl_reg - instance->reg_base,
3124                                   tmp);
3125                        spin_unlock(instance->ctrl_reg_lock);
3126
3127                } else {        //The most general case. We have concret numbe of required data and threshold. SC=TH
3128                        //Set the sample counter to threshold.
3129                        outl(instance->fifo_irq_threshold,
3130                             instance->sample_counter_reg);
3131                        PDEBUG_REG
3132                            ("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
3133                             instance->reg_base,
3134                             instance->sample_counter_reg - instance->reg_base,
3135                             instance->fifo_irq_threshold);
3136
3137                        spin_lock(instance->ctrl_reg_lock);
3138                        tmp = inl(instance->ctrl_reg);
3139                        //In this moment we are sure that SC will come more than once.
3140                        tmp |= ME4600_AI_CTRL_BIT_SC_RELOAD;
3141
3142                        if (instance->fifo_irq_threshold < ME4600_AI_FIFO_MAX_SC) {     //The threshold is so small that we do need HF.
3143                                tmp &= ~ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
3144                                instance->ISM.next =
3145                                    instance->fifo_irq_threshold;
3146                        } else {        //The threshold is large. The HF must be use.
3147                                tmp &=
3148                                    ~(ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
3149                                      ME4600_AI_CTRL_BIT_HF_IRQ_RESET);
3150                                instance->ISM.next =
3151                                    instance->fifo_irq_threshold %
3152                                    ME4600_AI_FIFO_HALF;
3153                                if (instance->ISM.next + ME4600_AI_FIFO_HALF <
3154                                    ME4600_AI_FIFO_MAX_SC) {
3155                                        instance->ISM.next +=
3156                                            ME4600_AI_FIFO_HALF;
3157                                }
3158                        }
3159                        outl(tmp, instance->ctrl_reg);
3160                        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3161                                   instance->reg_base,
3162                                   instance->ctrl_reg - instance->reg_base,
3163                                   tmp);
3164                        spin_unlock(instance->ctrl_reg_lock);
3165                }
3166        }
3167}
3168
3169static int ai_mux_toggler(me4600_ai_subdevice_t * instance)
3170{
3171        uint32_t tmp;
3172
3173        PDEBUG("executed. idx=0\n");
3174
3175        outl(0, instance->scan_pre_timer_low_reg);
3176        PDEBUG_REG("scan_pre_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
3177                   instance->reg_base,
3178                   instance->scan_pre_timer_low_reg - instance->reg_base, 0);
3179        outl(0, instance->scan_pre_timer_high_reg);
3180        PDEBUG_REG("scan_pre_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
3181                   instance->reg_base,
3182                   instance->scan_pre_timer_high_reg - instance->reg_base, 0);
3183        outl(0, instance->scan_timer_low_reg);
3184        PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
3185                   instance->reg_base,
3186                   instance->scan_timer_low_reg - instance->reg_base, 0);
3187        outl(0, instance->scan_timer_high_reg);
3188        PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
3189                   instance->reg_base,
3190                   instance->scan_timer_high_reg - instance->reg_base, 0);
3191        outl(65, instance->chan_timer_reg);
3192        PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
3193                   instance->reg_base,
3194                   instance->chan_timer_reg - instance->reg_base, 65);
3195        outl(65, instance->chan_pre_timer_reg);
3196        PDEBUG_REG("chan_pre_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
3197                   instance->reg_base,
3198                   instance->chan_pre_timer_reg - instance->reg_base, 65);
3199
3200        // Turn on internal reference.
3201        tmp = inl(instance->ctrl_reg);
3202        tmp |= ME4600_AI_CTRL_BIT_FULLSCALE;
3203        outl(tmp, instance->ctrl_reg);
3204        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3205                   instance->ctrl_reg - instance->reg_base, tmp);
3206
3207        // Clear data and channel fifo.
3208        tmp &=
3209            ~(ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO);
3210        outl(tmp, instance->ctrl_reg);
3211        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3212                   instance->ctrl_reg - instance->reg_base, tmp);
3213        tmp |= ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO;
3214        outl(tmp, instance->ctrl_reg);
3215        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3216                   instance->ctrl_reg - instance->reg_base, tmp);
3217
3218        // Write channel entry.
3219        outl(ME4600_AI_LIST_INPUT_DIFFERENTIAL |
3220             ME4600_AI_LIST_RANGE_UNIPOLAR_2_5 | 31,
3221             instance->channel_list_reg);
3222        PDEBUG_REG("channel_list_reg outl(0x%lX+0x%lX)=0x%x\n",
3223                   instance->reg_base,
3224                   instance->channel_list_reg - instance->reg_base,
3225                   ME4600_AI_LIST_INPUT_DIFFERENTIAL |
3226                   ME4600_AI_LIST_RANGE_UNIPOLAR_2_5 | 31);
3227
3228        // Start conversion.
3229        inl(instance->start_reg);
3230        PDEBUG_REG("start_reg inl(0x%lX+0x%lX)\n", instance->reg_base,
3231                   instance->start_reg - instance->reg_base);
3232        udelay(10);
3233
3234        // Clear data and channel fifo.
3235        tmp &=
3236            ~(ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO);
3237        outl(tmp, instance->ctrl_reg);
3238        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3239                   instance->ctrl_reg - instance->reg_base, tmp);
3240        tmp |= ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO;
3241        outl(tmp, instance->ctrl_reg);
3242        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3243                   instance->ctrl_reg - instance->reg_base, tmp);
3244
3245        // Write channel entry.
3246        // ME4600_AI_LIST_INPUT_SINGLE_ENDED | ME4600_AI_LIST_RANGE_BIPOLAR_10 <= 0x0000
3247        outl(ME4600_AI_LIST_INPUT_SINGLE_ENDED |
3248             ME4600_AI_LIST_RANGE_BIPOLAR_10, instance->channel_list_reg);
3249        PDEBUG_REG("channel_list_reg outl(0x%lX+0x%lX)=0x%x\n",
3250                   instance->reg_base,
3251                   instance->channel_list_reg - instance->reg_base,
3252                   ME4600_AI_LIST_INPUT_SINGLE_ENDED |
3253                   ME4600_AI_LIST_RANGE_BIPOLAR_10);
3254
3255        // Start conversion.
3256        inl(instance->start_reg);
3257        PDEBUG_REG("start_reg inl(0x%lX+0x%lX)\n", instance->reg_base,
3258                   instance->start_reg - instance->reg_base);
3259        udelay(10);
3260
3261        // Clear control register.
3262        tmp &= (ME4600_AI_CTRL_BIT_EX_IRQ | ME4600_AI_CTRL_BIT_EX_IRQ_RESET);
3263        outl(tmp, instance->ctrl_reg);
3264        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3265                   instance->ctrl_reg - instance->reg_base, tmp);
3266
3267        return ME_ERRNO_SUCCESS;
3268}
3269
3270/** @brief Copy rest of data from fifo to circular buffer.
3271* @note Helper for STOP command. After FSM is stopped.
3272* @note This is slow function that copy all remainig data from FIFO to buffer.
3273*
3274* @param instance The subdevice instance (pointer).
3275*
3276* @return On success: Number of copied values.
3277* @return On error: Negative error code -ME_ERRNO_RING_BUFFER_OVERFLOW.
3278*/
3279static int inline ai_read_data_pooling(me4600_ai_subdevice_t * instance)
3280{                               /// @note This is time critical function!
3281        int empty_space;
3282        int copied = 0;
3283        int status = ME_ERRNO_SUCCESS;
3284
3285        PDEBUG("Space left in circular buffer = %d.\n",
3286               me_circ_buf_space(&instance->circ_buf));
3287
3288        while ((empty_space = me_circ_buf_space(&instance->circ_buf))) {
3289                if (!(status = inl(instance->status_reg) & ME4600_AI_STATUS_BIT_EF_DATA)) {     //No more data. status = ME_ERRNO_SUCCESS = 0
3290                        break;
3291                }
3292                *(instance->circ_buf.buf + instance->circ_buf.head) =
3293                    (inw(instance->data_reg) ^ 0x8000);
3294                instance->circ_buf.head++;
3295                instance->circ_buf.head &= instance->circ_buf.mask;
3296        }
3297
3298#ifdef MEDEBUG_ERROR
3299        if (!status)
3300                PDEBUG
3301                    ("Copied all remaining datas (%d) from FIFO to circular buffer.\n",
3302                     copied);
3303        else {
3304                PDEBUG("No more empty space in buffer.\n");
3305                PDEBUG("Copied %d datas from FIFO to circular buffer.\n",
3306                       copied);
3307                PDEBUG("FIFO still not empty.\n");
3308        }
3309#endif
3310        return (!status) ? copied : -ME_ERRNO_RING_BUFFER_OVERFLOW;
3311}
3312
3313#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
3314static void me4600_ai_work_control_task(void *subdevice)
3315#else
3316static void me4600_ai_work_control_task(struct work_struct *work)
3317#endif
3318{
3319        me4600_ai_subdevice_t *instance;
3320        uint32_t status;
3321        uint32_t ctrl;
3322        unsigned long cpu_flags = 0;
3323        int reschedule = 0;
3324        int signaling = 0;
3325
3326#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
3327        instance = (me4600_ai_subdevice_t *) subdevice;
3328#else
3329        instance =
3330            container_of((void *)work, me4600_ai_subdevice_t, ai_control_task);
3331#endif
3332        PINFO("<%s: %ld> executed.\n", __func__, jiffies);
3333
3334        status = inl(instance->status_reg);
3335        PDEBUG_REG("status_reg inl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3336                   instance->status_reg - instance->reg_base, status);
3337
3338        switch (instance->status) {     // Checking actual mode.
3339                // Not configured for work.
3340        case ai_status_none:
3341                break;
3342
3343                //This are stable modes. No need to do anything. (?)
3344        case ai_status_single_configured:
3345        case ai_status_stream_configured:
3346        case ai_status_stream_fifo_error:
3347        case ai_status_stream_buffer_error:
3348        case ai_status_stream_error:
3349                PERROR("Shouldn't be running!.\n");
3350                break;
3351
3352                // Stream modes
3353        case ai_status_stream_run_wait:
3354                if (status & ME4600_AI_STATUS_BIT_FSM) {        // ISM started..
3355                        instance->status = ai_status_stream_run;
3356                        // Signal the end of wait for start.
3357                        signaling = 1;
3358                        // Wait now for stop.
3359                        reschedule = 1;
3360                        break;
3361
3362                        // Check timeout.
3363                        if ((instance->timeout.delay) && ((jiffies - instance->timeout.start_time) >= instance->timeout.delay)) {       // Timeout
3364                                PDEBUG("Timeout reached.\n");
3365                                // Stop all actions. No conditions! Block interrupts. Reset FIFO => Too late!
3366                                ai_stop_isr(instance);
3367
3368                                instance->status = ai_status_stream_end;
3369
3370                                // Signal the end.
3371                                signaling = 1;
3372                        }
3373                }
3374                break;
3375
3376        case ai_status_stream_run:
3377                // Wait for stop ISM.
3378                reschedule = 1;
3379                break;
3380
3381        case ai_status_stream_end_wait:
3382                if (!(status & ME4600_AI_STATUS_BIT_FSM)) {     // ISM stoped. Overwrite ISR.
3383                        instance->status = ai_status_stream_end;
3384                        // Signal the end of wait for stop.
3385                        signaling = 1;
3386                } else {
3387                        // Wait for stop ISM.
3388                        reschedule = 1;
3389                }
3390                break;
3391
3392        case ai_status_stream_end:
3393                //End work.
3394                if (status & ME4600_AI_STATUS_BIT_FSM) {        // Still working? Stop it!
3395                        PERROR
3396                            ("Status is 'ai_status_stream_end' but hardware is still working!\n");
3397                        spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
3398                        ctrl = inl(instance->ctrl_reg);
3399                        ctrl |=
3400                            (ME4600_AI_CTRL_BIT_IMMEDIATE_STOP |
3401                             ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
3402                             ME4600_AI_CTRL_BIT_SC_IRQ_RESET);
3403                        outl(ctrl, instance->ctrl_reg);
3404                        PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3405                                   instance->reg_base,
3406                                   instance->ctrl_reg - instance->reg_base,
3407                                   ctrl);
3408                        spin_unlock_irqrestore(instance->ctrl_reg_lock,
3409                                               cpu_flags);
3410                }
3411                break;
3412
3413        default:
3414                PERROR_CRITICAL("Status is in wrong state (%d)!\n",
3415                                instance->status);
3416                instance->status = ai_status_stream_error;
3417                // Signal the end.
3418                signaling = 1;
3419                break;
3420
3421        }
3422
3423        if (signaling) {        //Signal it.
3424                wake_up_interruptible_all(&instance->wait_queue);
3425        }
3426
3427        if (instance->ai_control_task_flag && reschedule) {     // Reschedule task
3428                queue_delayed_work(instance->me4600_workqueue,
3429                                   &instance->ai_control_task, 1);
3430        } else {
3431                PINFO("<%s> Ending control task.\n", __func__);
3432        }
3433
3434}
3435