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16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/fcntl.h>
20#include <linux/interrupt.h>
21#include <linux/ioport.h>
22#include <linux/in.h>
23#include <linux/slab.h>
24#include <linux/string.h>
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/ethtool.h>
28#include <linux/mii.h>
29#include <linux/crc32.h>
30#include <linux/random.h>
31#include <linux/errno.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/mm.h>
36#include <linux/bitops.h>
37#include <linux/dma-mapping.h>
38
39#include <asm/system.h>
40#include <asm/io.h>
41#include <asm/dma.h>
42#include <asm/byteorder.h>
43
44#ifdef CONFIG_SPARC
45#include <linux/of.h>
46#include <linux/of_device.h>
47#include <asm/idprom.h>
48#include <asm/openprom.h>
49#include <asm/oplib.h>
50#include <asm/prom.h>
51#include <asm/auxio.h>
52#endif
53#include <asm/uaccess.h>
54
55#include <asm/pgtable.h>
56#include <asm/irq.h>
57
58#ifdef CONFIG_PCI
59#include <linux/pci.h>
60#endif
61
62#include "sunhme.h"
63
64#define DRV_NAME "sunhme"
65#define DRV_VERSION "3.10"
66#define DRV_RELDATE "August 26, 2008"
67#define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
68
69static char version[] =
70 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
71
72MODULE_VERSION(DRV_VERSION);
73MODULE_AUTHOR(DRV_AUTHOR);
74MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver");
75MODULE_LICENSE("GPL");
76
77static int macaddr[6];
78
79
80module_param_array(macaddr, int, NULL, 0);
81MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
82
83#ifdef CONFIG_SBUS
84static struct quattro *qfe_sbus_list;
85#endif
86
87#ifdef CONFIG_PCI
88static struct quattro *qfe_pci_list;
89#endif
90
91#undef HMEDEBUG
92#undef SXDEBUG
93#undef RXDEBUG
94#undef TXDEBUG
95#undef TXLOGGING
96
97#ifdef TXLOGGING
98struct hme_tx_logent {
99 unsigned int tstamp;
100 int tx_new, tx_old;
101 unsigned int action;
102#define TXLOG_ACTION_IRQ 0x01
103#define TXLOG_ACTION_TXMIT 0x02
104#define TXLOG_ACTION_TBUSY 0x04
105#define TXLOG_ACTION_NBUFS 0x08
106 unsigned int status;
107};
108#define TX_LOG_LEN 128
109static struct hme_tx_logent tx_log[TX_LOG_LEN];
110static int txlog_cur_entry;
111static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
112{
113 struct hme_tx_logent *tlp;
114 unsigned long flags;
115
116 local_irq_save(flags);
117 tlp = &tx_log[txlog_cur_entry];
118 tlp->tstamp = (unsigned int)jiffies;
119 tlp->tx_new = hp->tx_new;
120 tlp->tx_old = hp->tx_old;
121 tlp->action = a;
122 tlp->status = s;
123 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
124 local_irq_restore(flags);
125}
126static __inline__ void tx_dump_log(void)
127{
128 int i, this;
129
130 this = txlog_cur_entry;
131 for (i = 0; i < TX_LOG_LEN; i++) {
132 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
133 tx_log[this].tstamp,
134 tx_log[this].tx_new, tx_log[this].tx_old,
135 tx_log[this].action, tx_log[this].status);
136 this = (this + 1) & (TX_LOG_LEN - 1);
137 }
138}
139static __inline__ void tx_dump_ring(struct happy_meal *hp)
140{
141 struct hmeal_init_block *hb = hp->happy_block;
142 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
143 int i;
144
145 for (i = 0; i < TX_RING_SIZE; i+=4) {
146 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
147 i, i + 4,
148 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
149 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
150 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
151 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
152 }
153}
154#else
155#define tx_add_log(hp, a, s) do { } while(0)
156#define tx_dump_log() do { } while(0)
157#define tx_dump_ring(hp) do { } while(0)
158#endif
159
160#ifdef HMEDEBUG
161#define HMD(x) printk x
162#else
163#define HMD(x)
164#endif
165
166
167
168#ifdef AUTO_SWITCH_DEBUG
169#define ASD(x) printk x
170#else
171#define ASD(x)
172#endif
173
174#define DEFAULT_IPG0 16
175#define DEFAULT_IPG1 8
176#define DEFAULT_IPG2 4
177#define DEFAULT_JAMSIZE 4
178
179
180
181
182
183
184
185
186#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
187static void sbus_hme_write32(void __iomem *reg, u32 val)
188{
189 sbus_writel(val, reg);
190}
191
192static u32 sbus_hme_read32(void __iomem *reg)
193{
194 return sbus_readl(reg);
195}
196
197static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
198{
199 rxd->rx_addr = (__force hme32)addr;
200 wmb();
201 rxd->rx_flags = (__force hme32)flags;
202}
203
204static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
205{
206 txd->tx_addr = (__force hme32)addr;
207 wmb();
208 txd->tx_flags = (__force hme32)flags;
209}
210
211static u32 sbus_hme_read_desc32(hme32 *p)
212{
213 return (__force u32)*p;
214}
215
216static void pci_hme_write32(void __iomem *reg, u32 val)
217{
218 writel(val, reg);
219}
220
221static u32 pci_hme_read32(void __iomem *reg)
222{
223 return readl(reg);
224}
225
226static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
227{
228 rxd->rx_addr = (__force hme32)cpu_to_le32(addr);
229 wmb();
230 rxd->rx_flags = (__force hme32)cpu_to_le32(flags);
231}
232
233static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
234{
235 txd->tx_addr = (__force hme32)cpu_to_le32(addr);
236 wmb();
237 txd->tx_flags = (__force hme32)cpu_to_le32(flags);
238}
239
240static u32 pci_hme_read_desc32(hme32 *p)
241{
242 return le32_to_cpup((__le32 *)p);
243}
244
245#define hme_write32(__hp, __reg, __val) \
246 ((__hp)->write32((__reg), (__val)))
247#define hme_read32(__hp, __reg) \
248 ((__hp)->read32(__reg))
249#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
250 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
251#define hme_write_txd(__hp, __txd, __flags, __addr) \
252 ((__hp)->write_txd((__txd), (__flags), (__addr)))
253#define hme_read_desc32(__hp, __p) \
254 ((__hp)->read_desc32(__p))
255#define hme_dma_map(__hp, __ptr, __size, __dir) \
256 ((__hp)->dma_map((__hp)->dma_dev, (__ptr), (__size), (__dir)))
257#define hme_dma_unmap(__hp, __addr, __size, __dir) \
258 ((__hp)->dma_unmap((__hp)->dma_dev, (__addr), (__size), (__dir)))
259#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
260 ((__hp)->dma_sync_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir)))
261#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
262 ((__hp)->dma_sync_for_device((__hp)->dma_dev, (__addr), (__size), (__dir)))
263#else
264#ifdef CONFIG_SBUS
265
266#define hme_write32(__hp, __reg, __val) \
267 sbus_writel((__val), (__reg))
268#define hme_read32(__hp, __reg) \
269 sbus_readl(__reg)
270#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
271do { (__rxd)->rx_addr = (__force hme32)(u32)(__addr); \
272 wmb(); \
273 (__rxd)->rx_flags = (__force hme32)(u32)(__flags); \
274} while(0)
275#define hme_write_txd(__hp, __txd, __flags, __addr) \
276do { (__txd)->tx_addr = (__force hme32)(u32)(__addr); \
277 wmb(); \
278 (__txd)->tx_flags = (__force hme32)(u32)(__flags); \
279} while(0)
280#define hme_read_desc32(__hp, __p) ((__force u32)(hme32)*(__p))
281#define hme_dma_map(__hp, __ptr, __size, __dir) \
282 dma_map_single((__hp)->dma_dev, (__ptr), (__size), (__dir))
283#define hme_dma_unmap(__hp, __addr, __size, __dir) \
284 dma_unmap_single((__hp)->dma_dev, (__addr), (__size), (__dir))
285#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
286 dma_dma_sync_single_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir))
287#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
288 dma_dma_sync_single_for_device((__hp)->dma_dev, (__addr), (__size), (__dir))
289#else
290
291#define hme_write32(__hp, __reg, __val) \
292 writel((__val), (__reg))
293#define hme_read32(__hp, __reg) \
294 readl(__reg)
295#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
296do { (__rxd)->rx_addr = (__force hme32)cpu_to_le32(__addr); \
297 wmb(); \
298 (__rxd)->rx_flags = (__force hme32)cpu_to_le32(__flags); \
299} while(0)
300#define hme_write_txd(__hp, __txd, __flags, __addr) \
301do { (__txd)->tx_addr = (__force hme32)cpu_to_le32(__addr); \
302 wmb(); \
303 (__txd)->tx_flags = (__force hme32)cpu_to_le32(__flags); \
304} while(0)
305static inline u32 hme_read_desc32(struct happy_meal *hp, hme32 *p)
306{
307 return le32_to_cpup((__le32 *)p);
308}
309#define hme_dma_map(__hp, __ptr, __size, __dir) \
310 pci_map_single((__hp)->dma_dev, (__ptr), (__size), (__dir))
311#define hme_dma_unmap(__hp, __addr, __size, __dir) \
312 pci_unmap_single((__hp)->dma_dev, (__addr), (__size), (__dir))
313#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
314 pci_dma_sync_single_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir))
315#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
316 pci_dma_sync_single_for_device((__hp)->dma_dev, (__addr), (__size), (__dir))
317#endif
318#endif
319
320
321
322static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
323{
324 hme_write32(hp, tregs + TCVR_BBDATA, bit);
325 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
326 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
327}
328
329#if 0
330static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
331{
332 u32 ret;
333
334 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
335 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
336 ret = hme_read32(hp, tregs + TCVR_CFG);
337 if (internal)
338 ret &= TCV_CFG_MDIO0;
339 else
340 ret &= TCV_CFG_MDIO1;
341
342 return ret;
343}
344#endif
345
346static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
347{
348 u32 retval;
349
350 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
351 udelay(1);
352 retval = hme_read32(hp, tregs + TCVR_CFG);
353 if (internal)
354 retval &= TCV_CFG_MDIO0;
355 else
356 retval &= TCV_CFG_MDIO1;
357 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
358
359 return retval;
360}
361
362#define TCVR_FAILURE 0x80000000
363
364static int happy_meal_bb_read(struct happy_meal *hp,
365 void __iomem *tregs, int reg)
366{
367 u32 tmp;
368 int retval = 0;
369 int i;
370
371 ASD(("happy_meal_bb_read: reg=%d ", reg));
372
373
374 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
375
376
377 for (i = 0; i < 32; i++)
378 BB_PUT_BIT(hp, tregs, 1);
379
380
381 BB_PUT_BIT(hp, tregs, 0);
382 BB_PUT_BIT(hp, tregs, 1);
383 BB_PUT_BIT(hp, tregs, 1);
384 BB_PUT_BIT(hp, tregs, 0);
385
386
387 tmp = hp->paddr & 0xff;
388 for (i = 4; i >= 0; i--)
389 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
390
391
392 tmp = (reg & 0xff);
393 for (i = 4; i >= 0; i--)
394 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
395
396
397 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
398
399
400 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
401 for (i = 15; i >= 0; i--)
402 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
403 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
404 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
405 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
406 ASD(("value=%x\n", retval));
407 return retval;
408}
409
410static void happy_meal_bb_write(struct happy_meal *hp,
411 void __iomem *tregs, int reg,
412 unsigned short value)
413{
414 u32 tmp;
415 int i;
416
417 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
418
419
420 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
421
422
423 for (i = 0; i < 32; i++)
424 BB_PUT_BIT(hp, tregs, 1);
425
426
427 BB_PUT_BIT(hp, tregs, 0);
428 BB_PUT_BIT(hp, tregs, 1);
429 BB_PUT_BIT(hp, tregs, 0);
430 BB_PUT_BIT(hp, tregs, 1);
431
432
433 tmp = (hp->paddr & 0xff);
434 for (i = 4; i >= 0; i--)
435 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
436
437
438 tmp = (reg & 0xff);
439 for (i = 4; i >= 0; i--)
440 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
441
442
443 BB_PUT_BIT(hp, tregs, 1);
444 BB_PUT_BIT(hp, tregs, 0);
445
446 for (i = 15; i >= 0; i--)
447 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
448
449
450 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
451}
452
453#define TCVR_READ_TRIES 16
454
455static int happy_meal_tcvr_read(struct happy_meal *hp,
456 void __iomem *tregs, int reg)
457{
458 int tries = TCVR_READ_TRIES;
459 int retval;
460
461 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
462 if (hp->tcvr_type == none) {
463 ASD(("no transceiver, value=TCVR_FAILURE\n"));
464 return TCVR_FAILURE;
465 }
466
467 if (!(hp->happy_flags & HFLAG_FENABLE)) {
468 ASD(("doing bit bang\n"));
469 return happy_meal_bb_read(hp, tregs, reg);
470 }
471
472 hme_write32(hp, tregs + TCVR_FRAME,
473 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
474 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
475 udelay(20);
476 if (!tries) {
477 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
478 return TCVR_FAILURE;
479 }
480 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
481 ASD(("value=%04x\n", retval));
482 return retval;
483}
484
485#define TCVR_WRITE_TRIES 16
486
487static void happy_meal_tcvr_write(struct happy_meal *hp,
488 void __iomem *tregs, int reg,
489 unsigned short value)
490{
491 int tries = TCVR_WRITE_TRIES;
492
493 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
494
495
496 if (!(hp->happy_flags & HFLAG_FENABLE)) {
497 happy_meal_bb_write(hp, tregs, reg, value);
498 return;
499 }
500
501
502 hme_write32(hp, tregs + TCVR_FRAME,
503 (FRAME_WRITE | (hp->paddr << 23) |
504 ((reg & 0xff) << 18) | (value & 0xffff)));
505 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
506 udelay(20);
507
508
509 if (!tries)
510 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
511
512
513}
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547static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
548{
549 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
550
551
552
553
554 if (hp->sw_bmcr & BMCR_FULLDPLX) {
555 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
556 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
557 return 0;
558 }
559
560
561 if (hp->sw_bmcr & BMCR_SPEED100) {
562 hp->sw_bmcr &= ~(BMCR_SPEED100);
563 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
564 return 0;
565 }
566
567
568 return -1;
569}
570
571static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
572{
573 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
574 if (hp->tcvr_type == external)
575 printk("external ");
576 else
577 printk("internal ");
578 printk("transceiver at ");
579 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
580 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
581 if (hp->sw_lpa & LPA_100FULL)
582 printk("100Mb/s, Full Duplex.\n");
583 else
584 printk("100Mb/s, Half Duplex.\n");
585 } else {
586 if (hp->sw_lpa & LPA_10FULL)
587 printk("10Mb/s, Full Duplex.\n");
588 else
589 printk("10Mb/s, Half Duplex.\n");
590 }
591}
592
593static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
594{
595 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
596 if (hp->tcvr_type == external)
597 printk("external ");
598 else
599 printk("internal ");
600 printk("transceiver at ");
601 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
602 if (hp->sw_bmcr & BMCR_SPEED100)
603 printk("100Mb/s, ");
604 else
605 printk("10Mb/s, ");
606 if (hp->sw_bmcr & BMCR_FULLDPLX)
607 printk("Full Duplex.\n");
608 else
609 printk("Half Duplex.\n");
610}
611
612static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
613{
614 int full;
615
616
617
618
619 if (hp->timer_state == arbwait) {
620 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
621 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
622 goto no_response;
623 if (hp->sw_lpa & LPA_100FULL)
624 full = 1;
625 else if (hp->sw_lpa & LPA_100HALF)
626 full = 0;
627 else if (hp->sw_lpa & LPA_10FULL)
628 full = 1;
629 else
630 full = 0;
631 } else {
632
633 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
634 if (hp->sw_bmcr & BMCR_FULLDPLX)
635 full = 1;
636 else
637 full = 0;
638 }
639
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646
647
648 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
649 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
650 ~(BIGMAC_TXCFG_ENABLE));
651 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
652 barrier();
653 if (full) {
654 hp->happy_flags |= HFLAG_FULL;
655 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
656 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
657 BIGMAC_TXCFG_FULLDPLX);
658 } else {
659 hp->happy_flags &= ~(HFLAG_FULL);
660 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
661 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
662 ~(BIGMAC_TXCFG_FULLDPLX));
663 }
664 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
665 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
666 BIGMAC_TXCFG_ENABLE);
667 return 0;
668no_response:
669 return 1;
670}
671
672static int happy_meal_init(struct happy_meal *hp);
673
674static int is_lucent_phy(struct happy_meal *hp)
675{
676 void __iomem *tregs = hp->tcvregs;
677 unsigned short mr2, mr3;
678 int ret = 0;
679
680 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
681 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
682 if ((mr2 & 0xffff) == 0x0180 &&
683 ((mr3 & 0xffff) >> 10) == 0x1d)
684 ret = 1;
685
686 return ret;
687}
688
689static void happy_meal_timer(unsigned long data)
690{
691 struct happy_meal *hp = (struct happy_meal *) data;
692 void __iomem *tregs = hp->tcvregs;
693 int restart_timer = 0;
694
695 spin_lock_irq(&hp->happy_lock);
696
697 hp->timer_ticks++;
698 switch(hp->timer_state) {
699 case arbwait:
700
701
702
703 if (hp->timer_ticks >= 10) {
704
705 do_force_mode:
706 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
707 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
708 hp->dev->name);
709 hp->sw_bmcr = BMCR_SPEED100;
710 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
711
712 if (!is_lucent_phy(hp)) {
713
714
715
716
717 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
718 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
719 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
720 }
721 hp->timer_state = ltrywait;
722 hp->timer_ticks = 0;
723 restart_timer = 1;
724 } else {
725
726 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
727 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
728 int ret;
729
730
731 ret = set_happy_link_modes(hp, tregs);
732 if (ret) {
733
734
735
736
737
738
739 goto do_force_mode;
740 }
741
742
743 hp->timer_state = lupwait;
744 restart_timer = 1;
745 } else {
746 restart_timer = 1;
747 }
748 }
749 break;
750
751 case lupwait:
752
753
754
755
756
757 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
758 if (hp->sw_bmsr & BMSR_LSTATUS) {
759
760
761
762 display_link_mode(hp, tregs);
763 hp->timer_state = asleep;
764 restart_timer = 0;
765 } else {
766 if (hp->timer_ticks >= 10) {
767 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
768 "not completely up.\n", hp->dev->name);
769 hp->timer_ticks = 0;
770 restart_timer = 1;
771 } else {
772 restart_timer = 1;
773 }
774 }
775 break;
776
777 case ltrywait:
778
779
780
781
782
783 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
784 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
785 if (hp->timer_ticks == 1) {
786 if (!is_lucent_phy(hp)) {
787
788
789
790 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
791 happy_meal_tcvr_write(hp, tregs,
792 DP83840_CSCONFIG, hp->sw_csconfig);
793 }
794 restart_timer = 1;
795 break;
796 }
797 if (hp->timer_ticks == 2) {
798 if (!is_lucent_phy(hp)) {
799 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
800 happy_meal_tcvr_write(hp, tregs,
801 DP83840_CSCONFIG, hp->sw_csconfig);
802 }
803 restart_timer = 1;
804 break;
805 }
806 if (hp->sw_bmsr & BMSR_LSTATUS) {
807
808 display_forced_link_mode(hp, tregs);
809 set_happy_link_modes(hp, tregs);
810 hp->timer_state = asleep;
811 restart_timer = 0;
812 } else {
813 if (hp->timer_ticks >= 4) {
814 int ret;
815
816 ret = try_next_permutation(hp, tregs);
817 if (ret == -1) {
818
819
820
821
822
823 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
824 hp->dev->name);
825
826 ret = happy_meal_init(hp);
827 if (ret) {
828
829 printk(KERN_ERR "%s: Error, cannot re-init the "
830 "Happy Meal.\n", hp->dev->name);
831 }
832 goto out;
833 }
834 if (!is_lucent_phy(hp)) {
835 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
836 DP83840_CSCONFIG);
837 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
838 happy_meal_tcvr_write(hp, tregs,
839 DP83840_CSCONFIG, hp->sw_csconfig);
840 }
841 hp->timer_ticks = 0;
842 restart_timer = 1;
843 } else {
844 restart_timer = 1;
845 }
846 }
847 break;
848
849 case asleep:
850 default:
851
852 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
853 hp->dev->name);
854 restart_timer = 0;
855 hp->timer_ticks = 0;
856 hp->timer_state = asleep;
857 break;
858 };
859
860 if (restart_timer) {
861 hp->happy_timer.expires = jiffies + ((12 * HZ)/10);
862 add_timer(&hp->happy_timer);
863 }
864
865out:
866 spin_unlock_irq(&hp->happy_lock);
867}
868
869#define TX_RESET_TRIES 32
870#define RX_RESET_TRIES 32
871
872
873static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
874{
875 int tries = TX_RESET_TRIES;
876
877 HMD(("happy_meal_tx_reset: reset, "));
878
879
880 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
881 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
882 udelay(20);
883
884
885 if (!tries)
886 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
887
888
889 HMD(("done\n"));
890}
891
892
893static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
894{
895 int tries = RX_RESET_TRIES;
896
897 HMD(("happy_meal_rx_reset: reset, "));
898
899
900 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
901 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
902 udelay(20);
903
904
905 if (!tries)
906 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
907
908
909 HMD(("done\n"));
910}
911
912#define STOP_TRIES 16
913
914
915static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
916{
917 int tries = STOP_TRIES;
918
919 HMD(("happy_meal_stop: reset, "));
920
921
922 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
923 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
924 udelay(20);
925
926
927 if (!tries)
928 printk(KERN_ERR "happy meal: Fry guys.");
929
930
931 HMD(("done\n"));
932}
933
934
935static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
936{
937 struct net_device_stats *stats = &hp->net_stats;
938
939 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
940 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
941
942 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
943 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
944
945 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
946 hme_write32(hp, bregs + BMAC_GLECTR, 0);
947
948 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
949
950 stats->collisions +=
951 (hme_read32(hp, bregs + BMAC_EXCTR) +
952 hme_read32(hp, bregs + BMAC_LTCTR));
953 hme_write32(hp, bregs + BMAC_EXCTR, 0);
954 hme_write32(hp, bregs + BMAC_LTCTR, 0);
955}
956
957
958static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
959{
960 ASD(("happy_meal_poll_stop: "));
961
962
963 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
964 (HFLAG_POLLENABLE | HFLAG_POLL)) {
965 HMD(("not polling, return\n"));
966 return;
967 }
968
969
970 ASD(("were polling, mif ints off, "));
971 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
972
973
974 ASD(("polling off, "));
975 hme_write32(hp, tregs + TCVR_CFG,
976 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
977
978
979 hp->happy_flags &= ~(HFLAG_POLL);
980
981
982 udelay(200);
983 ASD(("done\n"));
984}
985
986
987
988
989#define TCVR_RESET_TRIES 16
990#define TCVR_UNISOLATE_TRIES 32
991
992
993static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
994{
995 u32 tconfig;
996 int result, tries = TCVR_RESET_TRIES;
997
998 tconfig = hme_read32(hp, tregs + TCVR_CFG);
999 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
1000 if (hp->tcvr_type == external) {
1001 ASD(("external<"));
1002 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1003 hp->tcvr_type = internal;
1004 hp->paddr = TCV_PADDR_ITX;
1005 ASD(("ISOLATE,"));
1006 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1007 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1008 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1009 if (result == TCVR_FAILURE) {
1010 ASD(("phyread_fail>\n"));
1011 return -1;
1012 }
1013 ASD(("phyread_ok,PSELECT>"));
1014 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1015 hp->tcvr_type = external;
1016 hp->paddr = TCV_PADDR_ETX;
1017 } else {
1018 if (tconfig & TCV_CFG_MDIO1) {
1019 ASD(("internal<PSELECT,"));
1020 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1021 ASD(("ISOLATE,"));
1022 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1023 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1024 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1025 if (result == TCVR_FAILURE) {
1026 ASD(("phyread_fail>\n"));
1027 return -1;
1028 }
1029 ASD(("phyread_ok,~PSELECT>"));
1030 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1031 hp->tcvr_type = internal;
1032 hp->paddr = TCV_PADDR_ITX;
1033 }
1034 }
1035
1036 ASD(("BMCR_RESET "));
1037 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1038
1039 while (--tries) {
1040 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1041 if (result == TCVR_FAILURE)
1042 return -1;
1043 hp->sw_bmcr = result;
1044 if (!(result & BMCR_RESET))
1045 break;
1046 udelay(20);
1047 }
1048 if (!tries) {
1049 ASD(("BMCR RESET FAILED!\n"));
1050 return -1;
1051 }
1052 ASD(("RESET_OK\n"));
1053
1054
1055 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1056 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1057 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1058 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1059
1060 ASD(("UNISOLATE"));
1061 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1062 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1063
1064 tries = TCVR_UNISOLATE_TRIES;
1065 while (--tries) {
1066 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1067 if (result == TCVR_FAILURE)
1068 return -1;
1069 if (!(result & BMCR_ISOLATE))
1070 break;
1071 udelay(20);
1072 }
1073 if (!tries) {
1074 ASD((" FAILED!\n"));
1075 return -1;
1076 }
1077 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1078 if (!is_lucent_phy(hp)) {
1079 result = happy_meal_tcvr_read(hp, tregs,
1080 DP83840_CSCONFIG);
1081 happy_meal_tcvr_write(hp, tregs,
1082 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1083 }
1084 return 0;
1085}
1086
1087
1088
1089
1090
1091static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1092{
1093 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1094
1095 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1096 if (hp->happy_flags & HFLAG_POLL) {
1097
1098 ASD(("<polling> "));
1099 if (hp->tcvr_type == internal) {
1100 if (tconfig & TCV_CFG_MDIO1) {
1101 ASD(("<internal> <poll stop> "));
1102 happy_meal_poll_stop(hp, tregs);
1103 hp->paddr = TCV_PADDR_ETX;
1104 hp->tcvr_type = external;
1105 ASD(("<external>\n"));
1106 tconfig &= ~(TCV_CFG_PENABLE);
1107 tconfig |= TCV_CFG_PSELECT;
1108 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1109 }
1110 } else {
1111 if (hp->tcvr_type == external) {
1112 ASD(("<external> "));
1113 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1114 ASD(("<poll stop> "));
1115 happy_meal_poll_stop(hp, tregs);
1116 hp->paddr = TCV_PADDR_ITX;
1117 hp->tcvr_type = internal;
1118 ASD(("<internal>\n"));
1119 hme_write32(hp, tregs + TCVR_CFG,
1120 hme_read32(hp, tregs + TCVR_CFG) &
1121 ~(TCV_CFG_PSELECT));
1122 }
1123 ASD(("\n"));
1124 } else {
1125 ASD(("<none>\n"));
1126 }
1127 }
1128 } else {
1129 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1130
1131
1132 ASD(("<not polling> "));
1133 if (reread & TCV_CFG_MDIO1) {
1134 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1135 hp->paddr = TCV_PADDR_ETX;
1136 hp->tcvr_type = external;
1137 ASD(("<external>\n"));
1138 } else {
1139 if (reread & TCV_CFG_MDIO0) {
1140 hme_write32(hp, tregs + TCVR_CFG,
1141 tconfig & ~(TCV_CFG_PSELECT));
1142 hp->paddr = TCV_PADDR_ITX;
1143 hp->tcvr_type = internal;
1144 ASD(("<internal>\n"));
1145 } else {
1146 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1147 hp->tcvr_type = none;
1148 ASD(("<none>\n"));
1149 }
1150 }
1151 }
1152}
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198static void happy_meal_clean_rings(struct happy_meal *hp)
1199{
1200 int i;
1201
1202 for (i = 0; i < RX_RING_SIZE; i++) {
1203 if (hp->rx_skbs[i] != NULL) {
1204 struct sk_buff *skb = hp->rx_skbs[i];
1205 struct happy_meal_rxd *rxd;
1206 u32 dma_addr;
1207
1208 rxd = &hp->happy_block->happy_meal_rxd[i];
1209 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1210 dma_unmap_single(hp->dma_dev, dma_addr,
1211 RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
1212 dev_kfree_skb_any(skb);
1213 hp->rx_skbs[i] = NULL;
1214 }
1215 }
1216
1217 for (i = 0; i < TX_RING_SIZE; i++) {
1218 if (hp->tx_skbs[i] != NULL) {
1219 struct sk_buff *skb = hp->tx_skbs[i];
1220 struct happy_meal_txd *txd;
1221 u32 dma_addr;
1222 int frag;
1223
1224 hp->tx_skbs[i] = NULL;
1225
1226 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1227 txd = &hp->happy_block->happy_meal_txd[i];
1228 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1229 dma_unmap_single(hp->dma_dev, dma_addr,
1230 (hme_read_desc32(hp, &txd->tx_flags)
1231 & TXFLAG_SIZE),
1232 DMA_TO_DEVICE);
1233
1234 if (frag != skb_shinfo(skb)->nr_frags)
1235 i++;
1236 }
1237
1238 dev_kfree_skb_any(skb);
1239 }
1240 }
1241}
1242
1243
1244static void happy_meal_init_rings(struct happy_meal *hp)
1245{
1246 struct hmeal_init_block *hb = hp->happy_block;
1247 struct net_device *dev = hp->dev;
1248 int i;
1249
1250 HMD(("happy_meal_init_rings: counters to zero, "));
1251 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1252
1253
1254 HMD(("clean, "));
1255 happy_meal_clean_rings(hp);
1256
1257
1258 HMD(("init rxring, "));
1259 for (i = 0; i < RX_RING_SIZE; i++) {
1260 struct sk_buff *skb;
1261
1262 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1263 if (!skb) {
1264 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1265 continue;
1266 }
1267 hp->rx_skbs[i] = skb;
1268 skb->dev = dev;
1269
1270
1271 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
1272 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1273 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1274 dma_map_single(hp->dma_dev, skb->data, RX_BUF_ALLOC_SIZE,
1275 DMA_FROM_DEVICE));
1276 skb_reserve(skb, RX_OFFSET);
1277 }
1278
1279 HMD(("init txring, "));
1280 for (i = 0; i < TX_RING_SIZE; i++)
1281 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1282
1283 HMD(("done\n"));
1284}
1285
1286
1287static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1288 void __iomem *tregs,
1289 struct ethtool_cmd *ep)
1290{
1291 int timeout;
1292
1293
1294 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1295 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1296 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1297 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1298
1299
1300
1301 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1302 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1303
1304 if (hp->sw_bmsr & BMSR_10HALF)
1305 hp->sw_advertise |= (ADVERTISE_10HALF);
1306 else
1307 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1308
1309 if (hp->sw_bmsr & BMSR_10FULL)
1310 hp->sw_advertise |= (ADVERTISE_10FULL);
1311 else
1312 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1313 if (hp->sw_bmsr & BMSR_100HALF)
1314 hp->sw_advertise |= (ADVERTISE_100HALF);
1315 else
1316 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1317 if (hp->sw_bmsr & BMSR_100FULL)
1318 hp->sw_advertise |= (ADVERTISE_100FULL);
1319 else
1320 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1321 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1322
1323
1324
1325
1326
1327
1328
1329#ifdef AUTO_SWITCH_DEBUG
1330 ASD(("%s: Advertising [ ", hp->dev->name));
1331 if (hp->sw_advertise & ADVERTISE_10HALF)
1332 ASD(("10H "));
1333 if (hp->sw_advertise & ADVERTISE_10FULL)
1334 ASD(("10F "));
1335 if (hp->sw_advertise & ADVERTISE_100HALF)
1336 ASD(("100H "));
1337 if (hp->sw_advertise & ADVERTISE_100FULL)
1338 ASD(("100F "));
1339#endif
1340
1341
1342 hp->sw_bmcr |= BMCR_ANENABLE;
1343 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1344
1345
1346 hp->sw_bmcr |= BMCR_ANRESTART;
1347 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1348
1349
1350
1351 timeout = 64;
1352 while (--timeout) {
1353 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1354 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1355 break;
1356 udelay(10);
1357 }
1358 if (!timeout) {
1359 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1360 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1361 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1362 hp->dev->name);
1363 goto force_link;
1364 } else {
1365 hp->timer_state = arbwait;
1366 }
1367 } else {
1368force_link:
1369
1370
1371
1372
1373
1374
1375
1376
1377 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1378 hp->sw_bmcr = BMCR_SPEED100;
1379 } else {
1380 if (ep->speed == SPEED_100)
1381 hp->sw_bmcr = BMCR_SPEED100;
1382 else
1383 hp->sw_bmcr = 0;
1384 if (ep->duplex == DUPLEX_FULL)
1385 hp->sw_bmcr |= BMCR_FULLDPLX;
1386 }
1387 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1388
1389 if (!is_lucent_phy(hp)) {
1390
1391
1392
1393
1394 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1395 DP83840_CSCONFIG);
1396 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1397 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1398 hp->sw_csconfig);
1399 }
1400 hp->timer_state = ltrywait;
1401 }
1402
1403 hp->timer_ticks = 0;
1404 hp->happy_timer.expires = jiffies + (12 * HZ)/10;
1405 hp->happy_timer.data = (unsigned long) hp;
1406 hp->happy_timer.function = &happy_meal_timer;
1407 add_timer(&hp->happy_timer);
1408}
1409
1410
1411static int happy_meal_init(struct happy_meal *hp)
1412{
1413 void __iomem *gregs = hp->gregs;
1414 void __iomem *etxregs = hp->etxregs;
1415 void __iomem *erxregs = hp->erxregs;
1416 void __iomem *bregs = hp->bigmacregs;
1417 void __iomem *tregs = hp->tcvregs;
1418 u32 regtmp, rxcfg;
1419 unsigned char *e = &hp->dev->dev_addr[0];
1420
1421
1422 del_timer(&hp->happy_timer);
1423
1424 HMD(("happy_meal_init: happy_flags[%08x] ",
1425 hp->happy_flags));
1426 if (!(hp->happy_flags & HFLAG_INIT)) {
1427 HMD(("set HFLAG_INIT, "));
1428 hp->happy_flags |= HFLAG_INIT;
1429 happy_meal_get_counters(hp, bregs);
1430 }
1431
1432
1433 HMD(("to happy_meal_poll_stop\n"));
1434 happy_meal_poll_stop(hp, tregs);
1435
1436
1437 HMD(("happy_meal_init: to happy_meal_stop\n"));
1438 happy_meal_stop(hp, gregs);
1439
1440
1441 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1442 happy_meal_init_rings(hp);
1443
1444
1445 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1446 hme_read32(hp, tregs + TCVR_IMASK)));
1447 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1448
1449
1450 if (hp->happy_flags & HFLAG_FENABLE) {
1451 HMD(("use frame old[%08x], ",
1452 hme_read32(hp, tregs + TCVR_CFG)));
1453 hme_write32(hp, tregs + TCVR_CFG,
1454 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1455 } else {
1456 HMD(("use bitbang old[%08x], ",
1457 hme_read32(hp, tregs + TCVR_CFG)));
1458 hme_write32(hp, tregs + TCVR_CFG,
1459 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1460 }
1461
1462
1463 HMD(("to happy_meal_transceiver_check\n"));
1464 happy_meal_transceiver_check(hp, tregs);
1465
1466
1467 HMD(("happy_meal_init: "));
1468 switch(hp->tcvr_type) {
1469 case none:
1470
1471 HMD(("AAIEEE no transceiver type, EAGAIN"));
1472 return -EAGAIN;
1473
1474 case internal:
1475
1476 HMD(("internal, using MII, "));
1477 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1478 break;
1479
1480 case external:
1481
1482 HMD(("external, disable MII, "));
1483 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1484 break;
1485 };
1486
1487 if (happy_meal_tcvr_reset(hp, tregs))
1488 return -EAGAIN;
1489
1490
1491 HMD(("tx/rx reset, "));
1492 happy_meal_tx_reset(hp, bregs);
1493 happy_meal_rx_reset(hp, bregs);
1494
1495
1496 HMD(("jsize/ipg1/ipg2, "));
1497 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1498 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1499 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1500
1501
1502 HMD(("rseed/macaddr, "));
1503
1504
1505 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1506
1507 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1508 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1509 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1510
1511 HMD(("htable, "));
1512 if ((hp->dev->flags & IFF_ALLMULTI) ||
1513 (hp->dev->mc_count > 64)) {
1514 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1515 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1516 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1517 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1518 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1519 u16 hash_table[4];
1520 struct dev_mc_list *dmi = hp->dev->mc_list;
1521 char *addrs;
1522 int i;
1523 u32 crc;
1524
1525 for (i = 0; i < 4; i++)
1526 hash_table[i] = 0;
1527
1528 for (i = 0; i < hp->dev->mc_count; i++) {
1529 addrs = dmi->dmi_addr;
1530 dmi = dmi->next;
1531
1532 if (!(*addrs & 1))
1533 continue;
1534
1535 crc = ether_crc_le(6, addrs);
1536 crc >>= 26;
1537 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1538 }
1539 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1540 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1541 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1542 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1543 } else {
1544 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1545 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1546 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1547 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1548 }
1549
1550
1551 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1552 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1553 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1554 hme_write32(hp, erxregs + ERX_RING,
1555 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1556 hme_write32(hp, etxregs + ETX_RING,
1557 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1558
1559
1560
1561
1562
1563
1564 if (hme_read32(hp, erxregs + ERX_RING) !=
1565 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1566 hme_write32(hp, erxregs + ERX_RING,
1567 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1568 | 0x4);
1569
1570
1571 HMD(("happy_meal_init: old[%08x] bursts<",
1572 hme_read32(hp, gregs + GREG_CFG)));
1573
1574#ifndef CONFIG_SPARC
1575
1576 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1577#else
1578 if ((hp->happy_bursts & DMA_BURST64) &&
1579 ((hp->happy_flags & HFLAG_PCI) != 0
1580#ifdef CONFIG_SBUS
1581 || sbus_can_burst64()
1582#endif
1583 || 0)) {
1584 u32 gcfg = GREG_CFG_BURST64;
1585
1586
1587
1588
1589
1590#ifdef CONFIG_SBUS
1591 if ((hp->happy_flags & HFLAG_PCI) == 0) {
1592 struct of_device *op = hp->happy_dev;
1593 if (sbus_can_dma_64bit()) {
1594 sbus_set_sbus64(&op->dev,
1595 hp->happy_bursts);
1596 gcfg |= GREG_CFG_64BIT;
1597 }
1598 }
1599#endif
1600
1601 HMD(("64>"));
1602 hme_write32(hp, gregs + GREG_CFG, gcfg);
1603 } else if (hp->happy_bursts & DMA_BURST32) {
1604 HMD(("32>"));
1605 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1606 } else if (hp->happy_bursts & DMA_BURST16) {
1607 HMD(("16>"));
1608 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1609 } else {
1610 HMD(("XXX>"));
1611 hme_write32(hp, gregs + GREG_CFG, 0);
1612 }
1613#endif
1614
1615
1616 HMD((", enable global interrupts, "));
1617 hme_write32(hp, gregs + GREG_IMASK,
1618 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1619 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1620
1621
1622 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1623 hme_read32(hp, etxregs + ETX_RSIZE)));
1624 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1625
1626
1627 HMD(("tx dma enable old[%08x], ",
1628 hme_read32(hp, etxregs + ETX_CFG)));
1629 hme_write32(hp, etxregs + ETX_CFG,
1630 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1631
1632
1633
1634
1635
1636
1637 HMD(("erx regs bug old[%08x]\n",
1638 hme_read32(hp, erxregs + ERX_CFG)));
1639 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1640 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1641 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1642 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1643 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1644 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1645 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1646
1647 }
1648
1649
1650 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1651 hme_read32(hp, bregs + BMAC_RXCFG)));
1652 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
1653 if (hp->dev->flags & IFF_PROMISC)
1654 rxcfg |= BIGMAC_RXCFG_PMISC;
1655 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1656
1657
1658 udelay(10);
1659
1660
1661 HMD(("BIGMAC init, "));
1662 regtmp = 0;
1663 if (hp->happy_flags & HFLAG_FULL)
1664 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1665
1666
1667
1668
1669 hme_write32(hp, bregs + BMAC_TXCFG, regtmp );
1670
1671
1672 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1673
1674
1675 regtmp = BIGMAC_XCFG_ODENABLE;
1676
1677
1678 if (hp->happy_flags & HFLAG_LANCE)
1679 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1680
1681
1682 if (hp->tcvr_type == external)
1683 regtmp |= BIGMAC_XCFG_MIIDISAB;
1684
1685 HMD(("XIF config old[%08x], ",
1686 hme_read32(hp, bregs + BMAC_XIFCFG)));
1687 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1688
1689
1690 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1691 hme_read32(hp, bregs + BMAC_TXCFG),
1692 hme_read32(hp, bregs + BMAC_RXCFG)));
1693
1694
1695 hme_write32(hp, bregs + BMAC_TXMAX, ETH_FRAME_LEN + 8);
1696 hme_write32(hp, bregs + BMAC_RXMAX, ETH_FRAME_LEN + 8);
1697
1698 hme_write32(hp, bregs + BMAC_TXCFG,
1699 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1700 hme_write32(hp, bregs + BMAC_RXCFG,
1701 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1702
1703
1704 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1705
1706
1707 return 0;
1708}
1709
1710
1711static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1712{
1713 void __iomem *tregs = hp->tcvregs;
1714 void __iomem *bregs = hp->bigmacregs;
1715 void __iomem *gregs = hp->gregs;
1716
1717 happy_meal_stop(hp, gregs);
1718 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1719 if (hp->happy_flags & HFLAG_FENABLE)
1720 hme_write32(hp, tregs + TCVR_CFG,
1721 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1722 else
1723 hme_write32(hp, tregs + TCVR_CFG,
1724 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1725 happy_meal_transceiver_check(hp, tregs);
1726 switch(hp->tcvr_type) {
1727 case none:
1728 return;
1729 case internal:
1730 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1731 break;
1732 case external:
1733 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1734 break;
1735 };
1736 if (happy_meal_tcvr_reset(hp, tregs))
1737 return;
1738
1739
1740 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1741 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1742
1743
1744 if (hp->sw_bmsr & BMSR_10HALF)
1745 hp->sw_advertise |= (ADVERTISE_10HALF);
1746 else
1747 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1748
1749 if (hp->sw_bmsr & BMSR_10FULL)
1750 hp->sw_advertise |= (ADVERTISE_10FULL);
1751 else
1752 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1753 if (hp->sw_bmsr & BMSR_100HALF)
1754 hp->sw_advertise |= (ADVERTISE_100HALF);
1755 else
1756 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1757 if (hp->sw_bmsr & BMSR_100FULL)
1758 hp->sw_advertise |= (ADVERTISE_100FULL);
1759 else
1760 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1761
1762
1763 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1764}
1765
1766
1767
1768
1769
1770
1771static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1772{
1773 int reset = 0;
1774
1775
1776 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1777 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1778 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1779 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1780 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1781 GREG_STAT_SLVPERR))
1782 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1783 hp->dev->name, status);
1784
1785 if (status & GREG_STAT_RFIFOVF) {
1786
1787
1788 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1789 }
1790
1791 if (status & GREG_STAT_STSTERR) {
1792
1793 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1794 reset = 1;
1795 }
1796
1797 if (status & GREG_STAT_TFIFO_UND) {
1798
1799 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1800 hp->dev->name);
1801 reset = 1;
1802 }
1803
1804 if (status & GREG_STAT_MAXPKTERR) {
1805
1806
1807
1808 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1809 reset = 1;
1810 }
1811
1812 if (status & GREG_STAT_NORXD) {
1813
1814
1815
1816
1817
1818 printk(KERN_INFO "%s: Happy Meal out of receive "
1819 "descriptors, packet dropped.\n",
1820 hp->dev->name);
1821 }
1822
1823 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1824
1825 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1826 if (status & GREG_STAT_RXERR)
1827 printk("GenericError ");
1828 if (status & GREG_STAT_RXPERR)
1829 printk("ParityError ");
1830 if (status & GREG_STAT_RXTERR)
1831 printk("RxTagBotch ");
1832 printk("]\n");
1833 reset = 1;
1834 }
1835
1836 if (status & GREG_STAT_EOPERR) {
1837
1838
1839
1840 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1841 hp->dev->name);
1842 reset = 1;
1843 }
1844
1845 if (status & GREG_STAT_MIFIRQ) {
1846
1847 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1848 }
1849
1850 if (status &
1851 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1852
1853 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1854 if (status & GREG_STAT_TXEACK)
1855 printk("GenericError ");
1856 if (status & GREG_STAT_TXLERR)
1857 printk("LateError ");
1858 if (status & GREG_STAT_TXPERR)
1859 printk("ParityErro ");
1860 if (status & GREG_STAT_TXTERR)
1861 printk("TagBotch ");
1862 printk("]\n");
1863 reset = 1;
1864 }
1865
1866 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1867
1868
1869
1870 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1871 hp->dev->name,
1872 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1873 reset = 1;
1874 }
1875
1876 if (reset) {
1877 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1878 happy_meal_init(hp);
1879 return 1;
1880 }
1881 return 0;
1882}
1883
1884
1885static void happy_meal_mif_interrupt(struct happy_meal *hp)
1886{
1887 void __iomem *tregs = hp->tcvregs;
1888
1889 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1890 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1891 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1892
1893
1894 if (hp->sw_lpa & LPA_100FULL) {
1895 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1896 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1897 } else if (hp->sw_lpa & LPA_100HALF) {
1898 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1899 hp->sw_bmcr |= BMCR_SPEED100;
1900 } else if (hp->sw_lpa & LPA_10FULL) {
1901 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1902 hp->sw_bmcr |= BMCR_FULLDPLX;
1903 } else {
1904 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1905 }
1906 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1907
1908
1909 happy_meal_poll_stop(hp, tregs);
1910}
1911
1912#ifdef TXDEBUG
1913#define TXD(x) printk x
1914#else
1915#define TXD(x)
1916#endif
1917
1918
1919static void happy_meal_tx(struct happy_meal *hp)
1920{
1921 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1922 struct happy_meal_txd *this;
1923 struct net_device *dev = hp->dev;
1924 int elem;
1925
1926 elem = hp->tx_old;
1927 TXD(("TX<"));
1928 while (elem != hp->tx_new) {
1929 struct sk_buff *skb;
1930 u32 flags, dma_addr, dma_len;
1931 int frag;
1932
1933 TXD(("[%d]", elem));
1934 this = &txbase[elem];
1935 flags = hme_read_desc32(hp, &this->tx_flags);
1936 if (flags & TXFLAG_OWN)
1937 break;
1938 skb = hp->tx_skbs[elem];
1939 if (skb_shinfo(skb)->nr_frags) {
1940 int last;
1941
1942 last = elem + skb_shinfo(skb)->nr_frags;
1943 last &= (TX_RING_SIZE - 1);
1944 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1945 if (flags & TXFLAG_OWN)
1946 break;
1947 }
1948 hp->tx_skbs[elem] = NULL;
1949 hp->net_stats.tx_bytes += skb->len;
1950
1951 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1952 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1953 dma_len = hme_read_desc32(hp, &this->tx_flags);
1954
1955 dma_len &= TXFLAG_SIZE;
1956 dma_unmap_single(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE);
1957
1958 elem = NEXT_TX(elem);
1959 this = &txbase[elem];
1960 }
1961
1962 dev_kfree_skb_irq(skb);
1963 hp->net_stats.tx_packets++;
1964 }
1965 hp->tx_old = elem;
1966 TXD((">"));
1967
1968 if (netif_queue_stopped(dev) &&
1969 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
1970 netif_wake_queue(dev);
1971}
1972
1973#ifdef RXDEBUG
1974#define RXD(x) printk x
1975#else
1976#define RXD(x)
1977#endif
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
1989{
1990 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
1991 struct happy_meal_rxd *this;
1992 int elem = hp->rx_new, drops = 0;
1993 u32 flags;
1994
1995 RXD(("RX<"));
1996 this = &rxbase[elem];
1997 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
1998 struct sk_buff *skb;
1999 int len = flags >> 16;
2000 u16 csum = flags & RXFLAG_CSUM;
2001 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2002
2003 RXD(("[%d ", elem));
2004
2005
2006 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2007 RXD(("ERR(%08x)]", flags));
2008 hp->net_stats.rx_errors++;
2009 if (len < ETH_ZLEN)
2010 hp->net_stats.rx_length_errors++;
2011 if (len & (RXFLAG_OVERFLOW >> 16)) {
2012 hp->net_stats.rx_over_errors++;
2013 hp->net_stats.rx_fifo_errors++;
2014 }
2015
2016
2017 drop_it:
2018 hp->net_stats.rx_dropped++;
2019 hme_write_rxd(hp, this,
2020 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2021 dma_addr);
2022 goto next;
2023 }
2024 skb = hp->rx_skbs[elem];
2025 if (len > RX_COPY_THRESHOLD) {
2026 struct sk_buff *new_skb;
2027
2028
2029 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2030 if (new_skb == NULL) {
2031 drops++;
2032 goto drop_it;
2033 }
2034 dma_unmap_single(hp->dma_dev, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
2035 hp->rx_skbs[elem] = new_skb;
2036 new_skb->dev = dev;
2037 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
2038 hme_write_rxd(hp, this,
2039 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2040 dma_map_single(hp->dma_dev, new_skb->data, RX_BUF_ALLOC_SIZE,
2041 DMA_FROM_DEVICE));
2042 skb_reserve(new_skb, RX_OFFSET);
2043
2044
2045 skb_trim(skb, len);
2046 } else {
2047 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2048
2049 if (copy_skb == NULL) {
2050 drops++;
2051 goto drop_it;
2052 }
2053
2054 skb_reserve(copy_skb, 2);
2055 skb_put(copy_skb, len);
2056 dma_sync_single_for_cpu(hp->dma_dev, dma_addr, len, DMA_FROM_DEVICE);
2057 skb_copy_from_linear_data(skb, copy_skb->data, len);
2058 dma_sync_single_for_device(hp->dma_dev, dma_addr, len, DMA_FROM_DEVICE);
2059
2060 hme_write_rxd(hp, this,
2061 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2062 dma_addr);
2063
2064 skb = copy_skb;
2065 }
2066
2067
2068 skb->csum = csum_unfold(~(__force __sum16)htons(csum));
2069 skb->ip_summed = CHECKSUM_COMPLETE;
2070
2071 RXD(("len=%d csum=%4x]", len, csum));
2072 skb->protocol = eth_type_trans(skb, dev);
2073 netif_rx(skb);
2074
2075 hp->net_stats.rx_packets++;
2076 hp->net_stats.rx_bytes += len;
2077 next:
2078 elem = NEXT_RX(elem);
2079 this = &rxbase[elem];
2080 }
2081 hp->rx_new = elem;
2082 if (drops)
2083 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2084 RXD((">"));
2085}
2086
2087static irqreturn_t happy_meal_interrupt(int irq, void *dev_id)
2088{
2089 struct net_device *dev = dev_id;
2090 struct happy_meal *hp = netdev_priv(dev);
2091 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2092
2093 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2094
2095 spin_lock(&hp->happy_lock);
2096
2097 if (happy_status & GREG_STAT_ERRORS) {
2098 HMD(("ERRORS "));
2099 if (happy_meal_is_not_so_happy(hp, happy_status))
2100 goto out;
2101 }
2102
2103 if (happy_status & GREG_STAT_MIFIRQ) {
2104 HMD(("MIFIRQ "));
2105 happy_meal_mif_interrupt(hp);
2106 }
2107
2108 if (happy_status & GREG_STAT_TXALL) {
2109 HMD(("TXALL "));
2110 happy_meal_tx(hp);
2111 }
2112
2113 if (happy_status & GREG_STAT_RXTOHOST) {
2114 HMD(("RXTOHOST "));
2115 happy_meal_rx(hp, dev);
2116 }
2117
2118 HMD(("done\n"));
2119out:
2120 spin_unlock(&hp->happy_lock);
2121
2122 return IRQ_HANDLED;
2123}
2124
2125#ifdef CONFIG_SBUS
2126static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie)
2127{
2128 struct quattro *qp = (struct quattro *) cookie;
2129 int i;
2130
2131 for (i = 0; i < 4; i++) {
2132 struct net_device *dev = qp->happy_meals[i];
2133 struct happy_meal *hp = netdev_priv(dev);
2134 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2135
2136 HMD(("quattro_interrupt: status=%08x ", happy_status));
2137
2138 if (!(happy_status & (GREG_STAT_ERRORS |
2139 GREG_STAT_MIFIRQ |
2140 GREG_STAT_TXALL |
2141 GREG_STAT_RXTOHOST)))
2142 continue;
2143
2144 spin_lock(&hp->happy_lock);
2145
2146 if (happy_status & GREG_STAT_ERRORS) {
2147 HMD(("ERRORS "));
2148 if (happy_meal_is_not_so_happy(hp, happy_status))
2149 goto next;
2150 }
2151
2152 if (happy_status & GREG_STAT_MIFIRQ) {
2153 HMD(("MIFIRQ "));
2154 happy_meal_mif_interrupt(hp);
2155 }
2156
2157 if (happy_status & GREG_STAT_TXALL) {
2158 HMD(("TXALL "));
2159 happy_meal_tx(hp);
2160 }
2161
2162 if (happy_status & GREG_STAT_RXTOHOST) {
2163 HMD(("RXTOHOST "));
2164 happy_meal_rx(hp, dev);
2165 }
2166
2167 next:
2168 spin_unlock(&hp->happy_lock);
2169 }
2170 HMD(("done\n"));
2171
2172 return IRQ_HANDLED;
2173}
2174#endif
2175
2176static int happy_meal_open(struct net_device *dev)
2177{
2178 struct happy_meal *hp = netdev_priv(dev);
2179 int res;
2180
2181 HMD(("happy_meal_open: "));
2182
2183
2184
2185
2186 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2187 if (request_irq(dev->irq, &happy_meal_interrupt,
2188 IRQF_SHARED, dev->name, (void *)dev)) {
2189 HMD(("EAGAIN\n"));
2190 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2191 dev->irq);
2192
2193 return -EAGAIN;
2194 }
2195 }
2196
2197 HMD(("to happy_meal_init\n"));
2198
2199 spin_lock_irq(&hp->happy_lock);
2200 res = happy_meal_init(hp);
2201 spin_unlock_irq(&hp->happy_lock);
2202
2203 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2204 free_irq(dev->irq, dev);
2205 return res;
2206}
2207
2208static int happy_meal_close(struct net_device *dev)
2209{
2210 struct happy_meal *hp = netdev_priv(dev);
2211
2212 spin_lock_irq(&hp->happy_lock);
2213 happy_meal_stop(hp, hp->gregs);
2214 happy_meal_clean_rings(hp);
2215
2216
2217 del_timer(&hp->happy_timer);
2218
2219 spin_unlock_irq(&hp->happy_lock);
2220
2221
2222
2223
2224
2225 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2226 free_irq(dev->irq, dev);
2227
2228 return 0;
2229}
2230
2231#ifdef SXDEBUG
2232#define SXD(x) printk x
2233#else
2234#define SXD(x)
2235#endif
2236
2237static void happy_meal_tx_timeout(struct net_device *dev)
2238{
2239 struct happy_meal *hp = netdev_priv(dev);
2240
2241 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2242 tx_dump_log();
2243 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2244 hme_read32(hp, hp->gregs + GREG_STAT),
2245 hme_read32(hp, hp->etxregs + ETX_CFG),
2246 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2247
2248 spin_lock_irq(&hp->happy_lock);
2249 happy_meal_init(hp);
2250 spin_unlock_irq(&hp->happy_lock);
2251
2252 netif_wake_queue(dev);
2253}
2254
2255static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2256{
2257 struct happy_meal *hp = netdev_priv(dev);
2258 int entry;
2259 u32 tx_flags;
2260
2261 tx_flags = TXFLAG_OWN;
2262 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2263 const u32 csum_start_off = skb_transport_offset(skb);
2264 const u32 csum_stuff_off = csum_start_off + skb->csum_offset;
2265
2266 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2267 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2268 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2269 }
2270
2271 spin_lock_irq(&hp->happy_lock);
2272
2273 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2274 netif_stop_queue(dev);
2275 spin_unlock_irq(&hp->happy_lock);
2276 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
2277 dev->name);
2278 return 1;
2279 }
2280
2281 entry = hp->tx_new;
2282 SXD(("SX<l[%d]e[%d]>", len, entry));
2283 hp->tx_skbs[entry] = skb;
2284
2285 if (skb_shinfo(skb)->nr_frags == 0) {
2286 u32 mapping, len;
2287
2288 len = skb->len;
2289 mapping = dma_map_single(hp->dma_dev, skb->data, len, DMA_TO_DEVICE);
2290 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2291 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2292 (tx_flags | (len & TXFLAG_SIZE)),
2293 mapping);
2294 entry = NEXT_TX(entry);
2295 } else {
2296 u32 first_len, first_mapping;
2297 int frag, first_entry = entry;
2298
2299
2300
2301
2302 first_len = skb_headlen(skb);
2303 first_mapping = dma_map_single(hp->dma_dev, skb->data, first_len,
2304 DMA_TO_DEVICE);
2305 entry = NEXT_TX(entry);
2306
2307 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2308 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2309 u32 len, mapping, this_txflags;
2310
2311 len = this_frag->size;
2312 mapping = dma_map_page(hp->dma_dev, this_frag->page,
2313 this_frag->page_offset, len,
2314 DMA_TO_DEVICE);
2315 this_txflags = tx_flags;
2316 if (frag == skb_shinfo(skb)->nr_frags - 1)
2317 this_txflags |= TXFLAG_EOP;
2318 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2319 (this_txflags | (len & TXFLAG_SIZE)),
2320 mapping);
2321 entry = NEXT_TX(entry);
2322 }
2323 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2324 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2325 first_mapping);
2326 }
2327
2328 hp->tx_new = entry;
2329
2330 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2331 netif_stop_queue(dev);
2332
2333
2334 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2335
2336 spin_unlock_irq(&hp->happy_lock);
2337
2338 dev->trans_start = jiffies;
2339
2340 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2341 return 0;
2342}
2343
2344static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2345{
2346 struct happy_meal *hp = netdev_priv(dev);
2347
2348 spin_lock_irq(&hp->happy_lock);
2349 happy_meal_get_counters(hp, hp->bigmacregs);
2350 spin_unlock_irq(&hp->happy_lock);
2351
2352 return &hp->net_stats;
2353}
2354
2355static void happy_meal_set_multicast(struct net_device *dev)
2356{
2357 struct happy_meal *hp = netdev_priv(dev);
2358 void __iomem *bregs = hp->bigmacregs;
2359 struct dev_mc_list *dmi = dev->mc_list;
2360 char *addrs;
2361 int i;
2362 u32 crc;
2363
2364 spin_lock_irq(&hp->happy_lock);
2365
2366 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2367 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2368 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2369 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2370 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2371 } else if (dev->flags & IFF_PROMISC) {
2372 hme_write32(hp, bregs + BMAC_RXCFG,
2373 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2374 } else {
2375 u16 hash_table[4];
2376
2377 for (i = 0; i < 4; i++)
2378 hash_table[i] = 0;
2379
2380 for (i = 0; i < dev->mc_count; i++) {
2381 addrs = dmi->dmi_addr;
2382 dmi = dmi->next;
2383
2384 if (!(*addrs & 1))
2385 continue;
2386
2387 crc = ether_crc_le(6, addrs);
2388 crc >>= 26;
2389 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2390 }
2391 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2392 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2393 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2394 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2395 }
2396
2397 spin_unlock_irq(&hp->happy_lock);
2398}
2399
2400
2401static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2402{
2403 struct happy_meal *hp = netdev_priv(dev);
2404
2405 cmd->supported =
2406 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2407 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2408 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2409
2410
2411 cmd->port = PORT_TP;
2412 cmd->transceiver = XCVR_INTERNAL;
2413 cmd->phy_address = 0;
2414
2415
2416 spin_lock_irq(&hp->happy_lock);
2417 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2418 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2419 spin_unlock_irq(&hp->happy_lock);
2420
2421 if (hp->sw_bmcr & BMCR_ANENABLE) {
2422 cmd->autoneg = AUTONEG_ENABLE;
2423 cmd->speed =
2424 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2425 SPEED_100 : SPEED_10;
2426 if (cmd->speed == SPEED_100)
2427 cmd->duplex =
2428 (hp->sw_lpa & (LPA_100FULL)) ?
2429 DUPLEX_FULL : DUPLEX_HALF;
2430 else
2431 cmd->duplex =
2432 (hp->sw_lpa & (LPA_10FULL)) ?
2433 DUPLEX_FULL : DUPLEX_HALF;
2434 } else {
2435 cmd->autoneg = AUTONEG_DISABLE;
2436 cmd->speed =
2437 (hp->sw_bmcr & BMCR_SPEED100) ?
2438 SPEED_100 : SPEED_10;
2439 cmd->duplex =
2440 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2441 DUPLEX_FULL : DUPLEX_HALF;
2442 }
2443 return 0;
2444}
2445
2446static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2447{
2448 struct happy_meal *hp = netdev_priv(dev);
2449
2450
2451 if (cmd->autoneg != AUTONEG_ENABLE &&
2452 cmd->autoneg != AUTONEG_DISABLE)
2453 return -EINVAL;
2454 if (cmd->autoneg == AUTONEG_DISABLE &&
2455 ((cmd->speed != SPEED_100 &&
2456 cmd->speed != SPEED_10) ||
2457 (cmd->duplex != DUPLEX_HALF &&
2458 cmd->duplex != DUPLEX_FULL)))
2459 return -EINVAL;
2460
2461
2462 spin_lock_irq(&hp->happy_lock);
2463 del_timer(&hp->happy_timer);
2464 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2465 spin_unlock_irq(&hp->happy_lock);
2466
2467 return 0;
2468}
2469
2470static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2471{
2472 struct happy_meal *hp = netdev_priv(dev);
2473
2474 strcpy(info->driver, "sunhme");
2475 strcpy(info->version, "2.02");
2476 if (hp->happy_flags & HFLAG_PCI) {
2477 struct pci_dev *pdev = hp->happy_dev;
2478 strcpy(info->bus_info, pci_name(pdev));
2479 }
2480#ifdef CONFIG_SBUS
2481 else {
2482 const struct linux_prom_registers *regs;
2483 struct of_device *op = hp->happy_dev;
2484 regs = of_get_property(op->node, "regs", NULL);
2485 if (regs)
2486 sprintf(info->bus_info, "SBUS:%d",
2487 regs->which_io);
2488 }
2489#endif
2490}
2491
2492static u32 hme_get_link(struct net_device *dev)
2493{
2494 struct happy_meal *hp = netdev_priv(dev);
2495
2496 spin_lock_irq(&hp->happy_lock);
2497 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2498 spin_unlock_irq(&hp->happy_lock);
2499
2500 return (hp->sw_bmsr & BMSR_LSTATUS);
2501}
2502
2503static const struct ethtool_ops hme_ethtool_ops = {
2504 .get_settings = hme_get_settings,
2505 .set_settings = hme_set_settings,
2506 .get_drvinfo = hme_get_drvinfo,
2507 .get_link = hme_get_link,
2508};
2509
2510static int hme_version_printed;
2511
2512#ifdef CONFIG_SBUS
2513
2514
2515
2516
2517
2518static struct quattro * __devinit quattro_sbus_find(struct of_device *child)
2519{
2520 struct device *parent = child->dev.parent;
2521 struct of_device *op;
2522 struct quattro *qp;
2523
2524 op = to_of_device(parent);
2525 qp = dev_get_drvdata(&op->dev);
2526 if (qp)
2527 return qp;
2528
2529 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2530 if (qp != NULL) {
2531 int i;
2532
2533 for (i = 0; i < 4; i++)
2534 qp->happy_meals[i] = NULL;
2535
2536 qp->quattro_dev = child;
2537 qp->next = qfe_sbus_list;
2538 qfe_sbus_list = qp;
2539
2540 dev_set_drvdata(&op->dev, qp);
2541 }
2542 return qp;
2543}
2544
2545
2546
2547
2548
2549static int __init quattro_sbus_register_irqs(void)
2550{
2551 struct quattro *qp;
2552
2553 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2554 struct of_device *op = qp->quattro_dev;
2555 int err, qfe_slot, skip = 0;
2556
2557 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++) {
2558 if (!qp->happy_meals[qfe_slot])
2559 skip = 1;
2560 }
2561 if (skip)
2562 continue;
2563
2564 err = request_irq(op->irqs[0],
2565 quattro_sbus_interrupt,
2566 IRQF_SHARED, "Quattro",
2567 qp);
2568 if (err != 0) {
2569 printk(KERN_ERR "Quattro HME: IRQ registration "
2570 "error %d.\n", err);
2571 return err;
2572 }
2573 }
2574
2575 return 0;
2576}
2577
2578static void quattro_sbus_free_irqs(void)
2579{
2580 struct quattro *qp;
2581
2582 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2583 struct of_device *op = qp->quattro_dev;
2584 int qfe_slot, skip = 0;
2585
2586 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++) {
2587 if (!qp->happy_meals[qfe_slot])
2588 skip = 1;
2589 }
2590 if (skip)
2591 continue;
2592
2593 free_irq(op->irqs[0], qp);
2594 }
2595}
2596#endif
2597
2598#ifdef CONFIG_PCI
2599static struct quattro * __devinit quattro_pci_find(struct pci_dev *pdev)
2600{
2601 struct pci_dev *bdev = pdev->bus->self;
2602 struct quattro *qp;
2603
2604 if (!bdev) return NULL;
2605 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2606 struct pci_dev *qpdev = qp->quattro_dev;
2607
2608 if (qpdev == bdev)
2609 return qp;
2610 }
2611 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2612 if (qp != NULL) {
2613 int i;
2614
2615 for (i = 0; i < 4; i++)
2616 qp->happy_meals[i] = NULL;
2617
2618 qp->quattro_dev = bdev;
2619 qp->next = qfe_pci_list;
2620 qfe_pci_list = qp;
2621
2622
2623 qp->nranges = 0;
2624 }
2625 return qp;
2626}
2627#endif
2628
2629static const struct net_device_ops hme_netdev_ops = {
2630 .ndo_open = happy_meal_open,
2631 .ndo_stop = happy_meal_close,
2632 .ndo_start_xmit = happy_meal_start_xmit,
2633 .ndo_tx_timeout = happy_meal_tx_timeout,
2634 .ndo_get_stats = happy_meal_get_stats,
2635 .ndo_set_multicast_list = happy_meal_set_multicast,
2636 .ndo_change_mtu = eth_change_mtu,
2637 .ndo_set_mac_address = eth_mac_addr,
2638 .ndo_validate_addr = eth_validate_addr,
2639};
2640
2641#ifdef CONFIG_SBUS
2642static int __devinit happy_meal_sbus_probe_one(struct of_device *op, int is_qfe)
2643{
2644 struct device_node *dp = op->node, *sbus_dp;
2645 struct quattro *qp = NULL;
2646 struct happy_meal *hp;
2647 struct net_device *dev;
2648 int i, qfe_slot = -1;
2649 int err = -ENODEV;
2650
2651 sbus_dp = to_of_device(op->dev.parent)->node;
2652
2653
2654 if (strcmp(sbus_dp->name, "sbus"))
2655 return err;
2656
2657 if (is_qfe) {
2658 qp = quattro_sbus_find(op);
2659 if (qp == NULL)
2660 goto err_out;
2661 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2662 if (qp->happy_meals[qfe_slot] == NULL)
2663 break;
2664 if (qfe_slot == 4)
2665 goto err_out;
2666 }
2667
2668 err = -ENOMEM;
2669 dev = alloc_etherdev(sizeof(struct happy_meal));
2670 if (!dev)
2671 goto err_out;
2672 SET_NETDEV_DEV(dev, &op->dev);
2673
2674 if (hme_version_printed++ == 0)
2675 printk(KERN_INFO "%s", version);
2676
2677
2678
2679
2680 for (i = 0; i < 6; i++) {
2681 if (macaddr[i] != 0)
2682 break;
2683 }
2684 if (i < 6) {
2685 for (i = 0; i < 6; i++)
2686 dev->dev_addr[i] = macaddr[i];
2687 macaddr[5]++;
2688 } else {
2689 const unsigned char *addr;
2690 int len;
2691
2692 addr = of_get_property(dp, "local-mac-address", &len);
2693
2694 if (qfe_slot != -1 && addr && len == 6)
2695 memcpy(dev->dev_addr, addr, 6);
2696 else
2697 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2698 }
2699
2700 hp = netdev_priv(dev);
2701
2702 hp->happy_dev = op;
2703 hp->dma_dev = &op->dev;
2704
2705 spin_lock_init(&hp->happy_lock);
2706
2707 err = -ENODEV;
2708 if (qp != NULL) {
2709 hp->qfe_parent = qp;
2710 hp->qfe_ent = qfe_slot;
2711 qp->happy_meals[qfe_slot] = dev;
2712 }
2713
2714 hp->gregs = of_ioremap(&op->resource[0], 0,
2715 GREG_REG_SIZE, "HME Global Regs");
2716 if (!hp->gregs) {
2717 printk(KERN_ERR "happymeal: Cannot map global registers.\n");
2718 goto err_out_free_netdev;
2719 }
2720
2721 hp->etxregs = of_ioremap(&op->resource[1], 0,
2722 ETX_REG_SIZE, "HME TX Regs");
2723 if (!hp->etxregs) {
2724 printk(KERN_ERR "happymeal: Cannot map MAC TX registers.\n");
2725 goto err_out_iounmap;
2726 }
2727
2728 hp->erxregs = of_ioremap(&op->resource[2], 0,
2729 ERX_REG_SIZE, "HME RX Regs");
2730 if (!hp->erxregs) {
2731 printk(KERN_ERR "happymeal: Cannot map MAC RX registers.\n");
2732 goto err_out_iounmap;
2733 }
2734
2735 hp->bigmacregs = of_ioremap(&op->resource[3], 0,
2736 BMAC_REG_SIZE, "HME BIGMAC Regs");
2737 if (!hp->bigmacregs) {
2738 printk(KERN_ERR "happymeal: Cannot map BIGMAC registers.\n");
2739 goto err_out_iounmap;
2740 }
2741
2742 hp->tcvregs = of_ioremap(&op->resource[4], 0,
2743 TCVR_REG_SIZE, "HME Tranceiver Regs");
2744 if (!hp->tcvregs) {
2745 printk(KERN_ERR "happymeal: Cannot map TCVR registers.\n");
2746 goto err_out_iounmap;
2747 }
2748
2749 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
2750 if (hp->hm_revision == 0xff)
2751 hp->hm_revision = 0xa0;
2752
2753
2754 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2755 hp->happy_flags = HFLAG_20_21;
2756 else if (hp->hm_revision != 0xa0)
2757 hp->happy_flags = HFLAG_NOT_A0;
2758
2759 if (qp != NULL)
2760 hp->happy_flags |= HFLAG_QUATTRO;
2761
2762
2763 hp->happy_bursts = of_getintprop_default(sbus_dp,
2764 "burst-sizes", 0x00);
2765
2766 hp->happy_block = dma_alloc_coherent(hp->dma_dev,
2767 PAGE_SIZE,
2768 &hp->hblock_dvma,
2769 GFP_ATOMIC);
2770 err = -ENOMEM;
2771 if (!hp->happy_block) {
2772 printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
2773 goto err_out_iounmap;
2774 }
2775
2776
2777 hp->linkcheck = 0;
2778
2779
2780 hp->timer_state = asleep;
2781 hp->timer_ticks = 0;
2782
2783 init_timer(&hp->happy_timer);
2784
2785 hp->dev = dev;
2786 dev->netdev_ops = &hme_netdev_ops;
2787 dev->watchdog_timeo = 5*HZ;
2788 dev->ethtool_ops = &hme_ethtool_ops;
2789
2790
2791 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
2792
2793 dev->irq = op->irqs[0];
2794
2795#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2796
2797 hp->read_desc32 = sbus_hme_read_desc32;
2798 hp->write_txd = sbus_hme_write_txd;
2799 hp->write_rxd = sbus_hme_write_rxd;
2800 hp->read32 = sbus_hme_read32;
2801 hp->write32 = sbus_hme_write32;
2802#endif
2803
2804
2805
2806
2807 spin_lock_irq(&hp->happy_lock);
2808 happy_meal_set_initial_advertisement(hp);
2809 spin_unlock_irq(&hp->happy_lock);
2810
2811 if (register_netdev(hp->dev)) {
2812 printk(KERN_ERR "happymeal: Cannot register net device, "
2813 "aborting.\n");
2814 goto err_out_free_coherent;
2815 }
2816
2817 dev_set_drvdata(&op->dev, hp);
2818
2819 if (qfe_slot != -1)
2820 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2821 dev->name, qfe_slot);
2822 else
2823 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2824 dev->name);
2825
2826 printk("%pM\n", dev->dev_addr);
2827
2828 return 0;
2829
2830err_out_free_coherent:
2831 dma_free_coherent(hp->dma_dev,
2832 PAGE_SIZE,
2833 hp->happy_block,
2834 hp->hblock_dvma);
2835
2836err_out_iounmap:
2837 if (hp->gregs)
2838 of_iounmap(&op->resource[0], hp->gregs, GREG_REG_SIZE);
2839 if (hp->etxregs)
2840 of_iounmap(&op->resource[1], hp->etxregs, ETX_REG_SIZE);
2841 if (hp->erxregs)
2842 of_iounmap(&op->resource[2], hp->erxregs, ERX_REG_SIZE);
2843 if (hp->bigmacregs)
2844 of_iounmap(&op->resource[3], hp->bigmacregs, BMAC_REG_SIZE);
2845 if (hp->tcvregs)
2846 of_iounmap(&op->resource[4], hp->tcvregs, TCVR_REG_SIZE);
2847
2848 if (qp)
2849 qp->happy_meals[qfe_slot] = NULL;
2850
2851err_out_free_netdev:
2852 free_netdev(dev);
2853
2854err_out:
2855 return err;
2856}
2857#endif
2858
2859#ifdef CONFIG_PCI
2860#ifndef CONFIG_SPARC
2861static int is_quattro_p(struct pci_dev *pdev)
2862{
2863 struct pci_dev *busdev = pdev->bus->self;
2864 struct list_head *tmp;
2865 int n_hmes;
2866
2867 if (busdev == NULL ||
2868 busdev->vendor != PCI_VENDOR_ID_DEC ||
2869 busdev->device != PCI_DEVICE_ID_DEC_21153)
2870 return 0;
2871
2872 n_hmes = 0;
2873 tmp = pdev->bus->devices.next;
2874 while (tmp != &pdev->bus->devices) {
2875 struct pci_dev *this_pdev = pci_dev_b(tmp);
2876
2877 if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
2878 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
2879 n_hmes++;
2880
2881 tmp = tmp->next;
2882 }
2883
2884 if (n_hmes != 4)
2885 return 0;
2886
2887 return 1;
2888}
2889
2890
2891static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
2892{
2893 int this_offset;
2894
2895 for (this_offset = 0x20; this_offset < len; this_offset++) {
2896 void __iomem *p = rom_base + this_offset;
2897
2898 if (readb(p + 0) != 0x90 ||
2899 readb(p + 1) != 0x00 ||
2900 readb(p + 2) != 0x09 ||
2901 readb(p + 3) != 0x4e ||
2902 readb(p + 4) != 0x41 ||
2903 readb(p + 5) != 0x06)
2904 continue;
2905
2906 this_offset += 6;
2907 p += 6;
2908
2909 if (index == 0) {
2910 int i;
2911
2912 for (i = 0; i < 6; i++)
2913 dev_addr[i] = readb(p + i);
2914 return 1;
2915 }
2916 index--;
2917 }
2918 return 0;
2919}
2920
2921static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
2922{
2923 size_t size;
2924 void __iomem *p = pci_map_rom(pdev, &size);
2925
2926 if (p) {
2927 int index = 0;
2928 int found;
2929
2930 if (is_quattro_p(pdev))
2931 index = PCI_SLOT(pdev->devfn);
2932
2933 found = readb(p) == 0x55 &&
2934 readb(p + 1) == 0xaa &&
2935 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
2936 pci_unmap_rom(pdev, p);
2937 if (found)
2938 return;
2939 }
2940
2941
2942 dev_addr[0] = 0x08;
2943 dev_addr[1] = 0x00;
2944 dev_addr[2] = 0x20;
2945 get_random_bytes(&dev_addr[3], 3);
2946 return;
2947}
2948#endif
2949
2950static int __devinit happy_meal_pci_probe(struct pci_dev *pdev,
2951 const struct pci_device_id *ent)
2952{
2953 struct quattro *qp = NULL;
2954#ifdef CONFIG_SPARC
2955 struct device_node *dp;
2956#endif
2957 struct happy_meal *hp;
2958 struct net_device *dev;
2959 void __iomem *hpreg_base;
2960 unsigned long hpreg_res;
2961 int i, qfe_slot = -1;
2962 char prom_name[64];
2963 int err;
2964
2965
2966#ifdef CONFIG_SPARC
2967 dp = pci_device_to_OF_node(pdev);
2968 strcpy(prom_name, dp->name);
2969#else
2970 if (is_quattro_p(pdev))
2971 strcpy(prom_name, "SUNW,qfe");
2972 else
2973 strcpy(prom_name, "SUNW,hme");
2974#endif
2975
2976 err = -ENODEV;
2977
2978 if (pci_enable_device(pdev))
2979 goto err_out;
2980 pci_set_master(pdev);
2981
2982 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
2983 qp = quattro_pci_find(pdev);
2984 if (qp == NULL)
2985 goto err_out;
2986 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2987 if (qp->happy_meals[qfe_slot] == NULL)
2988 break;
2989 if (qfe_slot == 4)
2990 goto err_out;
2991 }
2992
2993 dev = alloc_etherdev(sizeof(struct happy_meal));
2994 err = -ENOMEM;
2995 if (!dev)
2996 goto err_out;
2997 SET_NETDEV_DEV(dev, &pdev->dev);
2998
2999 if (hme_version_printed++ == 0)
3000 printk(KERN_INFO "%s", version);
3001
3002 dev->base_addr = (long) pdev;
3003
3004 hp = netdev_priv(dev);
3005 memset(hp, 0, sizeof(*hp));
3006
3007 hp->happy_dev = pdev;
3008 hp->dma_dev = &pdev->dev;
3009
3010 spin_lock_init(&hp->happy_lock);
3011
3012 if (qp != NULL) {
3013 hp->qfe_parent = qp;
3014 hp->qfe_ent = qfe_slot;
3015 qp->happy_meals[qfe_slot] = dev;
3016 }
3017
3018 hpreg_res = pci_resource_start(pdev, 0);
3019 err = -ENODEV;
3020 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3021 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
3022 goto err_out_clear_quattro;
3023 }
3024 if (pci_request_regions(pdev, DRV_NAME)) {
3025 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
3026 "aborting.\n");
3027 goto err_out_clear_quattro;
3028 }
3029
3030 if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == NULL) {
3031 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
3032 goto err_out_free_res;
3033 }
3034
3035 for (i = 0; i < 6; i++) {
3036 if (macaddr[i] != 0)
3037 break;
3038 }
3039 if (i < 6) {
3040 for (i = 0; i < 6; i++)
3041 dev->dev_addr[i] = macaddr[i];
3042 macaddr[5]++;
3043 } else {
3044#ifdef CONFIG_SPARC
3045 const unsigned char *addr;
3046 int len;
3047
3048 if (qfe_slot != -1 &&
3049 (addr = of_get_property(dp,
3050 "local-mac-address", &len)) != NULL
3051 && len == 6) {
3052 memcpy(dev->dev_addr, addr, 6);
3053 } else {
3054 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
3055 }
3056#else
3057 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
3058#endif
3059 }
3060
3061
3062 hp->gregs = (hpreg_base + 0x0000UL);
3063 hp->etxregs = (hpreg_base + 0x2000UL);
3064 hp->erxregs = (hpreg_base + 0x4000UL);
3065 hp->bigmacregs = (hpreg_base + 0x6000UL);
3066 hp->tcvregs = (hpreg_base + 0x7000UL);
3067
3068#ifdef CONFIG_SPARC
3069 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
3070 if (hp->hm_revision == 0xff)
3071 hp->hm_revision = 0xc0 | (pdev->revision & 0x0f);
3072#else
3073
3074 hp->hm_revision = 0x20;
3075#endif
3076
3077
3078 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3079 hp->happy_flags = HFLAG_20_21;
3080 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3081 hp->happy_flags = HFLAG_NOT_A0;
3082
3083 if (qp != NULL)
3084 hp->happy_flags |= HFLAG_QUATTRO;
3085
3086
3087 hp->happy_flags |= HFLAG_PCI;
3088
3089#ifdef CONFIG_SPARC
3090
3091 hp->happy_bursts = DMA_BURSTBITS;
3092#endif
3093
3094 hp->happy_block = (struct hmeal_init_block *)
3095 dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &hp->hblock_dvma, GFP_KERNEL);
3096
3097 err = -ENODEV;
3098 if (!hp->happy_block) {
3099 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
3100 goto err_out_iounmap;
3101 }
3102
3103 hp->linkcheck = 0;
3104 hp->timer_state = asleep;
3105 hp->timer_ticks = 0;
3106
3107 init_timer(&hp->happy_timer);
3108
3109 hp->dev = dev;
3110 dev->netdev_ops = &hme_netdev_ops;
3111 dev->watchdog_timeo = 5*HZ;
3112 dev->ethtool_ops = &hme_ethtool_ops;
3113 dev->irq = pdev->irq;
3114 dev->dma = 0;
3115
3116
3117 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
3118
3119#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3120
3121 hp->read_desc32 = pci_hme_read_desc32;
3122 hp->write_txd = pci_hme_write_txd;
3123 hp->write_rxd = pci_hme_write_rxd;
3124 hp->read32 = pci_hme_read32;
3125 hp->write32 = pci_hme_write32;
3126#endif
3127
3128
3129
3130
3131 spin_lock_irq(&hp->happy_lock);
3132 happy_meal_set_initial_advertisement(hp);
3133 spin_unlock_irq(&hp->happy_lock);
3134
3135 if (register_netdev(hp->dev)) {
3136 printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
3137 "aborting.\n");
3138 goto err_out_iounmap;
3139 }
3140
3141 dev_set_drvdata(&pdev->dev, hp);
3142
3143 if (!qfe_slot) {
3144 struct pci_dev *qpdev = qp->quattro_dev;
3145
3146 prom_name[0] = 0;
3147 if (!strncmp(dev->name, "eth", 3)) {
3148 int i = simple_strtoul(dev->name + 3, NULL, 10);
3149 sprintf(prom_name, "-%d", i + 3);
3150 }
3151 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
3152 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
3153 qpdev->device == PCI_DEVICE_ID_DEC_21153)
3154 printk("DEC 21153 PCI Bridge\n");
3155 else
3156 printk("unknown bridge %04x.%04x\n",
3157 qpdev->vendor, qpdev->device);
3158 }
3159
3160 if (qfe_slot != -1)
3161 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
3162 dev->name, qfe_slot);
3163 else
3164 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
3165 dev->name);
3166
3167 printk("%pM\n", dev->dev_addr);
3168
3169 return 0;
3170
3171err_out_iounmap:
3172 iounmap(hp->gregs);
3173
3174err_out_free_res:
3175 pci_release_regions(pdev);
3176
3177err_out_clear_quattro:
3178 if (qp != NULL)
3179 qp->happy_meals[qfe_slot] = NULL;
3180
3181 free_netdev(dev);
3182
3183err_out:
3184 return err;
3185}
3186
3187static void __devexit happy_meal_pci_remove(struct pci_dev *pdev)
3188{
3189 struct happy_meal *hp = dev_get_drvdata(&pdev->dev);
3190 struct net_device *net_dev = hp->dev;
3191
3192 unregister_netdev(net_dev);
3193
3194 dma_free_coherent(hp->dma_dev, PAGE_SIZE,
3195 hp->happy_block, hp->hblock_dvma);
3196 iounmap(hp->gregs);
3197 pci_release_regions(hp->happy_dev);
3198
3199 free_netdev(net_dev);
3200
3201 dev_set_drvdata(&pdev->dev, NULL);
3202}
3203
3204static struct pci_device_id happymeal_pci_ids[] = {
3205 { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) },
3206 { }
3207};
3208
3209MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
3210
3211static struct pci_driver hme_pci_driver = {
3212 .name = "hme",
3213 .id_table = happymeal_pci_ids,
3214 .probe = happy_meal_pci_probe,
3215 .remove = __devexit_p(happy_meal_pci_remove),
3216};
3217
3218static int __init happy_meal_pci_init(void)
3219{
3220 return pci_register_driver(&hme_pci_driver);
3221}
3222
3223static void happy_meal_pci_exit(void)
3224{
3225 pci_unregister_driver(&hme_pci_driver);
3226
3227 while (qfe_pci_list) {
3228 struct quattro *qfe = qfe_pci_list;
3229 struct quattro *next = qfe->next;
3230
3231 kfree(qfe);
3232
3233 qfe_pci_list = next;
3234 }
3235}
3236
3237#endif
3238
3239#ifdef CONFIG_SBUS
3240static int __devinit hme_sbus_probe(struct of_device *op, const struct of_device_id *match)
3241{
3242 struct device_node *dp = op->node;
3243 const char *model = of_get_property(dp, "model", NULL);
3244 int is_qfe = (match->data != NULL);
3245
3246 if (!is_qfe && model && !strcmp(model, "SUNW,sbus-qfe"))
3247 is_qfe = 1;
3248
3249 return happy_meal_sbus_probe_one(op, is_qfe);
3250}
3251
3252static int __devexit hme_sbus_remove(struct of_device *op)
3253{
3254 struct happy_meal *hp = dev_get_drvdata(&op->dev);
3255 struct net_device *net_dev = hp->dev;
3256
3257 unregister_netdev(net_dev);
3258
3259
3260
3261 of_iounmap(&op->resource[0], hp->gregs, GREG_REG_SIZE);
3262 of_iounmap(&op->resource[1], hp->etxregs, ETX_REG_SIZE);
3263 of_iounmap(&op->resource[2], hp->erxregs, ERX_REG_SIZE);
3264 of_iounmap(&op->resource[3], hp->bigmacregs, BMAC_REG_SIZE);
3265 of_iounmap(&op->resource[4], hp->tcvregs, TCVR_REG_SIZE);
3266 dma_free_coherent(hp->dma_dev,
3267 PAGE_SIZE,
3268 hp->happy_block,
3269 hp->hblock_dvma);
3270
3271 free_netdev(net_dev);
3272
3273 dev_set_drvdata(&op->dev, NULL);
3274
3275 return 0;
3276}
3277
3278static const struct of_device_id hme_sbus_match[] = {
3279 {
3280 .name = "SUNW,hme",
3281 },
3282 {
3283 .name = "SUNW,qfe",
3284 .data = (void *) 1,
3285 },
3286 {
3287 .name = "qfe",
3288 .data = (void *) 1,
3289 },
3290 {},
3291};
3292
3293MODULE_DEVICE_TABLE(of, hme_sbus_match);
3294
3295static struct of_platform_driver hme_sbus_driver = {
3296 .name = "hme",
3297 .match_table = hme_sbus_match,
3298 .probe = hme_sbus_probe,
3299 .remove = __devexit_p(hme_sbus_remove),
3300};
3301
3302static int __init happy_meal_sbus_init(void)
3303{
3304 int err;
3305
3306 err = of_register_driver(&hme_sbus_driver, &of_bus_type);
3307 if (!err)
3308 err = quattro_sbus_register_irqs();
3309
3310 return err;
3311}
3312
3313static void happy_meal_sbus_exit(void)
3314{
3315 of_unregister_driver(&hme_sbus_driver);
3316 quattro_sbus_free_irqs();
3317
3318 while (qfe_sbus_list) {
3319 struct quattro *qfe = qfe_sbus_list;
3320 struct quattro *next = qfe->next;
3321
3322 kfree(qfe);
3323
3324 qfe_sbus_list = next;
3325 }
3326}
3327#endif
3328
3329static int __init happy_meal_probe(void)
3330{
3331 int err = 0;
3332
3333#ifdef CONFIG_SBUS
3334 err = happy_meal_sbus_init();
3335#endif
3336#ifdef CONFIG_PCI
3337 if (!err) {
3338 err = happy_meal_pci_init();
3339#ifdef CONFIG_SBUS
3340 if (err)
3341 happy_meal_sbus_exit();
3342#endif
3343 }
3344#endif
3345
3346 return err;
3347}
3348
3349
3350static void __exit happy_meal_exit(void)
3351{
3352#ifdef CONFIG_SBUS
3353 happy_meal_sbus_exit();
3354#endif
3355#ifdef CONFIG_PCI
3356 happy_meal_pci_exit();
3357#endif
3358}
3359
3360module_init(happy_meal_probe);
3361module_exit(happy_meal_exit);
3362