linux/drivers/ide/it821x.c
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   1/*
   2 * Copyright (C) 2004           Red Hat
   3 * Copyright (C) 2007           Bartlomiej Zolnierkiewicz
   4 *
   5 *  May be copied or modified under the terms of the GNU General Public License
   6 *  Based in part on the ITE vendor provided SCSI driver.
   7 *
   8 *  Documentation:
   9 *      Datasheet is freely available, some other documents under NDA.
  10 *
  11 *  The ITE8212 isn't exactly a standard IDE controller. It has two
  12 *  modes. In pass through mode then it is an IDE controller. In its smart
  13 *  mode its actually quite a capable hardware raid controller disguised
  14 *  as an IDE controller. Smart mode only understands DMA read/write and
  15 *  identify, none of the fancier commands apply. The IT8211 is identical
  16 *  in other respects but lacks the raid mode.
  17 *
  18 *  Errata:
  19 *  o   Rev 0x10 also requires master/slave hold the same DMA timings and
  20 *      cannot do ATAPI MWDMA.
  21 *  o   The identify data for raid volumes lacks CHS info (technically ok)
  22 *      but also fails to set the LBA28 and other bits. We fix these in
  23 *      the IDE probe quirk code.
  24 *  o   If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
  25 *      raid then the controller firmware dies
  26 *  o   Smart mode without RAID doesn't clear all the necessary identify
  27 *      bits to reduce the command set to the one used
  28 *
  29 *  This has a few impacts on the driver
  30 *  - In pass through mode we do all the work you would expect
  31 *  - In smart mode the clocking set up is done by the controller generally
  32 *    but we must watch the other limits and filter.
  33 *  - There are a few extra vendor commands that actually talk to the
  34 *    controller but only work PIO with no IRQ.
  35 *
  36 *  Vendor areas of the identify block in smart mode are used for the
  37 *  timing and policy set up. Each HDD in raid mode also has a serial
  38 *  block on the disk. The hardware extra commands are get/set chip status,
  39 *  rebuild, get rebuild status.
  40 *
  41 *  In Linux the driver supports pass through mode as if the device was
  42 *  just another IDE controller. If the smart mode is running then
  43 *  volumes are managed by the controller firmware and each IDE "disk"
  44 *  is a raid volume. Even more cute - the controller can do automated
  45 *  hotplug and rebuild.
  46 *
  47 *  The pass through controller itself is a little demented. It has a
  48 *  flaw that it has a single set of PIO/MWDMA timings per channel so
  49 *  non UDMA devices restrict each others performance. It also has a
  50 *  single clock source per channel so mixed UDMA100/133 performance
  51 *  isn't perfect and we have to pick a clock. Thankfully none of this
  52 *  matters in smart mode. ATAPI DMA is not currently supported.
  53 *
  54 *  It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
  55 *
  56 *  TODO
  57 *      -       ATAPI UDMA is ok but not MWDMA it seems
  58 *      -       RAID configuration ioctls
  59 *      -       Move to libata once it grows up
  60 */
  61
  62#include <linux/types.h>
  63#include <linux/module.h>
  64#include <linux/pci.h>
  65#include <linux/ide.h>
  66#include <linux/init.h>
  67
  68#define DRV_NAME "it821x"
  69
  70#define QUIRK_VORTEX86 1
  71
  72struct it821x_dev
  73{
  74        unsigned int smart:1,           /* Are we in smart raid mode */
  75                timing10:1;             /* Rev 0x10 */
  76        u8      clock_mode;             /* 0, ATA_50 or ATA_66 */
  77        u8      want[2][2];             /* Mode/Pri log for master slave */
  78        /* We need these for switching the clock when DMA goes on/off
  79           The high byte is the 66Mhz timing */
  80        u16     pio[2];                 /* Cached PIO values */
  81        u16     mwdma[2];               /* Cached MWDMA values */
  82        u16     udma[2];                /* Cached UDMA values (per drive) */
  83        u16     quirks;
  84};
  85
  86#define ATA_66          0
  87#define ATA_50          1
  88#define ATA_ANY         2
  89
  90#define UDMA_OFF        0
  91#define MWDMA_OFF       0
  92
  93/*
  94 *      We allow users to force the card into non raid mode without
  95 *      flashing the alternative BIOS. This is also necessary right now
  96 *      for embedded platforms that cannot run a PC BIOS but are using this
  97 *      device.
  98 */
  99
 100static int it8212_noraid;
 101
 102/**
 103 *      it821x_program  -       program the PIO/MWDMA registers
 104 *      @drive: drive to tune
 105 *      @timing: timing info
 106 *
 107 *      Program the PIO/MWDMA timing for this channel according to the
 108 *      current clock.
 109 */
 110
 111static void it821x_program(ide_drive_t *drive, u16 timing)
 112{
 113        ide_hwif_t *hwif = drive->hwif;
 114        struct pci_dev *dev = to_pci_dev(hwif->dev);
 115        struct it821x_dev *itdev = ide_get_hwifdata(hwif);
 116        int channel = hwif->channel;
 117        u8 conf;
 118
 119        /* Program PIO/MWDMA timing bits */
 120        if(itdev->clock_mode == ATA_66)
 121                conf = timing >> 8;
 122        else
 123                conf = timing & 0xFF;
 124
 125        pci_write_config_byte(dev, 0x54 + 4 * channel, conf);
 126}
 127
 128/**
 129 *      it821x_program_udma     -       program the UDMA registers
 130 *      @drive: drive to tune
 131 *      @timing: timing info
 132 *
 133 *      Program the UDMA timing for this drive according to the
 134 *      current clock.
 135 */
 136
 137static void it821x_program_udma(ide_drive_t *drive, u16 timing)
 138{
 139        ide_hwif_t *hwif = drive->hwif;
 140        struct pci_dev *dev = to_pci_dev(hwif->dev);
 141        struct it821x_dev *itdev = ide_get_hwifdata(hwif);
 142        int channel = hwif->channel;
 143        u8 unit = drive->dn & 1, conf;
 144
 145        /* Program UDMA timing bits */
 146        if(itdev->clock_mode == ATA_66)
 147                conf = timing >> 8;
 148        else
 149                conf = timing & 0xFF;
 150
 151        if (itdev->timing10 == 0)
 152                pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf);
 153        else {
 154                pci_write_config_byte(dev, 0x56 + 4 * channel, conf);
 155                pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf);
 156        }
 157}
 158
 159/**
 160 *      it821x_clock_strategy
 161 *      @drive: drive to set up
 162 *
 163 *      Select between the 50 and 66Mhz base clocks to get the best
 164 *      results for this interface.
 165 */
 166
 167static void it821x_clock_strategy(ide_drive_t *drive)
 168{
 169        ide_hwif_t *hwif = drive->hwif;
 170        struct pci_dev *dev = to_pci_dev(hwif->dev);
 171        struct it821x_dev *itdev = ide_get_hwifdata(hwif);
 172        ide_drive_t *pair = ide_get_pair_dev(drive);
 173        int clock, altclock, sel = 0;
 174        u8 unit = drive->dn & 1, v;
 175
 176        if(itdev->want[0][0] > itdev->want[1][0]) {
 177                clock = itdev->want[0][1];
 178                altclock = itdev->want[1][1];
 179        } else {
 180                clock = itdev->want[1][1];
 181                altclock = itdev->want[0][1];
 182        }
 183
 184        /*
 185         * if both clocks can be used for the mode with the higher priority
 186         * use the clock needed by the mode with the lower priority
 187         */
 188        if (clock == ATA_ANY)
 189                clock = altclock;
 190
 191        /* Nobody cares - keep the same clock */
 192        if(clock == ATA_ANY)
 193                return;
 194        /* No change */
 195        if(clock == itdev->clock_mode)
 196                return;
 197
 198        /* Load this into the controller ? */
 199        if(clock == ATA_66)
 200                itdev->clock_mode = ATA_66;
 201        else {
 202                itdev->clock_mode = ATA_50;
 203                sel = 1;
 204        }
 205
 206        pci_read_config_byte(dev, 0x50, &v);
 207        v &= ~(1 << (1 + hwif->channel));
 208        v |= sel << (1 + hwif->channel);
 209        pci_write_config_byte(dev, 0x50, v);
 210
 211        /*
 212         *      Reprogram the UDMA/PIO of the pair drive for the switch
 213         *      MWDMA will be dealt with by the dma switcher
 214         */
 215        if(pair && itdev->udma[1-unit] != UDMA_OFF) {
 216                it821x_program_udma(pair, itdev->udma[1-unit]);
 217                it821x_program(pair, itdev->pio[1-unit]);
 218        }
 219        /*
 220         *      Reprogram the UDMA/PIO of our drive for the switch.
 221         *      MWDMA will be dealt with by the dma switcher
 222         */
 223        if(itdev->udma[unit] != UDMA_OFF) {
 224                it821x_program_udma(drive, itdev->udma[unit]);
 225                it821x_program(drive, itdev->pio[unit]);
 226        }
 227}
 228
 229/**
 230 *      it821x_set_pio_mode     -       set host controller for PIO mode
 231 *      @drive: drive
 232 *      @pio: PIO mode number
 233 *
 234 *      Tune the host to the desired PIO mode taking into the consideration
 235 *      the maximum PIO mode supported by the other device on the cable.
 236 */
 237
 238static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio)
 239{
 240        ide_hwif_t *hwif = drive->hwif;
 241        struct it821x_dev *itdev = ide_get_hwifdata(hwif);
 242        ide_drive_t *pair = ide_get_pair_dev(drive);
 243        u8 unit = drive->dn & 1, set_pio = pio;
 244
 245        /* Spec says 89 ref driver uses 88 */
 246        static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
 247        static u8 pio_want[]    = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
 248
 249        /*
 250         * Compute the best PIO mode we can for a given device. We must
 251         * pick a speed that does not cause problems with the other device
 252         * on the cable.
 253         */
 254        if (pair) {
 255                u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
 256                /* trim PIO to the slowest of the master/slave */
 257                if (pair_pio < set_pio)
 258                        set_pio = pair_pio;
 259        }
 260
 261        /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
 262        itdev->want[unit][1] = pio_want[set_pio];
 263        itdev->want[unit][0] = 1;       /* PIO is lowest priority */
 264        itdev->pio[unit] = pio_timings[set_pio];
 265        it821x_clock_strategy(drive);
 266        it821x_program(drive, itdev->pio[unit]);
 267}
 268
 269/**
 270 *      it821x_tune_mwdma       -       tune a channel for MWDMA
 271 *      @drive: drive to set up
 272 *      @mode_wanted: the target operating mode
 273 *
 274 *      Load the timing settings for this device mode into the
 275 *      controller when doing MWDMA in pass through mode. The caller
 276 *      must manage the whole lack of per device MWDMA/PIO timings and
 277 *      the shared MWDMA/PIO timing register.
 278 */
 279
 280static void it821x_tune_mwdma(ide_drive_t *drive, u8 mode_wanted)
 281{
 282        ide_hwif_t *hwif = drive->hwif;
 283        struct pci_dev *dev = to_pci_dev(hwif->dev);
 284        struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif);
 285        u8 unit = drive->dn & 1, channel = hwif->channel, conf;
 286
 287        static u16 dma[]        = { 0x8866, 0x3222, 0x3121 };
 288        static u8 mwdma_want[]  = { ATA_ANY, ATA_66, ATA_ANY };
 289
 290        itdev->want[unit][1] = mwdma_want[mode_wanted];
 291        itdev->want[unit][0] = 2;       /* MWDMA is low priority */
 292        itdev->mwdma[unit] = dma[mode_wanted];
 293        itdev->udma[unit] = UDMA_OFF;
 294
 295        /* UDMA bits off - Revision 0x10 do them in pairs */
 296        pci_read_config_byte(dev, 0x50, &conf);
 297        if (itdev->timing10)
 298                conf |= channel ? 0x60: 0x18;
 299        else
 300                conf |= 1 << (3 + 2 * channel + unit);
 301        pci_write_config_byte(dev, 0x50, conf);
 302
 303        it821x_clock_strategy(drive);
 304        /* FIXME: do we need to program this ? */
 305        /* it821x_program(drive, itdev->mwdma[unit]); */
 306}
 307
 308/**
 309 *      it821x_tune_udma        -       tune a channel for UDMA
 310 *      @drive: drive to set up
 311 *      @mode_wanted: the target operating mode
 312 *
 313 *      Load the timing settings for this device mode into the
 314 *      controller when doing UDMA modes in pass through.
 315 */
 316
 317static void it821x_tune_udma(ide_drive_t *drive, u8 mode_wanted)
 318{
 319        ide_hwif_t *hwif = drive->hwif;
 320        struct pci_dev *dev = to_pci_dev(hwif->dev);
 321        struct it821x_dev *itdev = ide_get_hwifdata(hwif);
 322        u8 unit = drive->dn & 1, channel = hwif->channel, conf;
 323
 324        static u16 udma[]       = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
 325        static u8 udma_want[]   = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
 326
 327        itdev->want[unit][1] = udma_want[mode_wanted];
 328        itdev->want[unit][0] = 3;       /* UDMA is high priority */
 329        itdev->mwdma[unit] = MWDMA_OFF;
 330        itdev->udma[unit] = udma[mode_wanted];
 331        if(mode_wanted >= 5)
 332                itdev->udma[unit] |= 0x8080;    /* UDMA 5/6 select on */
 333
 334        /* UDMA on. Again revision 0x10 must do the pair */
 335        pci_read_config_byte(dev, 0x50, &conf);
 336        if (itdev->timing10)
 337                conf &= channel ? 0x9F: 0xE7;
 338        else
 339                conf &= ~ (1 << (3 + 2 * channel + unit));
 340        pci_write_config_byte(dev, 0x50, conf);
 341
 342        it821x_clock_strategy(drive);
 343        it821x_program_udma(drive, itdev->udma[unit]);
 344
 345}
 346
 347/**
 348 *      it821x_dma_read -       DMA hook
 349 *      @drive: drive for DMA
 350 *
 351 *      The IT821x has a single timing register for MWDMA and for PIO
 352 *      operations. As we flip back and forth we have to reload the
 353 *      clock. In addition the rev 0x10 device only works if the same
 354 *      timing value is loaded into the master and slave UDMA clock
 355 *      so we must also reload that.
 356 *
 357 *      FIXME: we could figure out in advance if we need to do reloads
 358 */
 359
 360static void it821x_dma_start(ide_drive_t *drive)
 361{
 362        ide_hwif_t *hwif = drive->hwif;
 363        struct it821x_dev *itdev = ide_get_hwifdata(hwif);
 364        u8 unit = drive->dn & 1;
 365
 366        if(itdev->mwdma[unit] != MWDMA_OFF)
 367                it821x_program(drive, itdev->mwdma[unit]);
 368        else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
 369                it821x_program_udma(drive, itdev->udma[unit]);
 370        ide_dma_start(drive);
 371}
 372
 373/**
 374 *      it821x_dma_write        -       DMA hook
 375 *      @drive: drive for DMA stop
 376 *
 377 *      The IT821x has a single timing register for MWDMA and for PIO
 378 *      operations. As we flip back and forth we have to reload the
 379 *      clock.
 380 */
 381
 382static int it821x_dma_end(ide_drive_t *drive)
 383{
 384        ide_hwif_t *hwif = drive->hwif;
 385        struct it821x_dev *itdev = ide_get_hwifdata(hwif);
 386        int ret = ide_dma_end(drive);
 387        u8 unit = drive->dn & 1;
 388
 389        if(itdev->mwdma[unit] != MWDMA_OFF)
 390                it821x_program(drive, itdev->pio[unit]);
 391        return ret;
 392}
 393
 394/**
 395 *      it821x_set_dma_mode     -       set host controller for DMA mode
 396 *      @drive: drive
 397 *      @speed: DMA mode
 398 *
 399 *      Tune the ITE chipset for the desired DMA mode.
 400 */
 401
 402static void it821x_set_dma_mode(ide_drive_t *drive, const u8 speed)
 403{
 404        /*
 405         * MWDMA tuning is really hard because our MWDMA and PIO
 406         * timings are kept in the same place.  We can switch in the
 407         * host dma on/off callbacks.
 408         */
 409        if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6)
 410                it821x_tune_udma(drive, speed - XFER_UDMA_0);
 411        else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
 412                it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0);
 413}
 414
 415/**
 416 *      it821x_cable_detect     -       cable detection
 417 *      @hwif: interface to check
 418 *
 419 *      Check for the presence of an ATA66 capable cable on the
 420 *      interface. Problematic as it seems some cards don't have
 421 *      the needed logic onboard.
 422 */
 423
 424static u8 it821x_cable_detect(ide_hwif_t *hwif)
 425{
 426        /* The reference driver also only does disk side */
 427        return ATA_CBL_PATA80;
 428}
 429
 430/**
 431 *      it821x_quirkproc        -       post init callback
 432 *      @drive: drive
 433 *
 434 *      This callback is run after the drive has been probed but
 435 *      before anything gets attached. It allows drivers to do any
 436 *      final tuning that is needed, or fixups to work around bugs.
 437 */
 438
 439static void it821x_quirkproc(ide_drive_t *drive)
 440{
 441        struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif);
 442        u16 *id = drive->id;
 443
 444        if (!itdev->smart) {
 445                /*
 446                 *      If we are in pass through mode then not much
 447                 *      needs to be done, but we do bother to clear the
 448                 *      IRQ mask as we may well be in PIO (eg rev 0x10)
 449                 *      for now and we know unmasking is safe on this chipset.
 450                 */
 451                drive->dev_flags |= IDE_DFLAG_UNMASK;
 452        } else {
 453        /*
 454         *      Perform fixups on smart mode. We need to "lose" some
 455         *      capabilities the firmware lacks but does not filter, and
 456         *      also patch up some capability bits that it forgets to set
 457         *      in RAID mode.
 458         */
 459
 460                /* Check for RAID v native */
 461                if (strstr((char *)&id[ATA_ID_PROD],
 462                           "Integrated Technology Express")) {
 463                        /* In raid mode the ident block is slightly buggy
 464                           We need to set the bits so that the IDE layer knows
 465                           LBA28. LBA48 and DMA ar valid */
 466                        id[ATA_ID_CAPABILITY]    |= (3 << 8); /* LBA28, DMA */
 467                        id[ATA_ID_COMMAND_SET_2] |= 0x0400;   /* LBA48 valid */
 468                        id[ATA_ID_CFS_ENABLE_2]  |= 0x0400;   /* LBA48 on */
 469                        /* Reporting logic */
 470                        printk(KERN_INFO "%s: IT8212 %sRAID %d volume",
 471                                drive->name, id[147] ? "Bootable " : "",
 472                                id[ATA_ID_CSFO]);
 473                        if (id[ATA_ID_CSFO] != 1)
 474                                printk(KERN_CONT "(%dK stripe)", id[146]);
 475                        printk(KERN_CONT ".\n");
 476                } else {
 477                        /* Non RAID volume. Fixups to stop the core code
 478                           doing unsupported things */
 479                        id[ATA_ID_FIELD_VALID]   &= 3;
 480                        id[ATA_ID_QUEUE_DEPTH]    = 0;
 481                        id[ATA_ID_COMMAND_SET_1]  = 0;
 482                        id[ATA_ID_COMMAND_SET_2] &= 0xC400;
 483                        id[ATA_ID_CFSSE]         &= 0xC000;
 484                        id[ATA_ID_CFS_ENABLE_1]   = 0;
 485                        id[ATA_ID_CFS_ENABLE_2]  &= 0xC400;
 486                        id[ATA_ID_CSF_DEFAULT]   &= 0xC000;
 487                        id[127]                   = 0;
 488                        id[ATA_ID_DLF]            = 0;
 489                        id[ATA_ID_CSFO]           = 0;
 490                        id[ATA_ID_CFA_POWER]      = 0;
 491                        printk(KERN_INFO "%s: Performing identify fixups.\n",
 492                                drive->name);
 493                }
 494
 495                /*
 496                 * Set MWDMA0 mode as enabled/support - just to tell
 497                 * IDE core that DMA is supported (it821x hardware
 498                 * takes care of DMA mode programming).
 499                 */
 500                if (ata_id_has_dma(id)) {
 501                        id[ATA_ID_MWDMA_MODES] |= 0x0101;
 502                        drive->current_speed = XFER_MW_DMA_0;
 503                }
 504        }
 505
 506}
 507
 508static struct ide_dma_ops it821x_pass_through_dma_ops = {
 509        .dma_host_set           = ide_dma_host_set,
 510        .dma_setup              = ide_dma_setup,
 511        .dma_exec_cmd           = ide_dma_exec_cmd,
 512        .dma_start              = it821x_dma_start,
 513        .dma_end                = it821x_dma_end,
 514        .dma_test_irq           = ide_dma_test_irq,
 515        .dma_timeout            = ide_dma_timeout,
 516        .dma_lost_irq           = ide_dma_lost_irq,
 517        .dma_sff_read_status    = ide_dma_sff_read_status,
 518};
 519
 520/**
 521 *      init_hwif_it821x        -       set up hwif structs
 522 *      @hwif: interface to set up
 523 *
 524 *      We do the basic set up of the interface structure. The IT8212
 525 *      requires several custom handlers so we override the default
 526 *      ide DMA handlers appropriately
 527 */
 528
 529static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
 530{
 531        struct pci_dev *dev = to_pci_dev(hwif->dev);
 532        struct ide_host *host = pci_get_drvdata(dev);
 533        struct it821x_dev *itdevs = host->host_priv;
 534        struct it821x_dev *idev = itdevs + hwif->channel;
 535        u8 conf;
 536
 537        ide_set_hwifdata(hwif, idev);
 538
 539        pci_read_config_byte(dev, 0x50, &conf);
 540        if (conf & 1) {
 541                idev->smart = 1;
 542                hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
 543                /* Long I/O's although allowed in LBA48 space cause the
 544                   onboard firmware to enter the twighlight zone */
 545                hwif->rqsize = 256;
 546        }
 547
 548        /* Pull the current clocks from 0x50 also */
 549        if (conf & (1 << (1 + hwif->channel)))
 550                idev->clock_mode = ATA_50;
 551        else
 552                idev->clock_mode = ATA_66;
 553
 554        idev->want[0][1] = ATA_ANY;
 555        idev->want[1][1] = ATA_ANY;
 556
 557        /*
 558         *      Not in the docs but according to the reference driver
 559         *      this is necessary.
 560         */
 561
 562        if (dev->revision == 0x10) {
 563                idev->timing10 = 1;
 564                hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
 565                if (idev->smart == 0)
 566                        printk(KERN_WARNING DRV_NAME " %s: revision 0x10, "
 567                                "workarounds activated\n", pci_name(dev));
 568        }
 569
 570        if (idev->smart == 0) {
 571                /* MWDMA/PIO clock switching for pass through mode */
 572                hwif->dma_ops = &it821x_pass_through_dma_ops;
 573        } else
 574                hwif->host_flags |= IDE_HFLAG_NO_SET_MODE;
 575
 576        if (hwif->dma_base == 0)
 577                return;
 578
 579        hwif->ultra_mask = ATA_UDMA6;
 580        hwif->mwdma_mask = ATA_MWDMA2;
 581
 582        /* Vortex86SX quirk: prevent Ultra-DMA mode to fix BadCRC issue */
 583        if (idev->quirks & QUIRK_VORTEX86) {
 584                if (dev->revision == 0x11)
 585                        hwif->ultra_mask = 0;
 586        }
 587}
 588
 589static void it8212_disable_raid(struct pci_dev *dev)
 590{
 591        /* Reset local CPU, and set BIOS not ready */
 592        pci_write_config_byte(dev, 0x5E, 0x01);
 593
 594        /* Set to bypass mode, and reset PCI bus */
 595        pci_write_config_byte(dev, 0x50, 0x00);
 596        pci_write_config_word(dev, PCI_COMMAND,
 597                              PCI_COMMAND_PARITY | PCI_COMMAND_IO |
 598                              PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 599        pci_write_config_word(dev, 0x40, 0xA0F3);
 600
 601        pci_write_config_dword(dev,0x4C, 0x02040204);
 602        pci_write_config_byte(dev, 0x42, 0x36);
 603        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
 604}
 605
 606static unsigned int init_chipset_it821x(struct pci_dev *dev)
 607{
 608        u8 conf;
 609        static char *mode[2] = { "pass through", "smart" };
 610
 611        /* Force the card into bypass mode if so requested */
 612        if (it8212_noraid) {
 613                printk(KERN_INFO DRV_NAME " %s: forcing bypass mode\n",
 614                        pci_name(dev));
 615                it8212_disable_raid(dev);
 616        }
 617        pci_read_config_byte(dev, 0x50, &conf);
 618        printk(KERN_INFO DRV_NAME " %s: controller in %s mode\n",
 619                pci_name(dev), mode[conf & 1]);
 620        return 0;
 621}
 622
 623static const struct ide_port_ops it821x_port_ops = {
 624        /* it821x_set_{pio,dma}_mode() are only used in pass-through mode */
 625        .set_pio_mode           = it821x_set_pio_mode,
 626        .set_dma_mode           = it821x_set_dma_mode,
 627        .quirkproc              = it821x_quirkproc,
 628        .cable_detect           = it821x_cable_detect,
 629};
 630
 631static const struct ide_port_info it821x_chipset __devinitdata = {
 632        .name           = DRV_NAME,
 633        .init_chipset   = init_chipset_it821x,
 634        .init_hwif      = init_hwif_it821x,
 635        .port_ops       = &it821x_port_ops,
 636        .pio_mask       = ATA_PIO4,
 637};
 638
 639/**
 640 *      it821x_init_one -       pci layer discovery entry
 641 *      @dev: PCI device
 642 *      @id: ident table entry
 643 *
 644 *      Called by the PCI code when it finds an ITE821x controller.
 645 *      We then use the IDE PCI generic helper to do most of the work.
 646 */
 647
 648static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 649{
 650        struct it821x_dev *itdevs;
 651        int rc;
 652
 653        itdevs = kzalloc(2 * sizeof(*itdevs), GFP_KERNEL);
 654        if (itdevs == NULL) {
 655                printk(KERN_ERR DRV_NAME " %s: out of memory\n", pci_name(dev));
 656                return -ENOMEM;
 657        }
 658
 659        itdevs->quirks = id->driver_data;
 660
 661        rc = ide_pci_init_one(dev, &it821x_chipset, itdevs);
 662        if (rc)
 663                kfree(itdevs);
 664
 665        return rc;
 666}
 667
 668static void __devexit it821x_remove(struct pci_dev *dev)
 669{
 670        struct ide_host *host = pci_get_drvdata(dev);
 671        struct it821x_dev *itdevs = host->host_priv;
 672
 673        ide_pci_remove(dev);
 674        kfree(itdevs);
 675}
 676
 677static const struct pci_device_id it821x_pci_tbl[] = {
 678        { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 },
 679        { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 },
 680        { PCI_VDEVICE(RDC, PCI_DEVICE_ID_RDC_D1010), QUIRK_VORTEX86 },
 681        { 0, },
 682};
 683
 684MODULE_DEVICE_TABLE(pci, it821x_pci_tbl);
 685
 686static struct pci_driver it821x_pci_driver = {
 687        .name           = "ITE821x IDE",
 688        .id_table       = it821x_pci_tbl,
 689        .probe          = it821x_init_one,
 690        .remove         = __devexit_p(it821x_remove),
 691        .suspend        = ide_pci_suspend,
 692        .resume         = ide_pci_resume,
 693};
 694
 695static int __init it821x_ide_init(void)
 696{
 697        return ide_pci_register_driver(&it821x_pci_driver);
 698}
 699
 700static void __exit it821x_ide_exit(void)
 701{
 702        pci_unregister_driver(&it821x_pci_driver);
 703}
 704
 705module_init(it821x_ide_init);
 706module_exit(it821x_ide_exit);
 707
 708module_param_named(noraid, it8212_noraid, int, S_IRUGO);
 709MODULE_PARM_DESC(noraid, "Force card into bypass mode");
 710
 711MODULE_AUTHOR("Alan Cox");
 712MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
 713MODULE_LICENSE("GPL");
 714
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