LXR linux/arch/x86/include/asm/apic.h

   1#ifndef _ASM_X86_APIC_H
   2#define _ASM_X86_APIC_H
   3
   4#include <linux/pm.h>
   5#include <linux/delay.h>
   6
   7#include <asm/alternative.h>
   8#include <asm/fixmap.h>
   9#include <asm/apicdef.h>
  10#include <asm/processor.h>
  11#include <asm/system.h>
  12#include <asm/cpufeature.h>
  13#include <asm/msr.h>
  14
  15#define ARCH_APICTIMER_STOPS_ON_C3      1
  16
  17/*
  18 * Debugging macros
  19 */
  20#define APIC_QUIET   0
  21#define APIC_VERBOSE 1
  22#define APIC_DEBUG   2
  23
  24/*
  25 * Define the default level of output to be very little
  26 * This can be turned up by using apic=verbose for more
  27 * information and apic=debug for _lots_ of information.
  28 * apic_verbosity is defined in apic.c
  29 */
  30#define apic_printk(v, s, a...) do {       \
  31                if ((v) <= apic_verbosity) \
  32                        printk(s, ##a);    \
  33        } while (0)
  34
  35
  36extern void generic_apic_probe(void);
  37
  38#ifdef CONFIG_X86_LOCAL_APIC
  39
  40extern unsigned int apic_verbosity;
  41extern int local_apic_timer_c2_ok;
  42
  43extern int disable_apic;
  44/*
  45 * Basic functions accessing APICs.
  46 */
  47#ifdef CONFIG_PARAVIRT
  48#include <asm/paravirt.h>
  49#else
  50#define setup_boot_clock setup_boot_APIC_clock
  51#define setup_secondary_clock setup_secondary_APIC_clock
  52#endif
  53
  54extern int is_vsmp_box(void);
  55extern void xapic_wait_icr_idle(void);
  56extern u32 safe_xapic_wait_icr_idle(void);
  57extern void xapic_icr_write(u32, u32);
  58extern int setup_profiling_timer(unsigned int);
  59
  60static inline void native_apic_mem_write(u32 reg, u32 v)
  61{
  62        volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
  63
  64        alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
  65                       ASM_OUTPUT2("=r" (v), "=m" (*addr)),
  66                       ASM_OUTPUT2("0" (v), "m" (*addr)));
  67}
  68
  69static inline u32 native_apic_mem_read(u32 reg)
  70{
  71        return *((volatile u32 *)(APIC_BASE + reg));
  72}
  73
  74static inline void native_apic_msr_write(u32 reg, u32 v)
  75{
  76        if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
  77            reg == APIC_LVR)
  78                return;
  79
  80        wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
  81}
  82
  83static inline u32 native_apic_msr_read(u32 reg)
  84{
  85        u32 low, high;
  86
  87        if (reg == APIC_DFR)
  88                return -1;
  89
  90        rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
  91        return low;
  92}
  93
  94#ifndef CONFIG_X86_32
  95extern int x2apic;
  96extern void check_x2apic(void);
  97extern void enable_x2apic(void);
  98extern void enable_IR_x2apic(void);
  99extern void x2apic_icr_write(u32 low, u32 id);
 100static inline int x2apic_enabled(void)
 101{
 102        int msr, msr2;
 103
 104        if (!cpu_has_x2apic)
 105                return 0;
 106
 107        rdmsr(MSR_IA32_APICBASE, msr, msr2);
 108        if (msr & X2APIC_ENABLE)
 109                return 1;
 110        return 0;
 111}
 112#else
 113#define x2apic_enabled()        0
 114#endif
 115
 116struct apic_ops {
 117        u32 (*read)(u32 reg);
 118        void (*write)(u32 reg, u32 v);
 119        u64 (*icr_read)(void);
 120        void (*icr_write)(u32 low, u32 high);
 121        void (*wait_icr_idle)(void);
 122        u32 (*safe_wait_icr_idle)(void);
 123};
 124
 125extern struct apic_ops *apic_ops;
 126
 127#define apic_read (apic_ops->read)
 128#define apic_write (apic_ops->write)
 129#define apic_icr_read (apic_ops->icr_read)
 130#define apic_icr_write (apic_ops->icr_write)
 131#define apic_wait_icr_idle (apic_ops->wait_icr_idle)
 132#define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle)
 133
 134extern int get_physical_broadcast(void);
 135
 136#ifdef CONFIG_X86_64
 137static inline void ack_x2APIC_irq(void)
 138{
 139        /* Docs say use 0 for future compatibility */
 140        native_apic_msr_write(APIC_EOI, 0);
 141}
 142#endif
 143
 144
 145static inline void ack_APIC_irq(void)
 146{
 147        /*
 148         * ack_APIC_irq() actually gets compiled as a single instruction
 149         * ... yummie.
 150         */
 151
 152        /* Docs say use 0 for future compatibility */
 153        apic_write(APIC_EOI, 0);
 154}
 155
 156extern int lapic_get_maxlvt(void);
 157extern void clear_local_APIC(void);
 158extern void connect_bsp_APIC(void);
 159extern void disconnect_bsp_APIC(int virt_wire_setup);
 160extern void disable_local_APIC(void);
 161extern void lapic_shutdown(void);
 162extern int verify_local_APIC(void);
 163extern void cache_APIC_registers(void);
 164extern void sync_Arb_IDs(void);
 165extern void init_bsp_APIC(void);
 166extern void setup_local_APIC(void);
 167extern void end_local_APIC_setup(void);
 168extern void init_apic_mappings(void);
 169extern void setup_boot_APIC_clock(void);
 170extern void setup_secondary_APIC_clock(void);
 171extern int APIC_init_uniprocessor(void);
 172extern void enable_NMI_through_LVT0(void);
 173
 174/*
 175 * On 32bit this is mach-xxx local
 176 */
 177#ifdef CONFIG_X86_64
 178extern void early_init_lapic_mapping(void);
 179extern int apic_is_clustered_box(void);
 180#else
 181static inline int apic_is_clustered_box(void)
 182{
 183        return 0;
 184}
 185#endif
 186
 187extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
 188extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
 189
 190
 191#else /* !CONFIG_X86_LOCAL_APIC */
 192static inline void lapic_shutdown(void) { }
 193#define local_apic_timer_c2_ok          1
 194static inline void init_apic_mappings(void) { }
 195static inline void disable_local_APIC(void) { }
 196
 197#endif /* !CONFIG_X86_LOCAL_APIC */
 198
 199#endif /* _ASM_X86_APIC_H */
 200