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21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/sched.h>
24#include <linux/spinlock.h>
25#include <linux/errno.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/io.h>
29
30#include <asm/system.h>
31#include <mach/hardware.h>
32#include <mach/dma.h>
33
34#include <mach/tc.h>
35
36#undef DEBUG
37
38#ifndef CONFIG_ARCH_OMAP1
39enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
40 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
41};
42
43enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
44#endif
45
46#define OMAP_DMA_ACTIVE 0x01
47#define OMAP_DMA_CCR_EN (1 << 7)
48#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
49
50#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
51
52static int enable_1510_mode;
53
54struct omap_dma_lch {
55 int next_lch;
56 int dev_id;
57 u16 saved_csr;
58 u16 enabled_irqs;
59 const char *dev_name;
60 void (*callback)(int lch, u16 ch_status, void *data);
61 void *data;
62
63#ifndef CONFIG_ARCH_OMAP1
64
65 int prev_linked_ch;
66 int next_linked_ch;
67 int state;
68 int chain_id;
69
70 int status;
71#endif
72 long flags;
73};
74
75struct dma_link_info {
76 int *linked_dmach_q;
77 int no_of_lchs_linked;
78
79 int q_count;
80 int q_tail;
81 int q_head;
82
83 int chain_state;
84 int chain_mode;
85
86};
87
88static struct dma_link_info *dma_linked_lch;
89
90#ifndef CONFIG_ARCH_OMAP1
91
92
93#define OMAP_DMA_CHAIN_QINIT(chain_id) \
94 do { \
95 dma_linked_lch[chain_id].q_head = \
96 dma_linked_lch[chain_id].q_tail = \
97 dma_linked_lch[chain_id].q_count = 0; \
98 } while (0)
99#define OMAP_DMA_CHAIN_QFULL(chain_id) \
100 (dma_linked_lch[chain_id].no_of_lchs_linked == \
101 dma_linked_lch[chain_id].q_count)
102#define OMAP_DMA_CHAIN_QLAST(chain_id) \
103 do { \
104 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
105 dma_linked_lch[chain_id].q_count) \
106 } while (0)
107#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
108 (0 == dma_linked_lch[chain_id].q_count)
109#define __OMAP_DMA_CHAIN_INCQ(end) \
110 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
111#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
112 do { \
113 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
114 dma_linked_lch[chain_id].q_count--; \
115 } while (0)
116
117#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
118 do { \
119 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
120 dma_linked_lch[chain_id].q_count++; \
121 } while (0)
122#endif
123
124static int dma_lch_count;
125static int dma_chan_count;
126
127static spinlock_t dma_chan_lock;
128static struct omap_dma_lch *dma_chan;
129static void __iomem *omap_dma_base;
130
131static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
132 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
133 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
134 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
135 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
136 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
137};
138
139static inline void disable_lnk(int lch);
140static void omap_disable_channel_irq(int lch);
141static inline void omap_enable_channel_irq(int lch);
142
143#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
144 __func__);
145
146#define dma_read(reg) \
147({ \
148 u32 __val; \
149 if (cpu_class_is_omap1()) \
150 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
151 else \
152 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
153 __val; \
154})
155
156#define dma_write(val, reg) \
157({ \
158 if (cpu_class_is_omap1()) \
159 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
160 else \
161 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
162})
163
164#ifdef CONFIG_ARCH_OMAP15XX
165
166int omap_dma_in_1510_mode(void)
167{
168 return enable_1510_mode;
169}
170#else
171#define omap_dma_in_1510_mode() 0
172#endif
173
174#ifdef CONFIG_ARCH_OMAP1
175static inline int get_gdma_dev(int req)
176{
177 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
178 int shift = ((req - 1) % 5) * 6;
179
180 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
181}
182
183static inline void set_gdma_dev(int req, int dev)
184{
185 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
186 int shift = ((req - 1) % 5) * 6;
187 u32 l;
188
189 l = omap_readl(reg);
190 l &= ~(0x3f << shift);
191 l |= (dev - 1) << shift;
192 omap_writel(l, reg);
193}
194#else
195#define set_gdma_dev(req, dev) do {} while (0)
196#endif
197
198
199static void clear_lch_regs(int lch)
200{
201 int i;
202 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
203
204 for (i = 0; i < 0x2c; i += 2)
205 __raw_writew(0, lch_base + i);
206}
207
208void omap_set_dma_priority(int lch, int dst_port, int priority)
209{
210 unsigned long reg;
211 u32 l;
212
213 if (cpu_class_is_omap1()) {
214 switch (dst_port) {
215 case OMAP_DMA_PORT_OCP_T1:
216 reg = OMAP_TC_OCPT1_PRIOR;
217 break;
218 case OMAP_DMA_PORT_OCP_T2:
219 reg = OMAP_TC_OCPT2_PRIOR;
220 break;
221 case OMAP_DMA_PORT_EMIFF:
222 reg = OMAP_TC_EMIFF_PRIOR;
223 break;
224 case OMAP_DMA_PORT_EMIFS:
225 reg = OMAP_TC_EMIFS_PRIOR;
226 break;
227 default:
228 BUG();
229 return;
230 }
231 l = omap_readl(reg);
232 l &= ~(0xf << 8);
233 l |= (priority & 0xf) << 8;
234 omap_writel(l, reg);
235 }
236
237 if (cpu_class_is_omap2()) {
238 u32 ccr;
239
240 ccr = dma_read(CCR(lch));
241 if (priority)
242 ccr |= (1 << 6);
243 else
244 ccr &= ~(1 << 6);
245 dma_write(ccr, CCR(lch));
246 }
247}
248EXPORT_SYMBOL(omap_set_dma_priority);
249
250void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
251 int frame_count, int sync_mode,
252 int dma_trigger, int src_or_dst_synch)
253{
254 u32 l;
255
256 l = dma_read(CSDP(lch));
257 l &= ~0x03;
258 l |= data_type;
259 dma_write(l, CSDP(lch));
260
261 if (cpu_class_is_omap1()) {
262 u16 ccr;
263
264 ccr = dma_read(CCR(lch));
265 ccr &= ~(1 << 5);
266 if (sync_mode == OMAP_DMA_SYNC_FRAME)
267 ccr |= 1 << 5;
268 dma_write(ccr, CCR(lch));
269
270 ccr = dma_read(CCR2(lch));
271 ccr &= ~(1 << 2);
272 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
273 ccr |= 1 << 2;
274 dma_write(ccr, CCR2(lch));
275 }
276
277 if (cpu_class_is_omap2() && dma_trigger) {
278 u32 val;
279
280 val = dma_read(CCR(lch));
281
282
283 val &= ~((3 << 19) | 0x1f);
284 val |= (dma_trigger & ~0x1f) << 14;
285 val |= dma_trigger & 0x1f;
286
287 if (sync_mode & OMAP_DMA_SYNC_FRAME)
288 val |= 1 << 5;
289 else
290 val &= ~(1 << 5);
291
292 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
293 val |= 1 << 18;
294 else
295 val &= ~(1 << 18);
296
297 if (src_or_dst_synch)
298 val |= 1 << 24;
299 else
300 val &= ~(1 << 24);
301
302 dma_write(val, CCR(lch));
303 }
304
305 dma_write(elem_count, CEN(lch));
306 dma_write(frame_count, CFN(lch));
307}
308EXPORT_SYMBOL(omap_set_dma_transfer_params);
309
310void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
311{
312 u16 w;
313
314 BUG_ON(omap_dma_in_1510_mode());
315
316 if (cpu_class_is_omap2()) {
317 REVISIT_24XX();
318 return;
319 }
320
321 w = dma_read(CCR2(lch));
322 w &= ~0x03;
323
324 switch (mode) {
325 case OMAP_DMA_CONSTANT_FILL:
326 w |= 0x01;
327 break;
328 case OMAP_DMA_TRANSPARENT_COPY:
329 w |= 0x02;
330 break;
331 case OMAP_DMA_COLOR_DIS:
332 break;
333 default:
334 BUG();
335 }
336 dma_write(w, CCR2(lch));
337
338 w = dma_read(LCH_CTRL(lch));
339 w &= ~0x0f;
340
341 if (mode) {
342 dma_write((u16)color, COLOR_L(lch));
343 dma_write((u16)(color >> 16), COLOR_U(lch));
344 w |= 1;
345 }
346 dma_write(w, LCH_CTRL(lch));
347}
348EXPORT_SYMBOL(omap_set_dma_color_mode);
349
350void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
351{
352 if (cpu_class_is_omap2()) {
353 u32 csdp;
354
355 csdp = dma_read(CSDP(lch));
356 csdp &= ~(0x3 << 16);
357 csdp |= (mode << 16);
358 dma_write(csdp, CSDP(lch));
359 }
360}
361EXPORT_SYMBOL(omap_set_dma_write_mode);
362
363void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
364{
365 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
366 u32 l;
367
368 l = dma_read(LCH_CTRL(lch));
369 l &= ~0x7;
370 l |= mode;
371 dma_write(l, LCH_CTRL(lch));
372 }
373}
374EXPORT_SYMBOL(omap_set_dma_channel_mode);
375
376
377void omap_set_dma_src_params(int lch, int src_port, int src_amode,
378 unsigned long src_start,
379 int src_ei, int src_fi)
380{
381 u32 l;
382
383 if (cpu_class_is_omap1()) {
384 u16 w;
385
386 w = dma_read(CSDP(lch));
387 w &= ~(0x1f << 2);
388 w |= src_port << 2;
389 dma_write(w, CSDP(lch));
390 }
391
392 l = dma_read(CCR(lch));
393 l &= ~(0x03 << 12);
394 l |= src_amode << 12;
395 dma_write(l, CCR(lch));
396
397 if (cpu_class_is_omap1()) {
398 dma_write(src_start >> 16, CSSA_U(lch));
399 dma_write((u16)src_start, CSSA_L(lch));
400 }
401
402 if (cpu_class_is_omap2())
403 dma_write(src_start, CSSA(lch));
404
405 dma_write(src_ei, CSEI(lch));
406 dma_write(src_fi, CSFI(lch));
407}
408EXPORT_SYMBOL(omap_set_dma_src_params);
409
410void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
411{
412 omap_set_dma_transfer_params(lch, params->data_type,
413 params->elem_count, params->frame_count,
414 params->sync_mode, params->trigger,
415 params->src_or_dst_synch);
416 omap_set_dma_src_params(lch, params->src_port,
417 params->src_amode, params->src_start,
418 params->src_ei, params->src_fi);
419
420 omap_set_dma_dest_params(lch, params->dst_port,
421 params->dst_amode, params->dst_start,
422 params->dst_ei, params->dst_fi);
423 if (params->read_prio || params->write_prio)
424 omap_dma_set_prio_lch(lch, params->read_prio,
425 params->write_prio);
426}
427EXPORT_SYMBOL(omap_set_dma_params);
428
429void omap_set_dma_src_index(int lch, int eidx, int fidx)
430{
431 if (cpu_class_is_omap2())
432 return;
433
434 dma_write(eidx, CSEI(lch));
435 dma_write(fidx, CSFI(lch));
436}
437EXPORT_SYMBOL(omap_set_dma_src_index);
438
439void omap_set_dma_src_data_pack(int lch, int enable)
440{
441 u32 l;
442
443 l = dma_read(CSDP(lch));
444 l &= ~(1 << 6);
445 if (enable)
446 l |= (1 << 6);
447 dma_write(l, CSDP(lch));
448}
449EXPORT_SYMBOL(omap_set_dma_src_data_pack);
450
451void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
452{
453 unsigned int burst = 0;
454 u32 l;
455
456 l = dma_read(CSDP(lch));
457 l &= ~(0x03 << 7);
458
459 switch (burst_mode) {
460 case OMAP_DMA_DATA_BURST_DIS:
461 break;
462 case OMAP_DMA_DATA_BURST_4:
463 if (cpu_class_is_omap2())
464 burst = 0x1;
465 else
466 burst = 0x2;
467 break;
468 case OMAP_DMA_DATA_BURST_8:
469 if (cpu_class_is_omap2()) {
470 burst = 0x2;
471 break;
472 }
473
474
475
476
477 case OMAP_DMA_DATA_BURST_16:
478 if (cpu_class_is_omap2()) {
479 burst = 0x3;
480 break;
481 }
482
483
484
485 default:
486 BUG();
487 }
488
489 l |= (burst << 7);
490 dma_write(l, CSDP(lch));
491}
492EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
493
494
495void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
496 unsigned long dest_start,
497 int dst_ei, int dst_fi)
498{
499 u32 l;
500
501 if (cpu_class_is_omap1()) {
502 l = dma_read(CSDP(lch));
503 l &= ~(0x1f << 9);
504 l |= dest_port << 9;
505 dma_write(l, CSDP(lch));
506 }
507
508 l = dma_read(CCR(lch));
509 l &= ~(0x03 << 14);
510 l |= dest_amode << 14;
511 dma_write(l, CCR(lch));
512
513 if (cpu_class_is_omap1()) {
514 dma_write(dest_start >> 16, CDSA_U(lch));
515 dma_write(dest_start, CDSA_L(lch));
516 }
517
518 if (cpu_class_is_omap2())
519 dma_write(dest_start, CDSA(lch));
520
521 dma_write(dst_ei, CDEI(lch));
522 dma_write(dst_fi, CDFI(lch));
523}
524EXPORT_SYMBOL(omap_set_dma_dest_params);
525
526void omap_set_dma_dest_index(int lch, int eidx, int fidx)
527{
528 if (cpu_class_is_omap2())
529 return;
530
531 dma_write(eidx, CDEI(lch));
532 dma_write(fidx, CDFI(lch));
533}
534EXPORT_SYMBOL(omap_set_dma_dest_index);
535
536void omap_set_dma_dest_data_pack(int lch, int enable)
537{
538 u32 l;
539
540 l = dma_read(CSDP(lch));
541 l &= ~(1 << 13);
542 if (enable)
543 l |= 1 << 13;
544 dma_write(l, CSDP(lch));
545}
546EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
547
548void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
549{
550 unsigned int burst = 0;
551 u32 l;
552
553 l = dma_read(CSDP(lch));
554 l &= ~(0x03 << 14);
555
556 switch (burst_mode) {
557 case OMAP_DMA_DATA_BURST_DIS:
558 break;
559 case OMAP_DMA_DATA_BURST_4:
560 if (cpu_class_is_omap2())
561 burst = 0x1;
562 else
563 burst = 0x2;
564 break;
565 case OMAP_DMA_DATA_BURST_8:
566 if (cpu_class_is_omap2())
567 burst = 0x2;
568 else
569 burst = 0x3;
570 break;
571 case OMAP_DMA_DATA_BURST_16:
572 if (cpu_class_is_omap2()) {
573 burst = 0x3;
574 break;
575 }
576
577
578
579 default:
580 printk(KERN_ERR "Invalid DMA burst mode\n");
581 BUG();
582 return;
583 }
584 l |= (burst << 14);
585 dma_write(l, CSDP(lch));
586}
587EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
588
589static inline void omap_enable_channel_irq(int lch)
590{
591 u32 status;
592
593
594 if (cpu_class_is_omap1())
595 status = dma_read(CSR(lch));
596 else if (cpu_class_is_omap2())
597 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
598
599
600 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
601}
602
603static void omap_disable_channel_irq(int lch)
604{
605 if (cpu_class_is_omap2())
606 dma_write(0, CICR(lch));
607}
608
609void omap_enable_dma_irq(int lch, u16 bits)
610{
611 dma_chan[lch].enabled_irqs |= bits;
612}
613EXPORT_SYMBOL(omap_enable_dma_irq);
614
615void omap_disable_dma_irq(int lch, u16 bits)
616{
617 dma_chan[lch].enabled_irqs &= ~bits;
618}
619EXPORT_SYMBOL(omap_disable_dma_irq);
620
621static inline void enable_lnk(int lch)
622{
623 u32 l;
624
625 l = dma_read(CLNK_CTRL(lch));
626
627 if (cpu_class_is_omap1())
628 l &= ~(1 << 14);
629
630
631 if (dma_chan[lch].next_lch != -1)
632 l = dma_chan[lch].next_lch | (1 << 15);
633
634#ifndef CONFIG_ARCH_OMAP1
635 if (cpu_class_is_omap2())
636 if (dma_chan[lch].next_linked_ch != -1)
637 l = dma_chan[lch].next_linked_ch | (1 << 15);
638#endif
639
640 dma_write(l, CLNK_CTRL(lch));
641}
642
643static inline void disable_lnk(int lch)
644{
645 u32 l;
646
647 l = dma_read(CLNK_CTRL(lch));
648
649
650 if (cpu_class_is_omap1()) {
651 dma_write(0, CICR(lch));
652
653 l |= 1 << 14;
654 }
655
656 if (cpu_class_is_omap2()) {
657 omap_disable_channel_irq(lch);
658
659 l &= ~(1 << 15);
660 }
661
662 dma_write(l, CLNK_CTRL(lch));
663 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
664}
665
666static inline void omap2_enable_irq_lch(int lch)
667{
668 u32 val;
669
670 if (!cpu_class_is_omap2())
671 return;
672
673 val = dma_read(IRQENABLE_L0);
674 val |= 1 << lch;
675 dma_write(val, IRQENABLE_L0);
676}
677
678int omap_request_dma(int dev_id, const char *dev_name,
679 void (*callback)(int lch, u16 ch_status, void *data),
680 void *data, int *dma_ch_out)
681{
682 int ch, free_ch = -1;
683 unsigned long flags;
684 struct omap_dma_lch *chan;
685
686 spin_lock_irqsave(&dma_chan_lock, flags);
687 for (ch = 0; ch < dma_chan_count; ch++) {
688 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
689 free_ch = ch;
690 if (dev_id == 0)
691 break;
692 }
693 }
694 if (free_ch == -1) {
695 spin_unlock_irqrestore(&dma_chan_lock, flags);
696 return -EBUSY;
697 }
698 chan = dma_chan + free_ch;
699 chan->dev_id = dev_id;
700
701 if (cpu_class_is_omap1())
702 clear_lch_regs(free_ch);
703
704 if (cpu_class_is_omap2())
705 omap_clear_dma(free_ch);
706
707 spin_unlock_irqrestore(&dma_chan_lock, flags);
708
709 chan->dev_name = dev_name;
710 chan->callback = callback;
711 chan->data = data;
712 chan->flags = 0;
713
714#ifndef CONFIG_ARCH_OMAP1
715 if (cpu_class_is_omap2()) {
716 chan->chain_id = -1;
717 chan->next_linked_ch = -1;
718 }
719#endif
720
721 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
722
723 if (cpu_class_is_omap1())
724 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
725 else if (cpu_class_is_omap2())
726 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
727 OMAP2_DMA_TRANS_ERR_IRQ;
728
729 if (cpu_is_omap16xx()) {
730
731 if (dev_id != 0) {
732 set_gdma_dev(free_ch + 1, dev_id);
733 dev_id = free_ch + 1;
734 }
735
736
737
738
739 dma_write(dev_id | (1 << 10), CCR(free_ch));
740 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
741 dma_write(dev_id, CCR(free_ch));
742 }
743
744 if (cpu_class_is_omap2()) {
745 omap2_enable_irq_lch(free_ch);
746 omap_enable_channel_irq(free_ch);
747
748 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
749 dma_write(1 << free_ch, IRQSTATUS_L0);
750 }
751
752 *dma_ch_out = free_ch;
753
754 return 0;
755}
756EXPORT_SYMBOL(omap_request_dma);
757
758void omap_free_dma(int lch)
759{
760 unsigned long flags;
761
762 spin_lock_irqsave(&dma_chan_lock, flags);
763 if (dma_chan[lch].dev_id == -1) {
764 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
765 lch);
766 spin_unlock_irqrestore(&dma_chan_lock, flags);
767 return;
768 }
769
770 dma_chan[lch].dev_id = -1;
771 dma_chan[lch].next_lch = -1;
772 dma_chan[lch].callback = NULL;
773 spin_unlock_irqrestore(&dma_chan_lock, flags);
774
775 if (cpu_class_is_omap1()) {
776
777 dma_write(0, CICR(lch));
778
779 dma_write(0, CCR(lch));
780 }
781
782 if (cpu_class_is_omap2()) {
783 u32 val;
784
785 val = dma_read(IRQENABLE_L0);
786 val &= ~(1 << lch);
787 dma_write(val, IRQENABLE_L0);
788
789
790 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
791 dma_write(1 << lch, IRQSTATUS_L0);
792
793
794 dma_write(0, CICR(lch));
795
796
797 dma_write(0, CCR(lch));
798 omap_clear_dma(lch);
799 }
800}
801EXPORT_SYMBOL(omap_free_dma);
802
803
804
805
806
807
808
809
810
811
812
813void
814omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
815{
816 u32 reg;
817
818 if (!cpu_class_is_omap2()) {
819 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
820 return;
821 }
822
823 if (arb_rate == 0)
824 arb_rate = 1;
825
826 reg = (arb_rate & 0xff) << 16;
827 reg |= (0xff & max_fifo_depth);
828
829 dma_write(reg, GCR);
830}
831EXPORT_SYMBOL(omap_dma_set_global_params);
832
833
834
835
836
837
838
839
840
841
842int
843omap_dma_set_prio_lch(int lch, unsigned char read_prio,
844 unsigned char write_prio)
845{
846 u32 l;
847
848 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
849 printk(KERN_ERR "Invalid channel id\n");
850 return -EINVAL;
851 }
852 l = dma_read(CCR(lch));
853 l &= ~((1 << 6) | (1 << 26));
854 if (cpu_is_omap2430() || cpu_is_omap34xx())
855 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
856 else
857 l |= ((read_prio & 0x1) << 6);
858
859 dma_write(l, CCR(lch));
860
861 return 0;
862}
863EXPORT_SYMBOL(omap_dma_set_prio_lch);
864
865
866
867
868
869void omap_clear_dma(int lch)
870{
871 unsigned long flags;
872
873 local_irq_save(flags);
874
875 if (cpu_class_is_omap1()) {
876 u32 l;
877
878 l = dma_read(CCR(lch));
879 l &= ~OMAP_DMA_CCR_EN;
880 dma_write(l, CCR(lch));
881
882
883 l = dma_read(CSR(lch));
884 }
885
886 if (cpu_class_is_omap2()) {
887 int i;
888 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
889 for (i = 0; i < 0x44; i += 4)
890 __raw_writel(0, lch_base + i);
891 }
892
893 local_irq_restore(flags);
894}
895EXPORT_SYMBOL(omap_clear_dma);
896
897void omap_start_dma(int lch)
898{
899 u32 l;
900
901 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
902 int next_lch, cur_lch;
903 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
904
905 dma_chan_link_map[lch] = 1;
906
907 enable_lnk(lch);
908
909 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
910 cur_lch = dma_chan[lch].next_lch;
911 do {
912 next_lch = dma_chan[cur_lch].next_lch;
913
914
915 if (dma_chan_link_map[cur_lch])
916 break;
917
918 dma_chan_link_map[cur_lch] = 1;
919
920 enable_lnk(cur_lch);
921 omap_enable_channel_irq(cur_lch);
922
923 cur_lch = next_lch;
924 } while (next_lch != -1);
925 } else if (cpu_class_is_omap2()) {
926
927 dma_write(lch, CLNK_CTRL(lch));
928 }
929
930 omap_enable_channel_irq(lch);
931
932 l = dma_read(CCR(lch));
933
934
935
936
937
938 if (cpu_is_omap24xx())
939 l |= OMAP_DMA_CCR_EN;
940
941 l |= OMAP_DMA_CCR_EN;
942 dma_write(l, CCR(lch));
943
944 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
945}
946EXPORT_SYMBOL(omap_start_dma);
947
948void omap_stop_dma(int lch)
949{
950 u32 l;
951
952 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
953 int next_lch, cur_lch = lch;
954 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
955
956 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
957 do {
958
959 if (dma_chan_link_map[cur_lch])
960 break;
961
962 dma_chan_link_map[cur_lch] = 1;
963
964 disable_lnk(cur_lch);
965
966 next_lch = dma_chan[cur_lch].next_lch;
967 cur_lch = next_lch;
968 } while (next_lch != -1);
969
970 return;
971 }
972
973
974 if (cpu_class_is_omap1())
975 dma_write(0, CICR(lch));
976
977 l = dma_read(CCR(lch));
978 l &= ~OMAP_DMA_CCR_EN;
979 dma_write(l, CCR(lch));
980
981 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
982}
983EXPORT_SYMBOL(omap_stop_dma);
984
985
986
987
988
989int omap_set_dma_callback(int lch,
990 void (*callback)(int lch, u16 ch_status, void *data),
991 void *data)
992{
993 unsigned long flags;
994
995 if (lch < 0)
996 return -ENODEV;
997
998 spin_lock_irqsave(&dma_chan_lock, flags);
999 if (dma_chan[lch].dev_id == -1) {
1000 printk(KERN_ERR "DMA callback for not set for free channel\n");
1001 spin_unlock_irqrestore(&dma_chan_lock, flags);
1002 return -EINVAL;
1003 }
1004 dma_chan[lch].callback = callback;
1005 dma_chan[lch].data = data;
1006 spin_unlock_irqrestore(&dma_chan_lock, flags);
1007
1008 return 0;
1009}
1010EXPORT_SYMBOL(omap_set_dma_callback);
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020dma_addr_t omap_get_dma_src_pos(int lch)
1021{
1022 dma_addr_t offset = 0;
1023
1024 if (cpu_is_omap15xx())
1025 offset = dma_read(CPC(lch));
1026 else
1027 offset = dma_read(CSAC(lch));
1028
1029
1030
1031
1032
1033 if (!cpu_is_omap15xx() && offset == 0)
1034 offset = dma_read(CSAC(lch));
1035
1036 if (cpu_class_is_omap1())
1037 offset |= (dma_read(CSSA_U(lch)) << 16);
1038
1039 return offset;
1040}
1041EXPORT_SYMBOL(omap_get_dma_src_pos);
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051dma_addr_t omap_get_dma_dst_pos(int lch)
1052{
1053 dma_addr_t offset = 0;
1054
1055 if (cpu_is_omap15xx())
1056 offset = dma_read(CPC(lch));
1057 else
1058 offset = dma_read(CDAC(lch));
1059
1060
1061
1062
1063
1064 if (!cpu_is_omap15xx() && offset == 0)
1065 offset = dma_read(CDAC(lch));
1066
1067 if (cpu_class_is_omap1())
1068 offset |= (dma_read(CDSA_U(lch)) << 16);
1069
1070 return offset;
1071}
1072EXPORT_SYMBOL(omap_get_dma_dst_pos);
1073
1074int omap_get_dma_active_status(int lch)
1075{
1076 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1077}
1078EXPORT_SYMBOL(omap_get_dma_active_status);
1079
1080int omap_dma_running(void)
1081{
1082 int lch;
1083
1084
1085 if (cpu_is_omap16xx())
1086 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1087 return 1;
1088
1089 for (lch = 0; lch < dma_chan_count; lch++)
1090 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1091 return 1;
1092
1093 return 0;
1094}
1095
1096
1097
1098
1099
1100
1101void omap_dma_link_lch(int lch_head, int lch_queue)
1102{
1103 if (omap_dma_in_1510_mode()) {
1104 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1105 BUG();
1106 return;
1107 }
1108
1109 if ((dma_chan[lch_head].dev_id == -1) ||
1110 (dma_chan[lch_queue].dev_id == -1)) {
1111 printk(KERN_ERR "omap_dma: trying to link "
1112 "non requested channels\n");
1113 dump_stack();
1114 }
1115
1116 dma_chan[lch_head].next_lch = lch_queue;
1117}
1118EXPORT_SYMBOL(omap_dma_link_lch);
1119
1120
1121
1122
1123void omap_dma_unlink_lch(int lch_head, int lch_queue)
1124{
1125 if (omap_dma_in_1510_mode()) {
1126 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1127 BUG();
1128 return;
1129 }
1130
1131 if (dma_chan[lch_head].next_lch != lch_queue ||
1132 dma_chan[lch_head].next_lch == -1) {
1133 printk(KERN_ERR "omap_dma: trying to unlink "
1134 "non linked channels\n");
1135 dump_stack();
1136 }
1137
1138 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1139 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1140 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1141 "before unlinking\n");
1142 dump_stack();
1143 }
1144
1145 dma_chan[lch_head].next_lch = -1;
1146}
1147EXPORT_SYMBOL(omap_dma_unlink_lch);
1148
1149
1150
1151#ifndef CONFIG_ARCH_OMAP1
1152
1153static void create_dma_lch_chain(int lch_head, int lch_queue)
1154{
1155 u32 l;
1156
1157
1158 if (dma_chan[lch_head].next_linked_ch == -1) {
1159 dma_chan[lch_head].next_linked_ch = lch_queue;
1160 dma_chan[lch_head].prev_linked_ch = lch_queue;
1161 dma_chan[lch_queue].next_linked_ch = lch_head;
1162 dma_chan[lch_queue].prev_linked_ch = lch_head;
1163 }
1164
1165
1166 else {
1167 dma_chan[lch_queue].next_linked_ch =
1168 dma_chan[lch_head].next_linked_ch;
1169 dma_chan[lch_queue].prev_linked_ch = lch_head;
1170 dma_chan[lch_head].next_linked_ch = lch_queue;
1171 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1172 lch_queue;
1173 }
1174
1175 l = dma_read(CLNK_CTRL(lch_head));
1176 l &= ~(0x1f);
1177 l |= lch_queue;
1178 dma_write(l, CLNK_CTRL(lch_head));
1179
1180 l = dma_read(CLNK_CTRL(lch_queue));
1181 l &= ~(0x1f);
1182 l |= (dma_chan[lch_queue].next_linked_ch);
1183 dma_write(l, CLNK_CTRL(lch_queue));
1184}
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201int omap_request_dma_chain(int dev_id, const char *dev_name,
1202 void (*callback) (int chain_id, u16 ch_status,
1203 void *data),
1204 int *chain_id, int no_of_chans, int chain_mode,
1205 struct omap_dma_channel_params params)
1206{
1207 int *channels;
1208 int i, err;
1209
1210
1211 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1212 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1213 printk(KERN_ERR "Invalid chain mode requested\n");
1214 return -EINVAL;
1215 }
1216
1217 if (unlikely((no_of_chans < 1
1218 || no_of_chans > dma_lch_count))) {
1219 printk(KERN_ERR "Invalid Number of channels requested\n");
1220 return -EINVAL;
1221 }
1222
1223
1224
1225 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1226 if (channels == NULL) {
1227 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1228 return -ENOMEM;
1229 }
1230
1231
1232 for (i = 0; i < no_of_chans; i++) {
1233 err = omap_request_dma(dev_id, dev_name,
1234 callback, NULL, &channels[i]);
1235 if (err < 0) {
1236 int j;
1237 for (j = 0; j < i; j++)
1238 omap_free_dma(channels[j]);
1239 kfree(channels);
1240 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1241 return err;
1242 }
1243 dma_chan[channels[i]].prev_linked_ch = -1;
1244 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1245
1246
1247
1248
1249
1250
1251 omap_set_dma_params(channels[i], ¶ms);
1252 }
1253
1254 *chain_id = channels[0];
1255 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1256 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1257 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1258 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1259
1260 for (i = 0; i < no_of_chans; i++)
1261 dma_chan[channels[i]].chain_id = *chain_id;
1262
1263
1264 OMAP_DMA_CHAIN_QINIT(*chain_id);
1265
1266
1267 if (no_of_chans == 1)
1268 create_dma_lch_chain(channels[0], channels[0]);
1269 else {
1270 for (i = 0; i < (no_of_chans - 1); i++)
1271 create_dma_lch_chain(channels[i], channels[i + 1]);
1272 }
1273
1274 return 0;
1275}
1276EXPORT_SYMBOL(omap_request_dma_chain);
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288int omap_modify_dma_chain_params(int chain_id,
1289 struct omap_dma_channel_params params)
1290{
1291 int *channels;
1292 u32 i;
1293
1294
1295 if (unlikely((chain_id < 0
1296 || chain_id >= dma_lch_count))) {
1297 printk(KERN_ERR "Invalid chain id\n");
1298 return -EINVAL;
1299 }
1300
1301
1302 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1303 printk(KERN_ERR "Chain doesn't exists\n");
1304 return -EINVAL;
1305 }
1306 channels = dma_linked_lch[chain_id].linked_dmach_q;
1307
1308 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1309
1310
1311
1312
1313
1314 omap_set_dma_params(channels[i], ¶ms);
1315 }
1316
1317 return 0;
1318}
1319EXPORT_SYMBOL(omap_modify_dma_chain_params);
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329int omap_free_dma_chain(int chain_id)
1330{
1331 int *channels;
1332 u32 i;
1333
1334
1335 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1336 printk(KERN_ERR "Invalid chain id\n");
1337 return -EINVAL;
1338 }
1339
1340
1341 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1342 printk(KERN_ERR "Chain doesn't exists\n");
1343 return -EINVAL;
1344 }
1345
1346 channels = dma_linked_lch[chain_id].linked_dmach_q;
1347 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1348 dma_chan[channels[i]].next_linked_ch = -1;
1349 dma_chan[channels[i]].prev_linked_ch = -1;
1350 dma_chan[channels[i]].chain_id = -1;
1351 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1352 omap_free_dma(channels[i]);
1353 }
1354
1355 kfree(channels);
1356
1357 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1358 dma_linked_lch[chain_id].chain_mode = -1;
1359 dma_linked_lch[chain_id].chain_state = -1;
1360
1361 return (0);
1362}
1363EXPORT_SYMBOL(omap_free_dma_chain);
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373int omap_dma_chain_status(int chain_id)
1374{
1375
1376 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1377 printk(KERN_ERR "Invalid chain id\n");
1378 return -EINVAL;
1379 }
1380
1381
1382 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1383 printk(KERN_ERR "Chain doesn't exists\n");
1384 return -EINVAL;
1385 }
1386 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1387 dma_linked_lch[chain_id].q_count);
1388
1389 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1390 return OMAP_DMA_CHAIN_INACTIVE;
1391
1392 return OMAP_DMA_CHAIN_ACTIVE;
1393}
1394EXPORT_SYMBOL(omap_dma_chain_status);
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1411 int elem_count, int frame_count, void *callbk_data)
1412{
1413 int *channels;
1414 u32 l, lch;
1415 int start_dma = 0;
1416
1417
1418
1419
1420
1421 if (elem_count < 1) {
1422 printk(KERN_ERR "Invalid buffer size\n");
1423 return -EINVAL;
1424 }
1425
1426
1427 if (unlikely((chain_id < 0
1428 || chain_id >= dma_lch_count))) {
1429 printk(KERN_ERR "Invalid chain id\n");
1430 return -EINVAL;
1431 }
1432
1433
1434 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1435 printk(KERN_ERR "Chain doesn't exist\n");
1436 return -EINVAL;
1437 }
1438
1439
1440 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1441 return -EBUSY;
1442
1443
1444 channels = dma_linked_lch[chain_id].linked_dmach_q;
1445
1446
1447 lch = channels[dma_linked_lch[chain_id].q_tail];
1448
1449
1450 dma_chan[lch].data = callbk_data;
1451
1452
1453 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1454
1455
1456 if (src_start != 0)
1457 dma_write(src_start, CSSA(lch));
1458 if (dest_start != 0)
1459 dma_write(dest_start, CDSA(lch));
1460
1461
1462 dma_write(elem_count, CEN(lch));
1463 dma_write(frame_count, CFN(lch));
1464
1465
1466
1467
1468
1469 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1470
1471
1472
1473
1474
1475 if (dma_linked_lch[chain_id].chain_state ==
1476 DMA_CHAIN_NOTSTARTED) {
1477
1478 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1479 DMA_CH_QUEUED)
1480 enable_lnk(dma_chan[lch].prev_linked_ch);
1481 dma_chan[lch].state = DMA_CH_QUEUED;
1482 }
1483
1484
1485
1486
1487
1488 else {
1489 start_dma = 1;
1490
1491 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1492 DMA_CH_STARTED) {
1493 enable_lnk(dma_chan[lch].prev_linked_ch);
1494 dma_chan[lch].state = DMA_CH_QUEUED;
1495 start_dma = 0;
1496 if (0 == ((1 << 7) & dma_read(
1497 CCR(dma_chan[lch].prev_linked_ch)))) {
1498 disable_lnk(dma_chan[lch].
1499 prev_linked_ch);
1500 pr_debug("\n prev ch is stopped\n");
1501 start_dma = 1;
1502 }
1503 }
1504
1505 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1506 == DMA_CH_QUEUED) {
1507 enable_lnk(dma_chan[lch].prev_linked_ch);
1508 dma_chan[lch].state = DMA_CH_QUEUED;
1509 start_dma = 0;
1510 }
1511 omap_enable_channel_irq(lch);
1512
1513 l = dma_read(CCR(lch));
1514
1515 if ((0 == (l & (1 << 24))))
1516 l &= ~(1 << 25);
1517 else
1518 l |= (1 << 25);
1519 if (start_dma == 1) {
1520 if (0 == (l & (1 << 7))) {
1521 l |= (1 << 7);
1522 dma_chan[lch].state = DMA_CH_STARTED;
1523 pr_debug("starting %d\n", lch);
1524 dma_write(l, CCR(lch));
1525 } else
1526 start_dma = 0;
1527 } else {
1528 if (0 == (l & (1 << 7)))
1529 dma_write(l, CCR(lch));
1530 }
1531 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1532 }
1533 }
1534
1535 return 0;
1536}
1537EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547int omap_start_dma_chain_transfers(int chain_id)
1548{
1549 int *channels;
1550 u32 l, i;
1551
1552 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1553 printk(KERN_ERR "Invalid chain id\n");
1554 return -EINVAL;
1555 }
1556
1557 channels = dma_linked_lch[chain_id].linked_dmach_q;
1558
1559 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1560 printk(KERN_ERR "Chain is already started\n");
1561 return -EBUSY;
1562 }
1563
1564 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1565 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1566 i++) {
1567 enable_lnk(channels[i]);
1568 omap_enable_channel_irq(channels[i]);
1569 }
1570 } else {
1571 omap_enable_channel_irq(channels[0]);
1572 }
1573
1574 l = dma_read(CCR(channels[0]));
1575 l |= (1 << 7);
1576 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1577 dma_chan[channels[0]].state = DMA_CH_STARTED;
1578
1579 if ((0 == (l & (1 << 24))))
1580 l &= ~(1 << 25);
1581 else
1582 l |= (1 << 25);
1583 dma_write(l, CCR(channels[0]));
1584
1585 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1586
1587 return 0;
1588}
1589EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599int omap_stop_dma_chain_transfers(int chain_id)
1600{
1601 int *channels;
1602 u32 l, i;
1603 u32 sys_cf;
1604
1605
1606 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1607 printk(KERN_ERR "Invalid chain id\n");
1608 return -EINVAL;
1609 }
1610
1611
1612 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1613 printk(KERN_ERR "Chain doesn't exists\n");
1614 return -EINVAL;
1615 }
1616 channels = dma_linked_lch[chain_id].linked_dmach_q;
1617
1618
1619
1620
1621
1622 sys_cf = dma_read(OCP_SYSCONFIG);
1623 l = sys_cf;
1624
1625 l &= ~((1 << 12)|(1 << 13));
1626 dma_write(l, OCP_SYSCONFIG);
1627
1628 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1629
1630
1631 l = dma_read(CCR(channels[i]));
1632 l &= ~(1 << 7);
1633 dma_write(l, CCR(channels[i]));
1634
1635
1636 disable_lnk(channels[i]);
1637 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1638
1639 }
1640 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1641
1642
1643 OMAP_DMA_CHAIN_QINIT(chain_id);
1644
1645
1646 dma_write(sys_cf, OCP_SYSCONFIG);
1647
1648 return 0;
1649}
1650EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1665{
1666 int lch;
1667 int *channels;
1668
1669
1670 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1671 printk(KERN_ERR "Invalid chain id\n");
1672 return -EINVAL;
1673 }
1674
1675
1676 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1677 printk(KERN_ERR "Chain doesn't exists\n");
1678 return -EINVAL;
1679 }
1680 if ((!ei) || (!fi))
1681 return -EINVAL;
1682
1683 channels = dma_linked_lch[chain_id].linked_dmach_q;
1684
1685
1686 lch = channels[dma_linked_lch[chain_id].q_head];
1687
1688 *ei = dma_read(CCEN(lch));
1689 *fi = dma_read(CCFN(lch));
1690
1691 return 0;
1692}
1693EXPORT_SYMBOL(omap_get_dma_chain_index);
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704int omap_get_dma_chain_dst_pos(int chain_id)
1705{
1706 int lch;
1707 int *channels;
1708
1709
1710 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1711 printk(KERN_ERR "Invalid chain id\n");
1712 return -EINVAL;
1713 }
1714
1715
1716 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1717 printk(KERN_ERR "Chain doesn't exists\n");
1718 return -EINVAL;
1719 }
1720
1721 channels = dma_linked_lch[chain_id].linked_dmach_q;
1722
1723
1724 lch = channels[dma_linked_lch[chain_id].q_head];
1725
1726 return dma_read(CDAC(lch));
1727}
1728EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738int omap_get_dma_chain_src_pos(int chain_id)
1739{
1740 int lch;
1741 int *channels;
1742
1743
1744 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1745 printk(KERN_ERR "Invalid chain id\n");
1746 return -EINVAL;
1747 }
1748
1749
1750 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1751 printk(KERN_ERR "Chain doesn't exists\n");
1752 return -EINVAL;
1753 }
1754
1755 channels = dma_linked_lch[chain_id].linked_dmach_q;
1756
1757
1758 lch = channels[dma_linked_lch[chain_id].q_head];
1759
1760 return dma_read(CSAC(lch));
1761}
1762EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1763#endif
1764
1765
1766
1767#ifdef CONFIG_ARCH_OMAP1
1768
1769static int omap1_dma_handle_ch(int ch)
1770{
1771 u32 csr;
1772
1773 if (enable_1510_mode && ch >= 6) {
1774 csr = dma_chan[ch].saved_csr;
1775 dma_chan[ch].saved_csr = 0;
1776 } else
1777 csr = dma_read(CSR(ch));
1778 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1779 dma_chan[ch + 6].saved_csr = csr >> 7;
1780 csr &= 0x7f;
1781 }
1782 if ((csr & 0x3f) == 0)
1783 return 0;
1784 if (unlikely(dma_chan[ch].dev_id == -1)) {
1785 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1786 "%d (CSR %04x)\n", ch, csr);
1787 return 0;
1788 }
1789 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1790 printk(KERN_WARNING "DMA timeout with device %d\n",
1791 dma_chan[ch].dev_id);
1792 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1793 printk(KERN_WARNING "DMA synchronization event drop occurred "
1794 "with device %d\n", dma_chan[ch].dev_id);
1795 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1796 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1797 if (likely(dma_chan[ch].callback != NULL))
1798 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1799
1800 return 1;
1801}
1802
1803static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1804{
1805 int ch = ((int) dev_id) - 1;
1806 int handled = 0;
1807
1808 for (;;) {
1809 int handled_now = 0;
1810
1811 handled_now += omap1_dma_handle_ch(ch);
1812 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1813 handled_now += omap1_dma_handle_ch(ch + 6);
1814 if (!handled_now)
1815 break;
1816 handled += handled_now;
1817 }
1818
1819 return handled ? IRQ_HANDLED : IRQ_NONE;
1820}
1821
1822#else
1823#define omap1_dma_irq_handler NULL
1824#endif
1825
1826#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1827
1828static int omap2_dma_handle_ch(int ch)
1829{
1830 u32 status = dma_read(CSR(ch));
1831
1832 if (!status) {
1833 if (printk_ratelimit())
1834 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1835 ch);
1836 dma_write(1 << ch, IRQSTATUS_L0);
1837 return 0;
1838 }
1839 if (unlikely(dma_chan[ch].dev_id == -1)) {
1840 if (printk_ratelimit())
1841 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1842 "channel %d\n", status, ch);
1843 return 0;
1844 }
1845 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1846 printk(KERN_INFO
1847 "DMA synchronization event drop occurred with device "
1848 "%d\n", dma_chan[ch].dev_id);
1849 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1850 printk(KERN_INFO "DMA transaction error with device %d\n",
1851 dma_chan[ch].dev_id);
1852 if (cpu_class_is_omap2()) {
1853
1854
1855
1856
1857 u32 ccr;
1858
1859 ccr = dma_read(CCR(ch));
1860 ccr &= ~OMAP_DMA_CCR_EN;
1861 dma_write(ccr, CCR(ch));
1862 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1863 }
1864 }
1865 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1866 printk(KERN_INFO "DMA secure error with device %d\n",
1867 dma_chan[ch].dev_id);
1868 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1869 printk(KERN_INFO "DMA misaligned error with device %d\n",
1870 dma_chan[ch].dev_id);
1871
1872 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1873 dma_write(1 << ch, IRQSTATUS_L0);
1874
1875
1876 if (dma_chan[ch].chain_id != -1) {
1877 int chain_id = dma_chan[ch].chain_id;
1878 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1879 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1880 dma_chan[dma_chan[ch].next_linked_ch].state =
1881 DMA_CH_STARTED;
1882 if (dma_linked_lch[chain_id].chain_mode ==
1883 OMAP_DMA_DYNAMIC_CHAIN)
1884 disable_lnk(ch);
1885
1886 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1887 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1888
1889 status = dma_read(CSR(ch));
1890 }
1891
1892 dma_write(status, CSR(ch));
1893
1894 if (likely(dma_chan[ch].callback != NULL))
1895 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1896
1897 return 0;
1898}
1899
1900
1901static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1902{
1903 u32 val;
1904 int i;
1905
1906 val = dma_read(IRQSTATUS_L0);
1907 if (val == 0) {
1908 if (printk_ratelimit())
1909 printk(KERN_WARNING "Spurious DMA IRQ\n");
1910 return IRQ_HANDLED;
1911 }
1912 for (i = 0; i < dma_lch_count && val != 0; i++) {
1913 if (val & 1)
1914 omap2_dma_handle_ch(i);
1915 val >>= 1;
1916 }
1917
1918 return IRQ_HANDLED;
1919}
1920
1921static struct irqaction omap24xx_dma_irq = {
1922 .name = "DMA",
1923 .handler = omap2_dma_irq_handler,
1924 .flags = IRQF_DISABLED
1925};
1926
1927#else
1928static struct irqaction omap24xx_dma_irq;
1929#endif
1930
1931
1932
1933static struct lcd_dma_info {
1934 spinlock_t lock;
1935 int reserved;
1936 void (*callback)(u16 status, void *data);
1937 void *cb_data;
1938
1939 int active;
1940 unsigned long addr, size;
1941 int rotate, data_type, xres, yres;
1942 int vxres;
1943 int mirror;
1944 int xscale, yscale;
1945 int ext_ctrl;
1946 int src_port;
1947 int single_transfer;
1948} lcd_dma;
1949
1950void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1951 int data_type)
1952{
1953 lcd_dma.addr = addr;
1954 lcd_dma.data_type = data_type;
1955 lcd_dma.xres = fb_xres;
1956 lcd_dma.yres = fb_yres;
1957}
1958EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1959
1960void omap_set_lcd_dma_src_port(int port)
1961{
1962 lcd_dma.src_port = port;
1963}
1964
1965void omap_set_lcd_dma_ext_controller(int external)
1966{
1967 lcd_dma.ext_ctrl = external;
1968}
1969EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1970
1971void omap_set_lcd_dma_single_transfer(int single)
1972{
1973 lcd_dma.single_transfer = single;
1974}
1975EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1976
1977void omap_set_lcd_dma_b1_rotation(int rotate)
1978{
1979 if (omap_dma_in_1510_mode()) {
1980 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1981 BUG();
1982 return;
1983 }
1984 lcd_dma.rotate = rotate;
1985}
1986EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1987
1988void omap_set_lcd_dma_b1_mirror(int mirror)
1989{
1990 if (omap_dma_in_1510_mode()) {
1991 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1992 BUG();
1993 }
1994 lcd_dma.mirror = mirror;
1995}
1996EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
1997
1998void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1999{
2000 if (omap_dma_in_1510_mode()) {
2001 printk(KERN_ERR "DMA virtual resulotion is not supported "
2002 "in 1510 mode\n");
2003 BUG();
2004 }
2005 lcd_dma.vxres = vxres;
2006}
2007EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2008
2009void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2010{
2011 if (omap_dma_in_1510_mode()) {
2012 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2013 BUG();
2014 }
2015 lcd_dma.xscale = xscale;
2016 lcd_dma.yscale = yscale;
2017}
2018EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2019
2020static void set_b1_regs(void)
2021{
2022 unsigned long top, bottom;
2023 int es;
2024 u16 w;
2025 unsigned long en, fn;
2026 long ei, fi;
2027 unsigned long vxres;
2028 unsigned int xscale, yscale;
2029
2030 switch (lcd_dma.data_type) {
2031 case OMAP_DMA_DATA_TYPE_S8:
2032 es = 1;
2033 break;
2034 case OMAP_DMA_DATA_TYPE_S16:
2035 es = 2;
2036 break;
2037 case OMAP_DMA_DATA_TYPE_S32:
2038 es = 4;
2039 break;
2040 default:
2041 BUG();
2042 return;
2043 }
2044
2045 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2046 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2047 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2048 BUG_ON(vxres < lcd_dma.xres);
2049
2050#define PIXADDR(x, y) (lcd_dma.addr + \
2051 ((y) * vxres * yscale + (x) * xscale) * es)
2052#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2053
2054 switch (lcd_dma.rotate) {
2055 case 0:
2056 if (!lcd_dma.mirror) {
2057 top = PIXADDR(0, 0);
2058 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2059
2060
2061 if (omap_dma_in_1510_mode() &&
2062 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2063 bottom += 2;
2064 ei = PIXSTEP(0, 0, 1, 0);
2065 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2066 } else {
2067 top = PIXADDR(lcd_dma.xres - 1, 0);
2068 bottom = PIXADDR(0, lcd_dma.yres - 1);
2069 ei = PIXSTEP(1, 0, 0, 0);
2070 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2071 }
2072 en = lcd_dma.xres;
2073 fn = lcd_dma.yres;
2074 break;
2075 case 90:
2076 if (!lcd_dma.mirror) {
2077 top = PIXADDR(0, lcd_dma.yres - 1);
2078 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2079 ei = PIXSTEP(0, 1, 0, 0);
2080 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2081 } else {
2082 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2083 bottom = PIXADDR(0, 0);
2084 ei = PIXSTEP(0, 1, 0, 0);
2085 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2086 }
2087 en = lcd_dma.yres;
2088 fn = lcd_dma.xres;
2089 break;
2090 case 180:
2091 if (!lcd_dma.mirror) {
2092 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2093 bottom = PIXADDR(0, 0);
2094 ei = PIXSTEP(1, 0, 0, 0);
2095 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2096 } else {
2097 top = PIXADDR(0, lcd_dma.yres - 1);
2098 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2099 ei = PIXSTEP(0, 0, 1, 0);
2100 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2101 }
2102 en = lcd_dma.xres;
2103 fn = lcd_dma.yres;
2104 break;
2105 case 270:
2106 if (!lcd_dma.mirror) {
2107 top = PIXADDR(lcd_dma.xres - 1, 0);
2108 bottom = PIXADDR(0, lcd_dma.yres - 1);
2109 ei = PIXSTEP(0, 0, 0, 1);
2110 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2111 } else {
2112 top = PIXADDR(0, 0);
2113 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2114 ei = PIXSTEP(0, 0, 0, 1);
2115 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2116 }
2117 en = lcd_dma.yres;
2118 fn = lcd_dma.xres;
2119 break;
2120 default:
2121 BUG();
2122 return;
2123 }
2124
2125 if (omap_dma_in_1510_mode()) {
2126 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2127 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2128 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2129 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2130
2131 return;
2132 }
2133
2134
2135 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2136 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2137 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2138 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2139
2140 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2141 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2142
2143 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2144 w &= ~0x03;
2145 w |= lcd_dma.data_type;
2146 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2147
2148 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2149
2150 w &= ~(0x03 << 6);
2151 if (lcd_dma.callback != NULL)
2152 w |= 1 << 1;
2153 else
2154 w &= ~(1 << 1);
2155 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2156
2157 if (!(lcd_dma.rotate || lcd_dma.mirror ||
2158 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2159 return;
2160
2161 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2162
2163 w |= (0x03 << 12);
2164 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2165
2166 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2167 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2168 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2169}
2170
2171static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2172{
2173 u16 w;
2174
2175 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2176 if (unlikely(!(w & (1 << 3)))) {
2177 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2178 return IRQ_NONE;
2179 }
2180
2181 w |= (1 << 3);
2182 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2183 lcd_dma.active = 0;
2184 if (lcd_dma.callback != NULL)
2185 lcd_dma.callback(w, lcd_dma.cb_data);
2186
2187 return IRQ_HANDLED;
2188}
2189
2190int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2191 void *data)
2192{
2193 spin_lock_irq(&lcd_dma.lock);
2194 if (lcd_dma.reserved) {
2195 spin_unlock_irq(&lcd_dma.lock);
2196 printk(KERN_ERR "LCD DMA channel already reserved\n");
2197 BUG();
2198 return -EBUSY;
2199 }
2200 lcd_dma.reserved = 1;
2201 spin_unlock_irq(&lcd_dma.lock);
2202 lcd_dma.callback = callback;
2203 lcd_dma.cb_data = data;
2204 lcd_dma.active = 0;
2205 lcd_dma.single_transfer = 0;
2206 lcd_dma.rotate = 0;
2207 lcd_dma.vxres = 0;
2208 lcd_dma.mirror = 0;
2209 lcd_dma.xscale = 0;
2210 lcd_dma.yscale = 0;
2211 lcd_dma.ext_ctrl = 0;
2212 lcd_dma.src_port = 0;
2213
2214 return 0;
2215}
2216EXPORT_SYMBOL(omap_request_lcd_dma);
2217
2218void omap_free_lcd_dma(void)
2219{
2220 spin_lock(&lcd_dma.lock);
2221 if (!lcd_dma.reserved) {
2222 spin_unlock(&lcd_dma.lock);
2223 printk(KERN_ERR "LCD DMA is not reserved\n");
2224 BUG();
2225 return;
2226 }
2227 if (!enable_1510_mode)
2228 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2229 OMAP1610_DMA_LCD_CCR);
2230 lcd_dma.reserved = 0;
2231 spin_unlock(&lcd_dma.lock);
2232}
2233EXPORT_SYMBOL(omap_free_lcd_dma);
2234
2235void omap_enable_lcd_dma(void)
2236{
2237 u16 w;
2238
2239
2240
2241
2242
2243
2244 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2245 return;
2246
2247 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2248 w |= 1 << 8;
2249 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2250
2251 lcd_dma.active = 1;
2252
2253 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2254 w |= 1 << 7;
2255 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2256}
2257EXPORT_SYMBOL(omap_enable_lcd_dma);
2258
2259void omap_setup_lcd_dma(void)
2260{
2261 BUG_ON(lcd_dma.active);
2262 if (!enable_1510_mode) {
2263
2264 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2265 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2266 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2267 }
2268 set_b1_regs();
2269 if (!enable_1510_mode) {
2270 u16 w;
2271
2272 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2273
2274
2275
2276
2277
2278 w |= 1 << 11;
2279 if (!lcd_dma.single_transfer)
2280 w |= (3 << 8);
2281 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2282 }
2283}
2284EXPORT_SYMBOL(omap_setup_lcd_dma);
2285
2286void omap_stop_lcd_dma(void)
2287{
2288 u16 w;
2289
2290 lcd_dma.active = 0;
2291 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2292 return;
2293
2294 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2295 w &= ~(1 << 7);
2296 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2297
2298 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2299 w &= ~(1 << 8);
2300 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2301}
2302EXPORT_SYMBOL(omap_stop_lcd_dma);
2303
2304
2305
2306static int __init omap_init_dma(void)
2307{
2308 int ch, r;
2309
2310 if (cpu_class_is_omap1()) {
2311 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2312 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2313 } else if (cpu_is_omap24xx()) {
2314 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2315 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2316 } else if (cpu_is_omap34xx()) {
2317 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2318 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2319 } else {
2320 pr_err("DMA init failed for unsupported omap\n");
2321 return -ENODEV;
2322 }
2323
2324 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2325 GFP_KERNEL);
2326 if (!dma_chan)
2327 return -ENOMEM;
2328
2329 if (cpu_class_is_omap2()) {
2330 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2331 dma_lch_count, GFP_KERNEL);
2332 if (!dma_linked_lch) {
2333 kfree(dma_chan);
2334 return -ENOMEM;
2335 }
2336 }
2337
2338 if (cpu_is_omap15xx()) {
2339 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2340 dma_chan_count = 9;
2341 enable_1510_mode = 1;
2342 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2343 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2344 dma_read(HW_ID));
2345 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2346 (dma_read(CAPS_0_U) << 16) |
2347 dma_read(CAPS_0_L),
2348 (dma_read(CAPS_1_U) << 16) |
2349 dma_read(CAPS_1_L),
2350 dma_read(CAPS_2), dma_read(CAPS_3),
2351 dma_read(CAPS_4));
2352 if (!enable_1510_mode) {
2353 u16 w;
2354
2355
2356 w = dma_read(GSCR);
2357 w |= 1 << 3;
2358 dma_write(w, GSCR);
2359 dma_chan_count = 16;
2360 } else
2361 dma_chan_count = 9;
2362 if (cpu_is_omap16xx()) {
2363 u16 w;
2364
2365
2366 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2367 w &= ~(1 << 8);
2368 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2369 }
2370 } else if (cpu_class_is_omap2()) {
2371 u8 revision = dma_read(REVISION) & 0xff;
2372 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2373 revision >> 4, revision & 0xf);
2374 dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2375 } else {
2376 dma_chan_count = 0;
2377 return 0;
2378 }
2379
2380 spin_lock_init(&lcd_dma.lock);
2381 spin_lock_init(&dma_chan_lock);
2382
2383 for (ch = 0; ch < dma_chan_count; ch++) {
2384 omap_clear_dma(ch);
2385 dma_chan[ch].dev_id = -1;
2386 dma_chan[ch].next_lch = -1;
2387
2388 if (ch >= 6 && enable_1510_mode)
2389 continue;
2390
2391 if (cpu_class_is_omap1()) {
2392
2393
2394
2395
2396 r = request_irq(omap1_dma_irq[ch],
2397 omap1_dma_irq_handler, 0, "DMA",
2398 (void *) (ch + 1));
2399 if (r != 0) {
2400 int i;
2401
2402 printk(KERN_ERR "unable to request IRQ %d "
2403 "for DMA (error %d)\n",
2404 omap1_dma_irq[ch], r);
2405 for (i = 0; i < ch; i++)
2406 free_irq(omap1_dma_irq[i],
2407 (void *) (i + 1));
2408 return r;
2409 }
2410 }
2411 }
2412
2413 if (cpu_is_omap2430() || cpu_is_omap34xx())
2414 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2415 DMA_DEFAULT_FIFO_DEPTH, 0);
2416
2417 if (cpu_class_is_omap2())
2418 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2419
2420
2421 if (cpu_class_is_omap1()) {
2422 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2423 "LCD DMA", NULL);
2424 if (r != 0) {
2425 int i;
2426
2427 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2428 "(error %d)\n", r);
2429 for (i = 0; i < dma_chan_count; i++)
2430 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2431 return r;
2432 }
2433 }
2434
2435 return 0;
2436}
2437
2438arch_initcall(omap_init_dma);
2439
2440
2441
