LXR linux/arch/arm/mach-mx3/iomux.c

   1/*
   2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
   3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License
   7 * as published by the Free Software Foundation; either version 2
   8 * of the License, or (at your option) any later version.
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 * GNU General Public License for more details.
  13 *
  14 * You should have received a copy of the GNU General Public License
  15 * along with this program; if not, write to the Free Software
  16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17 * MA 02110-1301, USA.
  18 */
  19
  20#include <linux/module.h>
  21#include <linux/spinlock.h>
  22#include <linux/io.h>
  23#include <linux/gpio.h>
  24#include <mach/hardware.h>
  25#include <mach/gpio.h>
  26#include <mach/iomux-mx3.h>
  27
  28/*
  29 * IOMUX register (base) addresses
  30 */
  31#define IOMUX_BASE      IO_ADDRESS(IOMUXC_BASE_ADDR)
  32#define IOMUXINT_OBS1   (IOMUX_BASE + 0x000)
  33#define IOMUXINT_OBS2   (IOMUX_BASE + 0x004)
  34#define IOMUXGPR        (IOMUX_BASE + 0x008)
  35#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
  36#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
  37
  38static DEFINE_SPINLOCK(gpio_mux_lock);
  39
  40#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
  41/*
  42 * set the mode for a IOMUX pin.
  43 */
  44int mxc_iomux_mode(unsigned int pin_mode)
  45{
  46        u32 field, l, mode, ret = 0;
  47        void __iomem *reg;
  48
  49        reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
  50        field = pin_mode & 0x3;
  51        mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
  52
  53        pr_debug("%s: reg offset = 0x%x field = %d mode = 0x%02x\n",
  54                        __func__, (pin_mode & IOMUX_REG_MASK), field, mode);
  55
  56        spin_lock(&gpio_mux_lock);
  57
  58        l = __raw_readl(reg);
  59        l &= ~(0xff << (field * 8));
  60        l |= mode << (field * 8);
  61        __raw_writel(l, reg);
  62
  63        spin_unlock(&gpio_mux_lock);
  64
  65        return ret;
  66}
  67EXPORT_SYMBOL(mxc_iomux_mode);
  68
  69/*
  70 * This function configures the pad value for a IOMUX pin.
  71 */
  72void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
  73{
  74        u32 field, l;
  75        void __iomem *reg;
  76
  77        pin &= IOMUX_PADNUM_MASK;
  78        reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
  79        field = (pin + 2) % 3;
  80
  81        pr_debug("%s: reg offset = 0x%x, field = %d\n",
  82                        __func__, (pin + 2) / 3, field);
  83
  84        spin_lock(&gpio_mux_lock);
  85
  86        l = __raw_readl(reg);
  87        l &= ~(0x1ff << (field * 10));
  88        l |= config << (field * 10);
  89        __raw_writel(l, reg);
  90
  91        spin_unlock(&gpio_mux_lock);
  92}
  93EXPORT_SYMBOL(mxc_iomux_set_pad);
  94
  95/*
  96 * This function enables/disables the general purpose function for a particular
  97 * signal.
  98 */
  99void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
 100{
 101        u32 l;
 102
 103        spin_lock(&gpio_mux_lock);
 104        l = __raw_readl(IOMUXGPR);
 105        if (en)
 106                l |= gp;
 107        else
 108                l &= ~gp;
 109
 110        __raw_writel(l, IOMUXGPR);
 111        spin_unlock(&gpio_mux_lock);
 112}
 113EXPORT_SYMBOL(mxc_iomux_set_gpr);
 114
 115