linux/drivers/serial/imx.c
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   1/*
   2 *  linux/drivers/serial/imx.c
   3 *
   4 *  Driver for Motorola IMX serial ports
   5 *
   6 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7 *
   8 *  Author: Sascha Hauer <sascha@saschahauer.de>
   9 *  Copyright (C) 2004 Pengutronix
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License as published by
  13 * the Free Software Foundation; either version 2 of the License, or
  14 * (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24 *
  25 * [29-Mar-2005] Mike Lee
  26 * Added hardware handshake
  27 */
  28
  29#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  30#define SUPPORT_SYSRQ
  31#endif
  32
  33#include <linux/module.h>
  34#include <linux/ioport.h>
  35#include <linux/init.h>
  36#include <linux/console.h>
  37#include <linux/sysrq.h>
  38#include <linux/platform_device.h>
  39#include <linux/tty.h>
  40#include <linux/tty_flip.h>
  41#include <linux/serial_core.h>
  42#include <linux/serial.h>
  43#include <linux/clk.h>
  44
  45#include <asm/io.h>
  46#include <asm/irq.h>
  47#include <mach/hardware.h>
  48#include <mach/imx-uart.h>
  49
  50/* Register definitions */
  51#define URXD0 0x0  /* Receiver Register */
  52#define URTX0 0x40 /* Transmitter Register */
  53#define UCR1  0x80 /* Control Register 1 */
  54#define UCR2  0x84 /* Control Register 2 */
  55#define UCR3  0x88 /* Control Register 3 */
  56#define UCR4  0x8c /* Control Register 4 */
  57#define UFCR  0x90 /* FIFO Control Register */
  58#define USR1  0x94 /* Status Register 1 */
  59#define USR2  0x98 /* Status Register 2 */
  60#define UESC  0x9c /* Escape Character Register */
  61#define UTIM  0xa0 /* Escape Timer Register */
  62#define UBIR  0xa4 /* BRM Incremental Register */
  63#define UBMR  0xa8 /* BRM Modulator Register */
  64#define UBRC  0xac /* Baud Rate Count Register */
  65#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
  66#define ONEMS 0xb0 /* One Millisecond register */
  67#define UTS   0xb4 /* UART Test Register */
  68#endif
  69#ifdef CONFIG_ARCH_IMX
  70#define BIPR1 0xb0 /* Incremental Preset Register 1 */
  71#define BIPR2 0xb4 /* Incremental Preset Register 2 */
  72#define BIPR3 0xb8 /* Incremental Preset Register 3 */
  73#define BIPR4 0xbc /* Incremental Preset Register 4 */
  74#define BMPR1 0xc0 /* BRM Modulator Register 1 */
  75#define BMPR2 0xc4 /* BRM Modulator Register 2 */
  76#define BMPR3 0xc8 /* BRM Modulator Register 3 */
  77#define BMPR4 0xcc /* BRM Modulator Register 4 */
  78#define UTS   0xd0 /* UART Test Register */
  79#endif
  80
  81/* UART Control Register Bit Fields.*/
  82#define  URXD_CHARRDY    (1<<15)
  83#define  URXD_ERR        (1<<14)
  84#define  URXD_OVRRUN     (1<<13)
  85#define  URXD_FRMERR     (1<<12)
  86#define  URXD_BRK        (1<<11)
  87#define  URXD_PRERR      (1<<10)
  88#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
  89#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  90#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  91#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  92#define  UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  93#define  UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
  94#define  UCR1_IREN       (1<<7)  /* Infrared interface enable */
  95#define  UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  96#define  UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  97#define  UCR1_SNDBRK     (1<<4)  /* Send break */
  98#define  UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
  99#ifdef CONFIG_ARCH_IMX
 100#define  UCR1_UARTCLKEN  (1<<2)  /* UART clock enabled */
 101#endif
 102#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
 103#define  UCR1_UARTCLKEN  (0)     /* not present on mx2/mx3 */
 104#endif
 105#define  UCR1_DOZE       (1<<1)  /* Doze */
 106#define  UCR1_UARTEN     (1<<0)  /* UART enabled */
 107#define  UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
 108#define  UCR2_IRTS       (1<<14) /* Ignore RTS pin */
 109#define  UCR2_CTSC       (1<<13) /* CTS pin control */
 110#define  UCR2_CTS        (1<<12) /* Clear to send */
 111#define  UCR2_ESCEN      (1<<11) /* Escape enable */
 112#define  UCR2_PREN       (1<<8)  /* Parity enable */
 113#define  UCR2_PROE       (1<<7)  /* Parity odd/even */
 114#define  UCR2_STPB       (1<<6)  /* Stop */
 115#define  UCR2_WS         (1<<5)  /* Word size */
 116#define  UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
 117#define  UCR2_TXEN       (1<<2)  /* Transmitter enabled */
 118#define  UCR2_RXEN       (1<<1)  /* Receiver enabled */
 119#define  UCR2_SRST       (1<<0)  /* SW reset */
 120#define  UCR3_DTREN      (1<<13) /* DTR interrupt enable */
 121#define  UCR3_PARERREN   (1<<12) /* Parity enable */
 122#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
 123#define  UCR3_DSR        (1<<10) /* Data set ready */
 124#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
 125#define  UCR3_RI         (1<<8)  /* Ring indicator */
 126#define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */
 127#define  UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
 128#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 129#define  UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
 130#ifdef CONFIG_ARCH_IMX
 131#define  UCR3_REF25      (1<<3)  /* Ref freq 25 MHz, only on mx1 */
 132#define  UCR3_REF30      (1<<2)  /* Ref Freq 30 MHz, only on mx1 */
 133#endif
 134#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
 135#define  UCR3_RXDMUXSEL  (1<<2)  /* RXD Muxed Input Select, on mx2/mx3 */
 136#endif
 137#define  UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
 138#define  UCR3_BPEN       (1<<0)  /* Preset registers enable */
 139#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
 140#define  UCR4_INVR       (1<<9)  /* Inverted infrared reception */
 141#define  UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
 142#define  UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
 143#define  UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
 144#define  UCR4_IRSC       (1<<5)  /* IR special case */
 145#define  UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
 146#define  UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
 147#define  UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
 148#define  UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
 149#define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 150#define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 151#define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 152#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 153#define  USR1_RTSS       (1<<14) /* RTS pin status */
 154#define  USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
 155#define  USR1_RTSD       (1<<12) /* RTS delta */
 156#define  USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
 157#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 158#define  USR1_RRDY       (1<<9)  /* Receiver ready interrupt/dma flag */
 159#define  USR1_TIMEOUT    (1<<7)  /* Receive timeout interrupt status */
 160#define  USR1_RXDS       (1<<6)  /* Receiver idle interrupt flag */
 161#define  USR1_AIRINT     (1<<5)  /* Async IR wake interrupt flag */
 162#define  USR1_AWAKE      (1<<4)  /* Aysnc wake interrupt flag */
 163#define  USR2_ADET       (1<<15) /* Auto baud rate detect complete */
 164#define  USR2_TXFE       (1<<14) /* Transmit buffer FIFO empty */
 165#define  USR2_DTRF       (1<<13) /* DTR edge interrupt flag */
 166#define  USR2_IDLE       (1<<12) /* Idle condition */
 167#define  USR2_IRINT      (1<<8)  /* Serial infrared interrupt flag */
 168#define  USR2_WAKE       (1<<7)  /* Wake */
 169#define  USR2_RTSF       (1<<4)  /* RTS edge interrupt flag */
 170#define  USR2_TXDC       (1<<3)  /* Transmitter complete */
 171#define  USR2_BRCD       (1<<2)  /* Break condition */
 172#define  USR2_ORE        (1<<1)  /* Overrun error */
 173#define  USR2_RDR        (1<<0)  /* Recv data ready */
 174#define  UTS_FRCPERR     (1<<13) /* Force parity error */
 175#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
 176#define  UTS_TXEMPTY     (1<<6)  /* TxFIFO empty */
 177#define  UTS_RXEMPTY     (1<<5)  /* RxFIFO empty */
 178#define  UTS_TXFULL      (1<<4)  /* TxFIFO full */
 179#define  UTS_RXFULL      (1<<3)  /* RxFIFO full */
 180#define  UTS_SOFTRST     (1<<0)  /* Software reset */
 181
 182/* We've been assigned a range on the "Low-density serial ports" major */
 183#ifdef CONFIG_ARCH_IMX
 184#define SERIAL_IMX_MAJOR        204
 185#define MINOR_START             41
 186#define DEV_NAME                "ttySMX"
 187#define MAX_INTERNAL_IRQ        IMX_IRQS
 188#endif
 189
 190#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
 191#define SERIAL_IMX_MAJOR        207
 192#define MINOR_START             16
 193#define DEV_NAME                "ttymxc"
 194#define MAX_INTERNAL_IRQ        MXC_MAX_INT_LINES
 195#endif
 196
 197/*
 198 * This determines how often we check the modem status signals
 199 * for any change.  They generally aren't connected to an IRQ
 200 * so we have to poll them.  We also check immediately before
 201 * filling the TX fifo incase CTS has been dropped.
 202 */
 203#define MCTRL_TIMEOUT   (250*HZ/1000)
 204
 205#define DRIVER_NAME "IMX-uart"
 206
 207#define UART_NR 8
 208
 209struct imx_port {
 210        struct uart_port        port;
 211        struct timer_list       timer;
 212        unsigned int            old_status;
 213        int                     txirq,rxirq,rtsirq;
 214        int                     have_rtscts:1;
 215        struct clk              *clk;
 216};
 217
 218/*
 219 * Handle any change of modem status signal since we were last called.
 220 */
 221static void imx_mctrl_check(struct imx_port *sport)
 222{
 223        unsigned int status, changed;
 224
 225        status = sport->port.ops->get_mctrl(&sport->port);
 226        changed = status ^ sport->old_status;
 227
 228        if (changed == 0)
 229                return;
 230
 231        sport->old_status = status;
 232
 233        if (changed & TIOCM_RI)
 234                sport->port.icount.rng++;
 235        if (changed & TIOCM_DSR)
 236                sport->port.icount.dsr++;
 237        if (changed & TIOCM_CAR)
 238                uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
 239        if (changed & TIOCM_CTS)
 240                uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
 241
 242        wake_up_interruptible(&sport->port.info->delta_msr_wait);
 243}
 244
 245/*
 246 * This is our per-port timeout handler, for checking the
 247 * modem status signals.
 248 */
 249static void imx_timeout(unsigned long data)
 250{
 251        struct imx_port *sport = (struct imx_port *)data;
 252        unsigned long flags;
 253
 254        if (sport->port.info) {
 255                spin_lock_irqsave(&sport->port.lock, flags);
 256                imx_mctrl_check(sport);
 257                spin_unlock_irqrestore(&sport->port.lock, flags);
 258
 259                mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
 260        }
 261}
 262
 263/*
 264 * interrupts disabled on entry
 265 */
 266static void imx_stop_tx(struct uart_port *port)
 267{
 268        struct imx_port *sport = (struct imx_port *)port;
 269        unsigned long temp;
 270
 271        temp = readl(sport->port.membase + UCR1);
 272        writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
 273}
 274
 275/*
 276 * interrupts disabled on entry
 277 */
 278static void imx_stop_rx(struct uart_port *port)
 279{
 280        struct imx_port *sport = (struct imx_port *)port;
 281        unsigned long temp;
 282
 283        temp = readl(sport->port.membase + UCR2);
 284        writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
 285}
 286
 287/*
 288 * Set the modem control timer to fire immediately.
 289 */
 290static void imx_enable_ms(struct uart_port *port)
 291{
 292        struct imx_port *sport = (struct imx_port *)port;
 293
 294        mod_timer(&sport->timer, jiffies);
 295}
 296
 297static inline void imx_transmit_buffer(struct imx_port *sport)
 298{
 299        struct circ_buf *xmit = &sport->port.info->xmit;
 300
 301        while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
 302                /* send xmit->buf[xmit->tail]
 303                 * out the port here */
 304                writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
 305                xmit->tail = (xmit->tail + 1) &
 306                         (UART_XMIT_SIZE - 1);
 307                sport->port.icount.tx++;
 308                if (uart_circ_empty(xmit))
 309                        break;
 310        }
 311
 312        if (uart_circ_empty(xmit))
 313                imx_stop_tx(&sport->port);
 314}
 315
 316/*
 317 * interrupts disabled on entry
 318 */
 319static void imx_start_tx(struct uart_port *port)
 320{
 321        struct imx_port *sport = (struct imx_port *)port;
 322        unsigned long temp;
 323
 324        temp = readl(sport->port.membase + UCR1);
 325        writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
 326
 327        if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
 328                imx_transmit_buffer(sport);
 329}
 330
 331static irqreturn_t imx_rtsint(int irq, void *dev_id)
 332{
 333        struct imx_port *sport = dev_id;
 334        unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
 335        unsigned long flags;
 336
 337        spin_lock_irqsave(&sport->port.lock, flags);
 338
 339        writel(USR1_RTSD, sport->port.membase + USR1);
 340        uart_handle_cts_change(&sport->port, !!val);
 341        wake_up_interruptible(&sport->port.info->delta_msr_wait);
 342
 343        spin_unlock_irqrestore(&sport->port.lock, flags);
 344        return IRQ_HANDLED;
 345}
 346
 347static irqreturn_t imx_txint(int irq, void *dev_id)
 348{
 349        struct imx_port *sport = dev_id;
 350        struct circ_buf *xmit = &sport->port.info->xmit;
 351        unsigned long flags;
 352
 353        spin_lock_irqsave(&sport->port.lock,flags);
 354        if (sport->port.x_char)
 355        {
 356                /* Send next char */
 357                writel(sport->port.x_char, sport->port.membase + URTX0);
 358                goto out;
 359        }
 360
 361        if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 362                imx_stop_tx(&sport->port);
 363                goto out;
 364        }
 365
 366        imx_transmit_buffer(sport);
 367
 368        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 369                uart_write_wakeup(&sport->port);
 370
 371out:
 372        spin_unlock_irqrestore(&sport->port.lock,flags);
 373        return IRQ_HANDLED;
 374}
 375
 376static irqreturn_t imx_rxint(int irq, void *dev_id)
 377{
 378        struct imx_port *sport = dev_id;
 379        unsigned int rx,flg,ignored = 0;
 380        struct tty_struct *tty = sport->port.info->port.tty;
 381        unsigned long flags, temp;
 382
 383        spin_lock_irqsave(&sport->port.lock,flags);
 384
 385        while (readl(sport->port.membase + USR2) & USR2_RDR) {
 386                flg = TTY_NORMAL;
 387                sport->port.icount.rx++;
 388
 389                rx = readl(sport->port.membase + URXD0);
 390
 391                temp = readl(sport->port.membase + USR2);
 392                if (temp & USR2_BRCD) {
 393                        writel(temp | USR2_BRCD, sport->port.membase + USR2);
 394                        if (uart_handle_break(&sport->port))
 395                                continue;
 396                }
 397
 398                if (uart_handle_sysrq_char
 399                            (&sport->port, (unsigned char)rx))
 400                        continue;
 401
 402                if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
 403                        if (rx & URXD_PRERR)
 404                                sport->port.icount.parity++;
 405                        else if (rx & URXD_FRMERR)
 406                                sport->port.icount.frame++;
 407                        if (rx & URXD_OVRRUN)
 408                                sport->port.icount.overrun++;
 409
 410                        if (rx & sport->port.ignore_status_mask) {
 411                                if (++ignored > 100)
 412                                        goto out;
 413                                continue;
 414                        }
 415
 416                        rx &= sport->port.read_status_mask;
 417
 418                        if (rx & URXD_PRERR)
 419                                flg = TTY_PARITY;
 420                        else if (rx & URXD_FRMERR)
 421                                flg = TTY_FRAME;
 422                        if (rx & URXD_OVRRUN)
 423                                flg = TTY_OVERRUN;
 424
 425#ifdef SUPPORT_SYSRQ
 426                        sport->port.sysrq = 0;
 427#endif
 428                }
 429
 430                tty_insert_flip_char(tty, rx, flg);
 431        }
 432
 433out:
 434        spin_unlock_irqrestore(&sport->port.lock,flags);
 435        tty_flip_buffer_push(tty);
 436        return IRQ_HANDLED;
 437}
 438
 439static irqreturn_t imx_int(int irq, void *dev_id)
 440{
 441        struct imx_port *sport = dev_id;
 442        unsigned int sts;
 443
 444        sts = readl(sport->port.membase + USR1);
 445
 446        if (sts & USR1_RRDY)
 447                imx_rxint(irq, dev_id);
 448
 449        if (sts & USR1_TRDY &&
 450                        readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
 451                imx_txint(irq, dev_id);
 452
 453        if (sts & USR1_RTSD)
 454                imx_rtsint(irq, dev_id);
 455
 456        return IRQ_HANDLED;
 457}
 458
 459/*
 460 * Return TIOCSER_TEMT when transmitter is not busy.
 461 */
 462static unsigned int imx_tx_empty(struct uart_port *port)
 463{
 464        struct imx_port *sport = (struct imx_port *)port;
 465
 466        return (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
 467}
 468
 469/*
 470 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
 471 */
 472static unsigned int imx_get_mctrl(struct uart_port *port)
 473{
 474        struct imx_port *sport = (struct imx_port *)port;
 475        unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
 476
 477        if (readl(sport->port.membase + USR1) & USR1_RTSS)
 478                tmp |= TIOCM_CTS;
 479
 480        if (readl(sport->port.membase + UCR2) & UCR2_CTS)
 481                tmp |= TIOCM_RTS;
 482
 483        return tmp;
 484}
 485
 486static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
 487{
 488        struct imx_port *sport = (struct imx_port *)port;
 489        unsigned long temp;
 490
 491        temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
 492
 493        if (mctrl & TIOCM_RTS)
 494                temp |= UCR2_CTS;
 495
 496        writel(temp, sport->port.membase + UCR2);
 497}
 498
 499/*
 500 * Interrupts always disabled.
 501 */
 502static void imx_break_ctl(struct uart_port *port, int break_state)
 503{
 504        struct imx_port *sport = (struct imx_port *)port;
 505        unsigned long flags, temp;
 506
 507        spin_lock_irqsave(&sport->port.lock, flags);
 508
 509        temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
 510
 511        if ( break_state != 0 )
 512                temp |= UCR1_SNDBRK;
 513
 514        writel(temp, sport->port.membase + UCR1);
 515
 516        spin_unlock_irqrestore(&sport->port.lock, flags);
 517}
 518
 519#define TXTL 2 /* reset default */
 520#define RXTL 1 /* reset default */
 521
 522static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
 523{
 524        unsigned int val;
 525        unsigned int ufcr_rfdiv;
 526
 527        /* set receiver / transmitter trigger level.
 528         * RFDIV is set such way to satisfy requested uartclk value
 529         */
 530        val = TXTL << 10 | RXTL;
 531        ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
 532                        / sport->port.uartclk;
 533
 534        if(!ufcr_rfdiv)
 535                ufcr_rfdiv = 1;
 536
 537        if(ufcr_rfdiv >= 7)
 538                ufcr_rfdiv = 6;
 539        else
 540                ufcr_rfdiv = 6 - ufcr_rfdiv;
 541
 542        val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
 543
 544        writel(val, sport->port.membase + UFCR);
 545
 546        return 0;
 547}
 548
 549static int imx_startup(struct uart_port *port)
 550{
 551        struct imx_port *sport = (struct imx_port *)port;
 552        int retval;
 553        unsigned long flags, temp;
 554
 555        imx_setup_ufcr(sport, 0);
 556
 557        /* disable the DREN bit (Data Ready interrupt enable) before
 558         * requesting IRQs
 559         */
 560        temp = readl(sport->port.membase + UCR4);
 561        writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
 562
 563        /*
 564         * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
 565         * chips only have one interrupt.
 566         */
 567        if (sport->txirq > 0) {
 568                retval = request_irq(sport->rxirq, imx_rxint, 0,
 569                                DRIVER_NAME, sport);
 570                if (retval)
 571                        goto error_out1;
 572
 573                retval = request_irq(sport->txirq, imx_txint, 0,
 574                                DRIVER_NAME, sport);
 575                if (retval)
 576                        goto error_out2;
 577
 578                retval = request_irq(sport->rtsirq, imx_rtsint,
 579                             (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
 580                               IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
 581                                DRIVER_NAME, sport);
 582                if (retval)
 583                        goto error_out3;
 584        } else {
 585                retval = request_irq(sport->port.irq, imx_int, 0,
 586                                DRIVER_NAME, sport);
 587                if (retval) {
 588                        free_irq(sport->port.irq, sport);
 589                        goto error_out1;
 590                }
 591        }
 592
 593        /*
 594         * Finally, clear and enable interrupts
 595         */
 596        writel(USR1_RTSD, sport->port.membase + USR1);
 597
 598        temp = readl(sport->port.membase + UCR1);
 599        temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
 600        writel(temp, sport->port.membase + UCR1);
 601
 602        temp = readl(sport->port.membase + UCR2);
 603        temp |= (UCR2_RXEN | UCR2_TXEN);
 604        writel(temp, sport->port.membase + UCR2);
 605
 606#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
 607        temp = readl(sport->port.membase + UCR3);
 608        temp |= UCR3_RXDMUXSEL;
 609        writel(temp, sport->port.membase + UCR3);
 610#endif
 611
 612        /*
 613         * Enable modem status interrupts
 614         */
 615        spin_lock_irqsave(&sport->port.lock,flags);
 616        imx_enable_ms(&sport->port);
 617        spin_unlock_irqrestore(&sport->port.lock,flags);
 618
 619        return 0;
 620
 621error_out3:
 622        if (sport->txirq)
 623                free_irq(sport->txirq, sport);
 624error_out2:
 625        if (sport->rxirq)
 626                free_irq(sport->rxirq, sport);
 627error_out1:
 628        return retval;
 629}
 630
 631static void imx_shutdown(struct uart_port *port)
 632{
 633        struct imx_port *sport = (struct imx_port *)port;
 634        unsigned long temp;
 635
 636        /*
 637         * Stop our timer.
 638         */
 639        del_timer_sync(&sport->timer);
 640
 641        /*
 642         * Free the interrupts
 643         */
 644        if (sport->txirq > 0) {
 645                free_irq(sport->rtsirq, sport);
 646                free_irq(sport->txirq, sport);
 647                free_irq(sport->rxirq, sport);
 648        } else
 649                free_irq(sport->port.irq, sport);
 650
 651        /*
 652         * Disable all interrupts, port and break condition.
 653         */
 654
 655        temp = readl(sport->port.membase + UCR1);
 656        temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
 657        writel(temp, sport->port.membase + UCR1);
 658}
 659
 660static void
 661imx_set_termios(struct uart_port *port, struct ktermios *termios,
 662                   struct ktermios *old)
 663{
 664        struct imx_port *sport = (struct imx_port *)port;
 665        unsigned long flags;
 666        unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
 667        unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
 668        unsigned int div, num, denom, ufcr;
 669
 670        /*
 671         * If we don't support modem control lines, don't allow
 672         * these to be set.
 673         */
 674        if (0) {
 675                termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
 676                termios->c_cflag |= CLOCAL;
 677        }
 678
 679        /*
 680         * We only support CS7 and CS8.
 681         */
 682        while ((termios->c_cflag & CSIZE) != CS7 &&
 683               (termios->c_cflag & CSIZE) != CS8) {
 684                termios->c_cflag &= ~CSIZE;
 685                termios->c_cflag |= old_csize;
 686                old_csize = CS8;
 687        }
 688
 689        if ((termios->c_cflag & CSIZE) == CS8)
 690                ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
 691        else
 692                ucr2 = UCR2_SRST | UCR2_IRTS;
 693
 694        if (termios->c_cflag & CRTSCTS) {
 695                if( sport->have_rtscts ) {
 696                        ucr2 &= ~UCR2_IRTS;
 697                        ucr2 |= UCR2_CTSC;
 698                } else {
 699                        termios->c_cflag &= ~CRTSCTS;
 700                }
 701        }
 702
 703        if (termios->c_cflag & CSTOPB)
 704                ucr2 |= UCR2_STPB;
 705        if (termios->c_cflag & PARENB) {
 706                ucr2 |= UCR2_PREN;
 707                if (termios->c_cflag & PARODD)
 708                        ucr2 |= UCR2_PROE;
 709        }
 710
 711        /*
 712         * Ask the core to calculate the divisor for us.
 713         */
 714        baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
 715        quot = uart_get_divisor(port, baud);
 716
 717        spin_lock_irqsave(&sport->port.lock, flags);
 718
 719        sport->port.read_status_mask = 0;
 720        if (termios->c_iflag & INPCK)
 721                sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
 722        if (termios->c_iflag & (BRKINT | PARMRK))
 723                sport->port.read_status_mask |= URXD_BRK;
 724
 725        /*
 726         * Characters to ignore
 727         */
 728        sport->port.ignore_status_mask = 0;
 729        if (termios->c_iflag & IGNPAR)
 730                sport->port.ignore_status_mask |= URXD_PRERR;
 731        if (termios->c_iflag & IGNBRK) {
 732                sport->port.ignore_status_mask |= URXD_BRK;
 733                /*
 734                 * If we're ignoring parity and break indicators,
 735                 * ignore overruns too (for real raw support).
 736                 */
 737                if (termios->c_iflag & IGNPAR)
 738                        sport->port.ignore_status_mask |= URXD_OVRRUN;
 739        }
 740
 741        del_timer_sync(&sport->timer);
 742
 743        /*
 744         * Update the per-port timeout.
 745         */
 746        uart_update_timeout(port, termios->c_cflag, baud);
 747
 748        /*
 749         * disable interrupts and drain transmitter
 750         */
 751        old_ucr1 = readl(sport->port.membase + UCR1);
 752        writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
 753                        sport->port.membase + UCR1);
 754
 755        while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
 756                barrier();
 757
 758        /* then, disable everything */
 759        old_txrxen = readl(sport->port.membase + UCR2);
 760        writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
 761                        sport->port.membase + UCR2);
 762        old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
 763
 764        div = sport->port.uartclk / (baud * 16);
 765        if (div > 7)
 766                div = 7;
 767        if (!div)
 768                div = 1;
 769
 770        num = baud;
 771        denom = port->uartclk / div / 16;
 772
 773        /* shift num and denom right until they fit into 16 bits */
 774        while (num > 0x10000 || denom > 0x10000) {
 775                num >>= 1;
 776                denom >>= 1;
 777        }
 778        if (num > 0)
 779                num -= 1;
 780        if (denom > 0)
 781                denom -= 1;
 782
 783        writel(num, sport->port.membase + UBIR);
 784        writel(denom, sport->port.membase + UBMR);
 785
 786        if (div == 7)
 787                div = 6; /* 6 in RFDIV means divide by 7 */
 788        else
 789                div = 6 - div;
 790
 791        ufcr = readl(sport->port.membase + UFCR);
 792        ufcr = (ufcr & (~UFCR_RFDIV)) |
 793            (div << 7);
 794        writel(ufcr, sport->port.membase + UFCR);
 795
 796#ifdef ONEMS
 797        writel(sport->port.uartclk / div / 1000, sport->port.membase + ONEMS);
 798#endif
 799
 800        writel(old_ucr1, sport->port.membase + UCR1);
 801
 802        /* set the parity, stop bits and data size */
 803        writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
 804
 805        if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
 806                imx_enable_ms(&sport->port);
 807
 808        spin_unlock_irqrestore(&sport->port.lock, flags);
 809}
 810
 811static const char *imx_type(struct uart_port *port)
 812{
 813        struct imx_port *sport = (struct imx_port *)port;
 814
 815        return sport->port.type == PORT_IMX ? "IMX" : NULL;
 816}
 817
 818/*
 819 * Release the memory region(s) being used by 'port'.
 820 */
 821static void imx_release_port(struct uart_port *port)
 822{
 823        struct platform_device *pdev = to_platform_device(port->dev);
 824        struct resource *mmres;
 825
 826        mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 827        release_mem_region(mmres->start, mmres->end - mmres->start + 1);
 828}
 829
 830/*
 831 * Request the memory region(s) being used by 'port'.
 832 */
 833static int imx_request_port(struct uart_port *port)
 834{
 835        struct platform_device *pdev = to_platform_device(port->dev);
 836        struct resource *mmres;
 837        void *ret;
 838
 839        mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 840        if (!mmres)
 841                return -ENODEV;
 842
 843        ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
 844                        "imx-uart");
 845
 846        return  ret ? 0 : -EBUSY;
 847}
 848
 849/*
 850 * Configure/autoconfigure the port.
 851 */
 852static void imx_config_port(struct uart_port *port, int flags)
 853{
 854        struct imx_port *sport = (struct imx_port *)port;
 855
 856        if (flags & UART_CONFIG_TYPE &&
 857            imx_request_port(&sport->port) == 0)
 858                sport->port.type = PORT_IMX;
 859}
 860
 861/*
 862 * Verify the new serial_struct (for TIOCSSERIAL).
 863 * The only change we allow are to the flags and type, and
 864 * even then only between PORT_IMX and PORT_UNKNOWN
 865 */
 866static int
 867imx_verify_port(struct uart_port *port, struct serial_struct *ser)
 868{
 869        struct imx_port *sport = (struct imx_port *)port;
 870        int ret = 0;
 871
 872        if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
 873                ret = -EINVAL;
 874        if (sport->port.irq != ser->irq)
 875                ret = -EINVAL;
 876        if (ser->io_type != UPIO_MEM)
 877                ret = -EINVAL;
 878        if (sport->port.uartclk / 16 != ser->baud_base)
 879                ret = -EINVAL;
 880        if ((void *)sport->port.mapbase != ser->iomem_base)
 881                ret = -EINVAL;
 882        if (sport->port.iobase != ser->port)
 883                ret = -EINVAL;
 884        if (ser->hub6 != 0)
 885                ret = -EINVAL;
 886        return ret;
 887}
 888
 889static struct uart_ops imx_pops = {
 890        .tx_empty       = imx_tx_empty,
 891        .set_mctrl      = imx_set_mctrl,
 892        .get_mctrl      = imx_get_mctrl,
 893        .stop_tx        = imx_stop_tx,
 894        .start_tx       = imx_start_tx,
 895        .stop_rx        = imx_stop_rx,
 896        .enable_ms      = imx_enable_ms,
 897        .break_ctl      = imx_break_ctl,
 898        .startup        = imx_startup,
 899        .shutdown       = imx_shutdown,
 900        .set_termios    = imx_set_termios,
 901        .type           = imx_type,
 902        .release_port   = imx_release_port,
 903        .request_port   = imx_request_port,
 904        .config_port    = imx_config_port,
 905        .verify_port    = imx_verify_port,
 906};
 907
 908static struct imx_port *imx_ports[UART_NR];
 909
 910#ifdef CONFIG_SERIAL_IMX_CONSOLE
 911static void imx_console_putchar(struct uart_port *port, int ch)
 912{
 913        struct imx_port *sport = (struct imx_port *)port;
 914
 915        while (readl(sport->port.membase + UTS) & UTS_TXFULL)
 916                barrier();
 917
 918        writel(ch, sport->port.membase + URTX0);
 919}
 920
 921/*
 922 * Interrupts are disabled on entering
 923 */
 924static void
 925imx_console_write(struct console *co, const char *s, unsigned int count)
 926{
 927        struct imx_port *sport = imx_ports[co->index];
 928        unsigned int old_ucr1, old_ucr2;
 929
 930        /*
 931         *      First, save UCR1/2 and then disable interrupts
 932         */
 933        old_ucr1 = readl(sport->port.membase + UCR1);
 934        old_ucr2 = readl(sport->port.membase + UCR2);
 935
 936        writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
 937                ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
 938                sport->port.membase + UCR1);
 939
 940        writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
 941
 942        uart_console_write(&sport->port, s, count, imx_console_putchar);
 943
 944        /*
 945         *      Finally, wait for transmitter to become empty
 946         *      and restore UCR1/2
 947         */
 948        while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
 949
 950        writel(old_ucr1, sport->port.membase + UCR1);
 951        writel(old_ucr2, sport->port.membase + UCR2);
 952}
 953
 954/*
 955 * If the port was already initialised (eg, by a boot loader),
 956 * try to determine the current setup.
 957 */
 958static void __init
 959imx_console_get_options(struct imx_port *sport, int *baud,
 960                           int *parity, int *bits)
 961{
 962
 963        if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
 964                /* ok, the port was enabled */
 965                unsigned int ucr2, ubir,ubmr, uartclk;
 966                unsigned int baud_raw;
 967                unsigned int ucfr_rfdiv;
 968
 969                ucr2 = readl(sport->port.membase + UCR2);
 970
 971                *parity = 'n';
 972                if (ucr2 & UCR2_PREN) {
 973                        if (ucr2 & UCR2_PROE)
 974                                *parity = 'o';
 975                        else
 976                                *parity = 'e';
 977                }
 978
 979                if (ucr2 & UCR2_WS)
 980                        *bits = 8;
 981                else
 982                        *bits = 7;
 983
 984                ubir = readl(sport->port.membase + UBIR) & 0xffff;
 985                ubmr = readl(sport->port.membase + UBMR) & 0xffff;
 986
 987                ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
 988                if (ucfr_rfdiv == 6)
 989                        ucfr_rfdiv = 7;
 990                else
 991                        ucfr_rfdiv = 6 - ucfr_rfdiv;
 992
 993                uartclk = clk_get_rate(sport->clk);
 994                uartclk /= ucfr_rfdiv;
 995
 996                {       /*
 997                         * The next code provides exact computation of
 998                         *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
 999                         * without need of float support or long long division,
1000                         * which would be required to prevent 32bit arithmetic overflow
1001                         */
1002                        unsigned int mul = ubir + 1;
1003                        unsigned int div = 16 * (ubmr + 1);
1004                        unsigned int rem = uartclk % div;
1005
1006                        baud_raw = (uartclk / div) * mul;
1007                        baud_raw += (rem * mul + div / 2) / div;
1008                        *baud = (baud_raw + 50) / 100 * 100;
1009                }
1010
1011                if(*baud != baud_raw)
1012                        printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1013                                baud_raw, *baud);
1014        }
1015}
1016
1017static int __init
1018imx_console_setup(struct console *co, char *options)
1019{
1020        struct imx_port *sport;
1021        int baud = 9600;
1022        int bits = 8;
1023        int parity = 'n';
1024        int flow = 'n';
1025
1026        /*
1027         * Check whether an invalid uart number has been specified, and
1028         * if so, search for the first available port that does have
1029         * console support.
1030         */
1031        if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1032                co->index = 0;
1033        sport = imx_ports[co->index];
1034
1035        if (options)
1036                uart_parse_options(options, &baud, &parity, &bits, &flow);
1037        else
1038                imx_console_get_options(sport, &baud, &parity, &bits);
1039
1040        imx_setup_ufcr(sport, 0);
1041
1042        return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1043}
1044
1045static struct uart_driver imx_reg;
1046static struct console imx_console = {
1047        .name           = DEV_NAME,
1048        .write          = imx_console_write,
1049        .device         = uart_console_device,
1050        .setup          = imx_console_setup,
1051        .flags          = CON_PRINTBUFFER,
1052        .index          = -1,
1053        .data           = &imx_reg,
1054};
1055
1056#define IMX_CONSOLE     &imx_console
1057#else
1058#define IMX_CONSOLE     NULL
1059#endif
1060
1061static struct uart_driver imx_reg = {
1062        .owner          = THIS_MODULE,
1063        .driver_name    = DRIVER_NAME,
1064        .dev_name       = DEV_NAME,
1065        .major          = SERIAL_IMX_MAJOR,
1066        .minor          = MINOR_START,
1067        .nr             = ARRAY_SIZE(imx_ports),
1068        .cons           = IMX_CONSOLE,
1069};
1070
1071static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1072{
1073        struct imx_port *sport = platform_get_drvdata(dev);
1074
1075        if (sport)
1076                uart_suspend_port(&imx_reg, &sport->port);
1077
1078        return 0;
1079}
1080
1081static int serial_imx_resume(struct platform_device *dev)
1082{
1083        struct imx_port *sport = platform_get_drvdata(dev);
1084
1085        if (sport)
1086                uart_resume_port(&imx_reg, &sport->port);
1087
1088        return 0;
1089}
1090
1091static int serial_imx_probe(struct platform_device *pdev)
1092{
1093        struct imx_port *sport;
1094        struct imxuart_platform_data *pdata;
1095        void __iomem *base;
1096        int ret = 0;
1097        struct resource *res;
1098
1099        sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1100        if (!sport)
1101                return -ENOMEM;
1102
1103        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1104        if (!res) {
1105                ret = -ENODEV;
1106                goto free;
1107        }
1108
1109        base = ioremap(res->start, PAGE_SIZE);
1110        if (!base) {
1111                ret = -ENOMEM;
1112                goto free;
1113        }
1114
1115        sport->port.dev = &pdev->dev;
1116        sport->port.mapbase = res->start;
1117        sport->port.membase = base;
1118        sport->port.type = PORT_IMX,
1119        sport->port.iotype = UPIO_MEM;
1120        sport->port.irq = platform_get_irq(pdev, 0);
1121        sport->rxirq = platform_get_irq(pdev, 0);
1122        sport->txirq = platform_get_irq(pdev, 1);
1123        sport->rtsirq = platform_get_irq(pdev, 2);
1124        sport->port.fifosize = 32;
1125        sport->port.ops = &imx_pops;
1126        sport->port.flags = UPF_BOOT_AUTOCONF;
1127        sport->port.line = pdev->id;
1128        init_timer(&sport->timer);
1129        sport->timer.function = imx_timeout;
1130        sport->timer.data     = (unsigned long)sport;
1131
1132        sport->clk = clk_get(&pdev->dev, "uart_clk");
1133        if (IS_ERR(sport->clk)) {
1134                ret = PTR_ERR(sport->clk);
1135                goto unmap;
1136        }
1137        clk_enable(sport->clk);
1138
1139        sport->port.uartclk = clk_get_rate(sport->clk);
1140
1141        imx_ports[pdev->id] = sport;
1142
1143        pdata = pdev->dev.platform_data;
1144        if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1145                sport->have_rtscts = 1;
1146
1147        if (pdata->init) {
1148                ret = pdata->init(pdev);
1149                if (ret)
1150                        goto clkput;
1151        }
1152
1153        uart_add_one_port(&imx_reg, &sport->port);
1154        platform_set_drvdata(pdev, &sport->port);
1155
1156        return 0;
1157clkput:
1158        clk_put(sport->clk);
1159        clk_disable(sport->clk);
1160unmap:
1161        iounmap(sport->port.membase);
1162free:
1163        kfree(sport);
1164
1165        return ret;
1166}
1167
1168static int serial_imx_remove(struct platform_device *pdev)
1169{
1170        struct imxuart_platform_data *pdata;
1171        struct imx_port *sport = platform_get_drvdata(pdev);
1172
1173        pdata = pdev->dev.platform_data;
1174
1175        platform_set_drvdata(pdev, NULL);
1176
1177        if (sport) {
1178                uart_remove_one_port(&imx_reg, &sport->port);
1179                clk_put(sport->clk);
1180        }
1181
1182        clk_disable(sport->clk);
1183
1184        if (pdata->exit)
1185                pdata->exit(pdev);
1186
1187        iounmap(sport->port.membase);
1188        kfree(sport);
1189
1190        return 0;
1191}
1192
1193static struct platform_driver serial_imx_driver = {
1194        .probe          = serial_imx_probe,
1195        .remove         = serial_imx_remove,
1196
1197        .suspend        = serial_imx_suspend,
1198        .resume         = serial_imx_resume,
1199        .driver         = {
1200                .name   = "imx-uart",
1201                .owner  = THIS_MODULE,
1202        },
1203};
1204
1205static int __init imx_serial_init(void)
1206{
1207        int ret;
1208
1209        printk(KERN_INFO "Serial: IMX driver\n");
1210
1211        ret = uart_register_driver(&imx_reg);
1212        if (ret)
1213                return ret;
1214
1215        ret = platform_driver_register(&serial_imx_driver);
1216        if (ret != 0)
1217                uart_unregister_driver(&imx_reg);
1218
1219        return 0;
1220}
1221
1222static void __exit imx_serial_exit(void)
1223{
1224        platform_driver_unregister(&serial_imx_driver);
1225        uart_unregister_driver(&imx_reg);
1226}
1227
1228module_init(imx_serial_init);
1229module_exit(imx_serial_exit);
1230
1231MODULE_AUTHOR("Sascha Hauer");
1232MODULE_DESCRIPTION("IMX generic serial port driver");
1233MODULE_LICENSE("GPL");
1234MODULE_ALIAS("platform:imx-uart");
1235
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