1/******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2004-2008 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21#define FDMI_DID 0xfffffaU 22#define NameServer_DID 0xfffffcU 23#define SCR_DID 0xfffffdU 24#define Fabric_DID 0xfffffeU 25#define Bcast_DID 0xffffffU 26#define Mask_DID 0xffffffU 27#define CT_DID_MASK 0xffff00U 28#define Fabric_DID_MASK 0xfff000U 29#define WELL_KNOWN_DID_MASK 0xfffff0U 30 31#define PT2PT_LocalID 1 32#define PT2PT_RemoteID 2 33 34#define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35#define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36#define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 37#define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38 39#define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40 0 */ 41 42#define FCELSSIZE 1024 /* maximum ELS transfer size */ 43 44#define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45#define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 46#define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47#define LPFC_FCP_NEXT_RING 3 48 49#define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 50#define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 51#define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 52#define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 53#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 54#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 55#define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 56#define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 57#define SLI2_IOCB_CMD_R3_ENTRIES 0 58#define SLI2_IOCB_RSP_R3_ENTRIES 0 59#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 60#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 61 62#define SLI2_IOCB_CMD_SIZE 32 63#define SLI2_IOCB_RSP_SIZE 32 64#define SLI3_IOCB_CMD_SIZE 128 65#define SLI3_IOCB_RSP_SIZE 64 66 67 68/* Common Transport structures and definitions */ 69 70union CtRevisionId { 71 /* Structure is in Big Endian format */ 72 struct { 73 uint32_t Revision:8; 74 uint32_t InId:24; 75 } bits; 76 uint32_t word; 77}; 78 79union CtCommandResponse { 80 /* Structure is in Big Endian format */ 81 struct { 82 uint32_t CmdRsp:16; 83 uint32_t Size:16; 84 } bits; 85 uint32_t word; 86}; 87 88#define FC4_FEATURE_INIT 0x2 89#define FC4_FEATURE_TARGET 0x1 90 91struct lpfc_sli_ct_request { 92 /* Structure is in Big Endian format */ 93 union CtRevisionId RevisionId; 94 uint8_t FsType; 95 uint8_t FsSubType; 96 uint8_t Options; 97 uint8_t Rsrvd1; 98 union CtCommandResponse CommandResponse; 99 uint8_t Rsrvd2; 100 uint8_t ReasonCode; 101 uint8_t Explanation; 102 uint8_t VendorUnique; 103 104 union { 105 uint32_t PortID; 106 struct gid { 107 uint8_t PortType; /* for GID_PT requests */ 108 uint8_t DomainScope; 109 uint8_t AreaScope; 110 uint8_t Fc4Type; /* for GID_FT requests */ 111 } gid; 112 struct rft { 113 uint32_t PortId; /* For RFT_ID requests */ 114 115#ifdef __BIG_ENDIAN_BITFIELD 116 uint32_t rsvd0:16; 117 uint32_t rsvd1:7; 118 uint32_t fcpReg:1; /* Type 8 */ 119 uint32_t rsvd2:2; 120 uint32_t ipReg:1; /* Type 5 */ 121 uint32_t rsvd3:5; 122#else /* __LITTLE_ENDIAN_BITFIELD */ 123 uint32_t rsvd0:16; 124 uint32_t fcpReg:1; /* Type 8 */ 125 uint32_t rsvd1:7; 126 uint32_t rsvd3:5; 127 uint32_t ipReg:1; /* Type 5 */ 128 uint32_t rsvd2:2; 129#endif 130 131 uint32_t rsvd[7]; 132 } rft; 133 struct rnn { 134 uint32_t PortId; /* For RNN_ID requests */ 135 uint8_t wwnn[8]; 136 } rnn; 137 struct rsnn { /* For RSNN_ID requests */ 138 uint8_t wwnn[8]; 139 uint8_t len; 140 uint8_t symbname[255]; 141 } rsnn; 142 struct da_id { /* For DA_ID requests */ 143 uint32_t port_id; 144 } da_id; 145 struct rspn { /* For RSPN_ID requests */ 146 uint32_t PortId; 147 uint8_t len; 148 uint8_t symbname[255]; 149 } rspn; 150 struct gff { 151 uint32_t PortId; 152 } gff; 153 struct gff_acc { 154 uint8_t fbits[128]; 155 } gff_acc; 156#define FCP_TYPE_FEATURE_OFFSET 7 157 struct rff { 158 uint32_t PortId; 159 uint8_t reserved[2]; 160 uint8_t fbits; 161 uint8_t type_code; /* type=8 for FCP */ 162 } rff; 163 } un; 164}; 165 166#define SLI_CT_REVISION 1 167#define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 168 sizeof(struct gid)) 169#define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 170 sizeof(struct gff)) 171#define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 172 sizeof(struct rft)) 173#define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 174 sizeof(struct rff)) 175#define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 176 sizeof(struct rnn)) 177#define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 178 sizeof(struct rsnn)) 179#define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 180 sizeof(struct da_id)) 181#define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 182 sizeof(struct rspn)) 183 184/* 185 * FsType Definitions 186 */ 187 188#define SLI_CT_MANAGEMENT_SERVICE 0xFA 189#define SLI_CT_TIME_SERVICE 0xFB 190#define SLI_CT_DIRECTORY_SERVICE 0xFC 191#define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 192 193/* 194 * Directory Service Subtypes 195 */ 196 197#define SLI_CT_DIRECTORY_NAME_SERVER 0x02 198 199/* 200 * Response Codes 201 */ 202 203#define SLI_CT_RESPONSE_FS_RJT 0x8001 204#define SLI_CT_RESPONSE_FS_ACC 0x8002 205 206/* 207 * Reason Codes 208 */ 209 210#define SLI_CT_NO_ADDITIONAL_EXPL 0x0 211#define SLI_CT_INVALID_COMMAND 0x01 212#define SLI_CT_INVALID_VERSION 0x02 213#define SLI_CT_LOGICAL_ERROR 0x03 214#define SLI_CT_INVALID_IU_SIZE 0x04 215#define SLI_CT_LOGICAL_BUSY 0x05 216#define SLI_CT_PROTOCOL_ERROR 0x07 217#define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 218#define SLI_CT_REQ_NOT_SUPPORTED 0x0b 219#define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 220#define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 221#define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 222#define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 223#define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 224#define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 225#define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 226#define SLI_CT_VENDOR_UNIQUE 0xff 227 228/* 229 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 230 */ 231 232#define SLI_CT_NO_PORT_ID 0x01 233#define SLI_CT_NO_PORT_NAME 0x02 234#define SLI_CT_NO_NODE_NAME 0x03 235#define SLI_CT_NO_CLASS_OF_SERVICE 0x04 236#define SLI_CT_NO_IP_ADDRESS 0x05 237#define SLI_CT_NO_IPA 0x06 238#define SLI_CT_NO_FC4_TYPES 0x07 239#define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 240#define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 241#define SLI_CT_NO_PORT_TYPE 0x0A 242#define SLI_CT_ACCESS_DENIED 0x10 243#define SLI_CT_INVALID_PORT_ID 0x11 244#define SLI_CT_DATABASE_EMPTY 0x12 245 246/* 247 * Name Server Command Codes 248 */ 249 250#define SLI_CTNS_GA_NXT 0x0100 251#define SLI_CTNS_GPN_ID 0x0112 252#define SLI_CTNS_GNN_ID 0x0113 253#define SLI_CTNS_GCS_ID 0x0114 254#define SLI_CTNS_GFT_ID 0x0117 255#define SLI_CTNS_GSPN_ID 0x0118 256#define SLI_CTNS_GPT_ID 0x011A 257#define SLI_CTNS_GFF_ID 0x011F 258#define SLI_CTNS_GID_PN 0x0121 259#define SLI_CTNS_GID_NN 0x0131 260#define SLI_CTNS_GIP_NN 0x0135 261#define SLI_CTNS_GIPA_NN 0x0136 262#define SLI_CTNS_GSNN_NN 0x0139 263#define SLI_CTNS_GNN_IP 0x0153 264#define SLI_CTNS_GIPA_IP 0x0156 265#define SLI_CTNS_GID_FT 0x0171 266#define SLI_CTNS_GID_PT 0x01A1 267#define SLI_CTNS_RPN_ID 0x0212 268#define SLI_CTNS_RNN_ID 0x0213 269#define SLI_CTNS_RCS_ID 0x0214 270#define SLI_CTNS_RFT_ID 0x0217 271#define SLI_CTNS_RSPN_ID 0x0218 272#define SLI_CTNS_RPT_ID 0x021A 273#define SLI_CTNS_RFF_ID 0x021F 274#define SLI_CTNS_RIP_NN 0x0235 275#define SLI_CTNS_RIPA_NN 0x0236 276#define SLI_CTNS_RSNN_NN 0x0239 277#define SLI_CTNS_DA_ID 0x0300 278 279/* 280 * Port Types 281 */ 282 283#define SLI_CTPT_N_PORT 0x01 284#define SLI_CTPT_NL_PORT 0x02 285#define SLI_CTPT_FNL_PORT 0x03 286#define SLI_CTPT_IP 0x04 287#define SLI_CTPT_FCP 0x08 288#define SLI_CTPT_NX_PORT 0x7F 289#define SLI_CTPT_F_PORT 0x81 290#define SLI_CTPT_FL_PORT 0x82 291#define SLI_CTPT_E_PORT 0x84 292 293#define SLI_CT_LAST_ENTRY 0x80000000 294 295/* Fibre Channel Service Parameter definitions */ 296 297#define FC_PH_4_0 6 /* FC-PH version 4.0 */ 298#define FC_PH_4_1 7 /* FC-PH version 4.1 */ 299#define FC_PH_4_2 8 /* FC-PH version 4.2 */ 300#define FC_PH_4_3 9 /* FC-PH version 4.3 */ 301 302#define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 303#define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 304#define FC_PH3 0x20 /* FC-PH-3 version */ 305 306#define FF_FRAME_SIZE 2048 307 308struct lpfc_name { 309 union { 310 struct { 311#ifdef __BIG_ENDIAN_BITFIELD 312 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 313 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 314 8:11 of IEEE ext */ 315#else /* __LITTLE_ENDIAN_BITFIELD */ 316 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 317 8:11 of IEEE ext */ 318 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 319#endif 320 321#define NAME_IEEE 0x1 /* IEEE name - nameType */ 322#define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 323#define NAME_FC_TYPE 0x3 /* FC native name type */ 324#define NAME_IP_TYPE 0x4 /* IP address */ 325#define NAME_CCITT_TYPE 0xC 326#define NAME_CCITT_GR_TYPE 0xE 327 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 328 extended Lsb */ 329 uint8_t IEEE[6]; /* FC IEEE address */ 330 } s; 331 uint8_t wwn[8]; 332 } u; 333}; 334 335struct csp { 336 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 337 uint8_t fcphLow; 338 uint8_t bbCreditMsb; 339 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 340 341#ifdef __BIG_ENDIAN_BITFIELD 342 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 343 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 344 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 345 uint16_t fPort:1; /* FC Word 1, bit 28 */ 346 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 347 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 348 uint16_t multicast:1; /* FC Word 1, bit 25 */ 349 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 350 351 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 352 uint16_t simplex:1; /* FC Word 1, bit 22 */ 353 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 354 uint16_t dhd:1; /* FC Word 1, bit 18 */ 355 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 356 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 357#else /* __LITTLE_ENDIAN_BITFIELD */ 358 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 359 uint16_t multicast:1; /* FC Word 1, bit 25 */ 360 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 361 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 362 uint16_t fPort:1; /* FC Word 1, bit 28 */ 363 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 364 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 365 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 366 367 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 368 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 369 uint16_t dhd:1; /* FC Word 1, bit 18 */ 370 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 371 uint16_t simplex:1; /* FC Word 1, bit 22 */ 372 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 373#endif 374 375 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 376 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 377 union { 378 struct { 379 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 380 381 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 382 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 383 384 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 385 } nPort; 386 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 387 } w2; 388 389 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 390}; 391 392struct class_parms { 393#ifdef __BIG_ENDIAN_BITFIELD 394 uint8_t classValid:1; /* FC Word 0, bit 31 */ 395 uint8_t intermix:1; /* FC Word 0, bit 30 */ 396 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 397 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 398 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 399 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 400#else /* __LITTLE_ENDIAN_BITFIELD */ 401 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 402 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 403 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 404 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 405 uint8_t intermix:1; /* FC Word 0, bit 30 */ 406 uint8_t classValid:1; /* FC Word 0, bit 31 */ 407 408#endif 409 410 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 411 412#ifdef __BIG_ENDIAN_BITFIELD 413 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 414 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 415 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 416 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 417 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 418#else /* __LITTLE_ENDIAN_BITFIELD */ 419 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 420 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 421 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 422 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 423 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 424#endif 425 426 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 427 428#ifdef __BIG_ENDIAN_BITFIELD 429 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 430 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 431 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 432 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 433 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 434 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 435#else /* __LITTLE_ENDIAN_BITFIELD */ 436 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 437 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 438 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 439 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 440 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 441 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 442#endif 443 444 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 445 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 446 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 447 448 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 449 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 450 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 451 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 452 453 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 454 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 455 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 456 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 457}; 458 459struct serv_parm { /* Structure is in Big Endian format */ 460 struct csp cmn; 461 struct lpfc_name portName; 462 struct lpfc_name nodeName; 463 struct class_parms cls1; 464 struct class_parms cls2; 465 struct class_parms cls3; 466 struct class_parms cls4; 467 uint8_t vendorVersion[16]; 468}; 469 470/* 471 * Extended Link Service LS_COMMAND codes (Payload Word 0) 472 */ 473#ifdef __BIG_ENDIAN_BITFIELD 474#define ELS_CMD_MASK 0xffff0000 475#define ELS_RSP_MASK 0xff000000 476#define ELS_CMD_LS_RJT 0x01000000 477#define ELS_CMD_ACC 0x02000000 478#define ELS_CMD_PLOGI 0x03000000 479#define ELS_CMD_FLOGI 0x04000000 480#define ELS_CMD_LOGO 0x05000000 481#define ELS_CMD_ABTX 0x06000000 482#define ELS_CMD_RCS 0x07000000 483#define ELS_CMD_RES 0x08000000 484#define ELS_CMD_RSS 0x09000000 485#define ELS_CMD_RSI 0x0A000000 486#define ELS_CMD_ESTS 0x0B000000 487#define ELS_CMD_ESTC 0x0C000000 488#define ELS_CMD_ADVC 0x0D000000 489#define ELS_CMD_RTV 0x0E000000 490#define ELS_CMD_RLS 0x0F000000 491#define ELS_CMD_ECHO 0x10000000 492#define ELS_CMD_TEST 0x11000000 493#define ELS_CMD_RRQ 0x12000000 494#define ELS_CMD_PRLI 0x20100014 495#define ELS_CMD_PRLO 0x21100014 496#define ELS_CMD_PRLO_ACC 0x02100014 497#define ELS_CMD_PDISC 0x50000000 498#define ELS_CMD_FDISC 0x51000000 499#define ELS_CMD_ADISC 0x52000000 500#define ELS_CMD_FARP 0x54000000 501#define ELS_CMD_FARPR 0x55000000 502#define ELS_CMD_RPS 0x56000000 503#define ELS_CMD_RPL 0x57000000 504#define ELS_CMD_FAN 0x60000000 505#define ELS_CMD_RSCN 0x61040000 506#define ELS_CMD_SCR 0x62000000 507#define ELS_CMD_RNID 0x78000000 508#define ELS_CMD_LIRR 0x7A000000 509#else /* __LITTLE_ENDIAN_BITFIELD */ 510#define ELS_CMD_MASK 0xffff 511#define ELS_RSP_MASK 0xff 512#define ELS_CMD_LS_RJT 0x01 513#define ELS_CMD_ACC 0x02 514#define ELS_CMD_PLOGI 0x03 515#define ELS_CMD_FLOGI 0x04 516#define ELS_CMD_LOGO 0x05 517#define ELS_CMD_ABTX 0x06 518#define ELS_CMD_RCS 0x07 519#define ELS_CMD_RES 0x08 520#define ELS_CMD_RSS 0x09 521#define ELS_CMD_RSI 0x0A 522#define ELS_CMD_ESTS 0x0B 523#define ELS_CMD_ESTC 0x0C 524#define ELS_CMD_ADVC 0x0D 525#define ELS_CMD_RTV 0x0E 526#define ELS_CMD_RLS 0x0F 527#define ELS_CMD_ECHO 0x10 528#define ELS_CMD_TEST 0x11 529#define ELS_CMD_RRQ 0x12 530#define ELS_CMD_PRLI 0x14001020 531#define ELS_CMD_PRLO 0x14001021 532#define ELS_CMD_PRLO_ACC 0x14001002 533#define ELS_CMD_PDISC 0x50 534#define ELS_CMD_FDISC 0x51 535#define ELS_CMD_ADISC 0x52 536#define ELS_CMD_FARP 0x54 537#define ELS_CMD_FARPR 0x55 538#define ELS_CMD_RPS 0x56 539#define ELS_CMD_RPL 0x57 540#define ELS_CMD_FAN 0x60 541#define ELS_CMD_RSCN 0x0461 542#define ELS_CMD_SCR 0x62 543#define ELS_CMD_RNID 0x78 544#define ELS_CMD_LIRR 0x7A 545#endif 546 547/* 548 * LS_RJT Payload Definition 549 */ 550 551struct ls_rjt { /* Structure is in Big Endian format */ 552 union { 553 uint32_t lsRjtError; 554 struct { 555 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 556 557 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 558 /* LS_RJT reason codes */ 559#define LSRJT_INVALID_CMD 0x01 560#define LSRJT_LOGICAL_ERR 0x03 561#define LSRJT_LOGICAL_BSY 0x05 562#define LSRJT_PROTOCOL_ERR 0x07 563#define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 564#define LSRJT_CMD_UNSUPPORTED 0x0B 565#define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 566 567 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 568 /* LS_RJT reason explanation */ 569#define LSEXP_NOTHING_MORE 0x00 570#define LSEXP_SPARM_OPTIONS 0x01 571#define LSEXP_SPARM_ICTL 0x03 572#define LSEXP_SPARM_RCTL 0x05 573#define LSEXP_SPARM_RCV_SIZE 0x07 574#define LSEXP_SPARM_CONCUR_SEQ 0x09 575#define LSEXP_SPARM_CREDIT 0x0B 576#define LSEXP_INVALID_PNAME 0x0D 577#define LSEXP_INVALID_NNAME 0x0E 578#define LSEXP_INVALID_CSP 0x0F 579#define LSEXP_INVALID_ASSOC_HDR 0x11 580#define LSEXP_ASSOC_HDR_REQ 0x13 581#define LSEXP_INVALID_O_SID 0x15 582#define LSEXP_INVALID_OX_RX 0x17 583#define LSEXP_CMD_IN_PROGRESS 0x19 584#define LSEXP_PORT_LOGIN_REQ 0x1E 585#define LSEXP_INVALID_NPORT_ID 0x1F 586#define LSEXP_INVALID_SEQ_ID 0x21 587#define LSEXP_INVALID_XCHG 0x23 588#define LSEXP_INACTIVE_XCHG 0x25 589#define LSEXP_RQ_REQUIRED 0x27 590#define LSEXP_OUT_OF_RESOURCE 0x29 591#define LSEXP_CANT_GIVE_DATA 0x2A 592#define LSEXP_REQ_UNSUPPORTED 0x2C 593 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 594 } b; 595 } un; 596}; 597 598/* 599 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 600 */ 601 602typedef struct _LOGO { /* Structure is in Big Endian format */ 603 union { 604 uint32_t nPortId32; /* Access nPortId as a word */ 605 struct { 606 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 607 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 608 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 609 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 610 } b; 611 } un; 612 struct lpfc_name portName; /* N_port name field */ 613} LOGO; 614 615/* 616 * FCP Login (PRLI Request / ACC) Payload Definition 617 */ 618 619#define PRLX_PAGE_LEN 0x10 620#define TPRLO_PAGE_LEN 0x14 621 622typedef struct _PRLI { /* Structure is in Big Endian format */ 623 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 624 625#define PRLI_FCP_TYPE 0x08 626 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 627 628#ifdef __BIG_ENDIAN_BITFIELD 629 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 630 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 631 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 632 633 /* ACC = imagePairEstablished */ 634 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 635 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 636#else /* __LITTLE_ENDIAN_BITFIELD */ 637 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 638 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 639 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 640 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 641 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 642 /* ACC = imagePairEstablished */ 643#endif 644 645#define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 646#define PRLI_NO_RESOURCES 0x2 647#define PRLI_INIT_INCOMPLETE 0x3 648#define PRLI_NO_SUCH_PA 0x4 649#define PRLI_PREDEF_CONFIG 0x5 650#define PRLI_PARTIAL_SUCCESS 0x6 651#define PRLI_INVALID_PAGE_CNT 0x7 652 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 653 654 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 655 656 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 657 658 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 659 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 660 661#ifdef __BIG_ENDIAN_BITFIELD 662 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 663 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 664 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 665 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 666 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 667 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 668 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 669 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 670 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 671 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 672 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 673 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 674 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 675 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 676 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 677 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 678#else /* __LITTLE_ENDIAN_BITFIELD */ 679 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 680 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 681 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 682 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 683 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 684 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 685 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 686 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 687 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 688 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 689 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 690 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 691 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 692 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 693 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 694 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 695#endif 696} PRLI; 697 698/* 699 * FCP Logout (PRLO Request / ACC) Payload Definition 700 */ 701 702typedef struct _PRLO { /* Structure is in Big Endian format */ 703 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 704 705#define PRLO_FCP_TYPE 0x08 706 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 707 708#ifdef __BIG_ENDIAN_BITFIELD 709 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 710 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 711 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 712 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 713#else /* __LITTLE_ENDIAN_BITFIELD */ 714 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 715 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 716 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 717 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 718#endif 719 720#define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 721#define PRLO_NO_SUCH_IMAGE 0x4 722#define PRLO_INVALID_PAGE_CNT 0x7 723 724 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 725 726 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 727 728 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 729 730 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 731} PRLO; 732 733typedef struct _ADISC { /* Structure is in Big Endian format */ 734 uint32_t hardAL_PA; 735 struct lpfc_name portName; 736 struct lpfc_name nodeName; 737 uint32_t DID; 738} ADISC; 739 740typedef struct _FARP { /* Structure is in Big Endian format */ 741 uint32_t Mflags:8; 742 uint32_t Odid:24; 743#define FARP_NO_ACTION 0 /* FARP information enclosed, no 744 action */ 745#define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 746#define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 747#define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 748#define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 749 supported */ 750#define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 751 supported */ 752 uint32_t Rflags:8; 753 uint32_t Rdid:24; 754#define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 755#define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 756 struct lpfc_name OportName; 757 struct lpfc_name OnodeName; 758 struct lpfc_name RportName; 759 struct lpfc_name RnodeName; 760 uint8_t Oipaddr[16]; 761 uint8_t Ripaddr[16]; 762} FARP; 763 764typedef struct _FAN { /* Structure is in Big Endian format */ 765 uint32_t Fdid; 766 struct lpfc_name FportName; 767 struct lpfc_name FnodeName; 768} FAN; 769 770typedef struct _SCR { /* Structure is in Big Endian format */ 771 uint8_t resvd1; 772 uint8_t resvd2; 773 uint8_t resvd3; 774 uint8_t Function; 775#define SCR_FUNC_FABRIC 0x01 776#define SCR_FUNC_NPORT 0x02 777#define SCR_FUNC_FULL 0x03 778#define SCR_CLEAR 0xff 779} SCR; 780 781typedef struct _RNID_TOP_DISC { 782 struct lpfc_name portName; 783 uint8_t resvd[8]; 784 uint32_t unitType; 785#define RNID_HBA 0x7 786#define RNID_HOST 0xa 787#define RNID_DRIVER 0xd 788 uint32_t physPort; 789 uint32_t attachedNodes; 790 uint16_t ipVersion; 791#define RNID_IPV4 0x1 792#define RNID_IPV6 0x2 793 uint16_t UDPport; 794 uint8_t ipAddr[16]; 795 uint16_t resvd1; 796 uint16_t flags; 797#define RNID_TD_SUPPORT 0x1 798#define RNID_LP_VALID 0x2 799} RNID_TOP_DISC; 800 801typedef struct _RNID { /* Structure is in Big Endian format */ 802 uint8_t Format; 803#define RNID_TOPOLOGY_DISC 0xdf 804 uint8_t CommonLen; 805 uint8_t resvd1; 806 uint8_t SpecificLen; 807 struct lpfc_name portName; 808 struct lpfc_name nodeName; 809 union { 810 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 811 } un; 812} RNID; 813 814typedef struct _RPS { /* Structure is in Big Endian format */ 815 union { 816 uint32_t portNum; 817 struct lpfc_name portName; 818 } un; 819} RPS; 820 821typedef struct _RPS_RSP { /* Structure is in Big Endian format */ 822 uint16_t rsvd1; 823 uint16_t portStatus; 824 uint32_t linkFailureCnt; 825 uint32_t lossSyncCnt; 826 uint32_t lossSignalCnt; 827 uint32_t primSeqErrCnt; 828 uint32_t invalidXmitWord; 829 uint32_t crcCnt; 830} RPS_RSP; 831 832typedef struct _RPL { /* Structure is in Big Endian format */ 833 uint32_t maxsize; 834 uint32_t index; 835} RPL; 836 837typedef struct _PORT_NUM_BLK { 838 uint32_t portNum; 839 uint32_t portID; 840 struct lpfc_name portName; 841} PORT_NUM_BLK; 842 843typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 844 uint32_t listLen; 845 uint32_t index; 846 PORT_NUM_BLK port_num_blk; 847} RPL_RSP; 848 849/* This is used for RSCN command */ 850typedef struct _D_ID { /* Structure is in Big Endian format */ 851 union { 852 uint32_t word; 853 struct { 854#ifdef __BIG_ENDIAN_BITFIELD 855 uint8_t resv; 856 uint8_t domain; 857 uint8_t area; 858 uint8_t id; 859#else /* __LITTLE_ENDIAN_BITFIELD */ 860 uint8_t id; 861 uint8_t area; 862 uint8_t domain; 863 uint8_t resv; 864#endif 865 } b; 866 } un; 867} D_ID; 868 869/* 870 * Structure to define all ELS Payload types 871 */ 872 873typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 874 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 875 uint8_t elsByte1; 876 uint8_t elsByte2; 877 uint8_t elsByte3; 878 union { 879 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 880 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 881 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 882 PRLI prli; /* Payload for PRLI/ACC */ 883 PRLO prlo; /* Payload for PRLO/ACC */ 884 ADISC adisc; /* Payload for ADISC/ACC */ 885 FARP farp; /* Payload for FARP/ACC */ 886 FAN fan; /* Payload for FAN */ 887 SCR scr; /* Payload for SCR/ACC */ 888 RNID rnid; /* Payload for RNID */ 889 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 890 } un; 891} ELS_PKT; 892 893/* 894 * FDMI 895 * HBA MAnagement Operations Command Codes 896 */ 897#define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 898#define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 899#define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 900#define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 901#define SLI_MGMT_RHBA 0x200 /* Register HBA */ 902#define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 903#define SLI_MGMT_RPRT 0x210 /* Register Port */ 904#define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 905#define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 906#define SLI_MGMT_DPRT 0x310 /* De-register Port */ 907 908/* 909 * Management Service Subtypes 910 */ 911#define SLI_CT_FDMI_Subtypes 0x10 912 913/* 914 * HBA Management Service Reject Code 915 */ 916#define REJECT_CODE 0x9 /* Unable to perform command request */ 917 918/* 919 * HBA Management Service Reject Reason Code 920 * Please refer to the Reason Codes above 921 */ 922 923/* 924 * HBA Attribute Types 925 */ 926#define NODE_NAME 0x1 927#define MANUFACTURER 0x2 928#define SERIAL_NUMBER 0x3 929#define MODEL 0x4 930#define MODEL_DESCRIPTION 0x5 931#define HARDWARE_VERSION 0x6 932#define DRIVER_VERSION 0x7 933#define OPTION_ROM_VERSION 0x8 934#define FIRMWARE_VERSION 0x9 935#define OS_NAME_VERSION 0xa 936#define MAX_CT_PAYLOAD_LEN 0xb 937 938/* 939 * Port Attrubute Types 940 */ 941#define SUPPORTED_FC4_TYPES 0x1 942#define SUPPORTED_SPEED 0x2 943#define PORT_SPEED 0x3 944#define MAX_FRAME_SIZE 0x4 945#define OS_DEVICE_NAME 0x5 946#define HOST_NAME 0x6 947 948union AttributesDef { 949 /* Structure is in Big Endian format */ 950 struct { 951 uint32_t AttrType:16; 952 uint32_t AttrLen:16; 953 } bits; 954 uint32_t word; 955}; 956 957 958/* 959 * HBA Attribute Entry (8 - 260 bytes) 960 */ 961typedef struct { 962 union AttributesDef ad; 963 union { 964 uint32_t VendorSpecific; 965 uint8_t Manufacturer[64]; 966 uint8_t SerialNumber[64]; 967 uint8_t Model[256]; 968 uint8_t ModelDescription[256]; 969 uint8_t HardwareVersion[256]; 970 uint8_t DriverVersion[256]; 971 uint8_t OptionROMVersion[256]; 972 uint8_t FirmwareVersion[256]; 973 struct lpfc_name NodeName; 974 uint8_t SupportFC4Types[32]; 975 uint32_t SupportSpeed; 976 uint32_t PortSpeed; 977 uint32_t MaxFrameSize; 978 uint8_t OsDeviceName[256]; 979 uint8_t OsNameVersion[256]; 980 uint32_t MaxCTPayloadLen; 981 uint8_t HostName[256]; 982 } un; 983} ATTRIBUTE_ENTRY; 984 985/* 986 * HBA Attribute Block 987 */ 988typedef struct { 989 uint32_t EntryCnt; /* Number of HBA attribute entries */ 990 ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 991} ATTRIBUTE_BLOCK; 992 993/* 994 * Port Entry 995 */ 996typedef struct { 997 struct lpfc_name PortName; 998} PORT_ENTRY; 999 1000/*
1001 * HBA Identifier 1002 */ 1003typedef struct { 1004 struct lpfc_name PortName; 1005} HBA_IDENTIFIER; 1006 1007/* 1008 * Registered Port List Format 1009 */ 1010typedef struct { 1011 uint32_t EntryCnt; 1012 PORT_ENTRY pe; /* Variable-length array */ 1013} REG_PORT_LIST; 1014 1015/* 1016 * Register HBA(RHBA) 1017 */ 1018typedef struct { 1019 HBA_IDENTIFIER hi; 1020 REG_PORT_LIST rpl; /* variable-length array */ 1021/* ATTRIBUTE_BLOCK ab; */ 1022} REG_HBA; 1023 1024/* 1025 * Register HBA Attributes (RHAT) 1026 */ 1027typedef struct { 1028 struct lpfc_name HBA_PortName; 1029 ATTRIBUTE_BLOCK ab; 1030} REG_HBA_ATTRIBUTE; 1031 1032/* 1033 * Register Port Attributes (RPA) 1034 */ 1035typedef struct { 1036 struct lpfc_name PortName; 1037 ATTRIBUTE_BLOCK ab; 1038} REG_PORT_ATTRIBUTE; 1039 1040/* 1041 * Get Registered HBA List (GRHL) Accept Payload Format 1042 */ 1043typedef struct { 1044 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */ 1045 struct lpfc_name HBA_PortName; /* Variable-length array */ 1046} GRHL_ACC_PAYLOAD; 1047 1048/* 1049 * Get Registered Port List (GRPL) Accept Payload Format 1050 */ 1051typedef struct { 1052 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */ 1053 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */ 1054} GRPL_ACC_PAYLOAD; 1055 1056/* 1057 * Get Port Attributes (GPAT) Accept Payload Format 1058 */ 1059 1060typedef struct { 1061 ATTRIBUTE_BLOCK pab; 1062} GPAT_ACC_PAYLOAD; 1063 1064 1065/* 1066 * Begin HBA configuration parameters. 1067 * The PCI configuration register BAR assignments are: 1068 * BAR0, offset 0x10 - SLIM base memory address 1069 * BAR1, offset 0x14 - SLIM base memory high address 1070 * BAR2, offset 0x18 - REGISTER base memory address 1071 * BAR3, offset 0x1c - REGISTER base memory high address 1072 * BAR4, offset 0x20 - BIU I/O registers 1073 * BAR5, offset 0x24 - REGISTER base io high address 1074 */ 1075 1076/* Number of rings currently used and available. */ 1077#define MAX_CONFIGURED_RINGS 3 1078#define MAX_RINGS 4 1079 1080/* IOCB / Mailbox is owned by FireFly */ 1081#define OWN_CHIP 1 1082 1083/* IOCB / Mailbox is owned by Host */ 1084#define OWN_HOST 0 1085 1086/* Number of 4-byte words in an IOCB. */ 1087#define IOCB_WORD_SZ 8 1088 1089/* defines for type field in fc header */ 1090#define FC_ELS_DATA 0x1 1091#define FC_LLC_SNAP 0x5 1092#define FC_FCP_DATA 0x8 1093#define FC_COMMON_TRANSPORT_ULP 0x20 1094 1095/* defines for rctl field in fc header */ 1096#define FC_DEV_DATA 0x0 1097#define FC_UNSOL_CTL 0x2 1098#define FC_SOL_CTL 0x3 1099#define FC_UNSOL_DATA 0x4 1100#define FC_FCP_CMND 0x6 1101#define FC_ELS_REQ 0x22 1102#define FC_ELS_RSP 0x23 1103 1104/* network headers for Dfctl field */ 1105#define FC_NET_HDR 0x20 1106 1107/* Start FireFly Register definitions */ 1108#define PCI_VENDOR_ID_EMULEX 0x10df 1109#define PCI_DEVICE_ID_FIREFLY 0x1ae5 1110#define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1111#define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1112#define PCI_DEVICE_ID_SAT_SMB 0xf011 1113#define PCI_DEVICE_ID_SAT_MID 0xf015 1114#define PCI_DEVICE_ID_RFLY 0xf095 1115#define PCI_DEVICE_ID_PFLY 0xf098 1116#define PCI_DEVICE_ID_LP101 0xf0a1 1117#define PCI_DEVICE_ID_TFLY 0xf0a5 1118#define PCI_DEVICE_ID_BSMB 0xf0d1 1119#define PCI_DEVICE_ID_BMID 0xf0d5 1120#define PCI_DEVICE_ID_ZSMB 0xf0e1 1121#define PCI_DEVICE_ID_ZMID 0xf0e5 1122#define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1123#define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1124#define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1125#define PCI_DEVICE_ID_SAT 0xf100 1126#define PCI_DEVICE_ID_SAT_SCSP 0xf111 1127#define PCI_DEVICE_ID_SAT_DCSP 0xf112 1128#define PCI_DEVICE_ID_SUPERFLY 0xf700 1129#define PCI_DEVICE_ID_DRAGONFLY 0xf800 1130#define PCI_DEVICE_ID_CENTAUR 0xf900 1131#define PCI_DEVICE_ID_PEGASUS 0xf980 1132#define PCI_DEVICE_ID_THOR 0xfa00 1133#define PCI_DEVICE_ID_VIPER 0xfb00 1134#define PCI_DEVICE_ID_LP10000S 0xfc00 1135#define PCI_DEVICE_ID_LP11000S 0xfc10 1136#define PCI_DEVICE_ID_LPE11000S 0xfc20 1137#define PCI_DEVICE_ID_SAT_S 0xfc40 1138#define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1139#define PCI_DEVICE_ID_HELIOS 0xfd00 1140#define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1141#define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1142#define PCI_DEVICE_ID_ZEPHYR 0xfe00 1143#define PCI_DEVICE_ID_HORNET 0xfe05 1144#define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1145#define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1146 1147#define JEDEC_ID_ADDRESS 0x0080001c 1148#define FIREFLY_JEDEC_ID 0x1ACC 1149#define SUPERFLY_JEDEC_ID 0x0020 1150#define DRAGONFLY_JEDEC_ID 0x0021 1151#define DRAGONFLY_V2_JEDEC_ID 0x0025 1152#define CENTAUR_2G_JEDEC_ID 0x0026 1153#define CENTAUR_1G_JEDEC_ID 0x0028 1154#define PEGASUS_ORION_JEDEC_ID 0x0036 1155#define PEGASUS_JEDEC_ID 0x0038 1156#define THOR_JEDEC_ID 0x0012 1157#define HELIOS_JEDEC_ID 0x0364 1158#define ZEPHYR_JEDEC_ID 0x0577 1159#define VIPER_JEDEC_ID 0x4838 1160#define SATURN_JEDEC_ID 0x1004 1161#define HORNET_JDEC_ID 0x2057706D 1162 1163#define JEDEC_ID_MASK 0x0FFFF000 1164#define JEDEC_ID_SHIFT 12 1165#define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1166 1167typedef struct { /* FireFly BIU registers */ 1168 uint32_t hostAtt; /* See definitions for Host Attention 1169 register */ 1170 uint32_t chipAtt; /* See definitions for Chip Attention 1171 register */ 1172 uint32_t hostStatus; /* See definitions for Host Status register */ 1173 uint32_t hostControl; /* See definitions for Host Control register */ 1174 uint32_t buiConfig; /* See definitions for BIU configuration 1175 register */ 1176} FF_REGS; 1177 1178/* IO Register size in bytes */ 1179#define FF_REG_AREA_SIZE 256 1180 1181/* Host Attention Register */ 1182 1183#define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1184 1185#define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1186#define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1187#define HA_R0ATT 0x00000008 /* Bit 3 */ 1188#define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1189#define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1190#define HA_R1ATT 0x00000080 /* Bit 7 */ 1191#define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1192#define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1193#define HA_R2ATT 0x00000800 /* Bit 11 */ 1194#define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1195#define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1196#define HA_R3ATT 0x00008000 /* Bit 15 */ 1197#define HA_LATT 0x20000000 /* Bit 29 */ 1198#define HA_MBATT 0x40000000 /* Bit 30 */ 1199#define HA_ERATT 0x80000000 /* Bit 31 */ 1200 1201#define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1202#define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1203#define HA_RXATT 0x00000008 /* Bit 3 */ 1204#define HA_RXMASK 0x0000000f 1205 1206#define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 1207#define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 1208#define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 1209#define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 1210 1211#define HA_R0_POS 3 1212#define HA_R1_POS 7 1213#define HA_R2_POS 11 1214#define HA_R3_POS 15 1215#define HA_LE_POS 29 1216#define HA_MB_POS 30 1217#define HA_ER_POS 31 1218/* Chip Attention Register */ 1219 1220#define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1221 1222#define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1223#define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1224#define CA_R0ATT 0x00000008 /* Bit 3 */ 1225#define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1226#define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1227#define CA_R1ATT 0x00000080 /* Bit 7 */ 1228#define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1229#define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1230#define CA_R2ATT 0x00000800 /* Bit 11 */ 1231#define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1232#define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1233#define CA_R3ATT 0x00008000 /* Bit 15 */ 1234#define CA_MBATT 0x40000000 /* Bit 30 */ 1235 1236/* Host Status Register */ 1237 1238#define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1239 1240#define HS_MBRDY 0x00400000 /* Bit 22 */ 1241#define HS_FFRDY 0x00800000 /* Bit 23 */ 1242#define HS_FFER8 0x01000000 /* Bit 24 */ 1243#define HS_FFER7 0x02000000 /* Bit 25 */ 1244#define HS_FFER6 0x04000000 /* Bit 26 */ 1245#define HS_FFER5 0x08000000 /* Bit 27 */ 1246#define HS_FFER4 0x10000000 /* Bit 28 */ 1247#define HS_FFER3 0x20000000 /* Bit 29 */ 1248#define HS_FFER2 0x40000000 /* Bit 30 */ 1249#define HS_FFER1 0x80000000 /* Bit 31 */ 1250#define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1251#define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1252 1253/* Host Control Register */ 1254 1255#define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1256 1257#define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1258#define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1259#define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1260#define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1261#define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1262#define HC_INITHBI 0x02000000 /* Bit 25 */ 1263#define HC_INITMB 0x04000000 /* Bit 26 */ 1264#define HC_INITFF 0x08000000 /* Bit 27 */ 1265#define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1266#define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1267 1268/* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 1269#define MSIX_DFLT_ID 0 1270#define MSIX_RNG0_ID 0 1271#define MSIX_RNG1_ID 1 1272#define MSIX_RNG2_ID 2 1273#define MSIX_RNG3_ID 3 1274 1275#define MSIX_LINK_ID 4 1276#define MSIX_MBOX_ID 5 1277 1278#define MSIX_SPARE0_ID 6 1279#define MSIX_SPARE1_ID 7 1280 1281/* Mailbox Commands */ 1282#define MBX_SHUTDOWN 0x00 /* terminate testing */ 1283#define MBX_LOAD_SM 0x01 1284#define MBX_READ_NV 0x02 1285#define MBX_WRITE_NV 0x03 1286#define MBX_RUN_BIU_DIAG 0x04 1287#define MBX_INIT_LINK 0x05 1288#define MBX_DOWN_LINK 0x06 1289#define MBX_CONFIG_LINK 0x07 1290#define MBX_CONFIG_RING 0x09 1291#define MBX_RESET_RING 0x0A 1292#define MBX_READ_CONFIG 0x0B 1293#define MBX_READ_RCONFIG 0x0C 1294#define MBX_READ_SPARM 0x0D 1295#define MBX_READ_STATUS 0x0E 1296#define MBX_READ_RPI 0x0F 1297#define MBX_READ_XRI 0x10 1298#define MBX_READ_REV 0x11 1299#define MBX_READ_LNK_STAT 0x12 1300#define MBX_REG_LOGIN 0x13 1301#define MBX_UNREG_LOGIN 0x14 1302#define MBX_READ_LA 0x15 1303#define MBX_CLEAR_LA 0x16 1304#define MBX_DUMP_MEMORY 0x17 1305#define MBX_DUMP_CONTEXT 0x18 1306#define MBX_RUN_DIAGS 0x19 1307#define MBX_RESTART 0x1A 1308#define MBX_UPDATE_CFG 0x1B 1309#define MBX_DOWN_LOAD 0x1C 1310#define MBX_DEL_LD_ENTRY 0x1D 1311#define MBX_RUN_PROGRAM 0x1E 1312#define MBX_SET_MASK 0x20 1313#define MBX_SET_VARIABLE 0x21 1314#define MBX_UNREG_D_ID 0x23 1315#define MBX_KILL_BOARD 0x24 1316#define MBX_CONFIG_FARP 0x25 1317#define MBX_BEACON 0x2A 1318#define MBX_CONFIG_MSI 0x30 1319#define MBX_HEARTBEAT 0x31 1320#define MBX_WRITE_VPARMS 0x32 1321#define MBX_ASYNCEVT_ENABLE 0x33 1322 1323#define MBX_PORT_CAPABILITIES 0x3B 1324#define MBX_PORT_IOV_CONTROL 0x3C 1325 1326#define MBX_CONFIG_HBQ 0x7C 1327#define MBX_LOAD_AREA 0x81 1328#define MBX_RUN_BIU_DIAG64 0x84 1329#define MBX_CONFIG_PORT 0x88 1330#define MBX_READ_SPARM64 0x8D 1331#define MBX_READ_RPI64 0x8F 1332#define MBX_REG_LOGIN64 0x93 1333#define MBX_READ_LA64 0x95 1334#define MBX_REG_VPI 0x96 1335#define MBX_UNREG_VPI 0x97 1336#define MBX_REG_VNPID 0x96 1337#define MBX_UNREG_VNPID 0x97 1338 1339#define MBX_WRITE_WWN 0x98 1340#define MBX_SET_DEBUG 0x99 1341#define MBX_LOAD_EXP_ROM 0x9C 1342 1343#define MBX_MAX_CMDS 0x9D 1344#define MBX_SLI2_CMD_MASK 0x80 1345 1346/* IOCB Commands */ 1347 1348#define CMD_RCV_SEQUENCE_CX 0x01 1349#define CMD_XMIT_SEQUENCE_CR 0x02 1350#define CMD_XMIT_SEQUENCE_CX 0x03 1351#define CMD_XMIT_BCAST_CN 0x04 1352#define CMD_XMIT_BCAST_CX 0x05 1353#define CMD_QUE_RING_BUF_CN 0x06 1354#define CMD_QUE_XRI_BUF_CX 0x07 1355#define CMD_IOCB_CONTINUE_CN 0x08 1356#define CMD_RET_XRI_BUF_CX 0x09 1357#define CMD_ELS_REQUEST_CR 0x0A 1358#define CMD_ELS_REQUEST_CX 0x0B 1359#define CMD_RCV_ELS_REQ_CX 0x0D 1360#define CMD_ABORT_XRI_CN 0x0E 1361#define CMD_ABORT_XRI_CX 0x0F 1362#define CMD_CLOSE_XRI_CN 0x10 1363#define CMD_CLOSE_XRI_CX 0x11 1364#define CMD_CREATE_XRI_CR 0x12 1365#define CMD_CREATE_XRI_CX 0x13 1366#define CMD_GET_RPI_CN 0x14 1367#define CMD_XMIT_ELS_RSP_CX 0x15 1368#define CMD_GET_RPI_CR 0x16 1369#define CMD_XRI_ABORTED_CX 0x17 1370#define CMD_FCP_IWRITE_CR 0x18 1371#define CMD_FCP_IWRITE_CX 0x19 1372#define CMD_FCP_IREAD_CR 0x1A 1373#define CMD_FCP_IREAD_CX 0x1B 1374#define CMD_FCP_ICMND_CR 0x1C 1375#define CMD_FCP_ICMND_CX 0x1D 1376#define CMD_FCP_TSEND_CX 0x1F 1377#define CMD_FCP_TRECEIVE_CX 0x21 1378#define CMD_FCP_TRSP_CX 0x23 1379#define CMD_FCP_AUTO_TRSP_CX 0x29 1380 1381#define CMD_ADAPTER_MSG 0x20 1382#define CMD_ADAPTER_DUMP 0x22 1383 1384/* SLI_2 IOCB Command Set */ 1385 1386#define CMD_ASYNC_STATUS 0x7C 1387#define CMD_RCV_SEQUENCE64_CX 0x81 1388#define CMD_XMIT_SEQUENCE64_CR 0x82 1389#define CMD_XMIT_SEQUENCE64_CX 0x83 1390#define CMD_XMIT_BCAST64_CN 0x84 1391#define CMD_XMIT_BCAST64_CX 0x85 1392#define CMD_QUE_RING_BUF64_CN 0x86 1393#define CMD_QUE_XRI_BUF64_CX 0x87 1394#define CMD_IOCB_CONTINUE64_CN 0x88 1395#define CMD_RET_XRI_BUF64_CX 0x89 1396#define CMD_ELS_REQUEST64_CR 0x8A 1397#define CMD_ELS_REQUEST64_CX 0x8B 1398#define CMD_ABORT_MXRI64_CN 0x8C 1399#define CMD_RCV_ELS_REQ64_CX 0x8D 1400#define CMD_XMIT_ELS_RSP64_CX 0x95 1401#define CMD_FCP_IWRITE64_CR 0x98 1402#define CMD_FCP_IWRITE64_CX 0x99 1403#define CMD_FCP_IREAD64_CR 0x9A 1404#define CMD_FCP_IREAD64_CX 0x9B 1405#define CMD_FCP_ICMND64_CR 0x9C 1406#define CMD_FCP_ICMND64_CX 0x9D 1407#define CMD_FCP_TSEND64_CX 0x9F 1408#define CMD_FCP_TRECEIVE64_CX 0xA1 1409#define CMD_FCP_TRSP64_CX 0xA3 1410 1411#define CMD_QUE_XRI64_CX 0xB3 1412#define CMD_IOCB_RCV_SEQ64_CX 0xB5 1413#define CMD_IOCB_RCV_ELS64_CX 0xB7 1414#define CMD_IOCB_RET_XRI64_CX 0xB9 1415#define CMD_IOCB_RCV_CONT64_CX 0xBB 1416 1417#define CMD_GEN_REQUEST64_CR 0xC2 1418#define CMD_GEN_REQUEST64_CX 0xC3 1419 1420/* Unhandled SLI-3 Commands */ 1421#define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 1422#define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 1423#define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 1424#define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 1425#define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 1426#define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 1427#define CMD_IOCB_RET_HBQE64_CN 0xCA 1428#define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 1429#define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 1430#define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 1431#define CMD_IOCB_LOGENTRY_CN 0x94 1432#define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 1433 1434#define CMD_MAX_IOCB_CMD 0xE6 1435#define CMD_IOCB_MASK 0xff 1436 1437#define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1438 iocb */ 1439#define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1440/* 1441 * Define Status 1442 */ 1443#define MBX_SUCCESS 0 1444#define MBXERR_NUM_RINGS 1 1445#define MBXERR_NUM_IOCBS 2 1446#define MBXERR_IOCBS_EXCEEDED 3 1447#define MBXERR_BAD_RING_NUMBER 4 1448#define MBXERR_MASK_ENTRIES_RANGE 5 1449#define MBXERR_MASKS_EXCEEDED 6 1450#define MBXERR_BAD_PROFILE 7 1451#define MBXERR_BAD_DEF_CLASS 8 1452#define MBXERR_BAD_MAX_RESPONDER 9 1453#define MBXERR_BAD_MAX_ORIGINATOR 10 1454#define MBXERR_RPI_REGISTERED 11 1455#define MBXERR_RPI_FULL 12 1456#define MBXERR_NO_RESOURCES 13 1457#define MBXERR_BAD_RCV_LENGTH 14 1458#define MBXERR_DMA_ERROR 15 1459#define MBXERR_ERROR 16 1460#define MBX_NOT_FINISHED 255 1461 1462#define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1463#define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1464 1465#define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 1466 1467/* 1468 * Begin Structure Definitions for Mailbox Commands 1469 */ 1470 1471typedef struct { 1472#ifdef __BIG_ENDIAN_BITFIELD 1473 uint8_t tval; 1474 uint8_t tmask; 1475 uint8_t rval; 1476 uint8_t rmask; 1477#else /* __LITTLE_ENDIAN_BITFIELD */ 1478 uint8_t rmask; 1479 uint8_t rval; 1480 uint8_t tmask; 1481 uint8_t tval; 1482#endif 1483} RR_REG; 1484 1485struct ulp_bde { 1486 uint32_t bdeAddress; 1487#ifdef __BIG_ENDIAN_BITFIELD 1488 uint32_t bdeReserved:4; 1489 uint32_t bdeAddrHigh:4; 1490 uint32_t bdeSize:24; 1491#else /* __LITTLE_ENDIAN_BITFIELD */ 1492 uint32_t bdeSize:24; 1493 uint32_t bdeAddrHigh:4; 1494 uint32_t bdeReserved:4; 1495#endif 1496}; 1497 1498struct ulp_bde64 { /* SLI-2 */ 1499 union ULP_BDE_TUS { 1500 uint32_t w; 1501 struct { 1502#ifdef __BIG_ENDIAN_BITFIELD 1503 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 1504 VALUE !! */ 1505 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1506#else /* __LITTLE_ENDIAN_BITFIELD */ 1507 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1508 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 1509 VALUE !! */ 1510#endif 1511#define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 1512#define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 1513#define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 1514#define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 1515#define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 1516#define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 1517#define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 1518 } f; 1519 } tus; 1520 uint32_t addrLow; 1521 uint32_t addrHigh; 1522}; 1523 1524typedef struct ULP_BDL { /* SLI-2 */ 1525#ifdef __BIG_ENDIAN_BITFIELD 1526 uint32_t bdeFlags:8; /* BDL Flags */ 1527 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1528#else /* __LITTLE_ENDIAN_BITFIELD */ 1529 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1530 uint32_t bdeFlags:8; /* BDL Flags */ 1531#endif 1532 1533 uint32_t addrLow; /* Address 0:31 */ 1534 uint32_t addrHigh; /* Address 32:63 */ 1535 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1536} ULP_BDL; 1537 1538/* Structure for MB Command LOAD_SM and DOWN_LOAD */ 1539 1540typedef struct { 1541#ifdef __BIG_ENDIAN_BITFIELD 1542 uint32_t rsvd2:25; 1543 uint32_t acknowledgment:1; 1544 uint32_t version:1; 1545 uint32_t erase_or_prog:1; 1546 uint32_t update_flash:1; 1547 uint32_t update_ram:1; 1548 uint32_t method:1; 1549 uint32_t load_cmplt:1; 1550#else /* __LITTLE_ENDIAN_BITFIELD */ 1551 uint32_t load_cmplt:1; 1552 uint32_t method:1; 1553 uint32_t update_ram:1; 1554 uint32_t update_flash:1; 1555 uint32_t erase_or_prog:1; 1556 uint32_t version:1; 1557 uint32_t acknowledgment:1; 1558 uint32_t rsvd2:25; 1559#endif 1560 1561 uint32_t dl_to_adr_low; 1562 uint32_t dl_to_adr_high; 1563 uint32_t dl_len; 1564 union { 1565 uint32_t dl_from_mbx_offset; 1566 struct ulp_bde dl_from_bde; 1567 struct ulp_bde64 dl_from_bde64; 1568 } un; 1569 1570} LOAD_SM_VAR; 1571 1572/* Structure for MB Command READ_NVPARM (02) */ 1573 1574typedef struct { 1575 uint32_t rsvd1[3]; /* Read as all one's */ 1576 uint32_t rsvd2; /* Read as all zero's */ 1577 uint32_t portname[2]; /* N_PORT name */ 1578 uint32_t nodename[2]; /* NODE name */ 1579 1580#ifdef __BIG_ENDIAN_BITFIELD 1581 uint32_t pref_DID:24; 1582 uint32_t hardAL_PA:8; 1583#else /* __LITTLE_ENDIAN_BITFIELD */ 1584 uint32_t hardAL_PA:8; 1585 uint32_t pref_DID:24; 1586#endif 1587 1588 uint32_t rsvd3[21]; /* Read as all one's */ 1589} READ_NV_VAR; 1590 1591/* Structure for MB Command WRITE_NVPARMS (03) */ 1592 1593typedef struct { 1594 uint32_t rsvd1[3]; /* Must be all one's */ 1595 uint32_t rsvd2; /* Must be all zero's */ 1596 uint32_t portname[2]; /* N_PORT name */ 1597 uint32_t nodename[2]; /* NODE name */ 1598 1599#ifdef __BIG_ENDIAN_BITFIELD 1600 uint32_t pref_DID:24; 1601 uint32_t hardAL_PA:8; 1602#else /* __LITTLE_ENDIAN_BITFIELD */ 1603 uint32_t hardAL_PA:8; 1604 uint32_t pref_DID:24; 1605#endif 1606 1607 uint32_t rsvd3[21]; /* Must be all one's */ 1608} WRITE_NV_VAR; 1609 1610/* Structure for MB Command RUN_BIU_DIAG (04) */ 1611/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 1612 1613typedef struct { 1614 uint32_t rsvd1; 1615 union { 1616 struct { 1617 struct ulp_bde xmit_bde; 1618 struct ulp_bde rcv_bde; 1619 } s1; 1620 struct { 1621 struct ulp_bde64 xmit_bde64; 1622 struct ulp_bde64 rcv_bde64; 1623 } s2; 1624 } un; 1625} BIU_DIAG_VAR; 1626 1627/* Structure for MB Command INIT_LINK (05) */ 1628 1629typedef struct { 1630#ifdef __BIG_ENDIAN_BITFIELD 1631 uint32_t rsvd1:24; 1632 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1633#else /* __LITTLE_ENDIAN_BITFIELD */ 1634 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1635 uint32_t rsvd1:24; 1636#endif 1637 1638#ifdef __BIG_ENDIAN_BITFIELD 1639 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1640 uint8_t rsvd2; 1641 uint16_t link_flags; 1642#else /* __LITTLE_ENDIAN_BITFIELD */ 1643 uint16_t link_flags; 1644 uint8_t rsvd2; 1645 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1646#endif 1647 1648#define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 1649#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 1650#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 1651#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 1652#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 1653#define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 1654#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 1655 1656#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 1657#define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 1658#define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 1659 1660 uint32_t link_speed; 1661#define LINK_SPEED_AUTO 0 /* Auto selection */ 1662#define LINK_SPEED_1G 1 /* 1 Gigabaud */ 1663#define LINK_SPEED_2G 2 /* 2 Gigabaud */ 1664#define LINK_SPEED_4G 4 /* 4 Gigabaud */ 1665#define LINK_SPEED_8G 8 /* 8 Gigabaud */ 1666#define LINK_SPEED_10G 16 /* 10 Gigabaud */ 1667 1668} INIT_LINK_VAR; 1669 1670/* Structure for MB Command DOWN_LINK (06) */ 1671 1672typedef struct { 1673 uint32_t rsvd1; 1674} DOWN_LINK_VAR; 1675 1676/* Structure for MB Command CONFIG_LINK (07) */ 1677 1678typedef struct { 1679#ifdef __BIG_ENDIAN_BITFIELD 1680 uint32_t cr:1; 1681 uint32_t ci:1; 1682 uint32_t cr_delay:6; 1683 uint32_t cr_count:8; 1684 uint32_t rsvd1:8; 1685 uint32_t MaxBBC:8; 1686#else /* __LITTLE_ENDIAN_BITFIELD */ 1687 uint32_t MaxBBC:8; 1688 uint32_t rsvd1:8; 1689 uint32_t cr_count:8; 1690 uint32_t cr_delay:6; 1691 uint32_t ci:1; 1692 uint32_t cr:1; 1693#endif 1694 1695 uint32_t myId; 1696 uint32_t rsvd2; 1697 uint32_t edtov; 1698 uint32_t arbtov; 1699 uint32_t ratov; 1700 uint32_t rttov; 1701 uint32_t altov; 1702 uint32_t crtov; 1703 uint32_t citov; 1704#ifdef __BIG_ENDIAN_BITFIELD 1705 uint32_t rrq_enable:1; 1706 uint32_t rrq_immed:1; 1707 uint32_t rsvd4:29; 1708 uint32_t ack0_enable:1; 1709#else /* __LITTLE_ENDIAN_BITFIELD */ 1710 uint32_t ack0_enable:1; 1711 uint32_t rsvd4:29; 1712 uint32_t rrq_immed:1; 1713 uint32_t rrq_enable:1; 1714#endif 1715} CONFIG_LINK; 1716 1717/* Structure for MB Command PART_SLIM (08) 1718 * will be removed since SLI1 is no longer supported! 1719 */ 1720typedef struct { 1721#ifdef __BIG_ENDIAN_BITFIELD 1722 uint16_t offCiocb; 1723 uint16_t numCiocb; 1724 uint16_t offRiocb; 1725 uint16_t numRiocb; 1726#else /* __LITTLE_ENDIAN_BITFIELD */ 1727 uint16_t numCiocb; 1728 uint16_t offCiocb; 1729 uint16_t numRiocb; 1730 uint16_t offRiocb; 1731#endif 1732} RING_DEF; 1733 1734typedef struct { 1735#ifdef __BIG_ENDIAN_BITFIELD 1736 uint32_t unused1:24; 1737 uint32_t numRing:8; 1738#else /* __LITTLE_ENDIAN_BITFIELD */ 1739 uint32_t numRing:8; 1740 uint32_t unused1:24; 1741#endif 1742 1743 RING_DEF ringdef[4]; 1744 uint32_t hbainit; 1745} PART_SLIM_VAR; 1746 1747/* Structure for MB Command CONFIG_RING (09) */ 1748 1749typedef struct { 1750#ifdef __BIG_ENDIAN_BITFIELD 1751 uint32_t unused2:6; 1752 uint32_t recvSeq:1; 1753 uint32_t recvNotify:1; 1754 uint32_t numMask:8; 1755 uint32_t profile:8; 1756 uint32_t unused1:4; 1757 uint32_t ring:4; 1758#else /* __LITTLE_ENDIAN_BITFIELD */ 1759 uint32_t ring:4; 1760 uint32_t unused1:4; 1761 uint32_t profile:8; 1762 uint32_t numMask:8; 1763 uint32_t recvNotify:1; 1764 uint32_t recvSeq:1; 1765 uint32_t unused2:6; 1766#endif 1767 1768#ifdef __BIG_ENDIAN_BITFIELD 1769 uint16_t maxRespXchg; 1770 uint16_t maxOrigXchg; 1771#else /* __LITTLE_ENDIAN_BITFIELD */ 1772 uint16_t maxOrigXchg; 1773 uint16_t maxRespXchg; 1774#endif 1775 1776 RR_REG rrRegs[6]; 1777} CONFIG_RING_VAR; 1778 1779/* Structure for MB Command RESET_RING (10) */ 1780 1781typedef struct { 1782 uint32_t ring_no; 1783} RESET_RING_VAR; 1784 1785/* Structure for MB Command READ_CONFIG (11) */ 1786 1787typedef struct { 1788#ifdef __BIG_ENDIAN_BITFIELD 1789 uint32_t cr:1; 1790 uint32_t ci:1; 1791 uint32_t cr_delay:6; 1792 uint32_t cr_count:8; 1793 uint32_t InitBBC:8; 1794 uint32_t MaxBBC:8; 1795#else /* __LITTLE_ENDIAN_BITFIELD */ 1796 uint32_t MaxBBC:8; 1797 uint32_t InitBBC:8; 1798 uint32_t cr_count:8; 1799 uint32_t cr_delay:6; 1800 uint32_t ci:1; 1801 uint32_t cr:1; 1802#endif 1803 1804#ifdef __BIG_ENDIAN_BITFIELD 1805 uint32_t topology:8; 1806 uint32_t myDid:24; 1807#else /* __LITTLE_ENDIAN_BITFIELD */ 1808 uint32_t myDid:24; 1809 uint32_t topology:8; 1810#endif 1811 1812 /* Defines for topology (defined previously) */ 1813#ifdef __BIG_ENDIAN_BITFIELD 1814 uint32_t AR:1; 1815 uint32_t IR:1; 1816 uint32_t rsvd1:29; 1817 uint32_t ack0:1; 1818#else /* __LITTLE_ENDIAN_BITFIELD */ 1819 uint32_t ack0:1; 1820 uint32_t rsvd1:29; 1821 uint32_t IR:1; 1822 uint32_t AR:1; 1823#endif 1824 1825 uint32_t edtov; 1826 uint32_t arbtov; 1827 uint32_t ratov; 1828 uint32_t rttov; 1829 uint32_t altov; 1830 uint32_t lmt; 1831#define LMT_RESERVED 0x000 /* Not used */ 1832#define LMT_1Gb 0x004 1833#define LMT_2Gb 0x008 1834#define LMT_4Gb 0x040 1835#define LMT_8Gb 0x080 1836#define LMT_10Gb 0x100 1837 uint32_t rsvd2; 1838 uint32_t rsvd3; 1839 uint32_t max_xri; 1840 uint32_t max_iocb; 1841 uint32_t max_rpi; 1842 uint32_t avail_xri; 1843 uint32_t avail_iocb; 1844 uint32_t avail_rpi; 1845 uint32_t max_vpi; 1846 uint32_t rsvd4; 1847 uint32_t rsvd5; 1848 uint32_t avail_vpi; 1849} READ_CONFIG_VAR; 1850 1851/* Structure for MB Command READ_RCONFIG (12) */ 1852 1853typedef struct { 1854#ifdef __BIG_ENDIAN_BITFIELD 1855 uint32_t rsvd2:7; 1856 uint32_t recvNotify:1; 1857 uint32_t numMask:8; 1858 uint32_t profile:8; 1859 uint32_t rsvd1:4; 1860 uint32_t ring:4; 1861#else /* __LITTLE_ENDIAN_BITFIELD */ 1862 uint32_t ring:4; 1863 uint32_t rsvd1:4; 1864 uint32_t profile:8; 1865 uint32_t numMask:8; 1866 uint32_t recvNotify:1; 1867 uint32_t rsvd2:7; 1868#endif 1869 1870#ifdef __BIG_ENDIAN_BITFIELD 1871 uint16_t maxResp; 1872 uint16_t maxOrig; 1873#else /* __LITTLE_ENDIAN_BITFIELD */ 1874 uint16_t maxOrig; 1875 uint16_t maxResp; 1876#endif 1877 1878 RR_REG rrRegs[6]; 1879 1880#ifdef __BIG_ENDIAN_BITFIELD 1881 uint16_t cmdRingOffset; 1882 uint16_t cmdEntryCnt; 1883 uint16_t rspRingOffset; 1884 uint16_t rspEntryCnt; 1885 uint16_t nextCmdOffset; 1886 uint16_t rsvd3; 1887 uint16_t nextRspOffset; 1888 uint16_t rsvd4; 1889#else /* __LITTLE_ENDIAN_BITFIELD */ 1890 uint16_t cmdEntryCnt; 1891 uint16_t cmdRingOffset; 1892 uint16_t rspEntryCnt; 1893 uint16_t rspRingOffset; 1894 uint16_t rsvd3; 1895 uint16_t nextCmdOffset; 1896 uint16_t rsvd4; 1897 uint16_t nextRspOffset; 1898#endif 1899} READ_RCONF_VAR; 1900 1901/* Structure for MB Command READ_SPARM (13) */ 1902/* Structure for MB Command READ_SPARM64 (0x8D) */ 1903 1904typedef struct { 1905 uint32_t rsvd1; 1906 uint32_t rsvd2; 1907 union { 1908 struct ulp_bde sp; /* This BDE points to struct serv_parm 1909 structure */ 1910 struct ulp_bde64 sp64; 1911 } un; 1912#ifdef __BIG_ENDIAN_BITFIELD 1913 uint16_t rsvd3; 1914 uint16_t vpi; 1915#else /* __LITTLE_ENDIAN_BITFIELD */ 1916 uint16_t vpi; 1917 uint16_t rsvd3; 1918#endif 1919} READ_SPARM_VAR; 1920 1921/* Structure for MB Command READ_STATUS (14) */ 1922 1923typedef struct { 1924#ifdef __BIG_ENDIAN_BITFIELD 1925 uint32_t rsvd1:31; 1926 uint32_t clrCounters:1; 1927 uint16_t activeXriCnt; 1928 uint16_t activeRpiCnt; 1929#else /* __LITTLE_ENDIAN_BITFIELD */ 1930 uint32_t clrCounters:1; 1931 uint32_t rsvd1:31; 1932 uint16_t activeRpiCnt; 1933 uint16_t activeXriCnt; 1934#endif 1935 1936 uint32_t xmitByteCnt; 1937 uint32_t rcvByteCnt; 1938 uint32_t xmitFrameCnt; 1939 uint32_t rcvFrameCnt; 1940 uint32_t xmitSeqCnt; 1941 uint32_t rcvSeqCnt; 1942 uint32_t totalOrigExchanges; 1943 uint32_t totalRespExchanges; 1944 uint32_t rcvPbsyCnt; 1945 uint32_t rcvFbsyCnt; 1946} READ_STATUS_VAR; 1947 1948/* Structure for MB Command READ_RPI (15) */ 1949/* Structure for MB Command READ_RPI64 (0x8F) */ 1950 1951typedef struct { 1952#ifdef __BIG_ENDIAN_BITFIELD 1953 uint16_t nextRpi; 1954 uint16_t reqRpi; 1955 uint32_t rsvd2:8; 1956 uint32_t DID:24; 1957#else /* __LITTLE_ENDIAN_BITFIELD */ 1958 uint16_t reqRpi; 1959 uint16_t nextRpi; 1960 uint32_t DID:24; 1961 uint32_t rsvd2:8; 1962#endif 1963 1964 union { 1965 struct ulp_bde sp; 1966 struct ulp_bde64 sp64; 1967 } un; 1968 1969} READ_RPI_VAR; 1970 1971/* Structure for MB Command READ_XRI (16) */ 1972 1973typedef struct { 1974#ifdef __BIG_ENDIAN_BITFIELD 1975 uint16_t nextXri; 1976 uint16_t reqXri; 1977 uint16_t rsvd1; 1978 uint16_t rpi; 1979 uint32_t rsvd2:8; 1980 uint32_t DID:24; 1981 uint32_t rsvd3:8; 1982 uint32_t SID:24; 1983 uint32_t rsvd4; 1984 uint8_t seqId; 1985 uint8_t rsvd5; 1986 uint16_t seqCount; 1987 uint16_t oxId; 1988 uint16_t rxId; 1989 uint32_t rsvd6:30; 1990 uint32_t si:1; 1991 uint32_t exchOrig:1; 1992#else /* __LITTLE_ENDIAN_BITFIELD */ 1993 uint16_t reqXri; 1994 uint16_t nextXri; 1995 uint16_t rpi; 1996 uint16_t rsvd1; 1997 uint32_t DID:24; 1998 uint32_t rsvd2:8; 1999 uint32_t SID:24; 2000 uint32_t rsvd3:8;
2001 uint32_t rsvd4; 2002 uint16_t seqCount; 2003 uint8_t rsvd5; 2004 uint8_t seqId; 2005 uint16_t rxId; 2006 uint16_t oxId; 2007 uint32_t exchOrig:1; 2008 uint32_t si:1; 2009 uint32_t rsvd6:30; 2010#endif 2011} READ_XRI_VAR; 2012 2013/* Structure for MB Command READ_REV (17) */ 2014 2015typedef struct { 2016#ifdef __BIG_ENDIAN_BITFIELD 2017 uint32_t cv:1; 2018 uint32_t rr:1; 2019 uint32_t rsvd2:2; 2020 uint32_t v3req:1; 2021 uint32_t v3rsp:1; 2022 uint32_t rsvd1:25; 2023 uint32_t rv:1; 2024#else /* __LITTLE_ENDIAN_BITFIELD */ 2025 uint32_t rv:1; 2026 uint32_t rsvd1:25; 2027 uint32_t v3rsp:1; 2028 uint32_t v3req:1; 2029 uint32_t rsvd2:2; 2030 uint32_t rr:1; 2031 uint32_t cv:1; 2032#endif 2033 2034 uint32_t biuRev; 2035 uint32_t smRev; 2036 union { 2037 uint32_t smFwRev; 2038 struct { 2039#ifdef __BIG_ENDIAN_BITFIELD 2040 uint8_t ProgType; 2041 uint8_t ProgId; 2042 uint16_t ProgVer:4; 2043 uint16_t ProgRev:4; 2044 uint16_t ProgFixLvl:2; 2045 uint16_t ProgDistType:2; 2046 uint16_t DistCnt:4; 2047#else /* __LITTLE_ENDIAN_BITFIELD */ 2048 uint16_t DistCnt:4; 2049 uint16_t ProgDistType:2; 2050 uint16_t ProgFixLvl:2; 2051 uint16_t ProgRev:4; 2052 uint16_t ProgVer:4; 2053 uint8_t ProgId; 2054 uint8_t ProgType; 2055#endif 2056 2057 } b; 2058 } un; 2059 uint32_t endecRev; 2060#ifdef __BIG_ENDIAN_BITFIELD 2061 uint8_t feaLevelHigh; 2062 uint8_t feaLevelLow; 2063 uint8_t fcphHigh; 2064 uint8_t fcphLow; 2065#else /* __LITTLE_ENDIAN_BITFIELD */ 2066 uint8_t fcphLow; 2067 uint8_t fcphHigh; 2068 uint8_t feaLevelLow; 2069 uint8_t feaLevelHigh; 2070#endif 2071 2072 uint32_t postKernRev; 2073 uint32_t opFwRev; 2074 uint8_t opFwName[16]; 2075 uint32_t sli1FwRev; 2076 uint8_t sli1FwName[16]; 2077 uint32_t sli2FwRev; 2078 uint8_t sli2FwName[16]; 2079 uint32_t sli3Feat; 2080 uint32_t RandomData[6]; 2081} READ_REV_VAR; 2082 2083/* Structure for MB Command READ_LINK_STAT (18) */ 2084 2085typedef struct { 2086 uint32_t rsvd1; 2087 uint32_t linkFailureCnt; 2088 uint32_t lossSyncCnt; 2089 2090 uint32_t lossSignalCnt; 2091 uint32_t primSeqErrCnt; 2092 uint32_t invalidXmitWord; 2093 uint32_t crcCnt; 2094 uint32_t primSeqTimeout; 2095 uint32_t elasticOverrun; 2096 uint32_t arbTimeout; 2097} READ_LNK_VAR; 2098 2099/* Structure for MB Command REG_LOGIN (19) */ 2100/* Structure for MB Command REG_LOGIN64 (0x93) */ 2101 2102typedef struct { 2103#ifdef __BIG_ENDIAN_BITFIELD 2104 uint16_t rsvd1; 2105 uint16_t rpi; 2106 uint32_t rsvd2:8; 2107 uint32_t did:24; 2108#else /* __LITTLE_ENDIAN_BITFIELD */ 2109 uint16_t rpi; 2110 uint16_t rsvd1; 2111 uint32_t did:24; 2112 uint32_t rsvd2:8; 2113#endif 2114 2115 union { 2116 struct ulp_bde sp; 2117 struct ulp_bde64 sp64; 2118 } un; 2119 2120#ifdef __BIG_ENDIAN_BITFIELD 2121 uint16_t rsvd6; 2122 uint16_t vpi; 2123#else /* __LITTLE_ENDIAN_BITFIELD */ 2124 uint16_t vpi; 2125 uint16_t rsvd6; 2126#endif 2127 2128} REG_LOGIN_VAR; 2129 2130/* Word 30 contents for REG_LOGIN */ 2131typedef union { 2132 struct { 2133#ifdef __BIG_ENDIAN_BITFIELD 2134 uint16_t rsvd1:12; 2135 uint16_t wd30_class:4; 2136 uint16_t xri; 2137#else /* __LITTLE_ENDIAN_BITFIELD */ 2138 uint16_t xri; 2139 uint16_t wd30_class:4; 2140 uint16_t rsvd1:12; 2141#endif 2142 } f; 2143 uint32_t word; 2144} REG_WD30; 2145 2146/* Structure for MB Command UNREG_LOGIN (20) */ 2147 2148typedef struct { 2149#ifdef __BIG_ENDIAN_BITFIELD 2150 uint16_t rsvd1; 2151 uint16_t rpi; 2152 uint32_t rsvd2; 2153 uint32_t rsvd3; 2154 uint32_t rsvd4; 2155 uint32_t rsvd5; 2156 uint16_t rsvd6; 2157 uint16_t vpi; 2158#else /* __LITTLE_ENDIAN_BITFIELD */ 2159 uint16_t rpi; 2160 uint16_t rsvd1; 2161 uint32_t rsvd2; 2162 uint32_t rsvd3; 2163 uint32_t rsvd4; 2164 uint32_t rsvd5; 2165 uint16_t vpi; 2166 uint16_t rsvd6; 2167#endif 2168} UNREG_LOGIN_VAR; 2169 2170/* Structure for MB Command REG_VPI (0x96) */ 2171typedef struct { 2172#ifdef __BIG_ENDIAN_BITFIELD 2173 uint32_t rsvd1; 2174 uint32_t rsvd2:8; 2175 uint32_t sid:24; 2176 uint32_t rsvd3; 2177 uint32_t rsvd4; 2178 uint32_t rsvd5; 2179 uint16_t rsvd6; 2180 uint16_t vpi; 2181#else /* __LITTLE_ENDIAN */ 2182 uint32_t rsvd1; 2183 uint32_t sid:24; 2184 uint32_t rsvd2:8; 2185 uint32_t rsvd3; 2186 uint32_t rsvd4; 2187 uint32_t rsvd5; 2188 uint16_t vpi; 2189 uint16_t rsvd6; 2190#endif 2191} REG_VPI_VAR; 2192 2193/* Structure for MB Command UNREG_VPI (0x97) */ 2194typedef struct { 2195 uint32_t rsvd1; 2196 uint32_t rsvd2; 2197 uint32_t rsvd3; 2198 uint32_t rsvd4; 2199 uint32_t rsvd5; 2200#ifdef __BIG_ENDIAN_BITFIELD 2201 uint16_t rsvd6; 2202 uint16_t vpi; 2203#else /* __LITTLE_ENDIAN */ 2204 uint16_t vpi; 2205 uint16_t rsvd6; 2206#endif 2207} UNREG_VPI_VAR; 2208 2209/* Structure for MB Command UNREG_D_ID (0x23) */ 2210 2211typedef struct { 2212 uint32_t did; 2213 uint32_t rsvd2; 2214 uint32_t rsvd3; 2215 uint32_t rsvd4; 2216 uint32_t rsvd5; 2217#ifdef __BIG_ENDIAN_BITFIELD 2218 uint16_t rsvd6; 2219 uint16_t vpi; 2220#else 2221 uint16_t vpi; 2222 uint16_t rsvd6; 2223#endif 2224} UNREG_D_ID_VAR; 2225 2226/* Structure for MB Command READ_LA (21) */ 2227/* Structure for MB Command READ_LA64 (0x95) */ 2228 2229typedef struct { 2230 uint32_t eventTag; /* Event tag */ 2231#ifdef __BIG_ENDIAN_BITFIELD 2232 uint32_t rsvd1:19; 2233 uint32_t fa:1; 2234 uint32_t mm:1; /* Menlo Maintenance mode enabled */ 2235 uint32_t rx:1; 2236 uint32_t pb:1; 2237 uint32_t il:1; 2238 uint32_t attType:8; 2239#else /* __LITTLE_ENDIAN_BITFIELD */ 2240 uint32_t attType:8; 2241 uint32_t il:1; 2242 uint32_t pb:1; 2243 uint32_t rx:1; 2244 uint32_t mm:1; 2245 uint32_t fa:1; 2246 uint32_t rsvd1:19; 2247#endif 2248 2249#define AT_RESERVED 0x00 /* Reserved - attType */ 2250#define AT_LINK_UP 0x01 /* Link is up */ 2251#define AT_LINK_DOWN 0x02 /* Link is down */ 2252 2253#ifdef __BIG_ENDIAN_BITFIELD 2254 uint8_t granted_AL_PA; 2255 uint8_t lipAlPs; 2256 uint8_t lipType; 2257 uint8_t topology; 2258#else /* __LITTLE_ENDIAN_BITFIELD */ 2259 uint8_t topology; 2260 uint8_t lipType; 2261 uint8_t lipAlPs; 2262 uint8_t granted_AL_PA; 2263#endif 2264 2265#define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2266#define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 2267#define TOPOLOGY_LNK_MENLO_MAINTENANCE 0x05 /* maint mode zephtr to menlo */ 2268 2269 union { 2270 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer 2271 to */ 2272 /* store the LILP AL_PA position map into */ 2273 struct ulp_bde64 lilpBde64; 2274 } un; 2275 2276#ifdef __BIG_ENDIAN_BITFIELD 2277 uint32_t Dlu:1; 2278 uint32_t Dtf:1; 2279 uint32_t Drsvd2:14; 2280 uint32_t DlnkSpeed:8; 2281 uint32_t DnlPort:4; 2282 uint32_t Dtx:2; 2283 uint32_t Drx:2; 2284#else /* __LITTLE_ENDIAN_BITFIELD */ 2285 uint32_t Drx:2; 2286 uint32_t Dtx:2; 2287 uint32_t DnlPort:4; 2288 uint32_t DlnkSpeed:8; 2289 uint32_t Drsvd2:14; 2290 uint32_t Dtf:1; 2291 uint32_t Dlu:1; 2292#endif 2293 2294#ifdef __BIG_ENDIAN_BITFIELD 2295 uint32_t Ulu:1; 2296 uint32_t Utf:1; 2297 uint32_t Ursvd2:14; 2298 uint32_t UlnkSpeed:8; 2299 uint32_t UnlPort:4; 2300 uint32_t Utx:2; 2301 uint32_t Urx:2; 2302#else /* __LITTLE_ENDIAN_BITFIELD */ 2303 uint32_t Urx:2; 2304 uint32_t Utx:2; 2305 uint32_t UnlPort:4; 2306 uint32_t UlnkSpeed:8; 2307 uint32_t Ursvd2:14; 2308 uint32_t Utf:1; 2309 uint32_t Ulu:1; 2310#endif 2311 2312#define LA_UNKNW_LINK 0x0 /* lnkSpeed */ 2313#define LA_1GHZ_LINK 0x04 /* lnkSpeed */ 2314#define LA_2GHZ_LINK 0x08 /* lnkSpeed */ 2315#define LA_4GHZ_LINK 0x10 /* lnkSpeed */ 2316#define LA_8GHZ_LINK 0x20 /* lnkSpeed */ 2317#define LA_10GHZ_LINK 0x40 /* lnkSpeed */ 2318 2319} READ_LA_VAR; 2320 2321/* Structure for MB Command CLEAR_LA (22) */ 2322 2323typedef struct { 2324 uint32_t eventTag; /* Event tag */ 2325 uint32_t rsvd1; 2326} CLEAR_LA_VAR; 2327 2328/* Structure for MB Command DUMP */ 2329 2330typedef struct { 2331#ifdef __BIG_ENDIAN_BITFIELD 2332 uint32_t rsvd:25; 2333 uint32_t ra:1; 2334 uint32_t co:1; 2335 uint32_t cv:1; 2336 uint32_t type:4; 2337 uint32_t entry_index:16; 2338 uint32_t region_id:16; 2339#else /* __LITTLE_ENDIAN_BITFIELD */ 2340 uint32_t type:4; 2341 uint32_t cv:1; 2342 uint32_t co:1; 2343 uint32_t ra:1; 2344 uint32_t rsvd:25; 2345 uint32_t region_id:16; 2346 uint32_t entry_index:16; 2347#endif 2348 2349 uint32_t rsvd1; 2350 uint32_t word_cnt; 2351 uint32_t resp_offset; 2352} DUMP_VAR; 2353 2354#define DMP_MEM_REG 0x1 2355#define DMP_NV_PARAMS 0x2 2356 2357#define DMP_REGION_VPD 0xe 2358#define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2359#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2360#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2361 2362/* Structure for MB Command UPDATE_CFG (0x1B) */ 2363 2364struct update_cfg_var { 2365#ifdef __BIG_ENDIAN_BITFIELD 2366 uint32_t rsvd2:16; 2367 uint32_t type:8; 2368 uint32_t rsvd:1; 2369 uint32_t ra:1; 2370 uint32_t co:1; 2371 uint32_t cv:1; 2372 uint32_t req:4; 2373 uint32_t entry_length:16; 2374 uint32_t region_id:16; 2375#else /* __LITTLE_ENDIAN_BITFIELD */ 2376 uint32_t req:4; 2377 uint32_t cv:1; 2378 uint32_t co:1; 2379 uint32_t ra:1; 2380 uint32_t rsvd:1; 2381 uint32_t type:8; 2382 uint32_t rsvd2:16; 2383 uint32_t region_id:16; 2384 uint32_t entry_length:16; 2385#endif 2386 2387 uint32_t resp_info; 2388 uint32_t byte_cnt; 2389 uint32_t data_offset; 2390}; 2391 2392struct hbq_mask { 2393#ifdef __BIG_ENDIAN_BITFIELD 2394 uint8_t tmatch; 2395 uint8_t tmask; 2396 uint8_t rctlmatch; 2397 uint8_t rctlmask; 2398#else /* __LITTLE_ENDIAN */ 2399 uint8_t rctlmask; 2400 uint8_t rctlmatch; 2401 uint8_t tmask; 2402 uint8_t tmatch; 2403#endif 2404}; 2405 2406 2407/* Structure for MB Command CONFIG_HBQ (7c) */ 2408 2409struct config_hbq_var { 2410#ifdef __BIG_ENDIAN_BITFIELD 2411 uint32_t rsvd1 :7; 2412 uint32_t recvNotify :1; /* Receive Notification */ 2413 uint32_t numMask :8; /* # Mask Entries */ 2414 uint32_t profile :8; /* Selection Profile */ 2415 uint32_t rsvd2 :8; 2416#else /* __LITTLE_ENDIAN */ 2417 uint32_t rsvd2 :8; 2418 uint32_t profile :8; /* Selection Profile */ 2419 uint32_t numMask :8; /* # Mask Entries */ 2420 uint32_t recvNotify :1; /* Receive Notification */ 2421 uint32_t rsvd1 :7; 2422#endif 2423 2424#ifdef __BIG_ENDIAN_BITFIELD 2425 uint32_t hbqId :16; 2426 uint32_t rsvd3 :12; 2427 uint32_t ringMask :4; 2428#else /* __LITTLE_ENDIAN */ 2429 uint32_t ringMask :4; 2430 uint32_t rsvd3 :12; 2431 uint32_t hbqId :16; 2432#endif 2433 2434#ifdef __BIG_ENDIAN_BITFIELD 2435 uint32_t entry_count :16; 2436 uint32_t rsvd4 :8; 2437 uint32_t headerLen :8; 2438#else /* __LITTLE_ENDIAN */ 2439 uint32_t headerLen :8; 2440 uint32_t rsvd4 :8; 2441 uint32_t entry_count :16; 2442#endif 2443 2444 uint32_t hbqaddrLow; 2445 uint32_t hbqaddrHigh; 2446 2447#ifdef __BIG_ENDIAN_BITFIELD 2448 uint32_t rsvd5 :31; 2449 uint32_t logEntry :1; 2450#else /* __LITTLE_ENDIAN */ 2451 uint32_t logEntry :1; 2452 uint32_t rsvd5 :31; 2453#endif 2454 2455 uint32_t rsvd6; /* w7 */ 2456 uint32_t rsvd7; /* w8 */ 2457 uint32_t rsvd8; /* w9 */ 2458 2459 struct hbq_mask hbqMasks[6]; 2460 2461 2462 union { 2463 uint32_t allprofiles[12]; 2464 2465 struct { 2466 #ifdef __BIG_ENDIAN_BITFIELD 2467 uint32_t seqlenoff :16; 2468 uint32_t maxlen :16; 2469 #else /* __LITTLE_ENDIAN */ 2470 uint32_t maxlen :16; 2471 uint32_t seqlenoff :16; 2472 #endif 2473 #ifdef __BIG_ENDIAN_BITFIELD 2474 uint32_t rsvd1 :28; 2475 uint32_t seqlenbcnt :4; 2476 #else /* __LITTLE_ENDIAN */ 2477 uint32_t seqlenbcnt :4; 2478 uint32_t rsvd1 :28; 2479 #endif 2480 uint32_t rsvd[10]; 2481 } profile2; 2482 2483 struct { 2484 #ifdef __BIG_ENDIAN_BITFIELD 2485 uint32_t seqlenoff :16; 2486 uint32_t maxlen :16; 2487 #else /* __LITTLE_ENDIAN */ 2488 uint32_t maxlen :16; 2489 uint32_t seqlenoff :16; 2490 #endif 2491 #ifdef __BIG_ENDIAN_BITFIELD 2492 uint32_t cmdcodeoff :28; 2493 uint32_t rsvd1 :12; 2494 uint32_t seqlenbcnt :4; 2495 #else /* __LITTLE_ENDIAN */ 2496 uint32_t seqlenbcnt :4; 2497 uint32_t rsvd1 :12; 2498 uint32_t cmdcodeoff :28; 2499 #endif 2500 uint32_t cmdmatch[8]; 2501 2502 uint32_t rsvd[2]; 2503 } profile3; 2504 2505 struct { 2506 #ifdef __BIG_ENDIAN_BITFIELD 2507 uint32_t seqlenoff :16; 2508 uint32_t maxlen :16; 2509 #else /* __LITTLE_ENDIAN */ 2510 uint32_t maxlen :16; 2511 uint32_t seqlenoff :16; 2512 #endif 2513 #ifdef __BIG_ENDIAN_BITFIELD 2514 uint32_t cmdcodeoff :28; 2515 uint32_t rsvd1 :12; 2516 uint32_t seqlenbcnt :4; 2517 #else /* __LITTLE_ENDIAN */ 2518 uint32_t seqlenbcnt :4; 2519 uint32_t rsvd1 :12; 2520 uint32_t cmdcodeoff :28; 2521 #endif 2522 uint32_t cmdmatch[8]; 2523 2524 uint32_t rsvd[2]; 2525 } profile5; 2526 2527 } profiles; 2528 2529}; 2530 2531 2532 2533/* Structure for MB Command CONFIG_PORT (0x88) */ 2534typedef struct { 2535#ifdef __BIG_ENDIAN_BITFIELD 2536 uint32_t cBE : 1; 2537 uint32_t cET : 1; 2538 uint32_t cHpcb : 1; 2539 uint32_t cMA : 1; 2540 uint32_t sli_mode : 4; 2541 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2542 * config block */ 2543#else /* __LITTLE_ENDIAN */ 2544 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2545 * config block */ 2546 uint32_t sli_mode : 4; 2547 uint32_t cMA : 1; 2548 uint32_t cHpcb : 1; 2549 uint32_t cET : 1; 2550 uint32_t cBE : 1; 2551#endif 2552 2553 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 2554 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 2555 uint32_t hbainit[6]; 2556 2557#ifdef __BIG_ENDIAN_BITFIELD 2558 uint32_t rsvd : 24; /* Reserved */ 2559 uint32_t cmv : 1; /* Configure Max VPIs */ 2560 uint32_t ccrp : 1; /* Config Command Ring Polling */ 2561 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2562 uint32_t chbs : 1; /* Cofigure Host Backing store */ 2563 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2564 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2565 uint32_t cmx : 1; /* Configure Max XRIs */ 2566 uint32_t cmr : 1; /* Configure Max RPIs */ 2567#else /* __LITTLE_ENDIAN */ 2568 uint32_t cmr : 1; /* Configure Max RPIs */ 2569 uint32_t cmx : 1; /* Configure Max XRIs */ 2570 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2571 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2572 uint32_t chbs : 1; /* Cofigure Host Backing store */ 2573 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2574 uint32_t ccrp : 1; /* Config Command Ring Polling */ 2575 uint32_t cmv : 1; /* Configure Max VPIs */ 2576 uint32_t rsvd : 24; /* Reserved */ 2577#endif 2578#ifdef __BIG_ENDIAN_BITFIELD 2579 uint32_t rsvd2 : 24; /* Reserved */ 2580 uint32_t gmv : 1; /* Grant Max VPIs */ 2581 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2582 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2583 uint32_t ghbs : 1; /* Grant Host Backing Store */ 2584 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2585 uint32_t gerbm : 1; /* Grant ERBM Request */ 2586 uint32_t gmx : 1; /* Grant Max XRIs */ 2587 uint32_t gmr : 1; /* Grant Max RPIs */ 2588#else /* __LITTLE_ENDIAN */ 2589 uint32_t gmr : 1; /* Grant Max RPIs */ 2590 uint32_t gmx : 1; /* Grant Max XRIs */ 2591 uint32_t gerbm : 1; /* Grant ERBM Request */ 2592 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2593 uint32_t ghbs : 1; /* Grant Host Backing Store */ 2594 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2595 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2596 uint32_t gmv : 1; /* Grant Max VPIs */ 2597 uint32_t rsvd2 : 24; /* Reserved */ 2598#endif 2599 2600#ifdef __BIG_ENDIAN_BITFIELD 2601 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2602 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2603#else /* __LITTLE_ENDIAN */ 2604 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2605 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2606#endif 2607 2608#ifdef __BIG_ENDIAN_BITFIELD 2609 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2610 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */ 2611#else /* __LITTLE_ENDIAN */ 2612 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */ 2613 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2614#endif 2615 2616 uint32_t rsvd4; /* Reserved */ 2617 2618#ifdef __BIG_ENDIAN_BITFIELD 2619 uint32_t rsvd5 : 16; /* Reserved */ 2620 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2621#else /* __LITTLE_ENDIAN */ 2622 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2623 uint32_t rsvd5 : 16; /* Reserved */ 2624#endif 2625 2626} CONFIG_PORT_VAR; 2627 2628/* Structure for MB Command CONFIG_MSI (0x30) */ 2629struct config_msi_var { 2630#ifdef __BIG_ENDIAN_BITFIELD 2631 uint32_t dfltMsgNum:8; /* Default message number */ 2632 uint32_t rsvd1:11; /* Reserved */ 2633 uint32_t NID:5; /* Number of secondary attention IDs */ 2634 uint32_t rsvd2:5; /* Reserved */ 2635 uint32_t dfltPresent:1; /* Default message number present */ 2636 uint32_t addFlag:1; /* Add association flag */ 2637 uint32_t reportFlag:1; /* Report association flag */ 2638#else /* __LITTLE_ENDIAN_BITFIELD */ 2639 uint32_t reportFlag:1; /* Report association flag */ 2640 uint32_t addFlag:1; /* Add association flag */ 2641 uint32_t dfltPresent:1; /* Default message number present */ 2642 uint32_t rsvd2:5; /* Reserved */ 2643 uint32_t NID:5; /* Number of secondary attention IDs */ 2644 uint32_t rsvd1:11; /* Reserved */ 2645 uint32_t dfltMsgNum:8; /* Default message number */ 2646#endif 2647 uint32_t attentionConditions[2]; 2648 uint8_t attentionId[16]; 2649 uint8_t messageNumberByHA[64]; 2650 uint8_t messageNumberByID[16]; 2651 uint32_t autoClearHA[2]; 2652#ifdef __BIG_ENDIAN_BITFIELD 2653 uint32_t rsvd3:16; 2654 uint32_t autoClearID:16; 2655#else /* __LITTLE_ENDIAN_BITFIELD */ 2656 uint32_t autoClearID:16; 2657 uint32_t rsvd3:16; 2658#endif 2659 uint32_t rsvd4; 2660}; 2661 2662/* SLI-2 Port Control Block */ 2663 2664/* SLIM POINTER */ 2665#define SLIMOFF 0x30 /* WORD */ 2666 2667typedef struct _SLI2_RDSC { 2668 uint32_t cmdEntries; 2669 uint32_t cmdAddrLow; 2670 uint32_t cmdAddrHigh; 2671 2672 uint32_t rspEntries; 2673 uint32_t rspAddrLow; 2674 uint32_t rspAddrHigh; 2675} SLI2_RDSC; 2676 2677typedef struct _PCB { 2678#ifdef __BIG_ENDIAN_BITFIELD 2679 uint32_t type:8; 2680#define TYPE_NATIVE_SLI2 0x01; 2681 uint32_t feature:8; 2682#define FEATURE_INITIAL_SLI2 0x01; 2683 uint32_t rsvd:12; 2684 uint32_t maxRing:4; 2685#else /* __LITTLE_ENDIAN_BITFIELD */ 2686 uint32_t maxRing:4; 2687 uint32_t rsvd:12; 2688 uint32_t feature:8; 2689#define FEATURE_INITIAL_SLI2 0x01; 2690 uint32_t type:8; 2691#define TYPE_NATIVE_SLI2 0x01; 2692#endif 2693 2694 uint32_t mailBoxSize; 2695 uint32_t mbAddrLow; 2696 uint32_t mbAddrHigh; 2697 2698 uint32_t hgpAddrLow; 2699 uint32_t hgpAddrHigh; 2700 2701 uint32_t pgpAddrLow; 2702 uint32_t pgpAddrHigh; 2703 SLI2_RDSC rdsc[MAX_RINGS]; 2704} PCB_t; 2705 2706/* NEW_FEATURE */ 2707typedef struct { 2708#ifdef __BIG_ENDIAN_BITFIELD 2709 uint32_t rsvd0:27; 2710 uint32_t discardFarp:1; 2711 uint32_t IPEnable:1; 2712 uint32_t nodeName:1; 2713 uint32_t portName:1; 2714 uint32_t filterEnable:1; 2715#else /* __LITTLE_ENDIAN_BITFIELD */ 2716 uint32_t filterEnable:1; 2717 uint32_t portName:1; 2718 uint32_t nodeName:1; 2719 uint32_t IPEnable:1; 2720 uint32_t discardFarp:1; 2721 uint32_t rsvd:27; 2722#endif 2723 2724 uint8_t portname[8]; /* Used to be struct lpfc_name */ 2725 uint8_t nodename[8]; 2726 uint32_t rsvd1; 2727 uint32_t rsvd2; 2728 uint32_t rsvd3; 2729 uint32_t IPAddress; 2730} CONFIG_FARP_VAR; 2731 2732/* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 2733 2734typedef struct { 2735#ifdef __BIG_ENDIAN_BITFIELD 2736 uint32_t rsvd:30; 2737 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 2738#else /* __LITTLE_ENDIAN */ 2739 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 2740 uint32_t rsvd:30; 2741#endif 2742} ASYNCEVT_ENABLE_VAR; 2743 2744/* Union of all Mailbox Command types */ 2745#define MAILBOX_CMD_WSIZE 32 2746#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 2747 2748typedef union { 2749 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 2750 * feature/max ring number 2751 */ 2752 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 2753 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 2754 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 2755 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 2756 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 2757 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 2758 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 2759 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 2760 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 2761 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 2762 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 2763 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 2764 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 2765 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 2766 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 2767 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 2768 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 2769 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 2770 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 2771 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 2772 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */ 2773 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 2774 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 2775 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 2776 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 2777 * NEW_FEATURE 2778 */ 2779 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 2780 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 2781 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 2782 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 2783 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 2784 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 2785 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 2786} MAILVARIANTS; 2787 2788/* 2789 * SLI-2 specific structures 2790 */ 2791 2792struct lpfc_hgp { 2793 __le32 cmdPutInx; 2794 __le32 rspGetInx; 2795}; 2796 2797struct lpfc_pgp { 2798 __le32 cmdGetInx; 2799 __le32 rspPutInx; 2800}; 2801 2802struct sli2_desc { 2803 uint32_t unused1[16]; 2804 struct lpfc_hgp host[MAX_RINGS]; 2805 struct lpfc_pgp port[MAX_RINGS]; 2806}; 2807 2808struct sli3_desc { 2809 struct lpfc_hgp host[MAX_RINGS]; 2810 uint32_t reserved[8]; 2811 uint32_t hbq_put[16]; 2812}; 2813 2814struct sli3_pgp { 2815 struct lpfc_pgp port[MAX_RINGS]; 2816 uint32_t hbq_get[16]; 2817}; 2818 2819struct sli3_inb_pgp { 2820 uint32_t ha_copy; 2821 uint32_t counter; 2822 struct lpfc_pgp port[MAX_RINGS]; 2823 uint32_t hbq_get[16]; 2824}; 2825 2826union sli_var { 2827 struct sli2_desc s2; 2828 struct sli3_desc s3; 2829 struct sli3_pgp s3_pgp; 2830 struct sli3_inb_pgp s3_inb_pgp; 2831}; 2832 2833typedef struct { 2834#ifdef __BIG_ENDIAN_BITFIELD 2835 uint16_t mbxStatus; 2836 uint8_t mbxCommand; 2837 uint8_t mbxReserved:6; 2838 uint8_t mbxHc:1; 2839 uint8_t mbxOwner:1; /* Low order bit first word */ 2840#else /* __LITTLE_ENDIAN_BITFIELD */ 2841 uint8_t mbxOwner:1; /* Low order bit first word */ 2842 uint8_t mbxHc:1; 2843 uint8_t mbxReserved:6; 2844 uint8_t mbxCommand; 2845 uint16_t mbxStatus; 2846#endif 2847 2848 MAILVARIANTS un; 2849 union sli_var us; 2850} MAILBOX_t; 2851 2852/* 2853 * Begin Structure Definitions for IOCB Commands 2854 */ 2855 2856typedef struct { 2857#ifdef __BIG_ENDIAN_BITFIELD 2858 uint8_t statAction; 2859 uint8_t statRsn; 2860 uint8_t statBaExp; 2861 uint8_t statLocalError; 2862#else /* __LITTLE_ENDIAN_BITFIELD */ 2863 uint8_t statLocalError; 2864 uint8_t statBaExp; 2865 uint8_t statRsn; 2866 uint8_t statAction; 2867#endif 2868 /* statRsn P/F_RJT reason codes */ 2869#define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 2870#define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 2871#define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 2872#define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 2873#define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 2874#define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 2875#define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 2876#define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 2877#define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 2878#define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 2879#define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 2880#define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 2881#define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 2882#define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 2883#define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 2884#define RJT_BAD_PARM 0x10 /* Param. field invalid */ 2885#define RJT_XCHG_ERR 0x11 /* Exchange error */ 2886#define RJT_PROT_ERR 0x12 /* Protocol error */ 2887#define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 2888#define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 2889#define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 2890#define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 2891#define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 2892#define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 2893#define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 2894#define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 2895 2896#define IOERR_SUCCESS 0x00 /* statLocalError */ 2897#define IOERR_MISSING_CONTINUE 0x01 2898#define IOERR_SEQUENCE_TIMEOUT 0x02 2899#define IOERR_INTERNAL_ERROR 0x03 2900#define IOERR_INVALID_RPI 0x04 2901#define IOERR_NO_XRI 0x05 2902#define IOERR_ILLEGAL_COMMAND 0x06 2903#define IOERR_XCHG_DROPPED 0x07 2904#define IOERR_ILLEGAL_FIELD 0x08 2905#define IOERR_BAD_CONTINUE 0x09 2906#define IOERR_TOO_MANY_BUFFERS 0x0A 2907#define IOERR_RCV_BUFFER_WAITING 0x0B 2908#define IOERR_NO_CONNECTION 0x0C 2909#define IOERR_TX_DMA_FAILED 0x0D 2910#define IOERR_RX_DMA_FAILED 0x0E 2911#define IOERR_ILLEGAL_FRAME 0x0F 2912#define IOERR_EXTRA_DATA 0x10 2913#define IOERR_NO_RESOURCES 0x11 2914#define IOERR_RESERVED 0x12 2915#define IOERR_ILLEGAL_LENGTH 0x13 2916#define IOERR_UNSUPPORTED_FEATURE 0x14 2917#define IOERR_ABORT_IN_PROGRESS 0x15 2918#define IOERR_ABORT_REQUESTED 0x16 2919#define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 2920#define IOERR_LOOP_OPEN_FAILURE 0x18 2921#define IOERR_RING_RESET 0x19 2922#define IOERR_LINK_DOWN 0x1A 2923#define IOERR_CORRUPTED_DATA 0x1B 2924#define IOERR_CORRUPTED_RPI 0x1C 2925#define IOERR_OUT_OF_ORDER_DATA 0x1D 2926#define IOERR_OUT_OF_ORDER_ACK 0x1E 2927#define IOERR_DUP_FRAME 0x1F 2928#define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 2929#define IOERR_BAD_HOST_ADDRESS 0x21 2930#define IOERR_RCV_HDRBUF_WAITING 0x22 2931#define IOERR_MISSING_HDR_BUFFER 0x23 2932#define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 2933#define IOERR_ABORTMULT_REQUESTED 0x25 2934#define IOERR_BUFFER_SHORTAGE 0x28 2935#define IOERR_DEFAULT 0x29 2936#define IOERR_CNT 0x2A 2937 2938#define IOERR_DRVR_MASK 0x100 2939#define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 2940#define IOERR_SLI_BRESET 0x102 2941#define IOERR_SLI_ABORTED 0x103 2942} PARM_ERR; 2943 2944typedef union { 2945 struct { 2946#ifdef __BIG_ENDIAN_BITFIELD 2947 uint8_t Rctl; /* R_CTL field */ 2948 uint8_t Type; /* TYPE field */ 2949 uint8_t Dfctl; /* DF_CTL field */ 2950 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 2951#else /* __LITTLE_ENDIAN_BITFIELD */ 2952 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 2953 uint8_t Dfctl; /* DF_CTL field */ 2954 uint8_t Type; /* TYPE field */ 2955 uint8_t Rctl; /* R_CTL field */ 2956#endif 2957 2958#define BC 0x02 /* Broadcast Received - Fctl */ 2959#define SI 0x04 /* Sequence Initiative */ 2960#define LA 0x08 /* Ignore Link Attention state */ 2961#define LS 0x80 /* Last Sequence */ 2962 } hcsw; 2963 uint32_t reserved; 2964} WORD5; 2965 2966/* IOCB Command template for a generic response */ 2967typedef struct { 2968 uint32_t reserved[4]; 2969 PARM_ERR perr; 2970} GENERIC_RSP; 2971 2972/* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 2973typedef struct { 2974 struct ulp_bde xrsqbde[2]; 2975 uint32_t xrsqRo; /* Starting Relative Offset */ 2976 WORD5 w5; /* Header control/status word */ 2977} XR_SEQ_FIELDS; 2978 2979/* IOCB Command template for ELS_REQUEST */ 2980typedef struct { 2981 struct ulp_bde elsReq; 2982 struct ulp_bde elsRsp; 2983 2984#ifdef __BIG_ENDIAN_BITFIELD 2985 uint32_t word4Rsvd:7; 2986 uint32_t fl:1; 2987 uint32_t myID:24; 2988 uint32_t word5Rsvd:8; 2989 uint32_t remoteID:24; 2990#else /* __LITTLE_ENDIAN_BITFIELD */ 2991 uint32_t myID:24; 2992 uint32_t fl:1; 2993 uint32_t word4Rsvd:7; 2994 uint32_t remoteID:24; 2995 uint32_t word5Rsvd:8; 2996#endif 2997} ELS_REQUEST; 2998 2999/* IOCB Command template for RCV_ELS_REQ */ 3000typedef struct {
3001 struct ulp_bde elsReq[2]; 3002 uint32_t parmRo; 3003 3004#ifdef __BIG_ENDIAN_BITFIELD 3005 uint32_t word5Rsvd:8; 3006 uint32_t remoteID:24; 3007#else /* __LITTLE_ENDIAN_BITFIELD */ 3008 uint32_t remoteID:24; 3009 uint32_t word5Rsvd:8; 3010#endif 3011} RCV_ELS_REQ; 3012 3013/* IOCB Command template for ABORT / CLOSE_XRI */ 3014typedef struct { 3015 uint32_t rsvd[3]; 3016 uint32_t abortType; 3017#define ABORT_TYPE_ABTX 0x00000000 3018#define ABORT_TYPE_ABTS 0x00000001 3019 uint32_t parm; 3020#ifdef __BIG_ENDIAN_BITFIELD 3021 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3022 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3023#else /* __LITTLE_ENDIAN_BITFIELD */ 3024 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3025 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3026#endif 3027} AC_XRI; 3028 3029/* IOCB Command template for ABORT_MXRI64 */ 3030typedef struct { 3031 uint32_t rsvd[3]; 3032 uint32_t abortType; 3033 uint32_t parm; 3034 uint32_t iotag32; 3035} A_MXRI64; 3036 3037/* IOCB Command template for GET_RPI */ 3038typedef struct { 3039 uint32_t rsvd[4]; 3040 uint32_t parmRo; 3041#ifdef __BIG_ENDIAN_BITFIELD 3042 uint32_t word5Rsvd:8; 3043 uint32_t remoteID:24; 3044#else /* __LITTLE_ENDIAN_BITFIELD */ 3045 uint32_t remoteID:24; 3046 uint32_t word5Rsvd:8; 3047#endif 3048} GET_RPI; 3049 3050/* IOCB Command template for all FCP Initiator commands */ 3051typedef struct { 3052 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 3053 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 3054 uint32_t fcpi_parm; 3055 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3056} FCPI_FIELDS; 3057 3058/* IOCB Command template for all FCP Target commands */ 3059typedef struct { 3060 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3061 uint32_t fcpt_Offset; 3062 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3063} FCPT_FIELDS; 3064 3065/* SLI-2 IOCB structure definitions */ 3066 3067/* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3068typedef struct { 3069 ULP_BDL bdl; 3070 uint32_t xrsqRo; /* Starting Relative Offset */ 3071 WORD5 w5; /* Header control/status word */ 3072} XMT_SEQ_FIELDS64; 3073 3074/* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3075typedef struct { 3076 struct ulp_bde64 rcvBde; 3077 uint32_t rsvd1; 3078 uint32_t xrsqRo; /* Starting Relative Offset */ 3079 WORD5 w5; /* Header control/status word */ 3080} RCV_SEQ_FIELDS64; 3081 3082/* IOCB Command template for ELS_REQUEST64 */ 3083typedef struct { 3084 ULP_BDL bdl; 3085#ifdef __BIG_ENDIAN_BITFIELD 3086 uint32_t word4Rsvd:7; 3087 uint32_t fl:1; 3088 uint32_t myID:24; 3089 uint32_t word5Rsvd:8; 3090 uint32_t remoteID:24; 3091#else /* __LITTLE_ENDIAN_BITFIELD */ 3092 uint32_t myID:24; 3093 uint32_t fl:1; 3094 uint32_t word4Rsvd:7; 3095 uint32_t remoteID:24; 3096 uint32_t word5Rsvd:8; 3097#endif 3098} ELS_REQUEST64; 3099 3100/* IOCB Command template for GEN_REQUEST64 */ 3101typedef struct { 3102 ULP_BDL bdl; 3103 uint32_t xrsqRo; /* Starting Relative Offset */ 3104 WORD5 w5; /* Header control/status word */ 3105} GEN_REQUEST64; 3106 3107/* IOCB Command template for RCV_ELS_REQ64 */ 3108typedef struct { 3109 struct ulp_bde64 elsReq; 3110 uint32_t rcvd1; 3111 uint32_t parmRo; 3112 3113#ifdef __BIG_ENDIAN_BITFIELD 3114 uint32_t word5Rsvd:8; 3115 uint32_t remoteID:24; 3116#else /* __LITTLE_ENDIAN_BITFIELD */ 3117 uint32_t remoteID:24; 3118 uint32_t word5Rsvd:8; 3119#endif 3120} RCV_ELS_REQ64; 3121 3122/* IOCB Command template for RCV_SEQ64 */ 3123struct rcv_seq64 { 3124 struct ulp_bde64 elsReq; 3125 uint32_t hbq_1; 3126 uint32_t parmRo; 3127#ifdef __BIG_ENDIAN_BITFIELD 3128 uint32_t rctl:8; 3129 uint32_t type:8; 3130 uint32_t dfctl:8; 3131 uint32_t ls:1; 3132 uint32_t fs:1; 3133 uint32_t rsvd2:3; 3134 uint32_t si:1; 3135 uint32_t bc:1; 3136 uint32_t rsvd3:1; 3137#else /* __LITTLE_ENDIAN_BITFIELD */ 3138 uint32_t rsvd3:1; 3139 uint32_t bc:1; 3140 uint32_t si:1; 3141 uint32_t rsvd2:3; 3142 uint32_t fs:1; 3143 uint32_t ls:1; 3144 uint32_t dfctl:8; 3145 uint32_t type:8; 3146 uint32_t rctl:8; 3147#endif 3148}; 3149 3150/* IOCB Command template for all 64 bit FCP Initiator commands */ 3151typedef struct { 3152 ULP_BDL bdl; 3153 uint32_t fcpi_parm; 3154 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3155} FCPI_FIELDS64; 3156 3157/* IOCB Command template for all 64 bit FCP Target commands */ 3158typedef struct { 3159 ULP_BDL bdl; 3160 uint32_t fcpt_Offset; 3161 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3162} FCPT_FIELDS64; 3163 3164/* IOCB Command template for Async Status iocb commands */ 3165typedef struct { 3166 uint32_t rsvd[4]; 3167 uint32_t param; 3168#ifdef __BIG_ENDIAN_BITFIELD 3169 uint16_t evt_code; /* High order bits word 5 */ 3170 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 3171#else /* __LITTLE_ENDIAN_BITFIELD */ 3172 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 3173 uint16_t evt_code; /* Low order bits word 5 */ 3174#endif 3175} ASYNCSTAT_FIELDS; 3176#define ASYNC_TEMP_WARN 0x100 3177#define ASYNC_TEMP_SAFE 0x101 3178 3179/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 3180 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 3181 3182struct rcv_sli3 { 3183 uint32_t word8Rsvd; 3184#ifdef __BIG_ENDIAN_BITFIELD 3185 uint16_t vpi; 3186 uint16_t word9Rsvd; 3187#else /* __LITTLE_ENDIAN */ 3188 uint16_t word9Rsvd; 3189 uint16_t vpi; 3190#endif 3191 uint32_t word10Rsvd; 3192 uint32_t acc_len; /* accumulated length */ 3193 struct ulp_bde64 bde2; 3194}; 3195 3196/* Structure used for a single HBQ entry */ 3197struct lpfc_hbq_entry { 3198 struct ulp_bde64 bde; 3199 uint32_t buffer_tag; 3200}; 3201 3202/* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 3203typedef struct { 3204 struct lpfc_hbq_entry buff; 3205 uint32_t rsvd; 3206 uint32_t rsvd1; 3207} QUE_XRI64_CX_FIELDS; 3208 3209struct que_xri64cx_ext_fields { 3210 uint32_t iotag64_low; 3211 uint32_t iotag64_high; 3212 uint32_t ebde_count; 3213 uint32_t rsvd; 3214 struct lpfc_hbq_entry buff[5]; 3215}; 3216 3217#define LPFC_EXT_DATA_BDE_COUNT 3 3218struct fcp_irw_ext { 3219 uint32_t io_tag64_low; 3220 uint32_t io_tag64_high; 3221#ifdef __BIG_ENDIAN_BITFIELD 3222 uint8_t reserved1; 3223 uint8_t reserved2; 3224 uint8_t reserved3; 3225 uint8_t ebde_count; 3226#else /* __LITTLE_ENDIAN */ 3227 uint8_t ebde_count; 3228 uint8_t reserved3; 3229 uint8_t reserved2; 3230 uint8_t reserved1; 3231#endif 3232 uint32_t reserved4; 3233 struct ulp_bde64 rbde; /* response bde */ 3234 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 3235 uint8_t icd[32]; /* immediate command data (32 bytes) */ 3236}; 3237 3238typedef struct _IOCB { /* IOCB structure */ 3239 union { 3240 GENERIC_RSP grsp; /* Generic response */ 3241 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 3242 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 3243 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 3244 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 3245 A_MXRI64 amxri; /* abort multiple xri command overlay */ 3246 GET_RPI getrpi; /* GET_RPI template */ 3247 FCPI_FIELDS fcpi; /* FCP Initiator template */ 3248 FCPT_FIELDS fcpt; /* FCP target template */ 3249 3250 /* SLI-2 structures */ 3251 3252 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 3253 * bde_64s */ 3254 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 3255 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 3256 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 3257 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 3258 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 3259 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 3260 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 3261 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 3262 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 3263 3264 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 3265 } un; 3266 union { 3267 struct { 3268#ifdef __BIG_ENDIAN_BITFIELD 3269 uint16_t ulpContext; /* High order bits word 6 */ 3270 uint16_t ulpIoTag; /* Low order bits word 6 */ 3271#else /* __LITTLE_ENDIAN_BITFIELD */ 3272 uint16_t ulpIoTag; /* Low order bits word 6 */ 3273 uint16_t ulpContext; /* High order bits word 6 */ 3274#endif 3275 } t1; 3276 struct { 3277#ifdef __BIG_ENDIAN_BITFIELD 3278 uint16_t ulpContext; /* High order bits word 6 */ 3279 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3280 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3281#else /* __LITTLE_ENDIAN_BITFIELD */ 3282 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3283 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3284 uint16_t ulpContext; /* High order bits word 6 */ 3285#endif 3286 } t2; 3287 } un1; 3288#define ulpContext un1.t1.ulpContext 3289#define ulpIoTag un1.t1.ulpIoTag 3290#define ulpIoTag0 un1.t2.ulpIoTag0 3291 3292#ifdef __BIG_ENDIAN_BITFIELD 3293 uint32_t ulpTimeout:8; 3294 uint32_t ulpXS:1; 3295 uint32_t ulpFCP2Rcvy:1; 3296 uint32_t ulpPU:2; 3297 uint32_t ulpIr:1; 3298 uint32_t ulpClass:3; 3299 uint32_t ulpCommand:8; 3300 uint32_t ulpStatus:4; 3301 uint32_t ulpBdeCount:2; 3302 uint32_t ulpLe:1; 3303 uint32_t ulpOwner:1; /* Low order bit word 7 */ 3304#else /* __LITTLE_ENDIAN_BITFIELD */ 3305 uint32_t ulpOwner:1; /* Low order bit word 7 */ 3306 uint32_t ulpLe:1; 3307 uint32_t ulpBdeCount:2; 3308 uint32_t ulpStatus:4; 3309 uint32_t ulpCommand:8; 3310 uint32_t ulpClass:3; 3311 uint32_t ulpIr:1; 3312 uint32_t ulpPU:2; 3313 uint32_t ulpFCP2Rcvy:1; 3314 uint32_t ulpXS:1; 3315 uint32_t ulpTimeout:8; 3316#endif 3317 3318 union { 3319 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 3320 3321 /* words 8-31 used for que_xri_cx iocb */ 3322 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 3323 struct fcp_irw_ext fcp_ext; 3324 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 3325 } unsli3; 3326 3327#define ulpCt_h ulpXS 3328#define ulpCt_l ulpFCP2Rcvy 3329 3330#define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 3331#define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 3332#define PARM_UNUSED 0 /* PU field (Word 4) not used */ 3333#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 3334#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 3335#define PARM_NPIV_DID 3 3336#define CLASS1 0 /* Class 1 */ 3337#define CLASS2 1 /* Class 2 */ 3338#define CLASS3 2 /* Class 3 */ 3339#define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 3340 3341#define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 3342#define IOSTAT_FCP_RSP_ERROR 0x1 3343#define IOSTAT_REMOTE_STOP 0x2 3344#define IOSTAT_LOCAL_REJECT 0x3 3345#define IOSTAT_NPORT_RJT 0x4 3346#define IOSTAT_FABRIC_RJT 0x5 3347#define IOSTAT_NPORT_BSY 0x6 3348#define IOSTAT_FABRIC_BSY 0x7 3349#define IOSTAT_INTERMED_RSP 0x8 3350#define IOSTAT_LS_RJT 0x9 3351#define IOSTAT_BA_RJT 0xA 3352#define IOSTAT_RSVD1 0xB 3353#define IOSTAT_RSVD2 0xC 3354#define IOSTAT_RSVD3 0xD 3355#define IOSTAT_RSVD4 0xE 3356#define IOSTAT_NEED_BUFFER 0xF 3357#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 3358#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 3359#define IOSTAT_CNT 0x11 3360 3361} IOCB_t; 3362 3363 3364#define SLI1_SLIM_SIZE (4 * 1024) 3365 3366/* Up to 498 IOCBs will fit into 16k 3367 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 3368 */ 3369#define SLI2_SLIM_SIZE (64 * 1024) 3370 3371/* Maximum IOCBs that will fit in SLI2 slim */ 3372#define MAX_SLI2_IOCB 498 3373#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 3374 (sizeof(MAILBOX_t) + sizeof(PCB_t))) 3375 3376/* HBQ entries are 4 words each = 4k */ 3377#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 3378 lpfc_sli_hbq_count()) 3379 3380struct lpfc_sli2_slim { 3381 MAILBOX_t mbx; 3382 PCB_t pcb; 3383 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 3384}; 3385 3386/* 3387 * This function checks PCI device to allow special handling for LC HBAs. 3388 * 3389 * Parameters: 3390 * device : struct pci_dev 's device field 3391 * 3392 * return 1 => TRUE 3393 * 0 => FALSE 3394 */ 3395static inline int 3396lpfc_is_LC_HBA(unsigned short device) 3397{ 3398 if ((device == PCI_DEVICE_ID_TFLY) || 3399 (device == PCI_DEVICE_ID_PFLY) || 3400 (device == PCI_DEVICE_ID_LP101) || 3401 (device == PCI_DEVICE_ID_BMID) || 3402 (device == PCI_DEVICE_ID_BSMB) || 3403 (device == PCI_DEVICE_ID_ZMID) || 3404 (device == PCI_DEVICE_ID_ZSMB) || 3405 (device == PCI_DEVICE_ID_SAT_MID) || 3406 (device == PCI_DEVICE_ID_SAT_SMB) || 3407 (device == PCI_DEVICE_ID_RFLY)) 3408 return 1; 3409 else 3410 return 0; 3411} 3412 3413/* 3414 * Determine if an IOCB failed because of a link event or firmware reset. 3415 */ 3416 3417static inline int 3418lpfc_error_lost_link(IOCB_t *iocbp) 3419{ 3420 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT && 3421 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED || 3422 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN || 3423 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN)); 3424} 3425 3426#define MENLO_TRANSPORT_TYPE 0xfe 3427#define MENLO_CONTEXT 0 3428#define MENLO_PU 3 3429#define MENLO_TIMEOUT 30 3430#define SETVAR_MLOMNT 0x103107 3431#define SETVAR_MLORST 0x103007 3432