linux/drivers/net/yellowfin.c
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   1/* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
   2/*
   3        Written 1997-2001 by Donald Becker.
   4
   5        This software may be used and distributed according to the terms of
   6        the GNU General Public License (GPL), incorporated herein by reference.
   7        Drivers based on or derived from this code fall under the GPL and must
   8        retain the authorship, copyright and license notice.  This file is not
   9        a complete program and may only be used when the entire operating
  10        system is licensed under the GPL.
  11
  12        This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
  13        It also supports the Symbios Logic version of the same chip core.
  14
  15        The author may be reached as becker@scyld.com, or C/O
  16        Scyld Computing Corporation
  17        410 Severn Ave., Suite 210
  18        Annapolis MD 21403
  19
  20        Support and updates available at
  21        http://www.scyld.com/network/yellowfin.html
  22        [link no longer provides useful info -jgarzik]
  23
  24*/
  25
  26#define DRV_NAME        "yellowfin"
  27#define DRV_VERSION     "2.1"
  28#define DRV_RELDATE     "Sep 11, 2006"
  29
  30#define PFX DRV_NAME ": "
  31
  32/* The user-configurable values.
  33   These may be modified when a driver module is loaded.*/
  34
  35static int debug = 1;                   /* 1 normal messages, 0 quiet .. 7 verbose. */
  36/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  37static int max_interrupt_work = 20;
  38static int mtu;
  39#ifdef YF_PROTOTYPE                     /* Support for prototype hardware errata. */
  40/* System-wide count of bogus-rx frames. */
  41static int bogus_rx;
  42static int dma_ctrl = 0x004A0263;                       /* Constrained by errata */
  43static int fifo_cfg = 0x0020;                           /* Bypass external Tx FIFO. */
  44#elif defined(YF_NEW)                                   /* A future perfect board :->.  */
  45static int dma_ctrl = 0x00CAC277;                       /* Override when loading module! */
  46static int fifo_cfg = 0x0028;
  47#else
  48static const int dma_ctrl = 0x004A0263;                         /* Constrained by errata */
  49static const int fifo_cfg = 0x0020;                             /* Bypass external Tx FIFO. */
  50#endif
  51
  52/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  53   Setting to > 1514 effectively disables this feature. */
  54static int rx_copybreak;
  55
  56/* Used to pass the media type, etc.
  57   No media types are currently defined.  These exist for driver
  58   interoperability.
  59*/
  60#define MAX_UNITS 8                             /* More are supported, limit only on options */
  61static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
  62static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
  63
  64/* Do ugly workaround for GX server chipset errata. */
  65static int gx_fix;
  66
  67/* Operational parameters that are set at compile time. */
  68
  69/* Keep the ring sizes a power of two for efficiency.
  70   Making the Tx ring too long decreases the effectiveness of channel
  71   bonding and packet priority.
  72   There are no ill effects from too-large receive rings. */
  73#define TX_RING_SIZE    16
  74#define TX_QUEUE_SIZE   12              /* Must be > 4 && <= TX_RING_SIZE */
  75#define RX_RING_SIZE    64
  76#define STATUS_TOTAL_SIZE       TX_RING_SIZE*sizeof(struct tx_status_words)
  77#define TX_TOTAL_SIZE           2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
  78#define RX_TOTAL_SIZE           RX_RING_SIZE*sizeof(struct yellowfin_desc)
  79
  80/* Operational parameters that usually are not changed. */
  81/* Time in jiffies before concluding the transmitter is hung. */
  82#define TX_TIMEOUT  (2*HZ)
  83#define PKT_BUF_SZ              1536                    /* Size of each temporary Rx buffer.*/
  84
  85#define yellowfin_debug debug
  86
  87#include <linux/module.h>
  88#include <linux/kernel.h>
  89#include <linux/string.h>
  90#include <linux/timer.h>
  91#include <linux/errno.h>
  92#include <linux/ioport.h>
  93#include <linux/slab.h>
  94#include <linux/interrupt.h>
  95#include <linux/pci.h>
  96#include <linux/init.h>
  97#include <linux/mii.h>
  98#include <linux/netdevice.h>
  99#include <linux/etherdevice.h>
 100#include <linux/skbuff.h>
 101#include <linux/ethtool.h>
 102#include <linux/crc32.h>
 103#include <linux/bitops.h>
 104#include <asm/uaccess.h>
 105#include <asm/processor.h>              /* Processor type for cache alignment. */
 106#include <asm/unaligned.h>
 107#include <asm/io.h>
 108
 109/* These identify the driver base version and may not be removed. */
 110static char version[] __devinitdata =
 111KERN_INFO DRV_NAME ".c:v1.05  1/09/2001  Written by Donald Becker <becker@scyld.com>\n"
 112KERN_INFO "  (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
 113
 114MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
 115MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
 116MODULE_LICENSE("GPL");
 117
 118module_param(max_interrupt_work, int, 0);
 119module_param(mtu, int, 0);
 120module_param(debug, int, 0);
 121module_param(rx_copybreak, int, 0);
 122module_param_array(options, int, NULL, 0);
 123module_param_array(full_duplex, int, NULL, 0);
 124module_param(gx_fix, int, 0);
 125MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
 126MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
 127MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
 128MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
 129MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
 130MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
 131MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
 132
 133/*
 134                                Theory of Operation
 135
 136I. Board Compatibility
 137
 138This device driver is designed for the Packet Engines "Yellowfin" Gigabit
 139Ethernet adapter.  The G-NIC 64-bit PCI card is supported, as well as the
 140Symbios 53C885E dual function chip.
 141
 142II. Board-specific settings
 143
 144PCI bus devices are configured by the system at boot time, so no jumpers
 145need to be set on the board.  The system BIOS preferably should assign the
 146PCI INTA signal to an otherwise unused system IRQ line.
 147Note: Kernel versions earlier than 1.3.73 do not support shared PCI
 148interrupt lines.
 149
 150III. Driver operation
 151
 152IIIa. Ring buffers
 153
 154The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
 155This is a descriptor list scheme similar to that used by the EEPro100 and
 156Tulip.  This driver uses two statically allocated fixed-size descriptor lists
 157formed into rings by a branch from the final descriptor to the beginning of
 158the list.  The ring sizes are set at compile time by RX/TX_RING_SIZE.
 159
 160The driver allocates full frame size skbuffs for the Rx ring buffers at
 161open() time and passes the skb->data field to the Yellowfin as receive data
 162buffers.  When an incoming frame is less than RX_COPYBREAK bytes long,
 163a fresh skbuff is allocated and the frame is copied to the new skbuff.
 164When the incoming frame is larger, the skbuff is passed directly up the
 165protocol stack and replaced by a newly allocated skbuff.
 166
 167The RX_COPYBREAK value is chosen to trade-off the memory wasted by
 168using a full-sized skbuff for small frames vs. the copying costs of larger
 169frames.  For small frames the copying cost is negligible (esp. considering
 170that we are pre-loading the cache with immediately useful header
 171information).  For large frames the copying cost is non-trivial, and the
 172larger copy might flush the cache of useful data.
 173
 174IIIC. Synchronization
 175
 176The driver runs as two independent, single-threaded flows of control.  One
 177is the send-packet routine, which enforces single-threaded use by the
 178dev->tbusy flag.  The other thread is the interrupt handler, which is single
 179threaded by the hardware and other software.
 180
 181The send packet thread has partial control over the Tx ring and 'dev->tbusy'
 182flag.  It sets the tbusy flag whenever it's queuing a Tx packet. If the next
 183queue slot is empty, it clears the tbusy flag when finished otherwise it sets
 184the 'yp->tx_full' flag.
 185
 186The interrupt handler has exclusive control over the Rx ring and records stats
 187from the Tx ring.  After reaping the stats, it marks the Tx queue entry as
 188empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
 189clears both the tx_full and tbusy flags.
 190
 191IV. Notes
 192
 193Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
 194Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
 195and an AlphaStation to verifty the Alpha port!
 196
 197IVb. References
 198
 199Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
 200Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
 201   Data Manual v3.0
 202http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
 203http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
 204
 205IVc. Errata
 206
 207See Packet Engines confidential appendix (prototype chips only).
 208*/
 209
 210
 211
 212enum capability_flags {
 213        HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
 214        HasMACAddrBug=32, /* Only on early revs.  */
 215        DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
 216};
 217
 218/* The PCI I/O space extent. */
 219enum {
 220        YELLOWFIN_SIZE  = 0x100,
 221};
 222
 223struct pci_id_info {
 224        const char *name;
 225        struct match_info {
 226                int     pci, pci_mask, subsystem, subsystem_mask;
 227                int revision, revision_mask;                            /* Only 8 bits. */
 228        } id;
 229        int drv_flags;                          /* Driver use, intended as capability flags. */
 230};
 231
 232static const struct pci_id_info pci_id_tbl[] = {
 233        {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
 234         FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
 235        {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
 236          HasMII | DontUseEeprom },
 237        { }
 238};
 239
 240static const struct pci_device_id yellowfin_pci_tbl[] = {
 241        { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 242        { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
 243        { }
 244};
 245MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
 246
 247
 248/* Offsets to the Yellowfin registers.  Various sizes and alignments. */
 249enum yellowfin_offsets {
 250        TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
 251        TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
 252        RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
 253        RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
 254        EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
 255        ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
 256        Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
 257        MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
 258        MII_Status=0xAE,
 259        RxDepth=0xB8, FlowCtrl=0xBC,
 260        AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
 261        EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
 262        EEFeature=0xF5,
 263};
 264
 265/* The Yellowfin Rx and Tx buffer descriptors.
 266   Elements are written as 32 bit for endian portability. */
 267struct yellowfin_desc {
 268        __le32 dbdma_cmd;
 269        __le32 addr;
 270        __le32 branch_addr;
 271        __le32 result_status;
 272};
 273
 274struct tx_status_words {
 275#ifdef __BIG_ENDIAN
 276        u16 tx_errs;
 277        u16 tx_cnt;
 278        u16 paused;
 279        u16 total_tx_cnt;
 280#else  /* Little endian chips. */
 281        u16 tx_cnt;
 282        u16 tx_errs;
 283        u16 total_tx_cnt;
 284        u16 paused;
 285#endif /* __BIG_ENDIAN */
 286};
 287
 288/* Bits in yellowfin_desc.cmd */
 289enum desc_cmd_bits {
 290        CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
 291        CMD_NOP=0x60000000, CMD_STOP=0x70000000,
 292        BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
 293        BRANCH_IFTRUE=0x040000,
 294};
 295
 296/* Bits in yellowfin_desc.status */
 297enum desc_status_bits { RX_EOP=0x0040, };
 298
 299/* Bits in the interrupt status/mask registers. */
 300enum intr_status_bits {
 301        IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
 302        IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
 303        IntrEarlyRx=0x100, IntrWakeup=0x200, };
 304
 305#define PRIV_ALIGN      31      /* Required alignment mask */
 306#define MII_CNT         4
 307struct yellowfin_private {
 308        /* Descriptor rings first for alignment.
 309           Tx requires a second descriptor for status. */
 310        struct yellowfin_desc *rx_ring;
 311        struct yellowfin_desc *tx_ring;
 312        struct sk_buff* rx_skbuff[RX_RING_SIZE];
 313        struct sk_buff* tx_skbuff[TX_RING_SIZE];
 314        dma_addr_t rx_ring_dma;
 315        dma_addr_t tx_ring_dma;
 316
 317        struct tx_status_words *tx_status;
 318        dma_addr_t tx_status_dma;
 319
 320        struct timer_list timer;        /* Media selection timer. */
 321        /* Frequently used and paired value: keep adjacent for cache effect. */
 322        int chip_id, drv_flags;
 323        struct pci_dev *pci_dev;
 324        unsigned int cur_rx, dirty_rx;          /* Producer/consumer ring indices */
 325        unsigned int rx_buf_sz;                         /* Based on MTU+slack. */
 326        struct tx_status_words *tx_tail_desc;
 327        unsigned int cur_tx, dirty_tx;
 328        int tx_threshold;
 329        unsigned int tx_full:1;                         /* The Tx queue is full. */
 330        unsigned int full_duplex:1;                     /* Full-duplex operation requested. */
 331        unsigned int duplex_lock:1;
 332        unsigned int medialock:1;                       /* Do not sense media. */
 333        unsigned int default_port:4;            /* Last dev->if_port value. */
 334        /* MII transceiver section. */
 335        int mii_cnt;                                            /* MII device addresses. */
 336        u16 advertising;                                        /* NWay media advertisement */
 337        unsigned char phys[MII_CNT];            /* MII device addresses, only first one used */
 338        spinlock_t lock;
 339        void __iomem *base;
 340};
 341
 342static int read_eeprom(void __iomem *ioaddr, int location);
 343static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
 344static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
 345static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 346static int yellowfin_open(struct net_device *dev);
 347static void yellowfin_timer(unsigned long data);
 348static void yellowfin_tx_timeout(struct net_device *dev);
 349static void yellowfin_init_ring(struct net_device *dev);
 350static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev);
 351static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance);
 352static int yellowfin_rx(struct net_device *dev);
 353static void yellowfin_error(struct net_device *dev, int intr_status);
 354static int yellowfin_close(struct net_device *dev);
 355static void set_rx_mode(struct net_device *dev);
 356static const struct ethtool_ops ethtool_ops;
 357
 358
 359static int __devinit yellowfin_init_one(struct pci_dev *pdev,
 360                                        const struct pci_device_id *ent)
 361{
 362        struct net_device *dev;
 363        struct yellowfin_private *np;
 364        int irq;
 365        int chip_idx = ent->driver_data;
 366        static int find_cnt;
 367        void __iomem *ioaddr;
 368        int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
 369        int drv_flags = pci_id_tbl[chip_idx].drv_flags;
 370        void *ring_space;
 371        dma_addr_t ring_dma;
 372#ifdef USE_IO_OPS
 373        int bar = 0;
 374#else
 375        int bar = 1;
 376#endif
 377        DECLARE_MAC_BUF(mac);
 378
 379/* when built into the kernel, we only print version if device is found */
 380#ifndef MODULE
 381        static int printed_version;
 382        if (!printed_version++)
 383                printk(version);
 384#endif
 385
 386        i = pci_enable_device(pdev);
 387        if (i) return i;
 388
 389        dev = alloc_etherdev(sizeof(*np));
 390        if (!dev) {
 391                printk (KERN_ERR PFX "cannot allocate ethernet device\n");
 392                return -ENOMEM;
 393        }
 394        SET_NETDEV_DEV(dev, &pdev->dev);
 395
 396        np = netdev_priv(dev);
 397
 398        if (pci_request_regions(pdev, DRV_NAME))
 399                goto err_out_free_netdev;
 400
 401        pci_set_master (pdev);
 402
 403        ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
 404        if (!ioaddr)
 405                goto err_out_free_res;
 406
 407        irq = pdev->irq;
 408
 409        if (drv_flags & DontUseEeprom)
 410                for (i = 0; i < 6; i++)
 411                        dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
 412        else {
 413                int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
 414                for (i = 0; i < 6; i++)
 415                        dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
 416        }
 417
 418        /* Reset the chip. */
 419        iowrite32(0x80000000, ioaddr + DMACtrl);
 420
 421        dev->base_addr = (unsigned long)ioaddr;
 422        dev->irq = irq;
 423
 424        pci_set_drvdata(pdev, dev);
 425        spin_lock_init(&np->lock);
 426
 427        np->pci_dev = pdev;
 428        np->chip_id = chip_idx;
 429        np->drv_flags = drv_flags;
 430        np->base = ioaddr;
 431
 432        ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
 433        if (!ring_space)
 434                goto err_out_cleardev;
 435        np->tx_ring = (struct yellowfin_desc *)ring_space;
 436        np->tx_ring_dma = ring_dma;
 437
 438        ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
 439        if (!ring_space)
 440                goto err_out_unmap_tx;
 441        np->rx_ring = (struct yellowfin_desc *)ring_space;
 442        np->rx_ring_dma = ring_dma;
 443
 444        ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
 445        if (!ring_space)
 446                goto err_out_unmap_rx;
 447        np->tx_status = (struct tx_status_words *)ring_space;
 448        np->tx_status_dma = ring_dma;
 449
 450        if (dev->mem_start)
 451                option = dev->mem_start;
 452
 453        /* The lower four bits are the media type. */
 454        if (option > 0) {
 455                if (option & 0x200)
 456                        np->full_duplex = 1;
 457                np->default_port = option & 15;
 458                if (np->default_port)
 459                        np->medialock = 1;
 460        }
 461        if (find_cnt < MAX_UNITS  &&  full_duplex[find_cnt] > 0)
 462                np->full_duplex = 1;
 463
 464        if (np->full_duplex)
 465                np->duplex_lock = 1;
 466
 467        /* The Yellowfin-specific entries in the device structure. */
 468        dev->open = &yellowfin_open;
 469        dev->hard_start_xmit = &yellowfin_start_xmit;
 470        dev->stop = &yellowfin_close;
 471        dev->set_multicast_list = &set_rx_mode;
 472        dev->do_ioctl = &netdev_ioctl;
 473        SET_ETHTOOL_OPS(dev, &ethtool_ops);
 474        dev->tx_timeout = yellowfin_tx_timeout;
 475        dev->watchdog_timeo = TX_TIMEOUT;
 476
 477        if (mtu)
 478                dev->mtu = mtu;
 479
 480        i = register_netdev(dev);
 481        if (i)
 482                goto err_out_unmap_status;
 483
 484        printk(KERN_INFO "%s: %s type %8x at %p, %s, IRQ %d.\n",
 485                   dev->name, pci_id_tbl[chip_idx].name,
 486                   ioread32(ioaddr + ChipRev), ioaddr,
 487                   print_mac(mac, dev->dev_addr), irq);
 488
 489        if (np->drv_flags & HasMII) {
 490                int phy, phy_idx = 0;
 491                for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
 492                        int mii_status = mdio_read(ioaddr, phy, 1);
 493                        if (mii_status != 0xffff  &&  mii_status != 0x0000) {
 494                                np->phys[phy_idx++] = phy;
 495                                np->advertising = mdio_read(ioaddr, phy, 4);
 496                                printk(KERN_INFO "%s: MII PHY found at address %d, status "
 497                                           "0x%4.4x advertising %4.4x.\n",
 498                                           dev->name, phy, mii_status, np->advertising);
 499                        }
 500                }
 501                np->mii_cnt = phy_idx;
 502        }
 503
 504        find_cnt++;
 505
 506        return 0;
 507
 508err_out_unmap_status:
 509        pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
 510                np->tx_status_dma);
 511err_out_unmap_rx:
 512        pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
 513err_out_unmap_tx:
 514        pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
 515err_out_cleardev:
 516        pci_set_drvdata(pdev, NULL);
 517        pci_iounmap(pdev, ioaddr);
 518err_out_free_res:
 519        pci_release_regions(pdev);
 520err_out_free_netdev:
 521        free_netdev (dev);
 522        return -ENODEV;
 523}
 524
 525static int __devinit read_eeprom(void __iomem *ioaddr, int location)
 526{
 527        int bogus_cnt = 10000;          /* Typical 33Mhz: 1050 ticks */
 528
 529        iowrite8(location, ioaddr + EEAddr);
 530        iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
 531        while ((ioread8(ioaddr + EEStatus) & 0x80)  &&  --bogus_cnt > 0)
 532                ;
 533        return ioread8(ioaddr + EERead);
 534}
 535
 536/* MII Managemen Data I/O accesses.
 537   These routines assume the MDIO controller is idle, and do not exit until
 538   the command is finished. */
 539
 540static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
 541{
 542        int i;
 543
 544        iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
 545        iowrite16(1, ioaddr + MII_Cmd);
 546        for (i = 10000; i >= 0; i--)
 547                if ((ioread16(ioaddr + MII_Status) & 1) == 0)
 548                        break;
 549        return ioread16(ioaddr + MII_Rd_Data);
 550}
 551
 552static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
 553{
 554        int i;
 555
 556        iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
 557        iowrite16(value, ioaddr + MII_Wr_Data);
 558
 559        /* Wait for the command to finish. */
 560        for (i = 10000; i >= 0; i--)
 561                if ((ioread16(ioaddr + MII_Status) & 1) == 0)
 562                        break;
 563        return;
 564}
 565
 566
 567static int yellowfin_open(struct net_device *dev)
 568{
 569        struct yellowfin_private *yp = netdev_priv(dev);
 570        void __iomem *ioaddr = yp->base;
 571        int i;
 572
 573        /* Reset the chip. */
 574        iowrite32(0x80000000, ioaddr + DMACtrl);
 575
 576        i = request_irq(dev->irq, &yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
 577        if (i) return i;
 578
 579        if (yellowfin_debug > 1)
 580                printk(KERN_DEBUG "%s: yellowfin_open() irq %d.\n",
 581                           dev->name, dev->irq);
 582
 583        yellowfin_init_ring(dev);
 584
 585        iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
 586        iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
 587
 588        for (i = 0; i < 6; i++)
 589                iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
 590
 591        /* Set up various condition 'select' registers.
 592           There are no options here. */
 593        iowrite32(0x00800080, ioaddr + TxIntrSel);      /* Interrupt on Tx abort */
 594        iowrite32(0x00800080, ioaddr + TxBranchSel);    /* Branch on Tx abort */
 595        iowrite32(0x00400040, ioaddr + TxWaitSel);      /* Wait on Tx status */
 596        iowrite32(0x00400040, ioaddr + RxIntrSel);      /* Interrupt on Rx done */
 597        iowrite32(0x00400040, ioaddr + RxBranchSel);    /* Branch on Rx error */
 598        iowrite32(0x00400040, ioaddr + RxWaitSel);      /* Wait on Rx done */
 599
 600        /* Initialize other registers: with so many this eventually this will
 601           converted to an offset/value list. */
 602        iowrite32(dma_ctrl, ioaddr + DMACtrl);
 603        iowrite16(fifo_cfg, ioaddr + FIFOcfg);
 604        /* Enable automatic generation of flow control frames, period 0xffff. */
 605        iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
 606
 607        yp->tx_threshold = 32;
 608        iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
 609
 610        if (dev->if_port == 0)
 611                dev->if_port = yp->default_port;
 612
 613        netif_start_queue(dev);
 614
 615        /* Setting the Rx mode will start the Rx process. */
 616        if (yp->drv_flags & IsGigabit) {
 617                /* We are always in full-duplex mode with gigabit! */
 618                yp->full_duplex = 1;
 619                iowrite16(0x01CF, ioaddr + Cnfg);
 620        } else {
 621                iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
 622                iowrite16(0x1018, ioaddr + FrameGap1);
 623                iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
 624        }
 625        set_rx_mode(dev);
 626
 627        /* Enable interrupts by setting the interrupt mask. */
 628        iowrite16(0x81ff, ioaddr + IntrEnb);                    /* See enum intr_status_bits */
 629        iowrite16(0x0000, ioaddr + EventStatus);                /* Clear non-interrupting events */
 630        iowrite32(0x80008000, ioaddr + RxCtrl);         /* Start Rx and Tx channels. */
 631        iowrite32(0x80008000, ioaddr + TxCtrl);
 632
 633        if (yellowfin_debug > 2) {
 634                printk(KERN_DEBUG "%s: Done yellowfin_open().\n",
 635                           dev->name);
 636        }
 637
 638        /* Set the timer to check for link beat. */
 639        init_timer(&yp->timer);
 640        yp->timer.expires = jiffies + 3*HZ;
 641        yp->timer.data = (unsigned long)dev;
 642        yp->timer.function = &yellowfin_timer;                          /* timer handler */
 643        add_timer(&yp->timer);
 644
 645        return 0;
 646}
 647
 648static void yellowfin_timer(unsigned long data)
 649{
 650        struct net_device *dev = (struct net_device *)data;
 651        struct yellowfin_private *yp = netdev_priv(dev);
 652        void __iomem *ioaddr = yp->base;
 653        int next_tick = 60*HZ;
 654
 655        if (yellowfin_debug > 3) {
 656                printk(KERN_DEBUG "%s: Yellowfin timer tick, status %8.8x.\n",
 657                           dev->name, ioread16(ioaddr + IntrStatus));
 658        }
 659
 660        if (yp->mii_cnt) {
 661                int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
 662                int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
 663                int negotiated = lpa & yp->advertising;
 664                if (yellowfin_debug > 1)
 665                        printk(KERN_DEBUG "%s: MII #%d status register is %4.4x, "
 666                                   "link partner capability %4.4x.\n",
 667                                   dev->name, yp->phys[0], bmsr, lpa);
 668
 669                yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
 670
 671                iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
 672
 673                if (bmsr & BMSR_LSTATUS)
 674                        next_tick = 60*HZ;
 675                else
 676                        next_tick = 3*HZ;
 677        }
 678
 679        yp->timer.expires = jiffies + next_tick;
 680        add_timer(&yp->timer);
 681}
 682
 683static void yellowfin_tx_timeout(struct net_device *dev)
 684{
 685        struct yellowfin_private *yp = netdev_priv(dev);
 686        void __iomem *ioaddr = yp->base;
 687
 688        printk(KERN_WARNING "%s: Yellowfin transmit timed out at %d/%d Tx "
 689                   "status %4.4x, Rx status %4.4x, resetting...\n",
 690                   dev->name, yp->cur_tx, yp->dirty_tx,
 691                   ioread32(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
 692
 693        /* Note: these should be KERN_DEBUG. */
 694        if (yellowfin_debug) {
 695                int i;
 696                printk(KERN_WARNING "  Rx ring %p: ", yp->rx_ring);
 697                for (i = 0; i < RX_RING_SIZE; i++)
 698                        printk(" %8.8x", yp->rx_ring[i].result_status);
 699                printk("\n"KERN_WARNING"  Tx ring %p: ", yp->tx_ring);
 700                for (i = 0; i < TX_RING_SIZE; i++)
 701                        printk(" %4.4x /%8.8x", yp->tx_status[i].tx_errs,
 702                                   yp->tx_ring[i].result_status);
 703                printk("\n");
 704        }
 705
 706        /* If the hardware is found to hang regularly, we will update the code
 707           to reinitialize the chip here. */
 708        dev->if_port = 0;
 709
 710        /* Wake the potentially-idle transmit channel. */
 711        iowrite32(0x10001000, yp->base + TxCtrl);
 712        if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
 713                netif_wake_queue (dev);         /* Typical path */
 714
 715        dev->trans_start = jiffies;
 716        dev->stats.tx_errors++;
 717}
 718
 719/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
 720static void yellowfin_init_ring(struct net_device *dev)
 721{
 722        struct yellowfin_private *yp = netdev_priv(dev);
 723        int i;
 724
 725        yp->tx_full = 0;
 726        yp->cur_rx = yp->cur_tx = 0;
 727        yp->dirty_tx = 0;
 728
 729        yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
 730
 731        for (i = 0; i < RX_RING_SIZE; i++) {
 732                yp->rx_ring[i].dbdma_cmd =
 733                        cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
 734                yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
 735                        ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
 736        }
 737
 738        for (i = 0; i < RX_RING_SIZE; i++) {
 739                struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
 740                yp->rx_skbuff[i] = skb;
 741                if (skb == NULL)
 742                        break;
 743                skb->dev = dev;         /* Mark as being used by this device. */
 744                skb_reserve(skb, 2);    /* 16 byte align the IP header. */
 745                yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
 746                        skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
 747        }
 748        yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
 749        yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
 750
 751#define NO_TXSTATS
 752#ifdef NO_TXSTATS
 753        /* In this mode the Tx ring needs only a single descriptor. */
 754        for (i = 0; i < TX_RING_SIZE; i++) {
 755                yp->tx_skbuff[i] = NULL;
 756                yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
 757                yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
 758                        ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
 759        }
 760        /* Wrap ring */
 761        yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
 762#else
 763{
 764        int j;
 765
 766        /* Tx ring needs a pair of descriptors, the second for the status. */
 767        for (i = 0; i < TX_RING_SIZE; i++) {
 768                j = 2*i;
 769                yp->tx_skbuff[i] = 0;
 770                /* Branch on Tx error. */
 771                yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
 772                yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
 773                        (j+1)*sizeof(struct yellowfin_desc));
 774                j++;
 775                if (yp->flags & FullTxStatus) {
 776                        yp->tx_ring[j].dbdma_cmd =
 777                                cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
 778                        yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
 779                        yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
 780                                i*sizeof(struct tx_status_words));
 781                } else {
 782                        /* Symbios chips write only tx_errs word. */
 783                        yp->tx_ring[j].dbdma_cmd =
 784                                cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
 785                        yp->tx_ring[j].request_cnt = 2;
 786                        /* Om pade ummmmm... */
 787                        yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
 788                                i*sizeof(struct tx_status_words) +
 789                                &(yp->tx_status[0].tx_errs) -
 790                                &(yp->tx_status[0]));
 791                }
 792                yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
 793                        ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
 794        }
 795        /* Wrap ring */
 796        yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
 797}
 798#endif
 799        yp->tx_tail_desc = &yp->tx_status[0];
 800        return;
 801}
 802
 803static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev)
 804{
 805        struct yellowfin_private *yp = netdev_priv(dev);
 806        unsigned entry;
 807        int len = skb->len;
 808
 809        netif_stop_queue (dev);
 810
 811        /* Note: Ordering is important here, set the field with the
 812           "ownership" bit last, and only then increment cur_tx. */
 813
 814        /* Calculate the next Tx descriptor entry. */
 815        entry = yp->cur_tx % TX_RING_SIZE;
 816
 817        if (gx_fix) {   /* Note: only works for paddable protocols e.g.  IP. */
 818                int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
 819                /* Fix GX chipset errata. */
 820                if (cacheline_end > 24  || cacheline_end == 0) {
 821                        len = skb->len + 32 - cacheline_end + 1;
 822                        if (skb_padto(skb, len)) {
 823                                yp->tx_skbuff[entry] = NULL;
 824                                netif_wake_queue(dev);
 825                                return 0;
 826                        }
 827                }
 828        }
 829        yp->tx_skbuff[entry] = skb;
 830
 831#ifdef NO_TXSTATS
 832        yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
 833                skb->data, len, PCI_DMA_TODEVICE));
 834        yp->tx_ring[entry].result_status = 0;
 835        if (entry >= TX_RING_SIZE-1) {
 836                /* New stop command. */
 837                yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
 838                yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
 839                        cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len);
 840        } else {
 841                yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
 842                yp->tx_ring[entry].dbdma_cmd =
 843                        cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len);
 844        }
 845        yp->cur_tx++;
 846#else
 847        yp->tx_ring[entry<<1].request_cnt = len;
 848        yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
 849                skb->data, len, PCI_DMA_TODEVICE));
 850        /* The input_last (status-write) command is constant, but we must
 851           rewrite the subsequent 'stop' command. */
 852
 853        yp->cur_tx++;
 854        {
 855                unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
 856                yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
 857        }
 858        /* Final step -- overwrite the old 'stop' command. */
 859
 860        yp->tx_ring[entry<<1].dbdma_cmd =
 861                cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
 862                                          CMD_TX_PKT | BRANCH_IFTRUE) | len);
 863#endif
 864
 865        /* Non-x86 Todo: explicitly flush cache lines here. */
 866
 867        /* Wake the potentially-idle transmit channel. */
 868        iowrite32(0x10001000, yp->base + TxCtrl);
 869
 870        if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
 871                netif_start_queue (dev);                /* Typical path */
 872        else
 873                yp->tx_full = 1;
 874        dev->trans_start = jiffies;
 875
 876        if (yellowfin_debug > 4) {
 877                printk(KERN_DEBUG "%s: Yellowfin transmit frame #%d queued in slot %d.\n",
 878                           dev->name, yp->cur_tx, entry);
 879        }
 880        return 0;
 881}
 882
 883/* The interrupt handler does all of the Rx thread work and cleans up
 884   after the Tx thread. */
 885static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance)
 886{
 887        struct net_device *dev = dev_instance;
 888        struct yellowfin_private *yp;
 889        void __iomem *ioaddr;
 890        int boguscnt = max_interrupt_work;
 891        unsigned int handled = 0;
 892
 893        yp = netdev_priv(dev);
 894        ioaddr = yp->base;
 895
 896        spin_lock (&yp->lock);
 897
 898        do {
 899                u16 intr_status = ioread16(ioaddr + IntrClear);
 900
 901                if (yellowfin_debug > 4)
 902                        printk(KERN_DEBUG "%s: Yellowfin interrupt, status %4.4x.\n",
 903                                   dev->name, intr_status);
 904
 905                if (intr_status == 0)
 906                        break;
 907                handled = 1;
 908
 909                if (intr_status & (IntrRxDone | IntrEarlyRx)) {
 910                        yellowfin_rx(dev);
 911                        iowrite32(0x10001000, ioaddr + RxCtrl);         /* Wake Rx engine. */
 912                }
 913
 914#ifdef NO_TXSTATS
 915                for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
 916                        int entry = yp->dirty_tx % TX_RING_SIZE;
 917                        struct sk_buff *skb;
 918
 919                        if (yp->tx_ring[entry].result_status == 0)
 920                                break;
 921                        skb = yp->tx_skbuff[entry];
 922                        dev->stats.tx_packets++;
 923                        dev->stats.tx_bytes += skb->len;
 924                        /* Free the original skb. */
 925                        pci_unmap_single(yp->pci_dev, le32_to_cpu(yp->tx_ring[entry].addr),
 926                                skb->len, PCI_DMA_TODEVICE);
 927                        dev_kfree_skb_irq(skb);
 928                        yp->tx_skbuff[entry] = NULL;
 929                }
 930                if (yp->tx_full
 931                        && yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
 932                        /* The ring is no longer full, clear tbusy. */
 933                        yp->tx_full = 0;
 934                        netif_wake_queue(dev);
 935                }
 936#else
 937                if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
 938                        unsigned dirty_tx = yp->dirty_tx;
 939
 940                        for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
 941                                 dirty_tx++) {
 942                                /* Todo: optimize this. */
 943                                int entry = dirty_tx % TX_RING_SIZE;
 944                                u16 tx_errs = yp->tx_status[entry].tx_errs;
 945                                struct sk_buff *skb;
 946
 947#ifndef final_version
 948                                if (yellowfin_debug > 5)
 949                                        printk(KERN_DEBUG "%s: Tx queue %d check, Tx status "
 950                                                   "%4.4x %4.4x %4.4x %4.4x.\n",
 951                                                   dev->name, entry,
 952                                                   yp->tx_status[entry].tx_cnt,
 953                                                   yp->tx_status[entry].tx_errs,
 954                                                   yp->tx_status[entry].total_tx_cnt,
 955                                                   yp->tx_status[entry].paused);
 956#endif
 957                                if (tx_errs == 0)
 958                                        break;  /* It still hasn't been Txed */
 959                                skb = yp->tx_skbuff[entry];
 960                                if (tx_errs & 0xF810) {
 961                                        /* There was an major error, log it. */
 962#ifndef final_version
 963                                        if (yellowfin_debug > 1)
 964                                                printk(KERN_DEBUG "%s: Transmit error, Tx status %4.4x.\n",
 965                                                           dev->name, tx_errs);
 966#endif
 967                                        dev->stats.tx_errors++;
 968                                        if (tx_errs & 0xF800) dev->stats.tx_aborted_errors++;
 969                                        if (tx_errs & 0x0800) dev->stats.tx_carrier_errors++;
 970                                        if (tx_errs & 0x2000) dev->stats.tx_window_errors++;
 971                                        if (tx_errs & 0x8000) dev->stats.tx_fifo_errors++;
 972                                } else {
 973#ifndef final_version
 974                                        if (yellowfin_debug > 4)
 975                                                printk(KERN_DEBUG "%s: Normal transmit, Tx status %4.4x.\n",
 976                                                           dev->name, tx_errs);
 977#endif
 978                                        dev->stats.tx_bytes += skb->len;
 979                                        dev->stats.collisions += tx_errs & 15;
 980                                        dev->stats.tx_packets++;
 981                                }
 982                                /* Free the original skb. */
 983                                pci_unmap_single(yp->pci_dev,
 984                                        yp->tx_ring[entry<<1].addr, skb->len,
 985                                        PCI_DMA_TODEVICE);
 986                                dev_kfree_skb_irq(skb);
 987                                yp->tx_skbuff[entry] = 0;
 988                                /* Mark status as empty. */
 989                                yp->tx_status[entry].tx_errs = 0;
 990                        }
 991
 992#ifndef final_version
 993                        if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
 994                                printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
 995                                           dev->name, dirty_tx, yp->cur_tx, yp->tx_full);
 996                                dirty_tx += TX_RING_SIZE;
 997                        }
 998#endif
 999
1000                        if (yp->tx_full
1001                                && yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1002                                /* The ring is no longer full, clear tbusy. */
1003                                yp->tx_full = 0;
1004                                netif_wake_queue(dev);
1005                        }
1006
1007                        yp->dirty_tx = dirty_tx;
1008                        yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1009                }
1010#endif
1011
1012                /* Log errors and other uncommon events. */
1013                if (intr_status & 0x2ee)        /* Abnormal error summary. */
1014                        yellowfin_error(dev, intr_status);
1015
1016                if (--boguscnt < 0) {
1017                        printk(KERN_WARNING "%s: Too much work at interrupt, "
1018                                   "status=0x%4.4x.\n",
1019                                   dev->name, intr_status);
1020                        break;
1021                }
1022        } while (1);
1023
1024        if (yellowfin_debug > 3)
1025                printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1026                           dev->name, ioread16(ioaddr + IntrStatus));
1027
1028        spin_unlock (&yp->lock);
1029        return IRQ_RETVAL(handled);
1030}
1031
1032/* This routine is logically part of the interrupt handler, but separated
1033   for clarity and better register allocation. */
1034static int yellowfin_rx(struct net_device *dev)
1035{
1036        struct yellowfin_private *yp = netdev_priv(dev);
1037        int entry = yp->cur_rx % RX_RING_SIZE;
1038        int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1039
1040        if (yellowfin_debug > 4) {
1041                printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %8.8x.\n",
1042                           entry, yp->rx_ring[entry].result_status);
1043                printk(KERN_DEBUG "   #%d desc. %8.8x %8.8x %8.8x.\n",
1044                           entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1045                           yp->rx_ring[entry].result_status);
1046        }
1047
1048        /* If EOP is set on the next entry, it's a new packet. Send it up. */
1049        while (1) {
1050                struct yellowfin_desc *desc = &yp->rx_ring[entry];
1051                struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1052                s16 frame_status;
1053                u16 desc_status;
1054                int data_size;
1055                u8 *buf_addr;
1056
1057                if(!desc->result_status)
1058                        break;
1059                pci_dma_sync_single_for_cpu(yp->pci_dev, le32_to_cpu(desc->addr),
1060                        yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1061                desc_status = le32_to_cpu(desc->result_status) >> 16;
1062                buf_addr = rx_skb->data;
1063                data_size = (le32_to_cpu(desc->dbdma_cmd) -
1064                        le32_to_cpu(desc->result_status)) & 0xffff;
1065                frame_status = get_unaligned_le16(&(buf_addr[data_size - 2]));
1066                if (yellowfin_debug > 4)
1067                        printk(KERN_DEBUG "  yellowfin_rx() status was %4.4x.\n",
1068                                   frame_status);
1069                if (--boguscnt < 0)
1070                        break;
1071                if ( ! (desc_status & RX_EOP)) {
1072                        if (data_size != 0)
1073                                printk(KERN_WARNING "%s: Oversized Ethernet frame spanned multiple buffers,"
1074                                           " status %4.4x, data_size %d!\n", dev->name, desc_status, data_size);
1075                        dev->stats.rx_length_errors++;
1076                } else if ((yp->drv_flags & IsGigabit)  &&  (frame_status & 0x0038)) {
1077                        /* There was a error. */
1078                        if (yellowfin_debug > 3)
1079                                printk(KERN_DEBUG "  yellowfin_rx() Rx error was %4.4x.\n",
1080                                           frame_status);
1081                        dev->stats.rx_errors++;
1082                        if (frame_status & 0x0060) dev->stats.rx_length_errors++;
1083                        if (frame_status & 0x0008) dev->stats.rx_frame_errors++;
1084                        if (frame_status & 0x0010) dev->stats.rx_crc_errors++;
1085                        if (frame_status < 0) dev->stats.rx_dropped++;
1086                } else if ( !(yp->drv_flags & IsGigabit)  &&
1087                                   ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1088                        u8 status1 = buf_addr[data_size-2];
1089                        u8 status2 = buf_addr[data_size-1];
1090                        dev->stats.rx_errors++;
1091                        if (status1 & 0xC0) dev->stats.rx_length_errors++;
1092                        if (status2 & 0x03) dev->stats.rx_frame_errors++;
1093                        if (status2 & 0x04) dev->stats.rx_crc_errors++;
1094                        if (status2 & 0x80) dev->stats.rx_dropped++;
1095#ifdef YF_PROTOTYPE             /* Support for prototype hardware errata. */
1096                } else if ((yp->flags & HasMACAddrBug)  &&
1097                        memcmp(le32_to_cpu(yp->rx_ring_dma +
1098                                entry*sizeof(struct yellowfin_desc)),
1099                                dev->dev_addr, 6) != 0 &&
1100                        memcmp(le32_to_cpu(yp->rx_ring_dma +
1101                                entry*sizeof(struct yellowfin_desc)),
1102                                "\377\377\377\377\377\377", 6) != 0) {
1103                        if (bogus_rx++ == 0) {
1104                                DECLARE_MAC_BUF(mac);
1105                                printk(KERN_WARNING "%s: Bad frame to %s\n",
1106                                           dev->name, print_mac(mac, buf_addr));
1107                        }
1108#endif
1109                } else {
1110                        struct sk_buff *skb;
1111                        int pkt_len = data_size -
1112                                (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1113                        /* To verify: Yellowfin Length should omit the CRC! */
1114
1115#ifndef final_version
1116                        if (yellowfin_debug > 4)
1117                                printk(KERN_DEBUG "  yellowfin_rx() normal Rx pkt length %d"
1118                                           " of %d, bogus_cnt %d.\n",
1119                                           pkt_len, data_size, boguscnt);
1120#endif
1121                        /* Check if the packet is long enough to just pass up the skbuff
1122                           without copying to a properly sized skbuff. */
1123                        if (pkt_len > rx_copybreak) {
1124                                skb_put(skb = rx_skb, pkt_len);
1125                                pci_unmap_single(yp->pci_dev,
1126                                        le32_to_cpu(yp->rx_ring[entry].addr),
1127                                        yp->rx_buf_sz,
1128                                        PCI_DMA_FROMDEVICE);
1129                                yp->rx_skbuff[entry] = NULL;
1130                        } else {
1131                                skb = dev_alloc_skb(pkt_len + 2);
1132                                if (skb == NULL)
1133                                        break;
1134                                skb_reserve(skb, 2);    /* 16 byte align the IP header */
1135                                skb_copy_to_linear_data(skb, rx_skb->data, pkt_len);
1136                                skb_put(skb, pkt_len);
1137                                pci_dma_sync_single_for_device(yp->pci_dev,
1138                                                                le32_to_cpu(desc->addr),
1139                                                                yp->rx_buf_sz,
1140                                                                PCI_DMA_FROMDEVICE);
1141                        }
1142                        skb->protocol = eth_type_trans(skb, dev);
1143                        netif_rx(skb);
1144                        dev->last_rx = jiffies;
1145                        dev->stats.rx_packets++;
1146                        dev->stats.rx_bytes += pkt_len;
1147                }
1148                entry = (++yp->cur_rx) % RX_RING_SIZE;
1149        }
1150
1151        /* Refill the Rx ring buffers. */
1152        for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1153                entry = yp->dirty_rx % RX_RING_SIZE;
1154                if (yp->rx_skbuff[entry] == NULL) {
1155                        struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
1156                        if (skb == NULL)
1157                                break;                          /* Better luck next round. */
1158                        yp->rx_skbuff[entry] = skb;
1159                        skb->dev = dev; /* Mark as being used by this device. */
1160                        skb_reserve(skb, 2);    /* Align IP on 16 byte boundaries */
1161                        yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1162                                skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1163                }
1164                yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1165                yp->rx_ring[entry].result_status = 0;   /* Clear complete bit. */
1166                if (entry != 0)
1167                        yp->rx_ring[entry - 1].dbdma_cmd =
1168                                cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1169                else
1170                        yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1171                                cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1172                                                        | yp->rx_buf_sz);
1173        }
1174
1175        return 0;
1176}
1177
1178static void yellowfin_error(struct net_device *dev, int intr_status)
1179{
1180        printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1181                   dev->name, intr_status);
1182        /* Hmmmmm, it's not clear what to do here. */
1183        if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1184                dev->stats.tx_errors++;
1185        if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1186                dev->stats.rx_errors++;
1187}
1188
1189static int yellowfin_close(struct net_device *dev)
1190{
1191        struct yellowfin_private *yp = netdev_priv(dev);
1192        void __iomem *ioaddr = yp->base;
1193        int i;
1194
1195        netif_stop_queue (dev);
1196
1197        if (yellowfin_debug > 1) {
1198                printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x "
1199                           "Rx %4.4x Int %2.2x.\n",
1200                           dev->name, ioread16(ioaddr + TxStatus),
1201                           ioread16(ioaddr + RxStatus),
1202                           ioread16(ioaddr + IntrStatus));
1203                printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d,  Rx %d / %d.\n",
1204                           dev->name, yp->cur_tx, yp->dirty_tx, yp->cur_rx, yp->dirty_rx);
1205        }
1206
1207        /* Disable interrupts by clearing the interrupt mask. */
1208        iowrite16(0x0000, ioaddr + IntrEnb);
1209
1210        /* Stop the chip's Tx and Rx processes. */
1211        iowrite32(0x80000000, ioaddr + RxCtrl);
1212        iowrite32(0x80000000, ioaddr + TxCtrl);
1213
1214        del_timer(&yp->timer);
1215
1216#if defined(__i386__)
1217        if (yellowfin_debug > 2) {
1218                printk("\n"KERN_DEBUG"  Tx ring at %8.8llx:\n",
1219                                (unsigned long long)yp->tx_ring_dma);
1220                for (i = 0; i < TX_RING_SIZE*2; i++)
1221                        printk(" %c #%d desc. %8.8x %8.8x %8.8x %8.8x.\n",
1222                                   ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1223                                   i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1224                                   yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1225                printk(KERN_DEBUG "  Tx status %p:\n", yp->tx_status);
1226                for (i = 0; i < TX_RING_SIZE; i++)
1227                        printk("   #%d status %4.4x %4.4x %4.4x %4.4x.\n",
1228                                   i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1229                                   yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1230
1231                printk("\n"KERN_DEBUG "  Rx ring %8.8llx:\n",
1232                                (unsigned long long)yp->rx_ring_dma);
1233                for (i = 0; i < RX_RING_SIZE; i++) {
1234                        printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x %8.8x\n",
1235                                   ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1236                                   i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1237                                   yp->rx_ring[i].result_status);
1238                        if (yellowfin_debug > 6) {
1239                                if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1240                                        int j;
1241                                        for (j = 0; j < 0x50; j++)
1242                                                printk(" %4.4x",
1243                                                           get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1244                                        printk("\n");
1245                                }
1246                        }
1247                }
1248        }
1249#endif /* __i386__ debugging only */
1250
1251        free_irq(dev->irq, dev);
1252
1253        /* Free all the skbuffs in the Rx queue. */
1254        for (i = 0; i < RX_RING_SIZE; i++) {
1255                yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
1256                yp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1257                if (yp->rx_skbuff[i]) {
1258                        dev_kfree_skb(yp->rx_skbuff[i]);
1259                }
1260                yp->rx_skbuff[i] = NULL;
1261        }
1262        for (i = 0; i < TX_RING_SIZE; i++) {
1263                if (yp->tx_skbuff[i])
1264                        dev_kfree_skb(yp->tx_skbuff[i]);
1265                yp->tx_skbuff[i] = NULL;
1266        }
1267
1268#ifdef YF_PROTOTYPE                     /* Support for prototype hardware errata. */
1269        if (yellowfin_debug > 0) {
1270                printk(KERN_DEBUG "%s: Received %d frames that we should not have.\n",
1271                           dev->name, bogus_rx);
1272        }
1273#endif
1274
1275        return 0;
1276}
1277
1278/* Set or clear the multicast filter for this adaptor. */
1279
1280static void set_rx_mode(struct net_device *dev)
1281{
1282        struct yellowfin_private *yp = netdev_priv(dev);
1283        void __iomem *ioaddr = yp->base;
1284        u16 cfg_value = ioread16(ioaddr + Cnfg);
1285
1286        /* Stop the Rx process to change any value. */
1287        iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1288        if (dev->flags & IFF_PROMISC) {                 /* Set promiscuous. */
1289                iowrite16(0x000F, ioaddr + AddrMode);
1290        } else if ((dev->mc_count > 64)  ||  (dev->flags & IFF_ALLMULTI)) {
1291                /* Too many to filter well, or accept all multicasts. */
1292                iowrite16(0x000B, ioaddr + AddrMode);
1293        } else if (dev->mc_count > 0) { /* Must use the multicast hash table. */
1294                struct dev_mc_list *mclist;
1295                u16 hash_table[4];
1296                int i;
1297                memset(hash_table, 0, sizeof(hash_table));
1298                for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1299                         i++, mclist = mclist->next) {
1300                        unsigned int bit;
1301
1302                        /* Due to a bug in the early chip versions, multiple filter
1303                           slots must be set for each address. */
1304                        if (yp->drv_flags & HasMulticastBug) {
1305                                bit = (ether_crc_le(3, mclist->dmi_addr) >> 3) & 0x3f;
1306                                hash_table[bit >> 4] |= (1 << bit);
1307                                bit = (ether_crc_le(4, mclist->dmi_addr) >> 3) & 0x3f;
1308                                hash_table[bit >> 4] |= (1 << bit);
1309                                bit = (ether_crc_le(5, mclist->dmi_addr) >> 3) & 0x3f;
1310                                hash_table[bit >> 4] |= (1 << bit);
1311                        }
1312                        bit = (ether_crc_le(6, mclist->dmi_addr) >> 3) & 0x3f;
1313                        hash_table[bit >> 4] |= (1 << bit);
1314                }
1315                /* Copy the hash table to the chip. */
1316                for (i = 0; i < 4; i++)
1317                        iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1318                iowrite16(0x0003, ioaddr + AddrMode);
1319        } else {                                        /* Normal, unicast/broadcast-only mode. */
1320                iowrite16(0x0001, ioaddr + AddrMode);
1321        }
1322        /* Restart the Rx process. */
1323        iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);
1324}
1325
1326static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1327{
1328        struct yellowfin_private *np = netdev_priv(dev);
1329        strcpy(info->driver, DRV_NAME);
1330        strcpy(info->version, DRV_VERSION);
1331        strcpy(info->bus_info, pci_name(np->pci_dev));
1332}
1333
1334static const struct ethtool_ops ethtool_ops = {
1335        .get_drvinfo = yellowfin_get_drvinfo
1336};
1337
1338static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1339{
1340        struct yellowfin_private *np = netdev_priv(dev);
1341        void __iomem *ioaddr = np->base;
1342        struct mii_ioctl_data *data = if_mii(rq);
1343
1344        switch(cmd) {
1345        case SIOCGMIIPHY:               /* Get address of MII PHY in use. */
1346                data->phy_id = np->phys[0] & 0x1f;
1347                /* Fall Through */
1348
1349        case SIOCGMIIREG:               /* Read MII PHY register. */
1350                data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1351                return 0;
1352
1353        case SIOCSMIIREG:               /* Write MII PHY register. */
1354                if (!capable(CAP_NET_ADMIN))
1355                        return -EPERM;
1356                if (data->phy_id == np->phys[0]) {
1357                        u16 value = data->val_in;
1358                        switch (data->reg_num) {
1359                        case 0:
1360                                /* Check for autonegotiation on or reset. */
1361                                np->medialock = (value & 0x9000) ? 0 : 1;
1362                                if (np->medialock)
1363                                        np->full_duplex = (value & 0x0100) ? 1 : 0;
1364                                break;
1365                        case 4: np->advertising = value; break;
1366                        }
1367                        /* Perhaps check_duplex(dev), depending on chip semantics. */
1368                }
1369                mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1370                return 0;
1371        default:
1372                return -EOPNOTSUPP;
1373        }
1374}
1375
1376
1377static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1378{
1379        struct net_device *dev = pci_get_drvdata(pdev);
1380        struct yellowfin_private *np;
1381
1382        BUG_ON(!dev);
1383        np = netdev_priv(dev);
1384
1385        pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1386                np->tx_status_dma);
1387        pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1388        pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1389        unregister_netdev (dev);
1390
1391        pci_iounmap(pdev, np->base);
1392
1393        pci_release_regions (pdev);
1394
1395        free_netdev (dev);
1396        pci_set_drvdata(pdev, NULL);
1397}
1398
1399
1400static struct pci_driver yellowfin_driver = {
1401        .name           = DRV_NAME,
1402        .id_table       = yellowfin_pci_tbl,
1403        .probe          = yellowfin_init_one,
1404        .remove         = __devexit_p(yellowfin_remove_one),
1405};
1406
1407
1408static int __init yellowfin_init (void)
1409{
1410/* when a module, this is printed whether or not devices are found in probe */
1411#ifdef MODULE
1412        printk(version);
1413#endif
1414        return pci_register_driver(&yellowfin_driver);
1415}
1416
1417
1418static void __exit yellowfin_cleanup (void)
1419{
1420        pci_unregister_driver (&yellowfin_driver);
1421}
1422
1423
1424module_init(yellowfin_init);
1425module_exit(yellowfin_cleanup);
1426
1427/*
1428 * Local variables:
1429 *  compile-command: "gcc -DMODULE -Wall -Wstrict-prototypes -O6 -c yellowfin.c"
1430 *  compile-command-alphaLX: "gcc -DMODULE -Wall -Wstrict-prototypes -O2 -c yellowfin.c -fomit-frame-pointer -fno-strength-reduce -mno-fp-regs -Wa,-m21164a -DBWX_USABLE -DBWIO_ENABLED"
1431 *  simple-compile-command: "gcc -DMODULE -O6 -c yellowfin.c"
1432 *  c-indent-level: 4
1433 *  c-basic-offset: 4
1434 *  tab-width: 4
1435 * End:
1436 */
1437
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