LXR linux/drivers/net/tulip/tulip.h

   1/*
   2        drivers/net/tulip/tulip.h
   3
   4        Copyright 2000,2001  The Linux Kernel Team
   5        Written/copyright 1994-2001 by Donald Becker.
   6
   7        This software may be used and distributed according to the terms
   8        of the GNU General Public License, incorporated herein by reference.
   9
  10        Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
  11        for more information on this driver.
  12
  13        Please submit bugs to http://bugzilla.kernel.org/ .
  14*/
  15
  16#ifndef __NET_TULIP_H__
  17#define __NET_TULIP_H__
  18
  19#include <linux/kernel.h>
  20#include <linux/types.h>
  21#include <linux/spinlock.h>
  22#include <linux/netdevice.h>
  23#include <linux/timer.h>
  24#include <linux/delay.h>
  25#include <linux/pci.h>
  26#include <asm/io.h>
  27#include <asm/irq.h>
  28#include <asm/unaligned.h>
  29
  30
  31
  32/* undefine, or define to various debugging levels (>4 == obscene levels) */
  33#define TULIP_DEBUG 1
  34
  35#ifdef CONFIG_TULIP_MMIO
  36#define TULIP_BAR       1       /* CBMA */
  37#else
  38#define TULIP_BAR       0       /* CBIO */
  39#endif
  40
  41
  42
  43struct tulip_chip_table {
  44        char *chip_name;
  45        int io_size;
  46        int valid_intrs;        /* CSR7 interrupt enable settings */
  47        int flags;
  48        void (*media_timer) (unsigned long);
  49        work_func_t media_task;
  50};
  51
  52
  53enum tbl_flag {
  54        HAS_MII                 = 0x0001,
  55        HAS_MEDIA_TABLE         = 0x0002,
  56        CSR12_IN_SROM           = 0x0004,
  57        ALWAYS_CHECK_MII        = 0x0008,
  58        HAS_ACPI                = 0x0010,
  59        MC_HASH_ONLY            = 0x0020, /* Hash-only multicast filter. */
  60        HAS_PNICNWAY            = 0x0080,
  61        HAS_NWAY                = 0x0040, /* Uses internal NWay xcvr. */
  62        HAS_INTR_MITIGATION     = 0x0100,
  63        IS_ASIX                 = 0x0200,
  64        HAS_8023X               = 0x0400,
  65        COMET_MAC_ADDR          = 0x0800,
  66        HAS_PCI_MWI             = 0x1000,
  67        HAS_PHY_IRQ             = 0x2000,
  68        HAS_SWAPPED_SEEPROM     = 0x4000,
  69        NEEDS_FAKE_MEDIA_TABLE  = 0x8000,
  70};
  71
  72
  73/* chip types.  careful!  order is VERY IMPORTANT here, as these
  74 * are used throughout the driver as indices into arrays */
  75/* Note 21142 == 21143. */
  76enum chips {
  77        DC21040 = 0,
  78        DC21041 = 1,
  79        DC21140 = 2,
  80        DC21142 = 3, DC21143 = 3,
  81        LC82C168,
  82        MX98713,
  83        MX98715,
  84        MX98725,
  85        AX88140,
  86        PNIC2,
  87        COMET,
  88        COMPEX9881,
  89        I21145,
  90        DM910X,
  91        CONEXANT,
  92};
  93
  94
  95enum MediaIs {
  96        MediaIsFD = 1,
  97        MediaAlwaysFD = 2,
  98        MediaIsMII = 4,
  99        MediaIsFx = 8,
 100        MediaIs100 = 16
 101};
 102
 103
 104/* Offsets to the Command and Status Registers, "CSRs".  All accesses
 105   must be longword instructions and quadword aligned. */
 106enum tulip_offsets {
 107        CSR0 = 0,
 108        CSR1 = 0x08,
 109        CSR2 = 0x10,
 110        CSR3 = 0x18,
 111        CSR4 = 0x20,
 112        CSR5 = 0x28,
 113        CSR6 = 0x30,
 114        CSR7 = 0x38,
 115        CSR8 = 0x40,
 116        CSR9 = 0x48,
 117        CSR10 = 0x50,
 118        CSR11 = 0x58,
 119        CSR12 = 0x60,
 120        CSR13 = 0x68,
 121        CSR14 = 0x70,
 122        CSR15 = 0x78,
 123};
 124
 125/* register offset and bits for CFDD PCI config reg */
 126enum pci_cfg_driver_reg {
 127        CFDD = 0x40,
 128        CFDD_Sleep = (1 << 31),
 129        CFDD_Snooze = (1 << 30),
 130};
 131
 132#define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
 133
 134/* The bits in the CSR5 status registers, mostly interrupt sources. */
 135enum status_bits {
 136        TimerInt = 0x800,
 137        SystemError = 0x2000,
 138        TPLnkFail = 0x1000,
 139        TPLnkPass = 0x10,
 140        NormalIntr = 0x10000,
 141        AbnormalIntr = 0x8000,
 142        RxJabber = 0x200,
 143        RxDied = 0x100,
 144        RxNoBuf = 0x80,
 145        RxIntr = 0x40,
 146        TxFIFOUnderflow = 0x20,
 147        RxErrIntr = 0x10,
 148        TxJabber = 0x08,
 149        TxNoBuf = 0x04,
 150        TxDied = 0x02,
 151        TxIntr = 0x01,
 152};
 153
 154/* bit mask for CSR5 TX/RX process state */
 155#define CSR5_TS 0x00700000
 156#define CSR5_RS 0x000e0000
 157
 158enum tulip_mode_bits {
 159        TxThreshold             = (1 << 22),
 160        FullDuplex              = (1 << 9),
 161        TxOn                    = 0x2000,
 162        AcceptBroadcast         = 0x0100,
 163        AcceptAllMulticast      = 0x0080,
 164        AcceptAllPhys           = 0x0040,
 165        AcceptRunt              = 0x0008,
 166        RxOn                    = 0x0002,
 167        RxTx                    = (TxOn | RxOn),
 168};
 169
 170
 171enum tulip_busconfig_bits {
 172        MWI                     = (1 << 24),
 173        MRL                     = (1 << 23),
 174        MRM                     = (1 << 21),
 175        CALShift                = 14,
 176        BurstLenShift           = 8,
 177};
 178
 179
 180/* The Tulip Rx and Tx buffer descriptors. */
 181struct tulip_rx_desc {
 182        __le32 status;
 183        __le32 length;
 184        __le32 buffer1;
 185        __le32 buffer2;
 186};
 187
 188
 189struct tulip_tx_desc {
 190        __le32 status;
 191        __le32 length;
 192        __le32 buffer1;
 193        __le32 buffer2;         /* We use only buffer 1.  */
 194};
 195
 196
 197enum desc_status_bits {
 198        DescOwned    = 0x80000000,
 199        DescWholePkt = 0x60000000,
 200        DescEndPkt   = 0x40000000,
 201        DescStartPkt = 0x20000000,
 202        DescEndRing  = 0x02000000,
 203        DescUseLink  = 0x01000000,
 204        RxDescFatalErr = 0x008000,
 205        RxWholePkt   = 0x00000300,
 206};
 207
 208
 209enum t21143_csr6_bits {
 210        csr6_sc = (1<<31),
 211        csr6_ra = (1<<30),
 212        csr6_ign_dest_msb = (1<<26),
 213        csr6_mbo = (1<<25),
 214        csr6_scr = (1<<24),  /* scramble mode flag: can't be set */
 215        csr6_pcs = (1<<23),  /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
 216        csr6_ttm = (1<<22),  /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
 217        csr6_sf = (1<<21),   /* Store and forward. If set ignores TR bits */
 218        csr6_hbd = (1<<19),  /* Heart beat disable. Disables SQE function in 10baseT */
 219        csr6_ps = (1<<18),   /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
 220        csr6_ca = (1<<17),   /* Collision Offset Enable. If set uses special algorithm in low collision situations */
 221        csr6_trh = (1<<15),  /* Transmit Threshold high bit */
 222        csr6_trl = (1<<14),  /* Transmit Threshold low bit */
 223
 224        /***************************************************************
 225         * This table shows transmit threshold values based on media   *
 226         * and these two registers (from PNIC1 & 2 docs) Note: this is *
 227         * all meaningless if sf is set.                               *
 228         ***************************************************************/
 229
 230        /***********************************
 231         * (trh,trl) * 100BaseTX * 10BaseT *
 232         ***********************************
 233         *   (0,0)   *     128   *    72   *
 234         *   (0,1)   *     256   *    96   *
 235         *   (1,0)   *     512   *   128   *
 236         *   (1,1)   *    1024   *   160   *
 237         ***********************************/
 238
 239        csr6_fc = (1<<12),   /* Forces a collision in next transmission (for testing in loopback mode) */
 240        csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
 241        csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
 242        /* set both and you get (PHY) loopback */
 243        csr6_fd = (1<<9),    /* Full duplex mode, disables hearbeat, no loopback */
 244        csr6_pm = (1<<7),    /* Pass All Multicast */
 245        csr6_pr = (1<<6),    /* Promiscuous mode */
 246        csr6_sb = (1<<5),    /* Start(1)/Stop(0) backoff counter */
 247        csr6_if = (1<<4),    /* Inverse Filtering, rejects only addresses in address table: can't be set */
 248        csr6_pb = (1<<3),    /* Pass Bad Frames, (1) causes even bad frames to be passed on */
 249        csr6_ho = (1<<2),    /* Hash-only filtering mode: can't be set */
 250        csr6_hp = (1<<0),    /* Hash/Perfect Receive Filtering Mode: can't be set */
 251
 252        csr6_mask_capture = (csr6_sc | csr6_ca),
 253        csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
 254        csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
 255        csr6_mask_hdcaptt = (csr6_mask_hdcap  | csr6_trh | csr6_trl),
 256        csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
 257        csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
 258        csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
 259        csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
 260};
 261
 262
 263/* Keep the ring sizes a power of two for efficiency.
 264   Making the Tx ring too large decreases the effectiveness of channel
 265   bonding and packet priority.
 266   There are no ill effects from too-large receive rings. */
 267
 268#define TX_RING_SIZE    32
 269#define RX_RING_SIZE    128
 270#define MEDIA_MASK     31
 271
 272/* The receiver on the DC21143 rev 65 can fail to close the last
 273 * receive descriptor in certain circumstances (see errata) when
 274 * using MWI. This can only occur if the receive buffer ends on
 275 * a cache line boundary, so the "+ 4" below ensures it doesn't.
 276 */
 277#define PKT_BUF_SZ      (1536 + 4)      /* Size of each temporary Rx buffer. */
 278
 279#define TULIP_MIN_CACHE_LINE    8       /* in units of 32-bit words */
 280
 281#if defined(__sparc__) || defined(__hppa__)
 282/* The UltraSparc PCI controllers will disconnect at every 64-byte
 283 * crossing anyways so it makes no sense to tell Tulip to burst
 284 * any more than that.
 285 */
 286#define TULIP_MAX_CACHE_LINE    16      /* in units of 32-bit words */
 287#else
 288#define TULIP_MAX_CACHE_LINE    32      /* in units of 32-bit words */
 289#endif
 290
 291
 292/* Ring-wrap flag in length field, use for last ring entry.
 293        0x01000000 means chain on buffer2 address,
 294        0x02000000 means use the ring start address in CSR2/3.
 295   Note: Some work-alike chips do not function correctly in chained mode.
 296   The ASIX chip works only in chained mode.
 297   Thus we indicates ring mode, but always write the 'next' field for
 298   chained mode as well.
 299*/
 300#define DESC_RING_WRAP 0x02000000
 301
 302
 303#define EEPROM_SIZE 512         /* 2 << EEPROM_ADDRLEN */
 304
 305
 306#define RUN_AT(x) (jiffies + (x))
 307
 308#define get_u16(ptr) get_unaligned_le16((ptr))
 309
 310struct medialeaf {
 311        u8 type;
 312        u8 media;
 313        unsigned char *leafdata;
 314};
 315
 316
 317struct mediatable {
 318        u16 defaultmedia;
 319        u8 leafcount;
 320        u8 csr12dir;            /* General purpose pin directions. */
 321        unsigned has_mii:1;
 322        unsigned has_nonmii:1;
 323        unsigned has_reset:6;
 324        u32 csr15dir;
 325        u32 csr15val;           /* 21143 NWay setting. */
 326        struct medialeaf mleaf[0];
 327};
 328
 329
 330struct mediainfo {
 331        struct mediainfo *next;
 332        int info_type;
 333        int index;
 334        unsigned char *info;
 335};
 336
 337struct ring_info {
 338        struct sk_buff  *skb;
 339        dma_addr_t      mapping;
 340};
 341
 342
 343struct tulip_private {
 344        const char *product_name;
 345        struct net_device *next_module;
 346        struct tulip_rx_desc *rx_ring;
 347        struct tulip_tx_desc *tx_ring;
 348        dma_addr_t rx_ring_dma;
 349        dma_addr_t tx_ring_dma;
 350        /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 351        struct ring_info tx_buffers[TX_RING_SIZE];
 352        /* The addresses of receive-in-place skbuffs. */
 353        struct ring_info rx_buffers[RX_RING_SIZE];
 354        u16 setup_frame[96];    /* Pseudo-Tx frame to init address table. */
 355        int chip_id;
 356        int revision;
 357        int flags;
 358        struct napi_struct napi;
 359        struct net_device_stats stats;
 360        struct timer_list timer;        /* Media selection timer. */
 361        struct timer_list oom_timer;    /* Out of memory timer. */
 362        u32 mc_filter[2];
 363        spinlock_t lock;
 364        spinlock_t mii_lock;
 365        unsigned int cur_rx, cur_tx;    /* The next free ring entry */
 366        unsigned int dirty_rx, dirty_tx;        /* The ring entries to be free()ed. */
 367
 368#ifdef  CONFIG_TULIP_NAPI_HW_MITIGATION
 369        int mit_on;
 370#endif
 371        unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 372        unsigned int full_duplex_lock:1;
 373        unsigned int fake_addr:1;       /* Multiport board faked address. */
 374        unsigned int default_port:4;    /* Last dev->if_port value. */
 375        unsigned int media2:4;  /* Secondary monitored media port. */
 376        unsigned int medialock:1;       /* Don't sense media type. */
 377        unsigned int mediasense:1;      /* Media sensing in progress. */
 378        unsigned int nway:1, nwayset:1;         /* 21143 internal NWay. */
 379        unsigned int timeout_recovery:1;
 380        unsigned int csr0;      /* CSR0 setting. */
 381        unsigned int csr6;      /* Current CSR6 control settings. */
 382        unsigned char eeprom[EEPROM_SIZE];      /* Serial EEPROM contents. */
 383        void (*link_change) (struct net_device * dev, int csr5);
 384        u16 sym_advertise, mii_advertise; /* NWay capabilities advertised.  */
 385        u16 lpar;               /* 21143 Link partner ability. */
 386        u16 advertising[4];
 387        signed char phys[4], mii_cnt;   /* MII device addresses. */
 388        struct mediatable *mtable;
 389        int cur_index;          /* Current media index. */
 390        int saved_if_port;
 391        struct pci_dev *pdev;
 392        int ttimer;
 393        int susp_rx;
 394        unsigned long nir;
 395        void __iomem *base_addr;
 396        int csr12_shadow;
 397        int pad0;               /* Used for 8-byte alignment */
 398        struct work_struct media_work;
 399        struct net_device *dev;
 400};
 401
 402
 403struct eeprom_fixup {
 404        char *name;
 405        unsigned char addr0;
 406        unsigned char addr1;
 407        unsigned char addr2;
 408        u16 newtable[32];       /* Max length below. */
 409};
 410
 411
 412/* 21142.c */
 413extern u16 t21142_csr14[];
 414void t21142_media_task(struct work_struct *work);
 415void t21142_start_nway(struct net_device *dev);
 416void t21142_lnk_change(struct net_device *dev, int csr5);
 417
 418
 419/* PNIC2.c */
 420void pnic2_lnk_change(struct net_device *dev, int csr5);
 421void pnic2_timer(unsigned long data);
 422void pnic2_start_nway(struct net_device *dev);
 423void pnic2_lnk_change(struct net_device *dev, int csr5);
 424
 425/* eeprom.c */
 426void tulip_parse_eeprom(struct net_device *dev);
 427int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
 428
 429/* interrupt.c */
 430extern unsigned int tulip_max_interrupt_work;
 431extern int tulip_rx_copybreak;
 432irqreturn_t tulip_interrupt(int irq, void *dev_instance);
 433int tulip_refill_rx(struct net_device *dev);
 434#ifdef CONFIG_TULIP_NAPI
 435int tulip_poll(struct napi_struct *napi, int budget);
 436#endif
 437
 438
 439/* media.c */
 440int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
 441void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
 442void tulip_select_media(struct net_device *dev, int startup);
 443int tulip_check_duplex(struct net_device *dev);
 444void tulip_find_mii (struct net_device *dev, int board_idx);
 445
 446/* pnic.c */
 447void pnic_do_nway(struct net_device *dev);
 448void pnic_lnk_change(struct net_device *dev, int csr5);
 449void pnic_timer(unsigned long data);
 450
 451/* timer.c */
 452void tulip_media_task(struct work_struct *work);
 453void mxic_timer(unsigned long data);
 454void comet_timer(unsigned long data);
 455
 456/* tulip_core.c */
 457extern int tulip_debug;
 458extern const char * const medianame[];
 459extern const char tulip_media_cap[];
 460extern struct tulip_chip_table tulip_tbl[];
 461void oom_timer(unsigned long data);
 462extern u8 t21040_csr13[];
 463
 464static inline void tulip_start_rxtx(struct tulip_private *tp)
 465{
 466        void __iomem *ioaddr = tp->base_addr;
 467        iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
 468        barrier();
 469        (void) ioread32(ioaddr + CSR6); /* mmio sync */
 470}
 471
 472static inline void tulip_stop_rxtx(struct tulip_private *tp)
 473{
 474        void __iomem *ioaddr = tp->base_addr;
 475        u32 csr6 = ioread32(ioaddr + CSR6);
 476
 477        if (csr6 & RxTx) {
 478                unsigned i=1300/10;
 479                iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
 480                barrier();
 481                /* wait until in-flight frame completes.
 482                 * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
 483                 * Typically expect this loop to end in < 50 us on 100BT.
 484                 */
 485                while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
 486                        udelay(10);
 487
 488                if (!i)
 489                        printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed"
 490                                        " (CSR5 0x%x CSR6 0x%x)\n",
 491                                        pci_name(tp->pdev),
 492                                        ioread32(ioaddr + CSR5),
 493                                        ioread32(ioaddr + CSR6));
 494        }
 495}
 496
 497static inline void tulip_restart_rxtx(struct tulip_private *tp)
 498{
 499        tulip_stop_rxtx(tp);
 500        udelay(5);
 501        tulip_start_rxtx(tp);
 502}
 503
 504static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr)
 505{
 506        /* Stop and restart the chip's Tx processes. */
 507        tulip_restart_rxtx(tp);
 508        /* Trigger an immediate transmit demand. */
 509        iowrite32(0, ioaddr + CSR1);
 510
 511        tp->stats.tx_errors++;
 512}
 513
 514#endif /* __NET_TULIP_H__ */
 515