linux/drivers/net/netxen/netxen_nic.h
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   1/*
   2 * Copyright (C) 2003 - 2006 NetXen, Inc.
   3 * All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License
   7 * as published by the Free Software Foundation; either version 2
   8 * of the License, or (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful, but
  11 * WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18 * MA  02111-1307, USA.
  19 *
  20 * The full GNU General Public License is included in this distribution
  21 * in the file called LICENSE.
  22 *
  23 * Contact Information:
  24 *    info@netxen.com
  25 * NetXen,
  26 * 3965 Freedom Circle, Fourth floor,
  27 * Santa Clara, CA 95054
  28 */
  29
  30#ifndef _NETXEN_NIC_H_
  31#define _NETXEN_NIC_H_
  32
  33#include <linux/module.h>
  34#include <linux/kernel.h>
  35#include <linux/types.h>
  36#include <linux/compiler.h>
  37#include <linux/slab.h>
  38#include <linux/delay.h>
  39#include <linux/init.h>
  40#include <linux/ioport.h>
  41#include <linux/pci.h>
  42#include <linux/netdevice.h>
  43#include <linux/etherdevice.h>
  44#include <linux/ip.h>
  45#include <linux/in.h>
  46#include <linux/tcp.h>
  47#include <linux/skbuff.h>
  48
  49#include <linux/ethtool.h>
  50#include <linux/mii.h>
  51#include <linux/interrupt.h>
  52#include <linux/timer.h>
  53
  54#include <linux/mm.h>
  55#include <linux/mman.h>
  56#include <linux/vmalloc.h>
  57
  58#include <asm/system.h>
  59#include <asm/io.h>
  60#include <asm/byteorder.h>
  61#include <asm/uaccess.h>
  62#include <asm/pgtable.h>
  63
  64#include "netxen_nic_hw.h"
  65
  66#define _NETXEN_NIC_LINUX_MAJOR 4
  67#define _NETXEN_NIC_LINUX_MINOR 0
  68#define _NETXEN_NIC_LINUX_SUBVERSION 11
  69#define NETXEN_NIC_LINUX_VERSIONID  "4.0.11"
  70
  71#define NETXEN_VERSION_CODE(a, b, c)    (((a) << 16) + ((b) << 8) + (c))
  72
  73#define NETXEN_NUM_FLASH_SECTORS (64)
  74#define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
  75#define NETXEN_FLASH_TOTAL_SIZE  (NETXEN_NUM_FLASH_SECTORS \
  76                                        * NETXEN_FLASH_SECTOR_SIZE)
  77
  78#define PHAN_VENDOR_ID 0x4040
  79
  80#define RCV_DESC_RINGSIZE       \
  81        (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
  82#define STATUS_DESC_RINGSIZE    \
  83        (sizeof(struct status_desc)* adapter->max_rx_desc_count)
  84#define LRO_DESC_RINGSIZE       \
  85        (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
  86#define TX_RINGSIZE     \
  87        (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
  88#define RCV_BUFFSIZE    \
  89        (sizeof(struct netxen_rx_buffer) * rds_ring->max_rx_desc_count)
  90#define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
  91
  92#define NETXEN_NETDEV_STATUS            0x1
  93#define NETXEN_RCV_PRODUCER_OFFSET      0
  94#define NETXEN_RCV_PEG_DB_ID            2
  95#define NETXEN_HOST_DUMMY_DMA_SIZE 1024
  96#define FLASH_SUCCESS 0
  97
  98#define ADDR_IN_WINDOW1(off)    \
  99        ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
 100
 101/*
 102 * normalize a 64MB crb address to 32MB PCI window
 103 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
 104 */
 105#define NETXEN_CRB_NORMAL(reg)  \
 106        ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
 107
 108#define NETXEN_CRB_NORMALIZE(adapter, reg) \
 109        pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
 110
 111#define DB_NORMALIZE(adapter, off) \
 112        (adapter->ahw.db_base + (off))
 113
 114#define NX_P2_C0                0x24
 115#define NX_P2_C1                0x25
 116#define NX_P3_A0                0x30
 117#define NX_P3_A2                0x30
 118#define NX_P3_B0                0x40
 119#define NX_P3_B1                0x41
 120
 121#define NX_IS_REVISION_P2(REVISION)     (REVISION <= NX_P2_C1)
 122#define NX_IS_REVISION_P3(REVISION)     (REVISION >= NX_P3_A0)
 123
 124#define FIRST_PAGE_GROUP_START  0
 125#define FIRST_PAGE_GROUP_END    0x100000
 126
 127#define SECOND_PAGE_GROUP_START 0x6000000
 128#define SECOND_PAGE_GROUP_END   0x68BC000
 129
 130#define THIRD_PAGE_GROUP_START  0x70E4000
 131#define THIRD_PAGE_GROUP_END    0x8000000
 132
 133#define FIRST_PAGE_GROUP_SIZE  FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
 134#define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
 135#define THIRD_PAGE_GROUP_SIZE  THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
 136
 137#define P2_MAX_MTU                     (8000)
 138#define P3_MAX_MTU                     (9600)
 139#define NX_ETHERMTU                    1500
 140#define NX_MAX_ETHERHDR                32 /* This contains some padding */
 141
 142#define NX_RX_NORMAL_BUF_MAX_LEN       (NX_MAX_ETHERHDR + NX_ETHERMTU)
 143#define NX_P2_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P2_MAX_MTU)
 144#define NX_P3_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P3_MAX_MTU)
 145#define NX_CT_DEFAULT_RX_BUF_LEN        2048
 146
 147#define MAX_RX_BUFFER_LENGTH            1760
 148#define MAX_RX_JUMBO_BUFFER_LENGTH      8062
 149#define MAX_RX_LRO_BUFFER_LENGTH        ((48*1024)-512)
 150#define RX_DMA_MAP_LEN                  (MAX_RX_BUFFER_LENGTH - 2)
 151#define RX_JUMBO_DMA_MAP_LEN    \
 152        (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
 153#define RX_LRO_DMA_MAP_LEN              (MAX_RX_LRO_BUFFER_LENGTH - 2)
 154
 155/*
 156 * Maximum number of ring contexts
 157 */
 158#define MAX_RING_CTX 1
 159
 160/* Opcodes to be used with the commands */
 161#define TX_ETHER_PKT    0x01
 162#define TX_TCP_PKT      0x02
 163#define TX_UDP_PKT      0x03
 164#define TX_IP_PKT       0x04
 165#define TX_TCP_LSO      0x05
 166#define TX_TCP_LSO6     0x06
 167#define TX_IPSEC        0x07
 168#define TX_IPSEC_CMD    0x0a
 169#define TX_TCPV6_PKT    0x0b
 170#define TX_UDPV6_PKT    0x0c
 171
 172/* The following opcodes are for internal consumption. */
 173#define NETXEN_CONTROL_OP       0x10
 174#define PEGNET_REQUEST          0x11
 175
 176#define MAX_NUM_CARDS           4
 177
 178#define MAX_BUFFERS_PER_CMD     32
 179
 180/*
 181 * Following are the states of the Phantom. Phantom will set them and
 182 * Host will read to check if the fields are correct.
 183 */
 184#define PHAN_INITIALIZE_START           0xff00
 185#define PHAN_INITIALIZE_FAILED          0xffff
 186#define PHAN_INITIALIZE_COMPLETE        0xff01
 187
 188/* Host writes the following to notify that it has done the init-handshake */
 189#define PHAN_INITIALIZE_ACK     0xf00f
 190
 191#define NUM_RCV_DESC_RINGS      3       /* No of Rcv Descriptor contexts */
 192
 193/* descriptor types */
 194#define RCV_DESC_NORMAL         0x01
 195#define RCV_DESC_JUMBO          0x02
 196#define RCV_DESC_LRO            0x04
 197#define RCV_DESC_NORMAL_CTXID   0
 198#define RCV_DESC_JUMBO_CTXID    1
 199#define RCV_DESC_LRO_CTXID      2
 200
 201#define RCV_DESC_TYPE(ID) \
 202        ((ID == RCV_DESC_JUMBO_CTXID)   \
 203                ? RCV_DESC_JUMBO        \
 204                : ((ID == RCV_DESC_LRO_CTXID)   \
 205                        ? RCV_DESC_LRO :        \
 206                        (RCV_DESC_NORMAL)))
 207
 208#define MAX_CMD_DESCRIPTORS             4096
 209#define MAX_RCV_DESCRIPTORS             16384
 210#define MAX_CMD_DESCRIPTORS_HOST        (MAX_CMD_DESCRIPTORS / 4)
 211#define MAX_RCV_DESCRIPTORS_1G          (MAX_RCV_DESCRIPTORS / 4)
 212#define MAX_RCV_DESCRIPTORS_10G         8192
 213#define MAX_JUMBO_RCV_DESCRIPTORS       1024
 214#define MAX_LRO_RCV_DESCRIPTORS         64
 215#define MAX_RCVSTATUS_DESCRIPTORS       MAX_RCV_DESCRIPTORS
 216#define MAX_JUMBO_RCV_DESC      MAX_JUMBO_RCV_DESCRIPTORS
 217#define MAX_RCV_DESC            MAX_RCV_DESCRIPTORS
 218#define MAX_RCVSTATUS_DESC      MAX_RCV_DESCRIPTORS
 219#define MAX_EPG_DESCRIPTORS     (MAX_CMD_DESCRIPTORS * 8)
 220#define NUM_RCV_DESC            (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
 221                                 MAX_LRO_RCV_DESCRIPTORS)
 222#define MIN_TX_COUNT    4096
 223#define MIN_RX_COUNT    4096
 224#define NETXEN_CTX_SIGNATURE    0xdee0
 225#define NETXEN_RCV_PRODUCER(ringid)     (ringid)
 226#define MAX_FRAME_SIZE  0x10000 /* 64K MAX size for LSO */
 227
 228#define PHAN_PEG_RCV_INITIALIZED        0xff01
 229#define PHAN_PEG_RCV_START_INITIALIZE   0xff00
 230
 231#define get_next_index(index, length)   \
 232        (((index) + 1) & ((length) - 1))
 233
 234#define get_index_range(index,length,count)     \
 235        (((index) + (count)) & ((length) - 1))
 236
 237#define MPORT_SINGLE_FUNCTION_MODE 0x1111
 238#define MPORT_MULTI_FUNCTION_MODE 0x2222
 239
 240#include "netxen_nic_phan_reg.h"
 241
 242/*
 243 * NetXen host-peg signal message structure
 244 *
 245 *      Bit 0-1         : peg_id => 0x2 for tx and 01 for rx
 246 *      Bit 2           : priv_id => must be 1
 247 *      Bit 3-17        : count => for doorbell
 248 *      Bit 18-27       : ctx_id => Context id
 249 *      Bit 28-31       : opcode
 250 */
 251
 252typedef u32 netxen_ctx_msg;
 253
 254#define netxen_set_msg_peg_id(config_word, val) \
 255        ((config_word) &= ~3, (config_word) |= val & 3)
 256#define netxen_set_msg_privid(config_word)      \
 257        ((config_word) |= 1 << 2)
 258#define netxen_set_msg_count(config_word, val)  \
 259        ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
 260#define netxen_set_msg_ctxid(config_word, val)  \
 261        ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
 262#define netxen_set_msg_opcode(config_word, val) \
 263        ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
 264
 265struct netxen_rcv_context {
 266        __le64 rcv_ring_addr;
 267        __le32 rcv_ring_size;
 268        __le32 rsrvd;
 269};
 270
 271struct netxen_ring_ctx {
 272
 273        /* one command ring */
 274        __le64 cmd_consumer_offset;
 275        __le64 cmd_ring_addr;
 276        __le32 cmd_ring_size;
 277        __le32 rsrvd;
 278
 279        /* three receive rings */
 280        struct netxen_rcv_context rcv_ctx[3];
 281
 282        /* one status ring */
 283        __le64 sts_ring_addr;
 284        __le32 sts_ring_size;
 285
 286        __le32 ctx_id;
 287} __attribute__ ((aligned(64)));
 288
 289/*
 290 * Following data structures describe the descriptors that will be used.
 291 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
 292 * we are doing LSO (above the 1500 size packet) only.
 293 */
 294
 295/*
 296 * The size of reference handle been changed to 16 bits to pass the MSS fields
 297 * for the LSO packet
 298 */
 299
 300#define FLAGS_CHECKSUM_ENABLED  0x01
 301#define FLAGS_LSO_ENABLED       0x02
 302#define FLAGS_IPSEC_SA_ADD      0x04
 303#define FLAGS_IPSEC_SA_DELETE   0x08
 304#define FLAGS_VLAN_TAGGED       0x10
 305
 306#define netxen_set_cmd_desc_port(cmd_desc, var) \
 307        ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
 308#define netxen_set_cmd_desc_ctxid(cmd_desc, var)        \
 309        ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
 310
 311#define netxen_set_cmd_desc_flags(cmd_desc, val)        \
 312        (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \
 313                ~cpu_to_le16(0x7f)) | cpu_to_le16((val) & 0x7f)
 314#define netxen_set_cmd_desc_opcode(cmd_desc, val)       \
 315        (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \
 316                ~cpu_to_le16((u16)0x3f << 7)) | cpu_to_le16(((val) & 0x3f) << 7)
 317
 318#define netxen_set_cmd_desc_num_of_buff(cmd_desc, val)  \
 319        (cmd_desc)->num_of_buffers_total_length = \
 320                ((cmd_desc)->num_of_buffers_total_length & \
 321                ~cpu_to_le32(0xff)) | cpu_to_le32((val) & 0xff)
 322#define netxen_set_cmd_desc_totallength(cmd_desc, val)  \
 323        (cmd_desc)->num_of_buffers_total_length = \
 324                ((cmd_desc)->num_of_buffers_total_length & \
 325                ~cpu_to_le32((u32)0xffffff << 8)) | \
 326                cpu_to_le32(((val) & 0xffffff) << 8)
 327
 328#define netxen_get_cmd_desc_opcode(cmd_desc)    \
 329        ((le16_to_cpu((cmd_desc)->flags_opcode) >> 7) & 0x003f)
 330#define netxen_get_cmd_desc_totallength(cmd_desc)       \
 331        ((le32_to_cpu((cmd_desc)->num_of_buffers_total_length) >> 8) & 0xffffff)
 332
 333struct cmd_desc_type0 {
 334        u8 tcp_hdr_offset;      /* For LSO only */
 335        u8 ip_hdr_offset;       /* For LSO only */
 336        /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
 337        __le16 flags_opcode;
 338        /* Bit pattern: 0-7 total number of segments,
 339           8-31 Total size of the packet */
 340        __le32 num_of_buffers_total_length;
 341        union {
 342                struct {
 343                        __le32 addr_low_part2;
 344                        __le32 addr_high_part2;
 345                };
 346                __le64 addr_buffer2;
 347        };
 348
 349        __le16 reference_handle;        /* changed to u16 to add mss */
 350        __le16 mss;             /* passed by NDIS_PACKET for LSO */
 351        /* Bit pattern 0-3 port, 0-3 ctx id */
 352        u8 port_ctxid;
 353        u8 total_hdr_length;    /* LSO only : MAC+IP+TCP Hdr size */
 354        __le16 conn_id;         /* IPSec offoad only */
 355
 356        union {
 357                struct {
 358                        __le32 addr_low_part3;
 359                        __le32 addr_high_part3;
 360                };
 361                __le64 addr_buffer3;
 362        };
 363        union {
 364                struct {
 365                        __le32 addr_low_part1;
 366                        __le32 addr_high_part1;
 367                };
 368                __le64 addr_buffer1;
 369        };
 370
 371        __le16 buffer1_length;
 372        __le16 buffer2_length;
 373        __le16 buffer3_length;
 374        __le16 buffer4_length;
 375
 376        union {
 377                struct {
 378                        __le32 addr_low_part4;
 379                        __le32 addr_high_part4;
 380                };
 381                __le64 addr_buffer4;
 382        };
 383
 384        __le64 unused;
 385
 386} __attribute__ ((aligned(64)));
 387
 388/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
 389struct rcv_desc {
 390        __le16 reference_handle;
 391        __le16 reserved;
 392        __le32 buffer_length;   /* allocated buffer length (usually 2K) */
 393        __le64 addr_buffer;
 394};
 395
 396/* opcode field in status_desc */
 397#define NETXEN_NIC_RXPKT_DESC  0x04
 398#define NETXEN_OLD_RXPKT_DESC  0x3f
 399
 400/* for status field in status_desc */
 401#define STATUS_NEED_CKSUM       (1)
 402#define STATUS_CKSUM_OK         (2)
 403
 404/* owner bits of status_desc */
 405#define STATUS_OWNER_HOST       (0x1)
 406#define STATUS_OWNER_PHANTOM    (0x2)
 407
 408#define NETXEN_PROT_IP          (1)
 409#define NETXEN_PROT_UNKNOWN     (0)
 410
 411/* Note: sizeof(status_desc) should always be a mutliple of 2 */
 412
 413#define netxen_get_sts_desc_lro_cnt(status_desc)        \
 414        ((status_desc)->lro & 0x7F)
 415#define netxen_get_sts_desc_lro_last_frag(status_desc)  \
 416        (((status_desc)->lro & 0x80) >> 7)
 417
 418#define netxen_get_sts_port(sts_data)   \
 419        ((sts_data) & 0x0F)
 420#define netxen_get_sts_status(sts_data) \
 421        (((sts_data) >> 4) & 0x0F)
 422#define netxen_get_sts_type(sts_data)   \
 423        (((sts_data) >> 8) & 0x0F)
 424#define netxen_get_sts_totallength(sts_data)    \
 425        (((sts_data) >> 12) & 0xFFFF)
 426#define netxen_get_sts_refhandle(sts_data)      \
 427        (((sts_data) >> 28) & 0xFFFF)
 428#define netxen_get_sts_prot(sts_data)   \
 429        (((sts_data) >> 44) & 0x0F)
 430#define netxen_get_sts_pkt_offset(sts_data)     \
 431        (((sts_data) >> 48) & 0x1F)
 432#define netxen_get_sts_opcode(sts_data) \
 433        (((sts_data) >> 58) & 0x03F)
 434
 435#define netxen_get_sts_owner(status_desc)       \
 436        ((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03)
 437#define netxen_set_sts_owner(status_desc, val)  { \
 438        (status_desc)->status_desc_data = \
 439                ((status_desc)->status_desc_data & \
 440                ~cpu_to_le64(0x3ULL << 56)) | \
 441                cpu_to_le64((u64)((val) & 0x3) << 56); \
 442}
 443
 444struct status_desc {
 445        /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
 446           28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
 447           53-55 desc_cnt, 56-57 owner, 58-63 opcode
 448         */
 449        __le64 status_desc_data;
 450        union {
 451                struct {
 452                        __le32 hash_value;
 453                        u8 hash_type;
 454                        u8 msg_type;
 455                        u8 unused;
 456                        union {
 457                                /* Bit pattern: 0-6 lro_count indicates frag
 458                                 * sequence, 7 last_frag indicates last frag
 459                                 */
 460                                u8 lro;
 461
 462                                /* chained buffers */
 463                                u8 nr_frags;
 464                        };
 465                };
 466                struct {
 467                        __le16 frag_handles[4];
 468                };
 469        };
 470} __attribute__ ((aligned(16)));
 471
 472enum {
 473        NETXEN_RCV_PEG_0 = 0,
 474        NETXEN_RCV_PEG_1
 475};
 476/* The version of the main data structure */
 477#define NETXEN_BDINFO_VERSION 1
 478
 479/* Magic number to let user know flash is programmed */
 480#define NETXEN_BDINFO_MAGIC 0x12345678
 481
 482/* Max number of Gig ports on a Phantom board */
 483#define NETXEN_MAX_PORTS 4
 484
 485typedef enum {
 486        NETXEN_BRDTYPE_P1_BD = 0x0000,
 487        NETXEN_BRDTYPE_P1_SB = 0x0001,
 488        NETXEN_BRDTYPE_P1_SMAX = 0x0002,
 489        NETXEN_BRDTYPE_P1_SOCK = 0x0003,
 490
 491        NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
 492        NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
 493        NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
 494        NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
 495        NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
 496
 497        NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
 498        NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
 499        NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f,
 500
 501        NETXEN_BRDTYPE_P3_REF_QG = 0x0021,
 502        NETXEN_BRDTYPE_P3_HMEZ = 0x0022,
 503        NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023,
 504        NETXEN_BRDTYPE_P3_4_GB = 0x0024,
 505        NETXEN_BRDTYPE_P3_IMEZ = 0x0025,
 506        NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026,
 507        NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027,
 508        NETXEN_BRDTYPE_P3_XG_LOM = 0x0028,
 509        NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029,
 510        NETXEN_BRDTYPE_P3_10G_SFP_CT = 0x002a,
 511        NETXEN_BRDTYPE_P3_10G_SFP_QT = 0x002b,
 512        NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031,
 513        NETXEN_BRDTYPE_P3_10G_XFP = 0x0032
 514
 515} netxen_brdtype_t;
 516
 517typedef enum {
 518        NETXEN_BRDMFG_INVENTEC = 1
 519} netxen_brdmfg;
 520
 521typedef enum {
 522        MEM_ORG_128Mbx4 = 0x0,  /* DDR1 only */
 523        MEM_ORG_128Mbx8 = 0x1,  /* DDR1 only */
 524        MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
 525        MEM_ORG_256Mbx4 = 0x3,
 526        MEM_ORG_256Mbx8 = 0x4,
 527        MEM_ORG_256Mbx16 = 0x5,
 528        MEM_ORG_512Mbx4 = 0x6,
 529        MEM_ORG_512Mbx8 = 0x7,
 530        MEM_ORG_512Mbx16 = 0x8,
 531        MEM_ORG_1Gbx4 = 0x9,
 532        MEM_ORG_1Gbx8 = 0xa,
 533        MEM_ORG_1Gbx16 = 0xb,
 534        MEM_ORG_2Gbx4 = 0xc,
 535        MEM_ORG_2Gbx8 = 0xd,
 536        MEM_ORG_2Gbx16 = 0xe,
 537        MEM_ORG_128Mbx32 = 0x10002,     /* GDDR only */
 538        MEM_ORG_256Mbx32 = 0x10005      /* GDDR only */
 539} netxen_mn_mem_org_t;
 540
 541typedef enum {
 542        MEM_ORG_512Kx36 = 0x0,
 543        MEM_ORG_1Mx36 = 0x1,
 544        MEM_ORG_2Mx36 = 0x2
 545} netxen_sn_mem_org_t;
 546
 547typedef enum {
 548        MEM_DEPTH_4MB = 0x1,
 549        MEM_DEPTH_8MB = 0x2,
 550        MEM_DEPTH_16MB = 0x3,
 551        MEM_DEPTH_32MB = 0x4,
 552        MEM_DEPTH_64MB = 0x5,
 553        MEM_DEPTH_128MB = 0x6,
 554        MEM_DEPTH_256MB = 0x7,
 555        MEM_DEPTH_512MB = 0x8,
 556        MEM_DEPTH_1GB = 0x9,
 557        MEM_DEPTH_2GB = 0xa,
 558        MEM_DEPTH_4GB = 0xb,
 559        MEM_DEPTH_8GB = 0xc,
 560        MEM_DEPTH_16GB = 0xd,
 561        MEM_DEPTH_32GB = 0xe
 562} netxen_mem_depth_t;
 563
 564struct netxen_board_info {
 565        u32 header_version;
 566
 567        u32 board_mfg;
 568        u32 board_type;
 569        u32 board_num;
 570        u32 chip_id;
 571        u32 chip_minor;
 572        u32 chip_major;
 573        u32 chip_pkg;
 574        u32 chip_lot;
 575
 576        u32 port_mask;          /* available niu ports */
 577        u32 peg_mask;           /* available pegs */
 578        u32 icache_ok;          /* can we run with icache? */
 579        u32 dcache_ok;          /* can we run with dcache? */
 580        u32 casper_ok;
 581
 582        u32 mac_addr_lo_0;
 583        u32 mac_addr_lo_1;
 584        u32 mac_addr_lo_2;
 585        u32 mac_addr_lo_3;
 586
 587        /* MN-related config */
 588        u32 mn_sync_mode;       /* enable/ sync shift cclk/ sync shift mclk */
 589        u32 mn_sync_shift_cclk;
 590        u32 mn_sync_shift_mclk;
 591        u32 mn_wb_en;
 592        u32 mn_crystal_freq;    /* in MHz */
 593        u32 mn_speed;           /* in MHz */
 594        u32 mn_org;
 595        u32 mn_depth;
 596        u32 mn_ranks_0;         /* ranks per slot */
 597        u32 mn_ranks_1;         /* ranks per slot */
 598        u32 mn_rd_latency_0;
 599        u32 mn_rd_latency_1;
 600        u32 mn_rd_latency_2;
 601        u32 mn_rd_latency_3;
 602        u32 mn_rd_latency_4;
 603        u32 mn_rd_latency_5;
 604        u32 mn_rd_latency_6;
 605        u32 mn_rd_latency_7;
 606        u32 mn_rd_latency_8;
 607        u32 mn_dll_val[18];
 608        u32 mn_mode_reg;        /* MIU DDR Mode Register */
 609        u32 mn_ext_mode_reg;    /* MIU DDR Extended Mode Register */
 610        u32 mn_timing_0;        /* MIU Memory Control Timing Rgister */
 611        u32 mn_timing_1;        /* MIU Extended Memory Ctrl Timing Register */
 612        u32 mn_timing_2;        /* MIU Extended Memory Ctrl Timing2 Register */
 613
 614        /* SN-related config */
 615        u32 sn_sync_mode;       /* enable/ sync shift cclk / sync shift mclk */
 616        u32 sn_pt_mode;         /* pass through mode */
 617        u32 sn_ecc_en;
 618        u32 sn_wb_en;
 619        u32 sn_crystal_freq;
 620        u32 sn_speed;
 621        u32 sn_org;
 622        u32 sn_depth;
 623        u32 sn_dll_tap;
 624        u32 sn_rd_latency;
 625
 626        u32 mac_addr_hi_0;
 627        u32 mac_addr_hi_1;
 628        u32 mac_addr_hi_2;
 629        u32 mac_addr_hi_3;
 630
 631        u32 magic;              /* indicates flash has been initialized */
 632
 633        u32 mn_rdimm;
 634        u32 mn_dll_override;
 635
 636};
 637
 638#define FLASH_NUM_PORTS         (4)
 639
 640struct netxen_flash_mac_addr {
 641        u32 flash_addr[32];
 642};
 643
 644struct netxen_user_old_info {
 645        u8 flash_md5[16];
 646        u8 crbinit_md5[16];
 647        u8 brdcfg_md5[16];
 648        /* bootloader */
 649        u32 bootld_version;
 650        u32 bootld_size;
 651        u8 bootld_md5[16];
 652        /* image */
 653        u32 image_version;
 654        u32 image_size;
 655        u8 image_md5[16];
 656        /* primary image status */
 657        u32 primary_status;
 658        u32 secondary_present;
 659
 660        /* MAC address , 4 ports */
 661        struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
 662};
 663#define FLASH_NUM_MAC_PER_PORT  32
 664struct netxen_user_info {
 665        u8 flash_md5[16 * 64];
 666        /* bootloader */
 667        u32 bootld_version;
 668        u32 bootld_size;
 669        /* image */
 670        u32 image_version;
 671        u32 image_size;
 672        /* primary image status */
 673        u32 primary_status;
 674        u32 secondary_present;
 675
 676        /* MAC address , 4 ports, 32 address per port */
 677        u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
 678        u32 sub_sys_id;
 679        u8 serial_num[32];
 680
 681        /* Any user defined data */
 682};
 683
 684/*
 685 * Flash Layout - new format.
 686 */
 687struct netxen_new_user_info {
 688        u8 flash_md5[16 * 64];
 689        /* bootloader */
 690        u32 bootld_version;
 691        u32 bootld_size;
 692        /* image */
 693        u32 image_version;
 694        u32 image_size;
 695        /* primary image status */
 696        u32 primary_status;
 697        u32 secondary_present;
 698
 699        /* MAC address , 4 ports, 32 address per port */
 700        u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
 701        u32 sub_sys_id;
 702        u8 serial_num[32];
 703
 704        /* Any user defined data */
 705};
 706
 707#define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
 708#define SECONDARY_IMAGE_ABSENT  0xffffffff
 709#define PRIMARY_IMAGE_GOOD      0x5a5a5a5a
 710#define PRIMARY_IMAGE_BAD       0xffffffff
 711
 712/* Flash memory map */
 713typedef enum {
 714        NETXEN_CRBINIT_START = 0,       /* Crbinit section */
 715        NETXEN_BRDCFG_START = 0x4000,   /* board config */
 716        NETXEN_INITCODE_START = 0x6000, /* pegtune code */
 717        NETXEN_BOOTLD_START = 0x10000,  /* bootld */
 718        NETXEN_IMAGE_START = 0x43000,   /* compressed image */
 719        NETXEN_SECONDARY_START = 0x200000,      /* backup images */
 720        NETXEN_PXE_START = 0x3E0000,    /* user defined region */
 721        NETXEN_USER_START = 0x3E8000,   /* User defined region for new boards */
 722        NETXEN_FIXED_START = 0x3F0000   /* backup of crbinit */
 723} netxen_flash_map_t;
 724
 725#define NETXEN_USER_START_OLD NETXEN_PXE_START  /* for backward compatibility */
 726
 727#define NETXEN_FLASH_START              (NETXEN_CRBINIT_START)
 728#define NETXEN_INIT_SECTOR              (0)
 729#define NETXEN_PRIMARY_START            (NETXEN_BOOTLD_START)
 730#define NETXEN_FLASH_CRBINIT_SIZE       (0x4000)
 731#define NETXEN_FLASH_BRDCFG_SIZE        (sizeof(struct netxen_board_info))
 732#define NETXEN_FLASH_USER_SIZE          (sizeof(struct netxen_user_info)/sizeof(u32))
 733#define NETXEN_FLASH_SECONDARY_SIZE     (NETXEN_USER_START-NETXEN_SECONDARY_START)
 734#define NETXEN_NUM_PRIMARY_SECTORS      (0x20)
 735#define NETXEN_NUM_CONFIG_SECTORS       (1)
 736#define PFX "NetXen: "
 737extern char netxen_nic_driver_name[];
 738
 739/* Note: Make sure to not call this before adapter->port is valid */
 740#if !defined(NETXEN_DEBUG)
 741#define DPRINTK(klevel, fmt, args...)   do { \
 742        } while (0)
 743#else
 744#define DPRINTK(klevel, fmt, args...)   do { \
 745        printk(KERN_##klevel PFX "%s: %s: " fmt, __func__,\
 746                (adapter != NULL && adapter->netdev != NULL) ? \
 747                adapter->netdev->name : NULL, \
 748                ## args); } while(0)
 749#endif
 750
 751/* Number of status descriptors to handle per interrupt */
 752#define MAX_STATUS_HANDLE       (128)
 753
 754/*
 755 * netxen_skb_frag{} is to contain mapping info for each SG list. This
 756 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
 757 */
 758struct netxen_skb_frag {
 759        u64 dma;
 760        u32 length;
 761};
 762
 763#define _netxen_set_bits(config_word, start, bits, val) {\
 764        unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
 765        unsigned long long __tvalue = (val);    \
 766        (config_word) &= ~__tmask;      \
 767        (config_word) |= (((__tvalue) << (start)) & __tmask); \
 768}
 769
 770#define _netxen_clear_bits(config_word, start, bits) {\
 771        unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));  \
 772        (config_word) &= ~__tmask; \
 773}
 774
 775/*    Following defines are for the state of the buffers    */
 776#define NETXEN_BUFFER_FREE      0
 777#define NETXEN_BUFFER_BUSY      1
 778
 779/*
 780 * There will be one netxen_buffer per skb packet.    These will be
 781 * used to save the dma info for pci_unmap_page()
 782 */
 783struct netxen_cmd_buffer {
 784        struct sk_buff *skb;
 785        struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
 786        u32 total_length;
 787        u32 mss;
 788        u16 port;
 789        u8 cmd;
 790        u8 frag_count;
 791        unsigned long time_stamp;
 792        u32 state;
 793};
 794
 795/* In rx_buffer, we do not need multiple fragments as is a single buffer */
 796struct netxen_rx_buffer {
 797        struct list_head list;
 798        struct sk_buff *skb;
 799        u64 dma;
 800        u16 ref_handle;
 801        u16 state;
 802        u32 lro_expected_frags;
 803        u32 lro_current_frags;
 804        u32 lro_length;
 805};
 806
 807/* Board types */
 808#define NETXEN_NIC_GBE  0x01
 809#define NETXEN_NIC_XGBE 0x02
 810
 811/*
 812 * One hardware_context{} per adapter
 813 * contains interrupt info as well shared hardware info.
 814 */
 815struct netxen_hardware_context {
 816        void __iomem *pci_base0;
 817        void __iomem *pci_base1;
 818        void __iomem *pci_base2;
 819        unsigned long first_page_group_end;
 820        unsigned long first_page_group_start;
 821        void __iomem *db_base;
 822        unsigned long db_len;
 823        unsigned long pci_len0;
 824
 825        u8 cut_through;
 826        int qdr_sn_window;
 827        int ddr_mn_window;
 828        unsigned long mn_win_crb;
 829        unsigned long ms_win_crb;
 830
 831        u8 revision_id;
 832        u16 board_type;
 833        struct netxen_board_info boardcfg;
 834        u32 linkup;
 835        /* Address of cmd ring in Phantom */
 836        struct cmd_desc_type0 *cmd_desc_head;
 837        dma_addr_t cmd_desc_phys_addr;
 838        struct netxen_adapter *adapter;
 839        int pci_func;
 840};
 841
 842#define RCV_RING_LRO    RCV_DESC_LRO
 843
 844#define MINIMUM_ETHERNET_FRAME_SIZE     64      /* With FCS */
 845#define ETHERNET_FCS_SIZE               4
 846
 847struct netxen_adapter_stats {
 848        u64  rcvdbadskb;
 849        u64  xmitcalled;
 850        u64  xmitedframes;
 851        u64  xmitfinished;
 852        u64  badskblen;
 853        u64  nocmddescriptor;
 854        u64  polled;
 855        u64  rxdropped;
 856        u64  txdropped;
 857        u64  csummed;
 858        u64  no_rcv;
 859        u64  rxbytes;
 860        u64  txbytes;
 861        u64  ints;
 862};
 863
 864/*
 865 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
 866 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
 867 */
 868struct nx_host_rds_ring {
 869        u32 flags;
 870        u32 producer;
 871        dma_addr_t phys_addr;
 872        u32 crb_rcv_producer;   /* reg offset */
 873        struct rcv_desc *desc_head;     /* address of rx ring in Phantom */
 874        u32 max_rx_desc_count;
 875        u32 dma_size;
 876        u32 skb_size;
 877        struct netxen_rx_buffer *rx_buf_arr;    /* rx buffers for receive   */
 878        struct list_head free_list;
 879        int begin_alloc;
 880};
 881
 882/*
 883 * Receive context. There is one such structure per instance of the
 884 * receive processing. Any state information that is relevant to
 885 * the receive, and is must be in this structure. The global data may be
 886 * present elsewhere.
 887 */
 888struct netxen_recv_context {
 889        u32 state;
 890        u16 context_id;
 891        u16 virt_port;
 892
 893        struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
 894        u32 status_rx_consumer;
 895        u32 crb_sts_consumer;   /* reg offset */
 896        dma_addr_t rcv_status_desc_phys_addr;
 897        struct status_desc *rcv_status_desc_head;
 898};
 899
 900/* New HW context creation */
 901
 902#define NX_OS_CRB_RETRY_COUNT   4000
 903#define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
 904        (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
 905
 906#define NX_CDRP_CLEAR           0x00000000
 907#define NX_CDRP_CMD_BIT         0x80000000
 908
 909/*
 910 * All responses must have the NX_CDRP_CMD_BIT cleared
 911 * in the crb NX_CDRP_CRB_OFFSET.
 912 */
 913#define NX_CDRP_FORM_RSP(rsp)   (rsp)
 914#define NX_CDRP_IS_RSP(rsp)     (((rsp) & NX_CDRP_CMD_BIT) == 0)
 915
 916#define NX_CDRP_RSP_OK          0x00000001
 917#define NX_CDRP_RSP_FAIL        0x00000002
 918#define NX_CDRP_RSP_TIMEOUT     0x00000003
 919
 920/*
 921 * All commands must have the NX_CDRP_CMD_BIT set in
 922 * the crb NX_CDRP_CRB_OFFSET.
 923 */
 924#define NX_CDRP_FORM_CMD(cmd)   (NX_CDRP_CMD_BIT | (cmd))
 925#define NX_CDRP_IS_CMD(cmd)     (((cmd) & NX_CDRP_CMD_BIT) != 0)
 926
 927#define NX_CDRP_CMD_SUBMIT_CAPABILITIES     0x00000001
 928#define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX    0x00000002
 929#define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX    0x00000003
 930#define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX  0x00000004
 931#define NX_CDRP_CMD_READ_MAX_RX_CTX         0x00000005
 932#define NX_CDRP_CMD_READ_MAX_TX_CTX         0x00000006
 933#define NX_CDRP_CMD_CREATE_RX_CTX           0x00000007
 934#define NX_CDRP_CMD_DESTROY_RX_CTX          0x00000008
 935#define NX_CDRP_CMD_CREATE_TX_CTX           0x00000009
 936#define NX_CDRP_CMD_DESTROY_TX_CTX          0x0000000a
 937#define NX_CDRP_CMD_SETUP_STATISTICS        0x0000000e
 938#define NX_CDRP_CMD_GET_STATISTICS          0x0000000f
 939#define NX_CDRP_CMD_DELETE_STATISTICS       0x00000010
 940#define NX_CDRP_CMD_SET_MTU                 0x00000012
 941#define NX_CDRP_CMD_MAX                     0x00000013
 942
 943#define NX_RCODE_SUCCESS                0
 944#define NX_RCODE_NO_HOST_MEM            1
 945#define NX_RCODE_NO_HOST_RESOURCE       2
 946#define NX_RCODE_NO_CARD_CRB            3
 947#define NX_RCODE_NO_CARD_MEM            4
 948#define NX_RCODE_NO_CARD_RESOURCE       5
 949#define NX_RCODE_INVALID_ARGS           6
 950#define NX_RCODE_INVALID_ACTION         7
 951#define NX_RCODE_INVALID_STATE          8
 952#define NX_RCODE_NOT_SUPPORTED          9
 953#define NX_RCODE_NOT_PERMITTED          10
 954#define NX_RCODE_NOT_READY              11
 955#define NX_RCODE_DOES_NOT_EXIST         12
 956#define NX_RCODE_ALREADY_EXISTS         13
 957#define NX_RCODE_BAD_SIGNATURE          14
 958#define NX_RCODE_CMD_NOT_IMPL           15
 959#define NX_RCODE_CMD_INVALID            16
 960#define NX_RCODE_TIMEOUT                17
 961#define NX_RCODE_CMD_FAILED             18
 962#define NX_RCODE_MAX_EXCEEDED           19
 963#define NX_RCODE_MAX                    20
 964
 965#define NX_DESTROY_CTX_RESET            0
 966#define NX_DESTROY_CTX_D3_RESET         1
 967#define NX_DESTROY_CTX_MAX              2
 968
 969/*
 970 * Capabilities
 971 */
 972#define NX_CAP_BIT(class, bit)          (1 << bit)
 973#define NX_CAP0_LEGACY_CONTEXT          NX_CAP_BIT(0, 0)
 974#define NX_CAP0_MULTI_CONTEXT           NX_CAP_BIT(0, 1)
 975#define NX_CAP0_LEGACY_MN               NX_CAP_BIT(0, 2)
 976#define NX_CAP0_LEGACY_MS               NX_CAP_BIT(0, 3)
 977#define NX_CAP0_CUT_THROUGH             NX_CAP_BIT(0, 4)
 978#define NX_CAP0_LRO                     NX_CAP_BIT(0, 5)
 979#define NX_CAP0_LSO                     NX_CAP_BIT(0, 6)
 980#define NX_CAP0_JUMBO_CONTIGUOUS        NX_CAP_BIT(0, 7)
 981#define NX_CAP0_LRO_CONTIGUOUS          NX_CAP_BIT(0, 8)
 982
 983/*
 984 * Context state
 985 */
 986#define NX_HOST_CTX_STATE_FREED         0
 987#define NX_HOST_CTX_STATE_ALLOCATED     1
 988#define NX_HOST_CTX_STATE_ACTIVE        2
 989#define NX_HOST_CTX_STATE_DISABLED      3
 990#define NX_HOST_CTX_STATE_QUIESCED      4
 991#define NX_HOST_CTX_STATE_MAX           5
 992
 993/*
 994 * Rx context
 995 */
 996
 997typedef struct {
 998        u64 host_phys_addr;     /* Ring base addr */
 999        u32 ring_size;          /* Ring entries */
1000        u16 msi_index;
1001        u16 rsvd;               /* Padding */
1002} nx_hostrq_sds_ring_t;
1003
1004typedef struct {
1005        u64 host_phys_addr;     /* Ring base addr */
1006        u64 buff_size;          /* Packet buffer size */
1007        u32 ring_size;          /* Ring entries */
1008        u32 ring_kind;          /* Class of ring */
1009} nx_hostrq_rds_ring_t;
1010
1011typedef struct {
1012        u64 host_rsp_dma_addr;  /* Response dma'd here */
1013        u32 capabilities[4];    /* Flag bit vector */
1014        u32 host_int_crb_mode;  /* Interrupt crb usage */
1015        u32 host_rds_crb_mode;  /* RDS crb usage */
1016        /* These ring offsets are relative to data[0] below */
1017        u32 rds_ring_offset;    /* Offset to RDS config */
1018        u32 sds_ring_offset;    /* Offset to SDS config */
1019        u16 num_rds_rings;      /* Count of RDS rings */
1020        u16 num_sds_rings;      /* Count of SDS rings */
1021        u16 rsvd1;              /* Padding */
1022        u16 rsvd2;              /* Padding */
1023        u8  reserved[128];      /* reserve space for future expansion*/
1024        /* MUST BE 64-bit aligned.
1025           The following is packed:
1026           - N hostrq_rds_rings
1027           - N hostrq_sds_rings */
1028        char data[0];
1029} nx_hostrq_rx_ctx_t;
1030
1031typedef struct {
1032        u32 host_producer_crb;  /* Crb to use */
1033        u32 rsvd1;              /* Padding */
1034} nx_cardrsp_rds_ring_t;
1035
1036typedef struct {
1037        u32 host_consumer_crb;  /* Crb to use */
1038        u32 interrupt_crb;      /* Crb to use */
1039} nx_cardrsp_sds_ring_t;
1040
1041typedef struct {
1042        /* These ring offsets are relative to data[0] below */
1043        u32 rds_ring_offset;    /* Offset to RDS config */
1044        u32 sds_ring_offset;    /* Offset to SDS config */
1045        u32 host_ctx_state;     /* Starting State */
1046        u32 num_fn_per_port;    /* How many PCI fn share the port */
1047        u16 num_rds_rings;      /* Count of RDS rings */
1048        u16 num_sds_rings;      /* Count of SDS rings */
1049        u16 context_id;         /* Handle for context */
1050        u8  phys_port;          /* Physical id of port */
1051        u8  virt_port;          /* Virtual/Logical id of port */
1052        u8  reserved[128];      /* save space for future expansion */
1053        /*  MUST BE 64-bit aligned.
1054           The following is packed:
1055           - N cardrsp_rds_rings
1056           - N cardrs_sds_rings */
1057        char data[0];
1058} nx_cardrsp_rx_ctx_t;
1059
1060#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings)       \
1061        (sizeof(HOSTRQ_RX) +                                    \
1062        (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) +            \
1063        (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
1064
1065#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings)     \
1066        (sizeof(CARDRSP_RX) +                                   \
1067        (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) +           \
1068        (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
1069
1070/*
1071 * Tx context
1072 */
1073
1074typedef struct {
1075        u64 host_phys_addr;     /* Ring base addr */
1076        u32 ring_size;          /* Ring entries */
1077        u32 rsvd;               /* Padding */
1078} nx_hostrq_cds_ring_t;
1079
1080typedef struct {
1081        u64 host_rsp_dma_addr;  /* Response dma'd here */
1082        u64 cmd_cons_dma_addr;  /*  */
1083        u64 dummy_dma_addr;     /*  */
1084        u32 capabilities[4];    /* Flag bit vector */
1085        u32 host_int_crb_mode;  /* Interrupt crb usage */
1086        u32 rsvd1;              /* Padding */
1087        u16 rsvd2;              /* Padding */
1088        u16 interrupt_ctl;
1089        u16 msi_index;
1090        u16 rsvd3;              /* Padding */
1091        nx_hostrq_cds_ring_t cds_ring;  /* Desc of cds ring */
1092        u8  reserved[128];      /* future expansion */
1093} nx_hostrq_tx_ctx_t;
1094
1095typedef struct {
1096        u32 host_producer_crb;  /* Crb to use */
1097        u32 interrupt_crb;      /* Crb to use */
1098} nx_cardrsp_cds_ring_t;
1099
1100typedef struct {
1101        u32 host_ctx_state;     /* Starting state */
1102        u16 context_id;         /* Handle for context */
1103        u8  phys_port;          /* Physical id of port */
1104        u8  virt_port;          /* Virtual/Logical id of port */
1105        nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
1106        u8  reserved[128];      /* future expansion */
1107} nx_cardrsp_tx_ctx_t;
1108
1109#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX)     (sizeof(HOSTRQ_TX))
1110#define SIZEOF_CARDRSP_TX(CARDRSP_TX)   (sizeof(CARDRSP_TX))
1111
1112/* CRB */
1113
1114#define NX_HOST_RDS_CRB_MODE_UNIQUE     0
1115#define NX_HOST_RDS_CRB_MODE_SHARED     1
1116#define NX_HOST_RDS_CRB_MODE_CUSTOM     2
1117#define NX_HOST_RDS_CRB_MODE_MAX        3
1118
1119#define NX_HOST_INT_CRB_MODE_UNIQUE     0
1120#define NX_HOST_INT_CRB_MODE_SHARED     1
1121#define NX_HOST_INT_CRB_MODE_NORX       2
1122#define NX_HOST_INT_CRB_MODE_NOTX       3
1123#define NX_HOST_INT_CRB_MODE_NORXTX     4
1124
1125
1126/* MAC */
1127
1128#define MC_COUNT_P2     16
1129#define MC_COUNT_P3     38
1130
1131#define NETXEN_MAC_NOOP 0
1132#define NETXEN_MAC_ADD  1
1133#define NETXEN_MAC_DEL  2
1134
1135typedef struct nx_mac_list_s {
1136        struct nx_mac_list_s *next;
1137        uint8_t mac_addr[MAX_ADDR_LEN];
1138} nx_mac_list_t;
1139
1140/*
1141 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1142 * adjusted based on configured MTU.
1143 */
1144#define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1145#define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1146#define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1147#define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1148
1149#define NETXEN_NIC_INTR_DEFAULT                 0x04
1150
1151typedef union {
1152        struct {
1153                uint16_t        rx_packets;
1154                uint16_t        rx_time_us;
1155                uint16_t        tx_packets;
1156                uint16_t        tx_time_us;
1157        } data;
1158        uint64_t                word;
1159} nx_nic_intr_coalesce_data_t;
1160
1161typedef struct {
1162        uint16_t                        stats_time_us;
1163        uint16_t                        rate_sample_time;
1164        uint16_t                        flags;
1165        uint16_t                        rsvd_1;
1166        uint32_t                        low_threshold;
1167        uint32_t                        high_threshold;
1168        nx_nic_intr_coalesce_data_t     normal;
1169        nx_nic_intr_coalesce_data_t     low;
1170        nx_nic_intr_coalesce_data_t     high;
1171        nx_nic_intr_coalesce_data_t     irq;
1172} nx_nic_intr_coalesce_t;
1173
1174#define NX_HOST_REQUEST         0x13
1175#define NX_NIC_REQUEST          0x14
1176
1177#define NX_MAC_EVENT            0x1
1178
1179enum {
1180        NX_NIC_H2C_OPCODE_START = 0,
1181        NX_NIC_H2C_OPCODE_CONFIG_RSS,
1182        NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL,
1183        NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE,
1184        NX_NIC_H2C_OPCODE_CONFIG_LED,
1185        NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS,
1186        NX_NIC_H2C_OPCODE_CONFIG_L2_MAC,
1187        NX_NIC_H2C_OPCODE_LRO_REQUEST,
1188        NX_NIC_H2C_OPCODE_GET_SNMP_STATS,
1189        NX_NIC_H2C_OPCODE_PROXY_START_REQUEST,
1190        NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST,
1191        NX_NIC_H2C_OPCODE_PROXY_SET_MTU,
1192        NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE,
1193        NX_H2P_OPCODE_GET_FINGER_PRINT_REQUEST,
1194        NX_H2P_OPCODE_INSTALL_LICENSE_REQUEST,
1195        NX_H2P_OPCODE_GET_LICENSE_CAPABILITY_REQUEST,
1196        NX_NIC_H2C_OPCODE_GET_NET_STATS,
1197        NX_NIC_H2C_OPCODE_LAST
1198};
1199
1200#define VPORT_MISS_MODE_DROP            0 /* drop all unmatched */
1201#define VPORT_MISS_MODE_ACCEPT_ALL      1 /* accept all packets */
1202#define VPORT_MISS_MODE_ACCEPT_MULTI    2 /* accept unmatched multicast */
1203
1204typedef struct {
1205        u64 qhdr;
1206        u64 req_hdr;
1207        u64 words[6];
1208} nx_nic_req_t;
1209
1210typedef struct {
1211        u8 op;
1212        u8 tag;
1213        u8 mac_addr[6];
1214} nx_mac_req_t;
1215
1216#define MAX_PENDING_DESC_BLOCK_SIZE     64
1217
1218#define NETXEN_NIC_MSI_ENABLED          0x02
1219#define NETXEN_NIC_MSIX_ENABLED         0x04
1220#define NETXEN_IS_MSI_FAMILY(adapter) \
1221        ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1222
1223#define MSIX_ENTRIES_PER_ADAPTER        8
1224#define NETXEN_MSIX_TBL_SPACE           8192
1225#define NETXEN_PCI_REG_MSIX_TBL         0x44
1226
1227#define NETXEN_DB_MAPSIZE_BYTES         0x1000
1228
1229#define NETXEN_NETDEV_WEIGHT 120
1230#define NETXEN_ADAPTER_UP_MAGIC 777
1231#define NETXEN_NIC_PEG_TUNE 0
1232
1233struct netxen_dummy_dma {
1234        void *addr;
1235        dma_addr_t phys_addr;
1236};
1237
1238struct netxen_adapter {
1239        struct netxen_hardware_context ahw;
1240
1241        struct net_device *netdev;
1242        struct pci_dev *pdev;
1243        int pci_using_dac;
1244        struct napi_struct napi;
1245        struct net_device_stats net_stats;
1246        int mtu;
1247        int portnum;
1248        u8 physical_port;
1249        u16 tx_context_id;
1250
1251        uint8_t         mc_enabled;
1252        uint8_t         max_mc_count;
1253        nx_mac_list_t   *mac_list;
1254
1255        struct netxen_legacy_intr_set legacy_intr;
1256        u32     crb_intr_mask;
1257
1258        struct work_struct watchdog_task;
1259        struct timer_list watchdog_timer;
1260        struct work_struct  tx_timeout_task;
1261
1262        u32 curr_window;
1263        u32 crb_win;
1264        rwlock_t adapter_lock;
1265
1266        uint64_t dma_mask;
1267
1268        u32 cmd_producer;
1269        __le32 *cmd_consumer;
1270        u32 last_cmd_consumer;
1271        u32 crb_addr_cmd_producer;
1272        u32 crb_addr_cmd_consumer;
1273
1274        u32 max_tx_desc_count;
1275        u32 max_rx_desc_count;
1276        u32 max_jumbo_rx_desc_count;
1277        u32 max_lro_rx_desc_count;
1278
1279        int max_rds_rings;
1280
1281        u32 flags;
1282        u32 irq;
1283        int driver_mismatch;
1284        u32 temp;
1285
1286        u32 fw_major;
1287
1288        u8 msix_supported;
1289        u8 max_possible_rss_rings;
1290        struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1291
1292        struct netxen_adapter_stats stats;
1293
1294        u16 link_speed;
1295        u16 link_duplex;
1296        u16 state;
1297        u16 link_autoneg;
1298        int rx_csum;
1299        int status;
1300
1301        struct netxen_cmd_buffer *cmd_buf_arr;  /* Command buffers for xmit */
1302
1303        /*
1304         * Receive instances. These can be either one per port,
1305         * or one per peg, etc.
1306         */
1307        struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
1308
1309        int is_up;
1310        struct netxen_dummy_dma dummy_dma;
1311        nx_nic_intr_coalesce_t coal;
1312
1313        /* Context interface shared between card and host */
1314        struct netxen_ring_ctx *ctx_desc;
1315        dma_addr_t ctx_desc_phys_addr;
1316        int intr_scheme;
1317        int msi_mode;
1318        int (*enable_phy_interrupts) (struct netxen_adapter *);
1319        int (*disable_phy_interrupts) (struct netxen_adapter *);
1320        int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
1321        int (*set_mtu) (struct netxen_adapter *, int);
1322        int (*set_promisc) (struct netxen_adapter *, u32);
1323        int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1324        int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1325        int (*init_port) (struct netxen_adapter *, int);
1326        int (*stop_port) (struct netxen_adapter *);
1327
1328        int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int);
1329        int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int);
1330        int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1331        int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1332        int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1333        u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1334        void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
1335        u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
1336        unsigned long (*pci_set_window)(struct netxen_adapter *,
1337                        unsigned long long);
1338};                              /* netxen_adapter structure */
1339
1340/*
1341 * NetXen dma watchdog control structure
1342 *
1343 *      Bit 0           : enabled => R/O: 1 watchdog active, 0 inactive
1344 *      Bit 1           : disable_request => 1 req disable dma watchdog
1345 *      Bit 2           : enable_request =>  1 req enable dma watchdog
1346 *      Bit 3-31        : unused
1347 */
1348
1349#define netxen_set_dma_watchdog_disable_req(config_word) \
1350        _netxen_set_bits(config_word, 1, 1, 1)
1351#define netxen_set_dma_watchdog_enable_req(config_word) \
1352        _netxen_set_bits(config_word, 2, 1, 1)
1353#define netxen_get_dma_watchdog_enabled(config_word) \
1354        ((config_word) & 0x1)
1355#define netxen_get_dma_watchdog_disabled(config_word) \
1356        (((config_word) >> 1) & 0x1)
1357
1358/* Max number of xmit producer threads that can run simultaneously */
1359#define MAX_XMIT_PRODUCERS              16
1360
1361#define PCI_OFFSET_FIRST_RANGE(adapter, off)    \
1362        ((adapter)->ahw.pci_base0 + (off))
1363#define PCI_OFFSET_SECOND_RANGE(adapter, off)   \
1364        ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
1365#define PCI_OFFSET_THIRD_RANGE(adapter, off)    \
1366        ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
1367
1368static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
1369                                            unsigned long off)
1370{
1371        if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1372                return (adapter->ahw.pci_base0 + off);
1373        } else if ((off < SECOND_PAGE_GROUP_END) &&
1374                   (off >= SECOND_PAGE_GROUP_START)) {
1375                return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
1376        } else if ((off < THIRD_PAGE_GROUP_END) &&
1377                   (off >= THIRD_PAGE_GROUP_START)) {
1378                return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
1379        }
1380        return NULL;
1381}
1382
1383static inline void __iomem *pci_base(struct netxen_adapter *adapter,
1384                                     unsigned long off)
1385{
1386        if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1387                return adapter->ahw.pci_base0;
1388        } else if ((off < SECOND_PAGE_GROUP_END) &&
1389                   (off >= SECOND_PAGE_GROUP_START)) {
1390                return adapter->ahw.pci_base1;
1391        } else if ((off < THIRD_PAGE_GROUP_END) &&
1392                   (off >= THIRD_PAGE_GROUP_START)) {
1393                return adapter->ahw.pci_base2;
1394        }
1395        return NULL;
1396}
1397
1398int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1399int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1400int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1401int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1402int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1403                            __u32 * readval);
1404int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1405                             long reg, __u32 val);
1406
1407/* Functions available from netxen_nic_hw.c */
1408int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1409int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1410void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
1411int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
1412void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
1413void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value);
1414void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value);
1415void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
1416
1417int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1418
1419int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1420                ulong off, void *data, int len);
1421int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1422                ulong off, void *data, int len);
1423int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1424                u64 off, void *data, int size);
1425int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1426                u64 off, void *data, int size);
1427int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1428                u64 off, u32 data);
1429u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1430void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1431                u64 off, u32 data);
1432u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1433unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1434                unsigned long long addr);
1435void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1436                u32 wndw);
1437
1438int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1439                ulong off, void *data, int len);
1440int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1441                ulong off, void *data, int len);
1442int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1443                u64 off, void *data, int size);
1444int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1445                u64 off, void *data, int size);
1446void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1447                                 unsigned long off, int data);
1448int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1449                u64 off, u32 data);
1450u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1451void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1452                u64 off, u32 data);
1453u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1454unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1455                unsigned long long addr);
1456
1457/* Functions from netxen_nic_init.c */
1458void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1459int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1460int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1461int netxen_receive_peg_ready(struct netxen_adapter *adapter);
1462int netxen_load_firmware(struct netxen_adapter *adapter);
1463int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1464
1465int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1466int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1467                                u8 *bytes, size_t size);
1468int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1469                                u8 *bytes, size_t size);
1470int netxen_flash_unlock(struct netxen_adapter *adapter);
1471int netxen_backup_crbinit(struct netxen_adapter *adapter);
1472int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1473int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1474void netxen_halt_pegs(struct netxen_adapter *adapter);
1475
1476int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1477
1478int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1479void netxen_free_sw_resources(struct netxen_adapter *adapter);
1480
1481int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1482void netxen_free_hw_resources(struct netxen_adapter *adapter);
1483
1484void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1485void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1486
1487void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1488int netxen_init_firmware(struct netxen_adapter *adapter);
1489void netxen_tso_check(struct netxen_adapter *adapter,
1490                      struct cmd_desc_type0 *desc, struct sk_buff *skb);
1491void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1492void netxen_watchdog_task(struct work_struct *work);
1493void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
1494                            u32 ringid);
1495int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1496u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
1497void netxen_p2_nic_set_multi(struct net_device *netdev);
1498void netxen_p3_nic_set_multi(struct net_device *netdev);
1499int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1500int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1501
1502int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1503int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1504
1505int netxen_nic_set_mac(struct net_device *netdev, void *p);
1506struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1507
1508void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1509                uint32_t crb_producer);
1510
1511/*
1512 * NetXen Board information
1513 */
1514
1515#define NETXEN_MAX_SHORT_NAME 32
1516struct netxen_brdinfo {
1517        netxen_brdtype_t brdtype;       /* type of board */
1518        long ports;             /* max no of physical ports */
1519        char short_name[NETXEN_MAX_SHORT_NAME];
1520};
1521
1522static const struct netxen_brdinfo netxen_boards[] = {
1523        {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1524        {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1525        {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1526        {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1527        {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1528        {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1529        {NETXEN_BRDTYPE_P3_REF_QG,  4, "Reference Quad Gig "},
1530        {NETXEN_BRDTYPE_P3_HMEZ,    2, "Dual XGb HMEZ"},
1531        {NETXEN_BRDTYPE_P3_10G_CX4_LP,   2, "Dual XGb CX4 LP"},
1532        {NETXEN_BRDTYPE_P3_4_GB,    4, "Quad Gig LP"},
1533        {NETXEN_BRDTYPE_P3_IMEZ,    2, "Dual XGb IMEZ"},
1534        {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1535        {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1536        {NETXEN_BRDTYPE_P3_XG_LOM,  2, "Dual XGb LOM"},
1537        {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1538        {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1539        {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1540        {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1541        {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1542};
1543
1544#define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1545
1546static inline void get_brd_name_by_type(u32 type, char *name)
1547{
1548        int i, found = 0;
1549        for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1550                if (netxen_boards[i].brdtype == type) {
1551                        strcpy(name, netxen_boards[i].short_name);
1552                        found = 1;
1553                        break;
1554                }
1555
1556        }
1557        if (!found)
1558                name = "Unknown";
1559}
1560
1561static inline int
1562dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1563{
1564        u32 ctrl;
1565
1566        /* check if already inactive */
1567        if (adapter->hw_read_wx(adapter,
1568            NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1569                printk(KERN_ERR "failed to read dma watchdog status\n");
1570
1571        if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1572                return 1;
1573
1574        /* Send the disable request */
1575        netxen_set_dma_watchdog_disable_req(ctrl);
1576        netxen_crb_writelit_adapter(adapter,
1577                NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1578
1579        return 0;
1580}
1581
1582static inline int
1583dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1584{
1585        u32 ctrl;
1586
1587        if (adapter->hw_read_wx(adapter,
1588            NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1589                printk(KERN_ERR "failed to read dma watchdog status\n");
1590
1591        return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1592}
1593
1594static inline int
1595dma_watchdog_wakeup(struct netxen_adapter *adapter)
1596{
1597        u32 ctrl;
1598
1599        if (adapter->hw_read_wx(adapter,
1600                NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1601                printk(KERN_ERR "failed to read dma watchdog status\n");
1602
1603        if (netxen_get_dma_watchdog_enabled(ctrl))
1604                return 1;
1605
1606        /* send the wakeup request */
1607        netxen_set_dma_watchdog_enable_req(ctrl);
1608
1609        netxen_crb_writelit_adapter(adapter,
1610                NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1611
1612        return 0;
1613}
1614
1615
1616int netxen_is_flash_supported(struct netxen_adapter *adapter);
1617int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1618int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1619extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1620extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1621                                int *valp);
1622
1623extern struct ethtool_ops netxen_nic_ethtool_ops;
1624
1625#endif                          /* __NETXEN_NIC_H_ */
1626
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