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11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/init.h>
14#include <linux/agp_backend.h>
15#include <linux/mmzone.h>
16#include <asm/page.h>
17#include <asm/e820.h>
18#include <asm/k8.h>
19#include <asm/gart.h>
20#include "agp.h"
21
22
23#define NVIDIA_X86_64_0_APBASE 0x10
24#define NVIDIA_X86_64_1_APBASE1 0x50
25#define NVIDIA_X86_64_1_APLIMIT1 0x54
26#define NVIDIA_X86_64_1_APSIZE 0xa8
27#define NVIDIA_X86_64_1_APBASE2 0xd8
28#define NVIDIA_X86_64_1_APLIMIT2 0xdc
29
30
31#define ULI_X86_64_BASE_ADDR 0x10
32#define ULI_X86_64_HTT_FEA_REG 0x50
33#define ULI_X86_64_ENU_SCR_REG 0x54
34
35static struct resource *aperture_resource;
36static int __initdata agp_try_unsupported = 1;
37static int agp_bridges_found;
38
39static void amd64_tlbflush(struct agp_memory *temp)
40{
41 k8_flush_garts();
42}
43
44static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
45{
46 int i, j, num_entries;
47 long long tmp;
48 int mask_type;
49 struct agp_bridge_data *bridge = mem->bridge;
50 u32 pte;
51
52 num_entries = agp_num_entries();
53
54 if (type != mem->type)
55 return -EINVAL;
56 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
57 if (mask_type != 0)
58 return -EINVAL;
59
60
61
62
63 if (((unsigned long)pg_start + mem->page_count) > num_entries)
64 return -EINVAL;
65
66 j = pg_start;
67
68
69 while (j < (pg_start + mem->page_count)) {
70 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
71 return -EBUSY;
72 j++;
73 }
74
75 if (!mem->is_flushed) {
76 global_cache_flush();
77 mem->is_flushed = true;
78 }
79
80 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
81 tmp = agp_bridge->driver->mask_memory(agp_bridge,
82 mem->memory[i], mask_type);
83
84 BUG_ON(tmp & 0xffffff0000000ffcULL);
85 pte = (tmp & 0x000000ff00000000ULL) >> 28;
86 pte |=(tmp & 0x00000000fffff000ULL);
87 pte |= GPTE_VALID | GPTE_COHERENT;
88
89 writel(pte, agp_bridge->gatt_table+j);
90 readl(agp_bridge->gatt_table+j);
91 }
92 amd64_tlbflush(mem);
93 return 0;
94}
95
96
97
98
99
100
101static struct aper_size_info_32 amd64_aperture_sizes[7] =
102{
103 {32, 8192, 3+(sizeof(long)/8), 0 },
104 {64, 16384, 4+(sizeof(long)/8), 1<<1 },
105 {128, 32768, 5+(sizeof(long)/8), 1<<2 },
106 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
107 {512, 131072, 7+(sizeof(long)/8), 1<<3 },
108 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
109 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
110};
111
112
113
114
115
116
117
118
119static int amd64_fetch_size(void)
120{
121 struct pci_dev *dev;
122 int i;
123 u32 temp;
124 struct aper_size_info_32 *values;
125
126 dev = k8_northbridges[0];
127 if (dev==NULL)
128 return 0;
129
130 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
131 temp = (temp & 0xe);
132 values = A_SIZE_32(amd64_aperture_sizes);
133
134 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
135 if (temp == values[i].size_value) {
136 agp_bridge->previous_size =
137 agp_bridge->current_size = (void *) (values + i);
138
139 agp_bridge->aperture_size_idx = i;
140 return values[i].size;
141 }
142 }
143 return 0;
144}
145
146
147
148
149
150static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
151{
152 u64 aperturebase;
153 u32 tmp;
154 u64 aper_base;
155
156
157 pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
158 aperturebase = tmp << 25;
159 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
160
161 enable_gart_translation(hammer, gatt_table);
162
163 return aper_base;
164}
165
166
167static const struct aper_size_info_32 amd_8151_sizes[7] =
168{
169 {2048, 524288, 9, 0x00000000 },
170 {1024, 262144, 8, 0x00000400 },
171 {512, 131072, 7, 0x00000600 },
172 {256, 65536, 6, 0x00000700 },
173 {128, 32768, 5, 0x00000720 },
174 {64, 16384, 4, 0x00000730 },
175 {32, 8192, 3, 0x00000738 }
176};
177
178static int amd_8151_configure(void)
179{
180 unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real);
181 int i;
182
183
184 for (i = 0; i < num_k8_northbridges; i++) {
185 agp_bridge->gart_bus_addr =
186 amd64_configure(k8_northbridges[i], gatt_bus);
187 }
188 k8_flush_garts();
189 return 0;
190}
191
192
193static void amd64_cleanup(void)
194{
195 u32 tmp;
196 int i;
197 for (i = 0; i < num_k8_northbridges; i++) {
198 struct pci_dev *dev = k8_northbridges[i];
199
200 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
201 tmp &= ~AMD64_GARTEN;
202 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
203 }
204}
205
206
207static const struct agp_bridge_driver amd_8151_driver = {
208 .owner = THIS_MODULE,
209 .aperture_sizes = amd_8151_sizes,
210 .size_type = U32_APER_SIZE,
211 .num_aperture_sizes = 7,
212 .configure = amd_8151_configure,
213 .fetch_size = amd64_fetch_size,
214 .cleanup = amd64_cleanup,
215 .tlb_flush = amd64_tlbflush,
216 .mask_memory = agp_generic_mask_memory,
217 .masks = NULL,
218 .agp_enable = agp_generic_enable,
219 .cache_flush = global_cache_flush,
220 .create_gatt_table = agp_generic_create_gatt_table,
221 .free_gatt_table = agp_generic_free_gatt_table,
222 .insert_memory = amd64_insert_memory,
223 .remove_memory = agp_generic_remove_memory,
224 .alloc_by_type = agp_generic_alloc_by_type,
225 .free_by_type = agp_generic_free_by_type,
226 .agp_alloc_page = agp_generic_alloc_page,
227 .agp_alloc_pages = agp_generic_alloc_pages,
228 .agp_destroy_page = agp_generic_destroy_page,
229 .agp_destroy_pages = agp_generic_destroy_pages,
230 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
231};
232
233
234static int __devinit agp_aperture_valid(u64 aper, u32 size)
235{
236 if (!aperture_valid(aper, size, 32*1024*1024))
237 return 0;
238
239
240
241
242
243
244 if (!aperture_resource &&
245 !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
246 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
247 return 0;
248 }
249 return 1;
250}
251
252
253
254
255
256
257
258
259
260
261static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
262 u16 cap)
263{
264 u32 aper_low, aper_hi;
265 u64 aper, nb_aper;
266 int order = 0;
267 u32 nb_order, nb_base;
268 u16 apsize;
269
270 pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
271 nb_order = (nb_order >> 1) & 7;
272 pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
273 nb_aper = nb_base << 25;
274 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
275 return 0;
276 }
277
278
279
280 pci_read_config_word(agp, cap+0x14, &apsize);
281 if (apsize == 0xffff)
282 return -1;
283
284 apsize &= 0xfff;
285
286 if (apsize & 0xff)
287 apsize |= 0xf00;
288 order = 7 - hweight16(apsize);
289
290 pci_read_config_dword(agp, 0x10, &aper_low);
291 pci_read_config_dword(agp, 0x14, &aper_hi);
292 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
293
294
295
296
297
298 if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
299 dev_info(&agp->dev, "aperture size %u MB is not right, using settings from NB\n",
300 32 << order);
301 order = nb_order;
302 }
303
304 dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n",
305 aper, 32 << order);
306 if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
307 return -1;
308
309 pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1);
310 pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
311
312 return 0;
313}
314
315static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
316{
317 int i;
318
319 if (cache_k8_northbridges() < 0)
320 return -ENODEV;
321
322 i = 0;
323 for (i = 0; i < num_k8_northbridges; i++) {
324 struct pci_dev *dev = k8_northbridges[i];
325 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
326 dev_err(&dev->dev, "no usable aperture found\n");
327#ifdef __x86_64__
328
329 dev_err(&dev->dev, "consider rebooting with iommu=memaper=2 to get a good aperture\n");
330#endif
331 return -1;
332 }
333 }
334 return 0;
335}
336
337
338static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
339{
340 char *revstring;
341
342 switch (pdev->revision) {
343 case 0x01: revstring="A0"; break;
344 case 0x02: revstring="A1"; break;
345 case 0x11: revstring="B0"; break;
346 case 0x12: revstring="B1"; break;
347 case 0x13: revstring="B2"; break;
348 case 0x14: revstring="B3"; break;
349 default: revstring="??"; break;
350 }
351
352 dev_info(&pdev->dev, "AMD 8151 AGP Bridge rev %s\n", revstring);
353
354
355
356
357
358 if (pdev->revision < 0x13) {
359 dev_info(&pdev->dev, "correcting AGP revision (reports 3.5, is really 3.0)\n");
360 bridge->major_version = 3;
361 bridge->minor_version = 0;
362 }
363}
364
365
366static const struct aper_size_info_32 uli_sizes[7] =
367{
368 {256, 65536, 6, 10},
369 {128, 32768, 5, 9},
370 {64, 16384, 4, 8},
371 {32, 8192, 3, 7},
372 {16, 4096, 2, 6},
373 {8, 2048, 1, 4},
374 {4, 1024, 0, 3}
375};
376static int __devinit uli_agp_init(struct pci_dev *pdev)
377{
378 u32 httfea,baseaddr,enuscr;
379 struct pci_dev *dev1;
380 int i;
381 unsigned size = amd64_fetch_size();
382
383 dev_info(&pdev->dev, "setting up ULi AGP\n");
384 dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0));
385 if (dev1 == NULL) {
386 dev_info(&pdev->dev, "can't find ULi secondary device\n");
387 return -ENODEV;
388 }
389
390 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
391 if (uli_sizes[i].size == size)
392 break;
393
394 if (i == ARRAY_SIZE(uli_sizes)) {
395 dev_info(&pdev->dev, "no ULi size found for %d\n", size);
396 return -ENODEV;
397 }
398
399
400 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
401
402
403 if ((httfea & 0x7fff) >> (32 - 25))
404 return -ENODEV;
405
406 httfea = (httfea& 0x7fff) << 25;
407
408 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
409 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
410 baseaddr|= httfea;
411 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
412
413 enuscr= httfea+ (size * 1024 * 1024) - 1;
414 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
415 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
416
417 pci_dev_put(dev1);
418 return 0;
419}
420
421
422static const struct aper_size_info_32 nforce3_sizes[5] =
423{
424 {512, 131072, 7, 0x00000000 },
425 {256, 65536, 6, 0x00000008 },
426 {128, 32768, 5, 0x0000000C },
427 {64, 16384, 4, 0x0000000E },
428 {32, 8192, 3, 0x0000000F }
429};
430
431
432
433static int nforce3_agp_init(struct pci_dev *pdev)
434{
435 u32 tmp, apbase, apbar, aplimit;
436 struct pci_dev *dev1;
437 int i;
438 unsigned size = amd64_fetch_size();
439
440 dev_info(&pdev->dev, "setting up Nforce3 AGP\n");
441
442 dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0));
443 if (dev1 == NULL) {
444 dev_info(&pdev->dev, "can't find Nforce3 secondary device\n");
445 return -ENODEV;
446 }
447
448 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
449 if (nforce3_sizes[i].size == size)
450 break;
451
452 if (i == ARRAY_SIZE(nforce3_sizes)) {
453 dev_info(&pdev->dev, "no NForce3 size found for %d\n", size);
454 return -ENODEV;
455 }
456
457 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
458 tmp &= ~(0xf);
459 tmp |= nforce3_sizes[i].size_value;
460 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
461
462
463 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
464
465
466 if ( (apbase & 0x7fff) >> (32 - 25) ) {
467 dev_info(&pdev->dev, "aperture base > 4G\n");
468 return -ENODEV;
469 }
470
471 apbase = (apbase & 0x7fff) << 25;
472
473 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
474 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
475 apbar |= apbase;
476 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
477
478 aplimit = apbase + (size * 1024 * 1024) - 1;
479 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
480 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
481 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
482 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
483
484 pci_dev_put(dev1);
485
486 return 0;
487}
488
489static int __devinit agp_amd64_probe(struct pci_dev *pdev,
490 const struct pci_device_id *ent)
491{
492 struct agp_bridge_data *bridge;
493 u8 cap_ptr;
494 int err;
495
496 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
497 if (!cap_ptr)
498 return -ENODEV;
499
500
501
502 bridge = agp_alloc_bridge();
503 if (!bridge)
504 return -ENOMEM;
505
506 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
507 pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
508 amd8151_init(pdev, bridge);
509 } else {
510 dev_info(&pdev->dev, "AGP bridge [%04x/%04x]\n",
511 pdev->vendor, pdev->device);
512 }
513
514 bridge->driver = &amd_8151_driver;
515 bridge->dev = pdev;
516 bridge->capndx = cap_ptr;
517
518
519 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
520
521 if (cache_nbs(pdev, cap_ptr) == -1) {
522 agp_put_bridge(bridge);
523 return -ENODEV;
524 }
525
526 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
527 int ret = nforce3_agp_init(pdev);
528 if (ret) {
529 agp_put_bridge(bridge);
530 return ret;
531 }
532 }
533
534 if (pdev->vendor == PCI_VENDOR_ID_AL) {
535 int ret = uli_agp_init(pdev);
536 if (ret) {
537 agp_put_bridge(bridge);
538 return ret;
539 }
540 }
541
542 pci_set_drvdata(pdev, bridge);
543 err = agp_add_bridge(bridge);
544 if (err < 0)
545 return err;
546
547 agp_bridges_found++;
548 return 0;
549}
550
551static void __devexit agp_amd64_remove(struct pci_dev *pdev)
552{
553 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
554
555 release_mem_region(virt_to_gart(bridge->gatt_table_real),
556 amd64_aperture_sizes[bridge->aperture_size_idx].size);
557 agp_remove_bridge(bridge);
558 agp_put_bridge(bridge);
559}
560
561#ifdef CONFIG_PM
562
563static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
564{
565 pci_save_state(pdev);
566 pci_set_power_state(pdev, pci_choose_state(pdev, state));
567
568 return 0;
569}
570
571static int agp_amd64_resume(struct pci_dev *pdev)
572{
573 pci_set_power_state(pdev, PCI_D0);
574 pci_restore_state(pdev);
575
576 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
577 nforce3_agp_init(pdev);
578
579 return amd_8151_configure();
580}
581
582#endif
583
584static struct pci_device_id agp_amd64_pci_table[] = {
585 {
586 .class = (PCI_CLASS_BRIDGE_HOST << 8),
587 .class_mask = ~0,
588 .vendor = PCI_VENDOR_ID_AMD,
589 .device = PCI_DEVICE_ID_AMD_8151_0,
590 .subvendor = PCI_ANY_ID,
591 .subdevice = PCI_ANY_ID,
592 },
593
594 {
595 .class = (PCI_CLASS_BRIDGE_HOST << 8),
596 .class_mask = ~0,
597 .vendor = PCI_VENDOR_ID_AL,
598 .device = PCI_DEVICE_ID_AL_M1689,
599 .subvendor = PCI_ANY_ID,
600 .subdevice = PCI_ANY_ID,
601 },
602
603 {
604 .class = (PCI_CLASS_BRIDGE_HOST << 8),
605 .class_mask = ~0,
606 .vendor = PCI_VENDOR_ID_VIA,
607 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
608 .subvendor = PCI_ANY_ID,
609 .subdevice = PCI_ANY_ID,
610 },
611
612 {
613 .class = (PCI_CLASS_BRIDGE_HOST << 8),
614 .class_mask = ~0,
615 .vendor = PCI_VENDOR_ID_VIA,
616 .device = PCI_DEVICE_ID_VIA_8385_0,
617 .subvendor = PCI_ANY_ID,
618 .subdevice = PCI_ANY_ID,
619 },
620
621 {
622 .class = (PCI_CLASS_BRIDGE_HOST << 8),
623 .class_mask = ~0,
624 .vendor = PCI_VENDOR_ID_VIA,
625 .device = PCI_DEVICE_ID_VIA_8380_0,
626 .subvendor = PCI_ANY_ID,
627 .subdevice = PCI_ANY_ID,
628 },
629
630 {
631 .class = (PCI_CLASS_BRIDGE_HOST << 8),
632 .class_mask = ~0,
633 .vendor = PCI_VENDOR_ID_VIA,
634 .device = PCI_DEVICE_ID_VIA_VT3336,
635 .subvendor = PCI_ANY_ID,
636 .subdevice = PCI_ANY_ID,
637 },
638
639 {
640 .class = (PCI_CLASS_BRIDGE_HOST << 8),
641 .class_mask = ~0,
642 .vendor = PCI_VENDOR_ID_VIA,
643 .device = PCI_DEVICE_ID_VIA_3238_0,
644 .subvendor = PCI_ANY_ID,
645 .subdevice = PCI_ANY_ID,
646 },
647
648 {
649 .class = (PCI_CLASS_BRIDGE_HOST << 8),
650 .class_mask = ~0,
651 .vendor = PCI_VENDOR_ID_VIA,
652 .device = PCI_DEVICE_ID_VIA_838X_1,
653 .subvendor = PCI_ANY_ID,
654 .subdevice = PCI_ANY_ID,
655 },
656
657 {
658 .class = (PCI_CLASS_BRIDGE_HOST << 8),
659 .class_mask = ~0,
660 .vendor = PCI_VENDOR_ID_NVIDIA,
661 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
662 .subvendor = PCI_ANY_ID,
663 .subdevice = PCI_ANY_ID,
664 },
665 {
666 .class = (PCI_CLASS_BRIDGE_HOST << 8),
667 .class_mask = ~0,
668 .vendor = PCI_VENDOR_ID_NVIDIA,
669 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
670 .subvendor = PCI_ANY_ID,
671 .subdevice = PCI_ANY_ID,
672 },
673
674 {
675 .class = (PCI_CLASS_BRIDGE_HOST << 8),
676 .class_mask = ~0,
677 .vendor = PCI_VENDOR_ID_SI,
678 .device = PCI_DEVICE_ID_SI_755,
679 .subvendor = PCI_ANY_ID,
680 .subdevice = PCI_ANY_ID,
681 },
682
683 {
684 .class = (PCI_CLASS_BRIDGE_HOST << 8),
685 .class_mask = ~0,
686 .vendor = PCI_VENDOR_ID_SI,
687 .device = PCI_DEVICE_ID_SI_760,
688 .subvendor = PCI_ANY_ID,
689 .subdevice = PCI_ANY_ID,
690 },
691
692 {
693 .class = (PCI_CLASS_BRIDGE_HOST << 8),
694 .class_mask = ~0,
695 .vendor = PCI_VENDOR_ID_AL,
696 .device = 0x1695,
697 .subvendor = PCI_ANY_ID,
698 .subdevice = PCI_ANY_ID,
699 },
700
701 { }
702};
703
704MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
705
706static struct pci_driver agp_amd64_pci_driver = {
707 .name = "agpgart-amd64",
708 .id_table = agp_amd64_pci_table,
709 .probe = agp_amd64_probe,
710 .remove = agp_amd64_remove,
711#ifdef CONFIG_PM
712 .suspend = agp_amd64_suspend,
713 .resume = agp_amd64_resume,
714#endif
715};
716
717
718
719int __init agp_amd64_init(void)
720{
721 int err = 0;
722
723 if (agp_off)
724 return -EINVAL;
725 err = pci_register_driver(&agp_amd64_pci_driver);
726 if (err < 0)
727 return err;
728
729 if (agp_bridges_found == 0) {
730 struct pci_dev *dev;
731 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
732 printk(KERN_INFO PFX "No supported AGP bridge found.\n");
733#ifdef MODULE
734 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
735#else
736 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
737#endif
738 return -ENODEV;
739 }
740
741
742 if (!pci_dev_present(k8_nb_ids))
743 return -ENODEV;
744
745
746 dev = NULL;
747 err = -ENODEV;
748 for_each_pci_dev(dev) {
749 if (!pci_find_capability(dev, PCI_CAP_ID_AGP))
750 continue;
751
752 if (agp_amd64_probe(dev, NULL) == 0) {
753 err = 0;
754 break;
755 }
756 }
757 }
758 return err;
759}
760
761static void __exit agp_amd64_cleanup(void)
762{
763 if (aperture_resource)
764 release_resource(aperture_resource);
765 pci_unregister_driver(&agp_amd64_pci_driver);
766}
767
768
769
770#ifndef CONFIG_GART_IOMMU
771module_init(agp_amd64_init);
772module_exit(agp_amd64_cleanup);
773#endif
774
775MODULE_AUTHOR("Dave Jones <davej@redhat.com>, Andi Kleen");
776module_param(agp_try_unsupported, bool, 0);
777MODULE_LICENSE("GPL");
778
