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25#include <linux/errno.h>
26#include <linux/kernel.h>
27#include <linux/delay.h>
28#include <linux/console.h>
29#include <linux/pci.h>
30#include <linux/of_platform.h>
31
32#include <asm/prom.h>
33#include <asm/system.h>
34#include <asm/iommu.h>
35#include <asm/machdep.h>
36#include <asm/mpic.h>
37#include <asm/smp.h>
38#include <asm/time.h>
39#include <asm/mmu.h>
40
41#include <pcmcia/ss.h>
42#include <pcmcia/cistpl.h>
43#include <pcmcia/ds.h>
44
45#include "pasemi.h"
46
47#if !defined(CONFIG_SMP)
48static void smp_send_stop(void) {}
49#endif
50
51
52static void __iomem *reset_reg;
53
54
55
56#define MAX_MCE_REGS 32
57struct mce_regs {
58 char *name;
59 void __iomem *addr;
60};
61
62static struct mce_regs mce_regs[MAX_MCE_REGS];
63static int num_mce_regs;
64static int nmi_virq = NO_IRQ;
65
66
67static void pas_restart(char *cmd)
68{
69
70 smp_send_stop();
71 udelay(10000);
72 printk("Restarting...\n");
73 while (1)
74 out_le32(reset_reg, 0x6000000);
75}
76
77#ifdef CONFIG_SMP
78static DEFINE_SPINLOCK(timebase_lock);
79static unsigned long timebase;
80
81static void __devinit pas_give_timebase(void)
82{
83 spin_lock(&timebase_lock);
84 mtspr(SPRN_TBCTL, TBCTL_FREEZE);
85 isync();
86 timebase = get_tb();
87 spin_unlock(&timebase_lock);
88
89 while (timebase)
90 barrier();
91 mtspr(SPRN_TBCTL, TBCTL_RESTART);
92}
93
94static void __devinit pas_take_timebase(void)
95{
96 while (!timebase)
97 smp_rmb();
98
99 spin_lock(&timebase_lock);
100 set_tb(timebase >> 32, timebase & 0xffffffff);
101 timebase = 0;
102 spin_unlock(&timebase_lock);
103}
104
105struct smp_ops_t pas_smp_ops = {
106 .probe = smp_mpic_probe,
107 .message_pass = smp_mpic_message_pass,
108 .kick_cpu = smp_generic_kick_cpu,
109 .setup_cpu = smp_mpic_setup_cpu,
110 .give_timebase = pas_give_timebase,
111 .take_timebase = pas_take_timebase,
112};
113#endif
114
115void __init pas_setup_arch(void)
116{
117#ifdef CONFIG_SMP
118
119 smp_ops = &pas_smp_ops;
120#endif
121
122 pas_pci_init();
123
124#ifdef CONFIG_DUMMY_CONSOLE
125 conswitchp = &dummy_con;
126#endif
127
128
129
130 reset_reg = ioremap(0xfc101100, 4);
131}
132
133static int __init pas_setup_mce_regs(void)
134{
135 struct pci_dev *dev;
136 int reg;
137
138
139
140 reg = 0;
141
142 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
143 while (dev && reg < MAX_MCE_REGS) {
144 mce_regs[reg].name = kasprintf(GFP_KERNEL,
145 "mc%d_mcdebug_errsta", reg);
146 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
147 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
148 reg++;
149 }
150
151 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
152 if (dev && reg+4 < MAX_MCE_REGS) {
153 mce_regs[reg].name = "iobdbg_IntStatus1";
154 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
155 reg++;
156 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
157 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
158 reg++;
159 mce_regs[reg].name = "iobiom_IntStatus";
160 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
161 reg++;
162 mce_regs[reg].name = "iobiom_IntDbgReg";
163 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
164 reg++;
165 }
166
167 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
168 if (dev && reg+2 < MAX_MCE_REGS) {
169 mce_regs[reg].name = "l2csts_IntStatus";
170 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
171 reg++;
172 mce_regs[reg].name = "l2csts_Cnt";
173 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
174 reg++;
175 }
176
177 num_mce_regs = reg;
178
179 return 0;
180}
181machine_device_initcall(pasemi, pas_setup_mce_regs);
182
183static __init void pas_init_IRQ(void)
184{
185 struct device_node *np;
186 struct device_node *root, *mpic_node;
187 unsigned long openpic_addr;
188 const unsigned int *opprop;
189 int naddr, opplen;
190 int mpic_flags;
191 const unsigned int *nmiprop;
192 struct mpic *mpic;
193
194 mpic_node = NULL;
195
196 for_each_node_by_type(np, "interrupt-controller")
197 if (of_device_is_compatible(np, "open-pic")) {
198 mpic_node = np;
199 break;
200 }
201 if (!mpic_node)
202 for_each_node_by_type(np, "open-pic") {
203 mpic_node = np;
204 break;
205 }
206 if (!mpic_node) {
207 printk(KERN_ERR
208 "Failed to locate the MPIC interrupt controller\n");
209 return;
210 }
211
212
213 root = of_find_node_by_path("/");
214 naddr = of_n_addr_cells(root);
215 opprop = of_get_property(root, "platform-open-pic", &opplen);
216 if (!opprop) {
217 printk(KERN_ERR "No platform-open-pic property.\n");
218 of_node_put(root);
219 return;
220 }
221 openpic_addr = of_read_number(opprop, naddr);
222 printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
223
224 mpic_flags = MPIC_PRIMARY | MPIC_LARGE_VECTORS | MPIC_NO_BIAS;
225
226 nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
227 if (nmiprop)
228 mpic_flags |= MPIC_ENABLE_MCK;
229
230 mpic = mpic_alloc(mpic_node, openpic_addr,
231 mpic_flags, 0, 0, "PASEMI-OPIC");
232 BUG_ON(!mpic);
233
234 mpic_assign_isu(mpic, 0, openpic_addr + 0x10000);
235 mpic_init(mpic);
236
237 if (nmiprop) {
238 nmi_virq = irq_create_mapping(NULL, *nmiprop);
239 mpic_irq_set_priority(nmi_virq, 15);
240 set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
241 mpic_unmask_irq(nmi_virq);
242 }
243
244 of_node_put(mpic_node);
245 of_node_put(root);
246}
247
248static void __init pas_progress(char *s, unsigned short hex)
249{
250 printk("[%04x] : %s\n", hex, s ? s : "");
251}
252
253
254static int pas_machine_check_handler(struct pt_regs *regs)
255{
256 int cpu = smp_processor_id();
257 unsigned long srr0, srr1, dsisr;
258 int dump_slb = 0;
259 int i;
260
261 srr0 = regs->nip;
262 srr1 = regs->msr;
263
264 if (nmi_virq != NO_IRQ && mpic_get_mcirq() == nmi_virq) {
265 printk(KERN_ERR "NMI delivered\n");
266 debugger(regs);
267 mpic_end_irq(nmi_virq);
268 goto out;
269 }
270
271 dsisr = mfspr(SPRN_DSISR);
272 printk(KERN_ERR "Machine Check on CPU %d\n", cpu);
273 printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1);
274 printk(KERN_ERR "DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar);
275 printk(KERN_ERR "BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER),
276 mfspr(SPRN_PA6T_MER));
277 printk(KERN_ERR "IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER),
278 mfspr(SPRN_PA6T_DER));
279 printk(KERN_ERR "Cause:\n");
280
281 if (srr1 & 0x200000)
282 printk(KERN_ERR "Signalled by SDC\n");
283
284 if (srr1 & 0x100000) {
285 printk(KERN_ERR "Load/Store detected error:\n");
286 if (dsisr & 0x8000)
287 printk(KERN_ERR "D-cache ECC double-bit error or bus error\n");
288 if (dsisr & 0x4000)
289 printk(KERN_ERR "LSU snoop response error\n");
290 if (dsisr & 0x2000) {
291 printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n");
292 dump_slb = 1;
293 }
294 if (dsisr & 0x1000)
295 printk(KERN_ERR "Recoverable Duptags\n");
296 if (dsisr & 0x800)
297 printk(KERN_ERR "Recoverable D-cache parity error count overflow\n");
298 if (dsisr & 0x400)
299 printk(KERN_ERR "TLB parity error count overflow\n");
300 }
301
302 if (srr1 & 0x80000)
303 printk(KERN_ERR "Bus Error\n");
304
305 if (srr1 & 0x40000) {
306 printk(KERN_ERR "I-side SLB multiple hit\n");
307 dump_slb = 1;
308 }
309
310 if (srr1 & 0x20000)
311 printk(KERN_ERR "I-cache parity error hit\n");
312
313 if (num_mce_regs == 0)
314 printk(KERN_ERR "No MCE registers mapped yet, can't dump\n");
315 else
316 printk(KERN_ERR "SoC debug registers:\n");
317
318 for (i = 0; i < num_mce_regs; i++)
319 printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name,
320 in_le32(mce_regs[i].addr));
321
322 if (dump_slb) {
323 unsigned long e, v;
324 int i;
325
326 printk(KERN_ERR "slb contents:\n");
327 for (i = 0; i < mmu_slb_size; i++) {
328 asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i));
329 asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
330 printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v);
331 }
332 }
333
334out:
335
336 return !!(srr1 & 0x2);
337}
338
339static void __init pas_init_early(void)
340{
341 iommu_init_early_pasemi();
342}
343
344#ifdef CONFIG_PCMCIA
345static int pcmcia_notify(struct notifier_block *nb, unsigned long action,
346 void *data)
347{
348 struct device *dev = data;
349 struct device *parent;
350 struct pcmcia_device *pdev = to_pcmcia_dev(dev);
351
352
353 if (action != BUS_NOTIFY_ADD_DEVICE)
354 return 0;
355
356 parent = pdev->socket->dev.parent;
357
358
359
360
361 if (!parent->archdata.of_node)
362 return 0;
363
364 if (!of_device_is_compatible(parent->archdata.of_node, "electra-cf"))
365 return 0;
366
367
368 dev->archdata.dma_ops = &dma_direct_ops;
369
370 return 0;
371}
372
373static struct notifier_block pcmcia_notifier = {
374 .notifier_call = pcmcia_notify,
375};
376
377static inline void pasemi_pcmcia_init(void)
378{
379 extern struct bus_type pcmcia_bus_type;
380
381 bus_register_notifier(&pcmcia_bus_type, &pcmcia_notifier);
382}
383
384#else
385
386static inline void pasemi_pcmcia_init(void)
387{
388}
389
390#endif
391
392
393static struct of_device_id pasemi_bus_ids[] = {
394
395 { .type = "localbus", },
396 { .type = "sdc", },
397
398 { .compatible = "pasemi,localbus", },
399 { .compatible = "pasemi,sdc", },
400 {},
401};
402
403static int __init pasemi_publish_devices(void)
404{
405 pasemi_pcmcia_init();
406
407
408 of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);
409
410 return 0;
411}
412machine_device_initcall(pasemi, pasemi_publish_devices);
413
414
415
416
417
418static int __init pas_probe(void)
419{
420 unsigned long root = of_get_flat_dt_root();
421
422 if (!of_flat_dt_is_compatible(root, "PA6T-1682M") &&
423 !of_flat_dt_is_compatible(root, "pasemi,pwrficient"))
424 return 0;
425
426 hpte_init_native();
427
428 alloc_iobmap_l2();
429
430 return 1;
431}
432
433define_machine(pasemi) {
434 .name = "PA Semi PWRficient",
435 .probe = pas_probe,
436 .setup_arch = pas_setup_arch,
437 .init_early = pas_init_early,
438 .init_IRQ = pas_init_IRQ,
439 .get_irq = mpic_get_irq,
440 .restart = pas_restart,
441 .get_boot_time = pas_get_boot_time,
442 .calibrate_decr = generic_calibrate_decr,
443 .progress = pas_progress,
444 .machine_check_exception = pas_machine_check_handler,
445};
446
