LXR linux/arch/mips/mti-malta/malta-init.c

   1/*
   2 * Copyright (C) 1999, 2000, 2004, 2005  MIPS Technologies, Inc.
   3 *      All rights reserved.
   4 *      Authors: Carsten Langgaard <carstenl@mips.com>
   5 *               Maciej W. Rozycki <macro@mips.com>
   6 *
   7 *  This program is free software; you can distribute it and/or modify it
   8 *  under the terms of the GNU General Public License (Version 2) as
   9 *  published by the Free Software Foundation.
  10 *
  11 *  This program is distributed in the hope it will be useful, but WITHOUT
  12 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 *  for more details.
  15 *
  16 *  You should have received a copy of the GNU General Public License along
  17 *  with this program; if not, write to the Free Software Foundation, Inc.,
  18 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  19 *
  20 * PROM library initialisation code.
  21 */
  22#include <linux/init.h>
  23#include <linux/string.h>
  24#include <linux/kernel.h>
  25
  26#include <asm/bootinfo.h>
  27#include <asm/gt64120.h>
  28#include <asm/io.h>
  29#include <asm/system.h>
  30#include <asm/cacheflush.h>
  31#include <asm/traps.h>
  32
  33#include <asm/mips-boards/prom.h>
  34#include <asm/mips-boards/generic.h>
  35#include <asm/mips-boards/bonito64.h>
  36#include <asm/mips-boards/msc01_pci.h>
  37
  38#include <asm/mips-boards/malta.h>
  39
  40int prom_argc;
  41int *_prom_argv, *_prom_envp;
  42
  43/*
  44 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
  45 * This macro take care of sign extension, if running in 64-bit mode.
  46 */
  47#define prom_envp(index) ((char *)(long)_prom_envp[(index)])
  48
  49int init_debug = 0;
  50
  51int mips_revision_corid;
  52int mips_revision_sconid;
  53
  54/* Bonito64 system controller register base. */
  55unsigned long _pcictrl_bonito;
  56unsigned long _pcictrl_bonito_pcicfg;
  57
  58/* GT64120 system controller register base */
  59unsigned long _pcictrl_gt64120;
  60
  61/* MIPS System controller register base */
  62unsigned long _pcictrl_msc;
  63
  64char *prom_getenv(char *envname)
  65{
  66        /*
  67         * Return a pointer to the given environment variable.
  68         * In 64-bit mode: we're using 64-bit pointers, but all pointers
  69         * in the PROM structures are only 32-bit, so we need some
  70         * workarounds, if we are running in 64-bit mode.
  71         */
  72        int i, index=0;
  73
  74        i = strlen(envname);
  75
  76        while (prom_envp(index)) {
  77                if(strncmp(envname, prom_envp(index), i) == 0) {
  78                        return(prom_envp(index+1));
  79                }
  80                index += 2;
  81        }
  82
  83        return NULL;
  84}
  85
  86static inline unsigned char str2hexnum(unsigned char c)
  87{
  88        if (c >= '0' && c <= '9')
  89                return c - '0';
  90        if (c >= 'a' && c <= 'f')
  91                return c - 'a' + 10;
  92        return 0; /* foo */
  93}
  94
  95static inline void str2eaddr(unsigned char *ea, unsigned char *str)
  96{
  97        int i;
  98
  99        for (i = 0; i < 6; i++) {
 100                unsigned char num;
 101
 102                if((*str == '.') || (*str == ':'))
 103                        str++;
 104                num = str2hexnum(*str++) << 4;
 105                num |= (str2hexnum(*str++));
 106                ea[i] = num;
 107        }
 108}
 109
 110int get_ethernet_addr(char *ethernet_addr)
 111{
 112        char *ethaddr_str;
 113
 114        ethaddr_str = prom_getenv("ethaddr");
 115        if (!ethaddr_str) {
 116                printk("ethaddr not set in boot prom\n");
 117                return -1;
 118        }
 119        str2eaddr(ethernet_addr, ethaddr_str);
 120
 121        if (init_debug > 1) {
 122                int i;
 123                printk("get_ethernet_addr: ");
 124                for (i=0; i<5; i++)
 125                        printk("%02x:", (unsigned char)*(ethernet_addr+i));
 126                printk("%02x\n", *(ethernet_addr+i));
 127        }
 128
 129        return 0;
 130}
 131
 132#ifdef CONFIG_SERIAL_8250_CONSOLE
 133static void __init console_config(void)
 134{
 135        char console_string[40];
 136        int baud = 0;
 137        char parity = '\0', bits = '\0', flow = '\0';
 138        char *s;
 139
 140        if ((strstr(prom_getcmdline(), "console=")) == NULL) {
 141                s = prom_getenv("modetty0");
 142                if (s) {
 143                        while (*s >= '0' && *s <= '9')
 144                                baud = baud*10 + *s++ - '0';
 145                        if (*s == ',') s++;
 146                        if (*s) parity = *s++;
 147                        if (*s == ',') s++;
 148                        if (*s) bits = *s++;
 149                        if (*s == ',') s++;
 150                        if (*s == 'h') flow = 'r';
 151                }
 152                if (baud == 0)
 153                        baud = 38400;
 154                if (parity != 'n' && parity != 'o' && parity != 'e')
 155                        parity = 'n';
 156                if (bits != '7' && bits != '8')
 157                        bits = '8';
 158                if (flow == '\0')
 159                        flow = 'r';
 160                sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
 161                strcat(prom_getcmdline(), console_string);
 162                pr_info("Config serial console:%s\n", console_string);
 163        }
 164}
 165#endif
 166
 167static void __init mips_nmi_setup(void)
 168{
 169        void *base;
 170        extern char except_vec_nmi;
 171
 172        base = cpu_has_veic ?
 173                (void *)(CAC_BASE + 0xa80) :
 174                (void *)(CAC_BASE + 0x380);
 175        memcpy(base, &except_vec_nmi, 0x80);
 176        flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
 177}
 178
 179static void __init mips_ejtag_setup(void)
 180{
 181        void *base;
 182        extern char except_vec_ejtag_debug;
 183
 184        base = cpu_has_veic ?
 185                (void *)(CAC_BASE + 0xa00) :
 186                (void *)(CAC_BASE + 0x300);
 187        memcpy(base, &except_vec_ejtag_debug, 0x80);
 188        flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
 189}
 190
 191extern struct plat_smp_ops msmtc_smp_ops;
 192
 193void __init prom_init(void)
 194{
 195        prom_argc = fw_arg0;
 196        _prom_argv = (int *) fw_arg1;
 197        _prom_envp = (int *) fw_arg2;
 198
 199        mips_display_message("LINUX");
 200
 201        /*
 202         * early setup of _pcictrl_bonito so that we can determine
 203         * the system controller on a CORE_EMUL board
 204         */
 205        _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE);
 206
 207        mips_revision_corid = MIPS_REVISION_CORID;
 208
 209        if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {
 210                if (BONITO_PCIDID == 0x0001df53 ||
 211                    BONITO_PCIDID == 0x0003df53)
 212                        mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;
 213                else
 214                        mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;
 215        }
 216
 217        mips_revision_sconid = MIPS_REVISION_SCONID;
 218        if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) {
 219                switch (mips_revision_corid) {
 220                case MIPS_REVISION_CORID_QED_RM5261:
 221                case MIPS_REVISION_CORID_CORE_LV:
 222                case MIPS_REVISION_CORID_CORE_FPGA:
 223                case MIPS_REVISION_CORID_CORE_FPGAR2:
 224                        mips_revision_sconid = MIPS_REVISION_SCON_GT64120;
 225                        break;
 226                case MIPS_REVISION_CORID_CORE_EMUL_BON:
 227                case MIPS_REVISION_CORID_BONITO64:
 228                case MIPS_REVISION_CORID_CORE_20K:
 229                        mips_revision_sconid = MIPS_REVISION_SCON_BONITO;
 230                        break;
 231                case MIPS_REVISION_CORID_CORE_MSC:
 232                case MIPS_REVISION_CORID_CORE_FPGA2:
 233                case MIPS_REVISION_CORID_CORE_24K:
 234                        /*
 235                         * SOCit/ROCit support is essentially identical
 236                         * but make an attempt to distinguish them
 237                         */
 238                        mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;
 239                        break;
 240                case MIPS_REVISION_CORID_CORE_FPGA3:
 241                case MIPS_REVISION_CORID_CORE_FPGA4:
 242                case MIPS_REVISION_CORID_CORE_FPGA5:
 243                case MIPS_REVISION_CORID_CORE_EMUL_MSC:
 244                default:
 245                        /* See above */
 246                        mips_revision_sconid = MIPS_REVISION_SCON_ROCIT;
 247                        break;
 248                }
 249        }
 250
 251        switch (mips_revision_sconid) {
 252                u32 start, map, mask, data;
 253
 254        case MIPS_REVISION_SCON_GT64120:
 255                /*
 256                 * Setup the North bridge to do Master byte-lane swapping
 257                 * when running in bigendian.
 258                 */
 259                _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000);
 260
 261#ifdef CONFIG_CPU_LITTLE_ENDIAN
 262                GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
 263                         GT_PCI0_CMD_SBYTESWAP_BIT);
 264#else
 265                GT_WRITE(GT_PCI0_CMD_OFS, 0);
 266#endif
 267                /* Fix up PCI I/O mapping if necessary (for Atlas).  */
 268                start = GT_READ(GT_PCI0IOLD_OFS);
 269                map = GT_READ(GT_PCI0IOREMAP_OFS);
 270                if ((start & map) != 0) {
 271                        map &= ~start;
 272                        GT_WRITE(GT_PCI0IOREMAP_OFS, map);
 273                }
 274
 275                set_io_port_base(MALTA_GT_PORT_BASE);
 276                break;
 277
 278        case MIPS_REVISION_SCON_BONITO:
 279                _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);
 280
 281                /*
 282                 * Disable Bonito IOBC.
 283                 */
 284                BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
 285                        ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 286                          BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 287
 288                /*
 289                 * Setup the North bridge to do Master byte-lane swapping
 290                 * when running in bigendian.
 291                 */
 292#ifdef CONFIG_CPU_LITTLE_ENDIAN
 293                BONITO_BONGENCFG = BONITO_BONGENCFG &
 294                        ~(BONITO_BONGENCFG_MSTRBYTESWAP |
 295                          BONITO_BONGENCFG_BYTESWAP);
 296#else
 297                BONITO_BONGENCFG = BONITO_BONGENCFG |
 298                        BONITO_BONGENCFG_MSTRBYTESWAP |
 299                        BONITO_BONGENCFG_BYTESWAP;
 300#endif
 301
 302                set_io_port_base(MALTA_BONITO_PORT_BASE);
 303                break;
 304
 305        case MIPS_REVISION_SCON_SOCIT:
 306        case MIPS_REVISION_SCON_ROCIT:
 307                _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
 308        mips_pci_controller:
 309                mb();
 310                MSC_READ(MSC01_PCI_CFG, data);
 311                MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
 312                wmb();
 313
 314                /* Fix up lane swapping.  */
 315#ifdef CONFIG_CPU_LITTLE_ENDIAN
 316                MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
 317#else
 318                MSC_WRITE(MSC01_PCI_SWAP,
 319                          MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF |
 320                          MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
 321                          MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
 322#endif
 323                /* Fix up target memory mapping.  */
 324                MSC_READ(MSC01_PCI_BAR0, mask);
 325                MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
 326
 327                /* Don't handle target retries indefinitely.  */
 328                if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
 329                    MSC01_PCI_CFG_MAXRTRY_MSK)
 330                        data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
 331                                         MSC01_PCI_CFG_MAXRTRY_SHF)) |
 332                               ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
 333                                MSC01_PCI_CFG_MAXRTRY_SHF);
 334
 335                wmb();
 336                MSC_WRITE(MSC01_PCI_CFG, data);
 337                mb();
 338
 339                set_io_port_base(MALTA_MSC_PORT_BASE);
 340                break;
 341
 342        case MIPS_REVISION_SCON_SOCITSC:
 343        case MIPS_REVISION_SCON_SOCITSCP:
 344                _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000);
 345                goto mips_pci_controller;
 346
 347        default:
 348                /* Unknown system controller */
 349                mips_display_message("SC Error");
 350                while (1);   /* We die here... */
 351        }
 352        board_nmi_handler_setup = mips_nmi_setup;
 353        board_ejtag_handler_setup = mips_ejtag_setup;
 354
 355        pr_info("\nLINUX started...\n");
 356        prom_init_cmdline();
 357        prom_meminit();
 358#ifdef CONFIG_SERIAL_8250_CONSOLE
 359        console_config();
 360#endif
 361#ifdef CONFIG_MIPS_CMP
 362        register_smp_ops(&cmp_smp_ops);
 363#endif
 364#ifdef CONFIG_MIPS_MT_SMP
 365        register_smp_ops(&vsmp_smp_ops);
 366#endif
 367#ifdef CONFIG_MIPS_MT_SMTC
 368        register_smp_ops(&msmtc_smp_ops);
 369#endif
 370}
 371