LXR linux/arch/arm/oprofile/op_model

   1/**
   2 * @file op_model_mpcore.c
   3 * MPCORE Event Monitor Driver
   4 * @remark Copyright 2004 ARM SMP Development Team
   5 * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
   6 * @remark Copyright 2000-2004 MontaVista Software Inc
   7 * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>
   8 * @remark Copyright 2004 Intel Corporation
   9 * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
  10 * @remark Copyright 2004 Oprofile Authors
  11 *
  12 * @remark Read the file COPYING
  13 *
  14 * @author Zwane Mwaikambo
  15 */
  16#ifndef OP_MODEL_MPCORE_H
  17#define OP_MODEL_MPCORE_H
  18
  19struct eventmonitor {
  20        unsigned long PMCR;
  21        unsigned char MCEB[8];
  22        unsigned long MC[8];
  23};
  24
  25/*
  26 * List of userspace counter numbers: note that the structure is important.
  27 * The code relies on CPUn's counters being CPU0's counters + 3n
  28 * and on CPU0's counters starting at 0
  29 */
  30
  31#define COUNTER_CPU0_PMN0 0
  32#define COUNTER_CPU0_PMN1 1
  33#define COUNTER_CPU0_CCNT 2
  34
  35#define COUNTER_CPU1_PMN0 3
  36#define COUNTER_CPU1_PMN1 4
  37#define COUNTER_CPU1_CCNT 5
  38
  39#define COUNTER_CPU2_PMN0 6
  40#define COUNTER_CPU2_PMN1 7
  41#define COUNTER_CPU2_CCNT 8
  42
  43#define COUNTER_CPU3_PMN0 9
  44#define COUNTER_CPU3_PMN1 10
  45#define COUNTER_CPU3_CCNT 11
  46
  47#define COUNTER_SCU_MN0 12
  48#define COUNTER_SCU_MN1 13
  49#define COUNTER_SCU_MN2 14
  50#define COUNTER_SCU_MN3 15
  51#define COUNTER_SCU_MN4 16
  52#define COUNTER_SCU_MN5 17
  53#define COUNTER_SCU_MN6 18
  54#define COUNTER_SCU_MN7 19
  55#define NUM_SCU_COUNTERS 8
  56
  57#define SCU_COUNTER(number)     ((number) + COUNTER_SCU_MN0)
  58
  59#define MPCORE_NUM_COUNTERS     SCU_COUNTER(NUM_SCU_COUNTERS)
  60
  61#endif
  62