LXR linux/arch/arm/include/asm/system.h

   1#ifndef __ASM_ARM_SYSTEM_H
   2#define __ASM_ARM_SYSTEM_H
   3
   4#ifdef __KERNEL__
   5
   6#include <asm/memory.h>
   7
   8#define CPU_ARCH_UNKNOWN        0
   9#define CPU_ARCH_ARMv3          1
  10#define CPU_ARCH_ARMv4          2
  11#define CPU_ARCH_ARMv4T         3
  12#define CPU_ARCH_ARMv5          4
  13#define CPU_ARCH_ARMv5T         5
  14#define CPU_ARCH_ARMv5TE        6
  15#define CPU_ARCH_ARMv5TEJ       7
  16#define CPU_ARCH_ARMv6          8
  17#define CPU_ARCH_ARMv7          9
  18
  19/*
  20 * CR1 bits (CP#15 CR1)
  21 */
  22#define CR_M    (1 << 0)        /* MMU enable                           */
  23#define CR_A    (1 << 1)        /* Alignment abort enable               */
  24#define CR_C    (1 << 2)        /* Dcache enable                        */
  25#define CR_W    (1 << 3)        /* Write buffer enable                  */
  26#define CR_P    (1 << 4)        /* 32-bit exception handler             */
  27#define CR_D    (1 << 5)        /* 32-bit data address range            */
  28#define CR_L    (1 << 6)        /* Implementation defined               */
  29#define CR_B    (1 << 7)        /* Big endian                           */
  30#define CR_S    (1 << 8)        /* System MMU protection                */
  31#define CR_R    (1 << 9)        /* ROM MMU protection                   */
  32#define CR_F    (1 << 10)       /* Implementation defined               */
  33#define CR_Z    (1 << 11)       /* Implementation defined               */
  34#define CR_I    (1 << 12)       /* Icache enable                        */
  35#define CR_V    (1 << 13)       /* Vectors relocated to 0xffff0000      */
  36#define CR_RR   (1 << 14)       /* Round Robin cache replacement        */
  37#define CR_L4   (1 << 15)       /* LDR pc can set T bit                 */
  38#define CR_DT   (1 << 16)
  39#define CR_IT   (1 << 18)
  40#define CR_ST   (1 << 19)
  41#define CR_FI   (1 << 21)       /* Fast interrupt (lower latency mode)  */
  42#define CR_U    (1 << 22)       /* Unaligned access operation           */
  43#define CR_XP   (1 << 23)       /* Extended page tables                 */
  44#define CR_VE   (1 << 24)       /* Vectored interrupts                  */
  45#define CR_EE   (1 << 25)       /* Exception (Big) Endian               */
  46#define CR_TRE  (1 << 28)       /* TEX remap enable                     */
  47#define CR_AFE  (1 << 29)       /* Access flag enable                   */
  48#define CR_TE   (1 << 30)       /* Thumb exception enable               */
  49
  50/*
  51 * This is used to ensure the compiler did actually allocate the register we
  52 * asked it for some inline assembly sequences.  Apparently we can't trust
  53 * the compiler from one version to another so a bit of paranoia won't hurt.
  54 * This string is meant to be concatenated with the inline asm string and
  55 * will cause compilation to stop on mismatch.
  56 * (for details, see gcc PR 15089)
  57 */
  58#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
  59
  60#ifndef __ASSEMBLY__
  61
  62#include <linux/linkage.h>
  63#include <linux/irqflags.h>
  64
  65#define __exception     __attribute__((section(".exception.text")))
  66
  67struct thread_info;
  68struct task_struct;
  69
  70/* information about the system we're running on */
  71extern unsigned int system_rev;
  72extern unsigned int system_serial_low;
  73extern unsigned int system_serial_high;
  74extern unsigned int mem_fclk_21285;
  75
  76struct pt_regs;
  77
  78void die(const char *msg, struct pt_regs *regs, int err)
  79                __attribute__((noreturn));
  80
  81struct siginfo;
  82void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
  83                unsigned long err, unsigned long trap);
  84
  85void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
  86                                       struct pt_regs *),
  87                     int sig, const char *name);
  88
  89#define xchg(ptr,x) \
  90        ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
  91
  92extern asmlinkage void __backtrace(void);
  93extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
  94
  95struct mm_struct;
  96extern void show_pte(struct mm_struct *mm, unsigned long addr);
  97extern void __show_regs(struct pt_regs *);
  98
  99extern int cpu_architecture(void);
 100extern void cpu_init(void);
 101
 102void arm_machine_restart(char mode);
 103extern void (*arm_pm_restart)(char str);
 104
 105#define UDBG_UNDEFINED  (1 << 0)
 106#define UDBG_SYSCALL    (1 << 1)
 107#define UDBG_BADABORT   (1 << 2)
 108#define UDBG_SEGV       (1 << 3)
 109#define UDBG_BUS        (1 << 4)
 110
 111extern unsigned int user_debug;
 112
 113#if __LINUX_ARM_ARCH__ >= 4
 114#define vectors_high()  (cr_alignment & CR_V)
 115#else
 116#define vectors_high()  (0)
 117#endif
 118
 119#if __LINUX_ARM_ARCH__ >= 7
 120#define isb() __asm__ __volatile__ ("isb" : : : "memory")
 121#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
 122#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
 123#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
 124#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
 125                                    : : "r" (0) : "memory")
 126#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
 127                                    : : "r" (0) : "memory")
 128#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
 129                                    : : "r" (0) : "memory")
 130#else
 131#define isb() __asm__ __volatile__ ("" : : : "memory")
 132#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
 133                                    : : "r" (0) : "memory")
 134#define dmb() __asm__ __volatile__ ("" : : : "memory")
 135#endif
 136
 137#ifndef CONFIG_SMP
 138#define mb()    do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 139#define rmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 140#define wmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 141#define smp_mb()        barrier()
 142#define smp_rmb()       barrier()
 143#define smp_wmb()       barrier()
 144#else
 145#define mb()            dmb()
 146#define rmb()           dmb()
 147#define wmb()           dmb()
 148#define smp_mb()        dmb()
 149#define smp_rmb()       dmb()
 150#define smp_wmb()       dmb()
 151#endif
 152#define read_barrier_depends()          do { } while(0)
 153#define smp_read_barrier_depends()      do { } while(0)
 154
 155#define set_mb(var, value)      do { var = value; smp_mb(); } while (0)
 156#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 157
 158extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
 159extern unsigned long cr_alignment;      /* defined in entry-armv.S */
 160
 161static inline unsigned int get_cr(void)
 162{
 163        unsigned int val;
 164        asm("mrc p15, 0, %0, c1, c0, 0  @ get CR" : "=r" (val) : : "cc");
 165        return val;
 166}
 167
 168static inline void set_cr(unsigned int val)
 169{
 170        asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
 171          : : "r" (val) : "cc");
 172        isb();
 173}
 174
 175#ifndef CONFIG_SMP
 176extern void adjust_cr(unsigned long mask, unsigned long set);
 177#endif
 178
 179#define CPACC_FULL(n)           (3 << (n * 2))
 180#define CPACC_SVC(n)            (1 << (n * 2))
 181#define CPACC_DISABLE(n)        (0 << (n * 2))
 182
 183static inline unsigned int get_copro_access(void)
 184{
 185        unsigned int val;
 186        asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
 187          : "=r" (val) : : "cc");
 188        return val;
 189}
 190
 191static inline void set_copro_access(unsigned int val)
 192{
 193        asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
 194          : : "r" (val) : "cc");
 195        isb();
 196}
 197
 198/*
 199 * switch_mm() may do a full cache flush over the context switch,
 200 * so enable interrupts over the context switch to avoid high
 201 * latency.
 202 */
 203#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
 204
 205/*
 206 * switch_to(prev, next) should switch from task `prev' to `next'
 207 * `prev' will never be the same as `next'.  schedule() itself
 208 * contains the memory barrier to tell GCC not to cache `current'.
 209 */
 210extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
 211
 212#define switch_to(prev,next,last)                                       \
 213do {                                                                    \
 214        last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));        \
 215} while (0)
 216
 217#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
 218/*
 219 * On the StrongARM, "swp" is terminally broken since it bypasses the
 220 * cache totally.  This means that the cache becomes inconsistent, and,
 221 * since we use normal loads/stores as well, this is really bad.
 222 * Typically, this causes oopsen in filp_close, but could have other,
 223 * more disasterous effects.  There are two work-arounds:
 224 *  1. Disable interrupts and emulate the atomic swap
 225 *  2. Clean the cache, perform atomic swap, flush the cache
 226 *
 227 * We choose (1) since its the "easiest" to achieve here and is not
 228 * dependent on the processor type.
 229 *
 230 * NOTE that this solution won't work on an SMP system, so explcitly
 231 * forbid it here.
 232 */
 233#define swp_is_buggy
 234#endif
 235
 236static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
 237{
 238        extern void __bad_xchg(volatile void *, int);
 239        unsigned long ret;
 240#ifdef swp_is_buggy
 241        unsigned long flags;
 242#endif
 243#if __LINUX_ARM_ARCH__ >= 6
 244        unsigned int tmp;
 245#endif
 246
 247        switch (size) {
 248#if __LINUX_ARM_ARCH__ >= 6
 249        case 1:
 250                asm volatile("@ __xchg1\n"
 251                "1:     ldrexb  %0, [%3]\n"
 252                "       strexb  %1, %2, [%3]\n"
 253                "       teq     %1, #0\n"
 254                "       bne     1b"
 255                        : "=&r" (ret), "=&r" (tmp)
 256                        : "r" (x), "r" (ptr)
 257                        : "memory", "cc");
 258                break;
 259        case 4:
 260                asm volatile("@ __xchg4\n"
 261                "1:     ldrex   %0, [%3]\n"
 262                "       strex   %1, %2, [%3]\n"
 263                "       teq     %1, #0\n"
 264                "       bne     1b"
 265                        : "=&r" (ret), "=&r" (tmp)
 266                        : "r" (x), "r" (ptr)
 267                        : "memory", "cc");
 268                break;
 269#elif defined(swp_is_buggy)
 270#ifdef CONFIG_SMP
 271#error SMP is not supported on this platform
 272#endif
 273        case 1:
 274                raw_local_irq_save(flags);
 275                ret = *(volatile unsigned char *)ptr;
 276                *(volatile unsigned char *)ptr = x;
 277                raw_local_irq_restore(flags);
 278                break;
 279
 280        case 4:
 281                raw_local_irq_save(flags);
 282                ret = *(volatile unsigned long *)ptr;
 283                *(volatile unsigned long *)ptr = x;
 284                raw_local_irq_restore(flags);
 285                break;
 286#else
 287        case 1:
 288                asm volatile("@ __xchg1\n"
 289                "       swpb    %0, %1, [%2]"
 290                        : "=&r" (ret)
 291                        : "r" (x), "r" (ptr)
 292                        : "memory", "cc");
 293                break;
 294        case 4:
 295                asm volatile("@ __xchg4\n"
 296                "       swp     %0, %1, [%2]"
 297                        : "=&r" (ret)
 298                        : "r" (x), "r" (ptr)
 299                        : "memory", "cc");
 300                break;
 301#endif
 302        default:
 303                __bad_xchg(ptr, size), ret = 0;
 304                break;
 305        }
 306
 307        return ret;
 308}
 309
 310extern void disable_hlt(void);
 311extern void enable_hlt(void);
 312
 313#include <asm-generic/cmpxchg-local.h>
 314
 315/*
 316 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
 317 * them available.
 318 */
 319#define cmpxchg_local(ptr, o, n)                                               \
 320        ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
 321                        (unsigned long)(n), sizeof(*(ptr))))
 322#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 323
 324#ifndef CONFIG_SMP
 325#include <asm-generic/cmpxchg.h>
 326#endif
 327
 328#endif /* __ASSEMBLY__ */
 329
 330#define arch_align_stack(x) (x)
 331
 332#endif /* __KERNEL__ */
 333
 334#endif
 335