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29#ifndef __LINUX_ATA_H__
30#define __LINUX_ATA_H__
31
32#include <linux/types.h>
33#include <asm/byteorder.h>
34
35
36#define ATA_DMA_BOUNDARY 0xffffUL
37#define ATA_DMA_MASK 0xffffffffULL
38
39enum {
40
41 ATA_MAX_DEVICES = 2,
42 ATA_MAX_PRD = 256,
43 ATA_SECT_SIZE = 512,
44 ATA_MAX_SECTORS_128 = 128,
45 ATA_MAX_SECTORS = 256,
46 ATA_MAX_SECTORS_LBA48 = 65535,
47 ATA_MAX_SECTORS_TAPE = 65535,
48
49 ATA_ID_WORDS = 256,
50 ATA_ID_CONFIG = 0,
51 ATA_ID_CYLS = 1,
52 ATA_ID_HEADS = 3,
53 ATA_ID_SECTORS = 6,
54 ATA_ID_SERNO = 10,
55 ATA_ID_BUF_SIZE = 21,
56 ATA_ID_FW_REV = 23,
57 ATA_ID_PROD = 27,
58 ATA_ID_MAX_MULTSECT = 47,
59 ATA_ID_DWORD_IO = 48,
60 ATA_ID_CAPABILITY = 49,
61 ATA_ID_OLD_PIO_MODES = 51,
62 ATA_ID_OLD_DMA_MODES = 52,
63 ATA_ID_FIELD_VALID = 53,
64 ATA_ID_CUR_CYLS = 54,
65 ATA_ID_CUR_HEADS = 55,
66 ATA_ID_CUR_SECTORS = 56,
67 ATA_ID_MULTSECT = 59,
68 ATA_ID_LBA_CAPACITY = 60,
69 ATA_ID_SWDMA_MODES = 62,
70 ATA_ID_MWDMA_MODES = 63,
71 ATA_ID_PIO_MODES = 64,
72 ATA_ID_EIDE_DMA_MIN = 65,
73 ATA_ID_EIDE_DMA_TIME = 66,
74 ATA_ID_EIDE_PIO = 67,
75 ATA_ID_EIDE_PIO_IORDY = 68,
76 ATA_ID_QUEUE_DEPTH = 75,
77 ATA_ID_MAJOR_VER = 80,
78 ATA_ID_COMMAND_SET_1 = 82,
79 ATA_ID_COMMAND_SET_2 = 83,
80 ATA_ID_CFSSE = 84,
81 ATA_ID_CFS_ENABLE_1 = 85,
82 ATA_ID_CFS_ENABLE_2 = 86,
83 ATA_ID_CSF_DEFAULT = 87,
84 ATA_ID_UDMA_MODES = 88,
85 ATA_ID_HW_CONFIG = 93,
86 ATA_ID_SPG = 98,
87 ATA_ID_LBA_CAPACITY_2 = 100,
88 ATA_ID_LAST_LUN = 126,
89 ATA_ID_DLF = 128,
90 ATA_ID_CSFO = 129,
91 ATA_ID_CFA_POWER = 160,
92 ATA_ID_ROT_SPEED = 217,
93 ATA_ID_PIO4 = (1 << 1),
94
95 ATA_ID_SERNO_LEN = 20,
96 ATA_ID_FW_REV_LEN = 8,
97 ATA_ID_PROD_LEN = 40,
98
99 ATA_PCI_CTL_OFS = 2,
100
101 ATA_PIO0 = (1 << 0),
102 ATA_PIO1 = ATA_PIO0 | (1 << 1),
103 ATA_PIO2 = ATA_PIO1 | (1 << 2),
104 ATA_PIO3 = ATA_PIO2 | (1 << 3),
105 ATA_PIO4 = ATA_PIO3 | (1 << 4),
106 ATA_PIO5 = ATA_PIO4 | (1 << 5),
107 ATA_PIO6 = ATA_PIO5 | (1 << 6),
108
109 ATA_SWDMA0 = (1 << 0),
110 ATA_SWDMA1 = ATA_SWDMA0 | (1 << 1),
111 ATA_SWDMA2 = ATA_SWDMA1 | (1 << 2),
112
113 ATA_SWDMA2_ONLY = (1 << 2),
114
115 ATA_MWDMA0 = (1 << 0),
116 ATA_MWDMA1 = ATA_MWDMA0 | (1 << 1),
117 ATA_MWDMA2 = ATA_MWDMA1 | (1 << 2),
118
119 ATA_MWDMA12_ONLY = (1 << 1) | (1 << 2),
120 ATA_MWDMA2_ONLY = (1 << 2),
121
122 ATA_UDMA0 = (1 << 0),
123 ATA_UDMA1 = ATA_UDMA0 | (1 << 1),
124 ATA_UDMA2 = ATA_UDMA1 | (1 << 2),
125 ATA_UDMA3 = ATA_UDMA2 | (1 << 3),
126 ATA_UDMA4 = ATA_UDMA3 | (1 << 4),
127 ATA_UDMA5 = ATA_UDMA4 | (1 << 5),
128 ATA_UDMA6 = ATA_UDMA5 | (1 << 6),
129 ATA_UDMA7 = ATA_UDMA6 | (1 << 7),
130
131
132 ATA_UDMA_MASK_40C = ATA_UDMA2,
133
134
135 ATA_PRD_SZ = 8,
136 ATA_PRD_TBL_SZ = (ATA_MAX_PRD * ATA_PRD_SZ),
137 ATA_PRD_EOT = (1 << 31),
138
139 ATA_DMA_TABLE_OFS = 4,
140 ATA_DMA_STATUS = 2,
141 ATA_DMA_CMD = 0,
142 ATA_DMA_WR = (1 << 3),
143 ATA_DMA_START = (1 << 0),
144 ATA_DMA_INTR = (1 << 2),
145 ATA_DMA_ERR = (1 << 1),
146 ATA_DMA_ACTIVE = (1 << 0),
147
148
149 ATA_HOB = (1 << 7),
150 ATA_NIEN = (1 << 1),
151 ATA_LBA = (1 << 6),
152 ATA_DEV1 = (1 << 4),
153 ATA_DEVICE_OBS = (1 << 7) | (1 << 5),
154 ATA_DEVCTL_OBS = (1 << 3),
155 ATA_BUSY = (1 << 7),
156 ATA_DRDY = (1 << 6),
157 ATA_DF = (1 << 5),
158 ATA_DSC = (1 << 4),
159 ATA_DRQ = (1 << 3),
160 ATA_CORR = (1 << 2),
161 ATA_IDX = (1 << 1),
162 ATA_ERR = (1 << 0),
163 ATA_SRST = (1 << 2),
164 ATA_ICRC = (1 << 7),
165 ATA_BBK = ATA_ICRC,
166 ATA_UNC = (1 << 6),
167 ATA_MC = (1 << 5),
168 ATA_IDNF = (1 << 4),
169 ATA_MCR = (1 << 3),
170 ATA_ABORTED = (1 << 2),
171 ATA_TRK0NF = (1 << 1),
172 ATA_AMNF = (1 << 0),
173 ATAPI_LFS = 0xF0,
174 ATAPI_EOM = ATA_TRK0NF,
175 ATAPI_ILI = ATA_AMNF,
176 ATAPI_IO = (1 << 1),
177 ATAPI_COD = (1 << 0),
178
179
180 ATA_REG_DATA = 0x00,
181 ATA_REG_ERR = 0x01,
182 ATA_REG_NSECT = 0x02,
183 ATA_REG_LBAL = 0x03,
184 ATA_REG_LBAM = 0x04,
185 ATA_REG_LBAH = 0x05,
186 ATA_REG_DEVICE = 0x06,
187 ATA_REG_STATUS = 0x07,
188
189 ATA_REG_FEATURE = ATA_REG_ERR,
190 ATA_REG_CMD = ATA_REG_STATUS,
191 ATA_REG_BYTEL = ATA_REG_LBAM,
192 ATA_REG_BYTEH = ATA_REG_LBAH,
193 ATA_REG_DEVSEL = ATA_REG_DEVICE,
194 ATA_REG_IRQ = ATA_REG_NSECT,
195
196
197 ATA_CMD_DEV_RESET = 0x08,
198 ATA_CMD_CHK_POWER = 0xE5,
199 ATA_CMD_STANDBY = 0xE2,
200 ATA_CMD_IDLE = 0xE3,
201 ATA_CMD_EDD = 0x90,
202 ATA_CMD_FLUSH = 0xE7,
203 ATA_CMD_FLUSH_EXT = 0xEA,
204 ATA_CMD_ID_ATA = 0xEC,
205 ATA_CMD_ID_ATAPI = 0xA1,
206 ATA_CMD_READ = 0xC8,
207 ATA_CMD_READ_EXT = 0x25,
208 ATA_CMD_WRITE = 0xCA,
209 ATA_CMD_WRITE_EXT = 0x35,
210 ATA_CMD_WRITE_FUA_EXT = 0x3D,
211 ATA_CMD_FPDMA_READ = 0x60,
212 ATA_CMD_FPDMA_WRITE = 0x61,
213 ATA_CMD_PIO_READ = 0x20,
214 ATA_CMD_PIO_READ_EXT = 0x24,
215 ATA_CMD_PIO_WRITE = 0x30,
216 ATA_CMD_PIO_WRITE_EXT = 0x34,
217 ATA_CMD_READ_MULTI = 0xC4,
218 ATA_CMD_READ_MULTI_EXT = 0x29,
219 ATA_CMD_WRITE_MULTI = 0xC5,
220 ATA_CMD_WRITE_MULTI_EXT = 0x39,
221 ATA_CMD_WRITE_MULTI_FUA_EXT = 0xCE,
222 ATA_CMD_SET_FEATURES = 0xEF,
223 ATA_CMD_SET_MULTI = 0xC6,
224 ATA_CMD_PACKET = 0xA0,
225 ATA_CMD_VERIFY = 0x40,
226 ATA_CMD_VERIFY_EXT = 0x42,
227 ATA_CMD_STANDBYNOW1 = 0xE0,
228 ATA_CMD_IDLEIMMEDIATE = 0xE1,
229 ATA_CMD_SLEEP = 0xE6,
230 ATA_CMD_INIT_DEV_PARAMS = 0x91,
231 ATA_CMD_READ_NATIVE_MAX = 0xF8,
232 ATA_CMD_READ_NATIVE_MAX_EXT = 0x27,
233 ATA_CMD_SET_MAX = 0xF9,
234 ATA_CMD_SET_MAX_EXT = 0x37,
235 ATA_CMD_READ_LOG_EXT = 0x2f,
236 ATA_CMD_PMP_READ = 0xE4,
237 ATA_CMD_PMP_WRITE = 0xE8,
238 ATA_CMD_CONF_OVERLAY = 0xB1,
239 ATA_CMD_SEC_FREEZE_LOCK = 0xF5,
240 ATA_CMD_SMART = 0xB0,
241 ATA_CMD_MEDIA_LOCK = 0xDE,
242 ATA_CMD_MEDIA_UNLOCK = 0xDF,
243
244 ATA_CMD_RESTORE = 0x10,
245
246 ATA_EXABYTE_ENABLE_NEST = 0xF0,
247
248
249 ATA_LOG_SATA_NCQ = 0x10,
250
251
252 ATA_CMD_READ_LONG = 0x22,
253 ATA_CMD_READ_LONG_ONCE = 0x23,
254 ATA_CMD_WRITE_LONG = 0x32,
255 ATA_CMD_WRITE_LONG_ONCE = 0x33,
256
257
258 SETFEATURES_XFER = 0x03,
259 XFER_UDMA_7 = 0x47,
260 XFER_UDMA_6 = 0x46,
261 XFER_UDMA_5 = 0x45,
262 XFER_UDMA_4 = 0x44,
263 XFER_UDMA_3 = 0x43,
264 XFER_UDMA_2 = 0x42,
265 XFER_UDMA_1 = 0x41,
266 XFER_UDMA_0 = 0x40,
267 XFER_MW_DMA_4 = 0x24,
268 XFER_MW_DMA_3 = 0x23,
269 XFER_MW_DMA_2 = 0x22,
270 XFER_MW_DMA_1 = 0x21,
271 XFER_MW_DMA_0 = 0x20,
272 XFER_SW_DMA_2 = 0x12,
273 XFER_SW_DMA_1 = 0x11,
274 XFER_SW_DMA_0 = 0x10,
275 XFER_PIO_6 = 0x0E,
276 XFER_PIO_5 = 0x0D,
277 XFER_PIO_4 = 0x0C,
278 XFER_PIO_3 = 0x0B,
279 XFER_PIO_2 = 0x0A,
280 XFER_PIO_1 = 0x09,
281 XFER_PIO_0 = 0x08,
282 XFER_PIO_SLOW = 0x00,
283
284 SETFEATURES_WC_ON = 0x02,
285 SETFEATURES_WC_OFF = 0x82,
286
287
288 SETFEATURES_AAM_ON = 0x42,
289 SETFEATURES_AAM_OFF = 0xC2,
290
291 SETFEATURES_SPINUP = 0x07,
292
293 SETFEATURES_SATA_ENABLE = 0x10,
294 SETFEATURES_SATA_DISABLE = 0x90,
295
296
297 SATA_AN = 0x05,
298 SATA_DIPM = 0x03,
299
300
301 ATA_SET_MAX_ADDR = 0x00,
302 ATA_SET_MAX_PASSWD = 0x01,
303 ATA_SET_MAX_LOCK = 0x02,
304 ATA_SET_MAX_UNLOCK = 0x03,
305 ATA_SET_MAX_FREEZE_LOCK = 0x04,
306
307
308 ATA_DCO_RESTORE = 0xC0,
309 ATA_DCO_FREEZE_LOCK = 0xC1,
310 ATA_DCO_IDENTIFY = 0xC2,
311 ATA_DCO_SET = 0xC3,
312
313
314 ATA_SMART_ENABLE = 0xD8,
315 ATA_SMART_READ_VALUES = 0xD0,
316 ATA_SMART_READ_THRESHOLDS = 0xD1,
317
318
319 ATA_SMART_LBAM_PASS = 0x4F,
320 ATA_SMART_LBAH_PASS = 0xC2,
321
322
323 ATAPI_PKT_DMA = (1 << 0),
324 ATAPI_DMADIR = (1 << 2),
325
326 ATAPI_CDB_LEN = 16,
327
328
329 SATA_PMP_MAX_PORTS = 15,
330 SATA_PMP_CTRL_PORT = 15,
331
332 SATA_PMP_GSCR_DWORDS = 128,
333 SATA_PMP_GSCR_PROD_ID = 0,
334 SATA_PMP_GSCR_REV = 1,
335 SATA_PMP_GSCR_PORT_INFO = 2,
336 SATA_PMP_GSCR_ERROR = 32,
337 SATA_PMP_GSCR_ERROR_EN = 33,
338 SATA_PMP_GSCR_FEAT = 64,
339 SATA_PMP_GSCR_FEAT_EN = 96,
340
341 SATA_PMP_PSCR_STATUS = 0,
342 SATA_PMP_PSCR_ERROR = 1,
343 SATA_PMP_PSCR_CONTROL = 2,
344
345 SATA_PMP_FEAT_BIST = (1 << 0),
346 SATA_PMP_FEAT_PMREQ = (1 << 1),
347 SATA_PMP_FEAT_DYNSSC = (1 << 2),
348 SATA_PMP_FEAT_NOTIFY = (1 << 3),
349
350
351 ATA_CBL_NONE = 0,
352 ATA_CBL_PATA40 = 1,
353 ATA_CBL_PATA80 = 2,
354 ATA_CBL_PATA40_SHORT = 3,
355 ATA_CBL_PATA_UNK = 4,
356 ATA_CBL_PATA_IGN = 5,
357 ATA_CBL_SATA = 6,
358
359
360 SCR_STATUS = 0,
361 SCR_ERROR = 1,
362 SCR_CONTROL = 2,
363 SCR_ACTIVE = 3,
364 SCR_NOTIFICATION = 4,
365
366
367 SERR_DATA_RECOVERED = (1 << 0),
368 SERR_COMM_RECOVERED = (1 << 1),
369 SERR_DATA = (1 << 8),
370 SERR_PERSISTENT = (1 << 9),
371 SERR_PROTOCOL = (1 << 10),
372 SERR_INTERNAL = (1 << 11),
373 SERR_PHYRDY_CHG = (1 << 16),
374 SERR_PHY_INT_ERR = (1 << 17),
375 SERR_COMM_WAKE = (1 << 18),
376 SERR_10B_8B_ERR = (1 << 19),
377 SERR_DISPARITY = (1 << 20),
378 SERR_CRC = (1 << 21),
379 SERR_HANDSHAKE = (1 << 22),
380 SERR_LINK_SEQ_ERR = (1 << 23),
381 SERR_TRANS_ST_ERROR = (1 << 24),
382 SERR_UNRECOG_FIS = (1 << 25),
383 SERR_DEV_XCHG = (1 << 26),
384
385
386 ATA_TFLAG_LBA48 = (1 << 0),
387 ATA_TFLAG_ISADDR = (1 << 1),
388 ATA_TFLAG_DEVICE = (1 << 2),
389 ATA_TFLAG_WRITE = (1 << 3),
390 ATA_TFLAG_LBA = (1 << 4),
391 ATA_TFLAG_FUA = (1 << 5),
392 ATA_TFLAG_POLLING = (1 << 6),
393
394
395 ATA_PROT_FLAG_PIO = (1 << 0),
396 ATA_PROT_FLAG_DMA = (1 << 1),
397 ATA_PROT_FLAG_DATA = ATA_PROT_FLAG_PIO | ATA_PROT_FLAG_DMA,
398 ATA_PROT_FLAG_NCQ = (1 << 2),
399 ATA_PROT_FLAG_ATAPI = (1 << 3),
400};
401
402enum ata_tf_protocols {
403
404 ATA_PROT_UNKNOWN,
405 ATA_PROT_NODATA,
406 ATA_PROT_PIO,
407 ATA_PROT_DMA,
408 ATA_PROT_NCQ,
409 ATAPI_PROT_NODATA,
410 ATAPI_PROT_PIO,
411 ATAPI_PROT_DMA,
412};
413
414enum ata_ioctls {
415 ATA_IOC_GET_IO32 = 0x309,
416 ATA_IOC_SET_IO32 = 0x324,
417};
418
419
420
421struct ata_prd {
422 __le32 addr;
423 __le32 flags_len;
424};
425
426struct ata_taskfile {
427 unsigned long flags;
428 u8 protocol;
429
430 u8 ctl;
431
432 u8 hob_feature;
433 u8 hob_nsect;
434 u8 hob_lbal;
435 u8 hob_lbam;
436 u8 hob_lbah;
437
438 u8 feature;
439 u8 nsect;
440 u8 lbal;
441 u8 lbam;
442 u8 lbah;
443
444 u8 device;
445
446 u8 command;
447};
448
449
450
451
452static inline unsigned int ata_prot_flags(u8 prot)
453{
454 switch (prot) {
455 case ATA_PROT_NODATA:
456 return 0;
457 case ATA_PROT_PIO:
458 return ATA_PROT_FLAG_PIO;
459 case ATA_PROT_DMA:
460 return ATA_PROT_FLAG_DMA;
461 case ATA_PROT_NCQ:
462 return ATA_PROT_FLAG_DMA | ATA_PROT_FLAG_NCQ;
463 case ATAPI_PROT_NODATA:
464 return ATA_PROT_FLAG_ATAPI;
465 case ATAPI_PROT_PIO:
466 return ATA_PROT_FLAG_ATAPI | ATA_PROT_FLAG_PIO;
467 case ATAPI_PROT_DMA:
468 return ATA_PROT_FLAG_ATAPI | ATA_PROT_FLAG_DMA;
469 }
470 return 0;
471}
472
473static inline int ata_is_atapi(u8 prot)
474{
475 return ata_prot_flags(prot) & ATA_PROT_FLAG_ATAPI;
476}
477
478static inline int ata_is_nodata(u8 prot)
479{
480 return !(ata_prot_flags(prot) & ATA_PROT_FLAG_DATA);
481}
482
483static inline int ata_is_pio(u8 prot)
484{
485 return ata_prot_flags(prot) & ATA_PROT_FLAG_PIO;
486}
487
488static inline int ata_is_dma(u8 prot)
489{
490 return ata_prot_flags(prot) & ATA_PROT_FLAG_DMA;
491}
492
493static inline int ata_is_ncq(u8 prot)
494{
495 return ata_prot_flags(prot) & ATA_PROT_FLAG_NCQ;
496}
497
498static inline int ata_is_data(u8 prot)
499{
500 return ata_prot_flags(prot) & ATA_PROT_FLAG_DATA;
501}
502
503
504
505
506#define ata_id_is_ata(id) (((id)[ATA_ID_CONFIG] & (1 << 15)) == 0)
507#define ata_id_has_lba(id) ((id)[ATA_ID_CAPABILITY] & (1 << 9))
508#define ata_id_has_dma(id) ((id)[ATA_ID_CAPABILITY] & (1 << 8))
509#define ata_id_has_ncq(id) ((id)[76] & (1 << 8))
510#define ata_id_queue_depth(id) (((id)[ATA_ID_QUEUE_DEPTH] & 0x1f) + 1)
511#define ata_id_removeable(id) ((id)[ATA_ID_CONFIG] & (1 << 7))
512#define ata_id_has_atapi_AN(id) \
513 ( (((id)[76] != 0x0000) && ((id)[76] != 0xffff)) && \
514 ((id)[78] & (1 << 5)) )
515#define ata_id_iordy_disable(id) ((id)[ATA_ID_CAPABILITY] & (1 << 10))
516#define ata_id_has_iordy(id) ((id)[ATA_ID_CAPABILITY] & (1 << 11))
517#define ata_id_u32(id,n) \
518 (((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
519#define ata_id_u64(id,n) \
520 ( ((u64) (id)[(n) + 3] << 48) | \
521 ((u64) (id)[(n) + 2] << 32) | \
522 ((u64) (id)[(n) + 1] << 16) | \
523 ((u64) (id)[(n) + 0]) )
524
525#define ata_id_cdb_intr(id) (((id)[ATA_ID_CONFIG] & 0x60) == 0x20)
526
527static inline bool ata_id_has_hipm(const u16 *id)
528{
529 u16 val = id[76];
530
531 if (val == 0 || val == 0xffff)
532 return false;
533
534 return val & (1 << 9);
535}
536
537static inline bool ata_id_has_dipm(const u16 *id)
538{
539 u16 val = id[78];
540
541 if (val == 0 || val == 0xffff)
542 return false;
543
544 return val & (1 << 3);
545}
546
547
548static inline int ata_id_has_fua(const u16 *id)
549{
550 if ((id[ATA_ID_CFSSE] & 0xC000) != 0x4000)
551 return 0;
552 return id[ATA_ID_CFSSE] & (1 << 6);
553}
554
555static inline int ata_id_has_flush(const u16 *id)
556{
557 if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
558 return 0;
559 return id[ATA_ID_COMMAND_SET_2] & (1 << 12);
560}
561
562static inline int ata_id_flush_enabled(const u16 *id)
563{
564 if (ata_id_has_flush(id) == 0)
565 return 0;
566 if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
567 return 0;
568 return id[ATA_ID_CFS_ENABLE_2] & (1 << 12);
569}
570
571static inline int ata_id_has_flush_ext(const u16 *id)
572{
573 if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
574 return 0;
575 return id[ATA_ID_COMMAND_SET_2] & (1 << 13);
576}
577
578static inline int ata_id_flush_ext_enabled(const u16 *id)
579{
580 if (ata_id_has_flush_ext(id) == 0)
581 return 0;
582 if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
583 return 0;
584
585
586
587
588 return (id[ATA_ID_CFS_ENABLE_2] & 0x2400) == 0x2400;
589}
590
591static inline int ata_id_has_lba48(const u16 *id)
592{
593 if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
594 return 0;
595 if (!ata_id_u64(id, ATA_ID_LBA_CAPACITY_2))
596 return 0;
597 return id[ATA_ID_COMMAND_SET_2] & (1 << 10);
598}
599
600static inline int ata_id_lba48_enabled(const u16 *id)
601{
602 if (ata_id_has_lba48(id) == 0)
603 return 0;
604 if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
605 return 0;
606 return id[ATA_ID_CFS_ENABLE_2] & (1 << 10);
607}
608
609static inline int ata_id_hpa_enabled(const u16 *id)
610{
611
612 if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
613 return 0;
614
615 if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
616 return 0;
617
618 if ((id[ATA_ID_CFS_ENABLE_1] & (1 << 10)) == 0)
619 return 0;
620 return id[ATA_ID_COMMAND_SET_1] & (1 << 10);
621}
622
623static inline int ata_id_has_wcache(const u16 *id)
624{
625
626 if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
627 return 0;
628 return id[ATA_ID_COMMAND_SET_1] & (1 << 5);
629}
630
631static inline int ata_id_has_pm(const u16 *id)
632{
633 if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
634 return 0;
635 return id[ATA_ID_COMMAND_SET_1] & (1 << 3);
636}
637
638static inline int ata_id_rahead_enabled(const u16 *id)
639{
640 if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
641 return 0;
642 return id[ATA_ID_CFS_ENABLE_1] & (1 << 6);
643}
644
645static inline int ata_id_wcache_enabled(const u16 *id)
646{
647 if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
648 return 0;
649 return id[ATA_ID_CFS_ENABLE_1] & (1 << 5);
650}
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665static inline unsigned int ata_id_major_version(const u16 *id)
666{
667 unsigned int mver;
668
669 if (id[ATA_ID_MAJOR_VER] == 0xFFFF)
670 return 0;
671
672 for (mver = 14; mver >= 1; mver--)
673 if (id[ATA_ID_MAJOR_VER] & (1 << mver))
674 break;
675 return mver;
676}
677
678static inline int ata_id_is_sata(const u16 *id)
679{
680
681
682
683
684
685
686 if (id[ATA_ID_HW_CONFIG] == 0 && (short)id[ATA_ID_MAJOR_VER] >= 0x0020)
687 return 1;
688 return 0;
689}
690
691static inline int ata_id_has_tpm(const u16 *id)
692{
693
694 if (ata_id_major_version(id) < 8)
695 return 0;
696 if ((id[48] & 0xC000) != 0x4000)
697 return 0;
698 return id[48] & (1 << 0);
699}
700
701static inline int ata_id_has_dword_io(const u16 *id)
702{
703
704 if (ata_id_major_version(id) > 7)
705 return 0;
706 if (id[ATA_ID_DWORD_IO] & (1 << 0))
707 return 1;
708 return 0;
709}
710
711static inline int ata_id_has_unload(const u16 *id)
712{
713 if (ata_id_major_version(id) >= 7 &&
714 (id[ATA_ID_CFSSE] & 0xC000) == 0x4000 &&
715 id[ATA_ID_CFSSE] & (1 << 13))
716 return 1;
717 return 0;
718}
719
720static inline int ata_id_current_chs_valid(const u16 *id)
721{
722
723
724
725 return (id[ATA_ID_FIELD_VALID] & 1) &&
726 id[ATA_ID_CUR_CYLS] &&
727 id[ATA_ID_CUR_HEADS] &&
728 id[ATA_ID_CUR_HEADS] <= 16 &&
729 id[ATA_ID_CUR_SECTORS];
730}
731
732static inline int ata_id_is_cfa(const u16 *id)
733{
734 if (id[ATA_ID_CONFIG] == 0x848A)
735 return 1;
736
737 if (ata_id_major_version(id) >= 3 &&
738 id[ATA_ID_COMMAND_SET_1] != 0xFFFF &&
739 (id[ATA_ID_COMMAND_SET_1] & (1 << 2)))
740 return 1;
741 return 0;
742}
743
744static inline int ata_id_is_ssd(const u16 *id)
745{
746 return id[ATA_ID_ROT_SPEED] == 0x01;
747}
748
749static inline int ata_drive_40wire(const u16 *dev_id)
750{
751 if (ata_id_is_sata(dev_id))
752 return 0;
753 if ((dev_id[ATA_ID_HW_CONFIG] & 0xE000) == 0x6000)
754 return 0;
755 return 1;
756}
757
758static inline int ata_drive_40wire_relaxed(const u16 *dev_id)
759{
760 if ((dev_id[ATA_ID_HW_CONFIG] & 0x2000) == 0x2000)
761 return 0;
762 return 1;
763}
764
765static inline int atapi_cdb_len(const u16 *dev_id)
766{
767 u16 tmp = dev_id[ATA_ID_CONFIG] & 0x3;
768 switch (tmp) {
769 case 0: return 12;
770 case 1: return 16;
771 default: return -1;
772 }
773}
774
775static inline int atapi_command_packet_set(const u16 *dev_id)
776{
777 return (dev_id[ATA_ID_CONFIG] >> 8) & 0x1f;
778}
779
780static inline int atapi_id_dmadir(const u16 *dev_id)
781{
782 return ata_id_major_version(dev_id) >= 7 && (dev_id[62] & 0x8000);
783}
784
785
786
787
788
789
790
791
792
793static inline int ata_id_is_lba_capacity_ok(u16 *id)
794{
795 unsigned long lba_sects, chs_sects, head, tail;
796
797
798 if (id[ATA_ID_CYLS] == 0)
799 return 1;
800
801 lba_sects = ata_id_u32(id, ATA_ID_LBA_CAPACITY);
802
803
804
805
806
807
808
809 if ((id[ATA_ID_CYLS] == 16383 ||
810 (id[ATA_ID_CYLS] == 4092 && id[ATA_ID_CUR_CYLS] == 16383)) &&
811 id[ATA_ID_SECTORS] == 63 &&
812 (id[ATA_ID_HEADS] == 15 || id[ATA_ID_HEADS] == 16) &&
813 (lba_sects >= 16383 * 63 * id[ATA_ID_HEADS]))
814 return 1;
815
816 chs_sects = id[ATA_ID_CYLS] * id[ATA_ID_HEADS] * id[ATA_ID_SECTORS];
817
818
819 if (lba_sects - chs_sects < chs_sects/10)
820 return 1;
821
822
823 head = (lba_sects >> 16) & 0xffff;
824 tail = lba_sects & 0xffff;
825 lba_sects = head | (tail << 16);
826
827 if (lba_sects - chs_sects < chs_sects/10) {
828 *(__le32 *)&id[ATA_ID_LBA_CAPACITY] = __cpu_to_le32(lba_sects);
829 return 1;
830 }
831
832 return 0;
833}
834
835static inline void ata_id_to_hd_driveid(u16 *id)
836{
837#ifdef __BIG_ENDIAN
838
839 id[ATA_ID_MAX_MULTSECT] = __cpu_to_le16(id[ATA_ID_MAX_MULTSECT]);
840 id[ATA_ID_CAPABILITY] = __cpu_to_le16(id[ATA_ID_CAPABILITY]);
841 id[ATA_ID_OLD_PIO_MODES] = __cpu_to_le16(id[ATA_ID_OLD_PIO_MODES]);
842 id[ATA_ID_OLD_DMA_MODES] = __cpu_to_le16(id[ATA_ID_OLD_DMA_MODES]);
843 id[ATA_ID_MULTSECT] = __cpu_to_le16(id[ATA_ID_MULTSECT]);
844
845
846 *(u32 *)&id[ATA_ID_LBA_CAPACITY] = ata_id_u32(id, ATA_ID_LBA_CAPACITY);
847 *(u32 *)&id[ATA_ID_SPG] = ata_id_u32(id, ATA_ID_SPG);
848
849
850 *(u64 *)&id[ATA_ID_LBA_CAPACITY_2] =
851 ata_id_u64(id, ATA_ID_LBA_CAPACITY_2);
852#endif
853}
854
855static inline int is_multi_taskfile(struct ata_taskfile *tf)
856{
857 return (tf->command == ATA_CMD_READ_MULTI) ||
858 (tf->command == ATA_CMD_WRITE_MULTI) ||
859 (tf->command == ATA_CMD_READ_MULTI_EXT) ||
860 (tf->command == ATA_CMD_WRITE_MULTI_EXT) ||
861 (tf->command == ATA_CMD_WRITE_MULTI_FUA_EXT);
862}
863
864static inline int ata_ok(u8 status)
865{
866 return ((status & (ATA_BUSY | ATA_DRDY | ATA_DF | ATA_DRQ | ATA_ERR))
867 == ATA_DRDY);
868}
869
870static inline int lba_28_ok(u64 block, u32 n_block)
871{
872
873 return ((block + n_block) < ((u64)1 << 28)) && (n_block <= 256);
874}
875
876static inline int lba_48_ok(u64 block, u32 n_block)
877{
878
879 return ((block + n_block - 1) < ((u64)1 << 48)) && (n_block <= 65536);
880}
881
882#define sata_pmp_gscr_vendor(gscr) ((gscr)[SATA_PMP_GSCR_PROD_ID] & 0xffff)
883#define sata_pmp_gscr_devid(gscr) ((gscr)[SATA_PMP_GSCR_PROD_ID] >> 16)
884#define sata_pmp_gscr_rev(gscr) (((gscr)[SATA_PMP_GSCR_REV] >> 8) & 0xff)
885#define sata_pmp_gscr_ports(gscr) ((gscr)[SATA_PMP_GSCR_PORT_INFO] & 0xf)
886
887#endif
888
