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246#include "ixj-ver.h"
247
248#define PERFMON_STATS
249#define IXJDEBUG 0
250#define MAXRINGS 5
251
252#include <linux/module.h>
253
254#include <linux/init.h>
255#include <linux/sched.h>
256#include <linux/kernel.h>
257#include <linux/fs.h>
258#include <linux/errno.h>
259#include <linux/slab.h>
260#include <linux/mm.h>
261#include <linux/ioport.h>
262#include <linux/interrupt.h>
263#include <linux/proc_fs.h>
264#include <linux/poll.h>
265#include <linux/timer.h>
266#include <linux/delay.h>
267#include <linux/pci.h>
268
269#include <asm/io.h>
270#include <asm/uaccess.h>
271
272#include <linux/isapnp.h>
273
274#include "ixj.h"
275
276#define TYPE(inode) (iminor(inode) >> 4)
277#define NUM(inode) (iminor(inode) & 0xf)
278
279static int ixjdebug;
280static int hertz = HZ;
281static int samplerate = 100;
282
283module_param(ixjdebug, int, 0);
284
285static struct pci_device_id ixj_pci_tbl[] __devinitdata = {
286 { PCI_VENDOR_ID_QUICKNET, PCI_DEVICE_ID_QUICKNET_XJ,
287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
288 { }
289};
290
291MODULE_DEVICE_TABLE(pci, ixj_pci_tbl);
292
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310
311#ifdef IXJ_DYN_ALLOC
312
313static IXJ *ixj[IXJMAX];
314#define get_ixj(b) ixj[(b)]
315
316
317
318
319
320static IXJ *ixj_alloc()
321{
322 for(cnt=0; cnt<IXJMAX; cnt++)
323 {
324 if(ixj[cnt] == NULL || !ixj[cnt]->DSPbase)
325 {
326 j = kmalloc(sizeof(IXJ), GFP_KERNEL);
327 if (j == NULL)
328 return NULL;
329 ixj[cnt] = j;
330 return j;
331 }
332 }
333 return NULL;
334}
335
336static void ixj_fsk_free(IXJ *j)
337{
338 kfree(j->fskdata);
339 j->fskdata = NULL;
340}
341
342static void ixj_fsk_alloc(IXJ *j)
343{
344 if(!j->fskdata) {
345 j->fskdata = kmalloc(8000, GFP_KERNEL);
346 if (!j->fskdata) {
347 if(ixjdebug & 0x0200) {
348 printk("IXJ phone%d - allocate failed\n", j->board);
349 }
350 return;
351 } else {
352 j->fsksize = 8000;
353 if(ixjdebug & 0x0200) {
354 printk("IXJ phone%d - allocate succeded\n", j->board);
355 }
356 }
357 }
358}
359
360#else
361
362static IXJ ixj[IXJMAX];
363#define get_ixj(b) (&ixj[(b)])
364
365
366
367
368
369static IXJ *ixj_alloc(void)
370{
371 int cnt;
372 for(cnt=0; cnt<IXJMAX; cnt++) {
373 if(!ixj[cnt].DSPbase)
374 return &ixj[cnt];
375 }
376 return NULL;
377}
378
379static inline void ixj_fsk_free(IXJ *j) {;}
380
381static inline void ixj_fsk_alloc(IXJ *j)
382{
383 j->fsksize = 8000;
384}
385
386#endif
387
388#ifdef PERFMON_STATS
389#define ixj_perfmon(x) ((x)++)
390#else
391#define ixj_perfmon(x) do { } while(0)
392#endif
393
394static int ixj_convert_loaded;
395
396static int ixj_WriteDSPCommand(unsigned short, IXJ *j);
397
398
399
400
401
402
403
404
405static int Stub(IXJ * J, unsigned long arg)
406{
407 return 0;
408}
409
410static IXJ_REGFUNC ixj_PreRead = &Stub;
411static IXJ_REGFUNC ixj_PostRead = &Stub;
412static IXJ_REGFUNC ixj_PreWrite = &Stub;
413static IXJ_REGFUNC ixj_PostWrite = &Stub;
414
415static void ixj_read_frame(IXJ *j);
416static void ixj_write_frame(IXJ *j);
417static void ixj_init_timer(IXJ *j);
418static void ixj_add_timer(IXJ * j);
419static void ixj_timeout(unsigned long ptr);
420static int read_filters(IXJ *j);
421static int LineMonitor(IXJ *j);
422static int ixj_fasync(int fd, struct file *, int mode);
423static int ixj_set_port(IXJ *j, int arg);
424static int ixj_set_pots(IXJ *j, int arg);
425static int ixj_hookstate(IXJ *j);
426static int ixj_record_start(IXJ *j);
427static void ixj_record_stop(IXJ *j);
428static void set_rec_volume(IXJ *j, int volume);
429static int get_rec_volume(IXJ *j);
430static int set_rec_codec(IXJ *j, int rate);
431static void ixj_vad(IXJ *j, int arg);
432static int ixj_play_start(IXJ *j);
433static void ixj_play_stop(IXJ *j);
434static int ixj_set_tone_on(unsigned short arg, IXJ *j);
435static int ixj_set_tone_off(unsigned short, IXJ *j);
436static int ixj_play_tone(IXJ *j, char tone);
437static void ixj_aec_start(IXJ *j, int level);
438static int idle(IXJ *j);
439static void ixj_ring_on(IXJ *j);
440static void ixj_ring_off(IXJ *j);
441static void aec_stop(IXJ *j);
442static void ixj_ringback(IXJ *j);
443static void ixj_busytone(IXJ *j);
444static void ixj_dialtone(IXJ *j);
445static void ixj_cpt_stop(IXJ *j);
446static char daa_int_read(IXJ *j);
447static char daa_CR_read(IXJ *j, int cr);
448static int daa_set_mode(IXJ *j, int mode);
449static int ixj_linetest(IXJ *j);
450static int ixj_daa_write(IXJ *j);
451static int ixj_daa_cid_read(IXJ *j);
452static void DAA_Coeff_US(IXJ *j);
453static void DAA_Coeff_UK(IXJ *j);
454static void DAA_Coeff_France(IXJ *j);
455static void DAA_Coeff_Germany(IXJ *j);
456static void DAA_Coeff_Australia(IXJ *j);
457static void DAA_Coeff_Japan(IXJ *j);
458static int ixj_init_filter(IXJ *j, IXJ_FILTER * jf);
459static int ixj_init_filter_raw(IXJ *j, IXJ_FILTER_RAW * jfr);
460static int ixj_init_tone(IXJ *j, IXJ_TONE * ti);
461static int ixj_build_cadence(IXJ *j, IXJ_CADENCE __user * cp);
462static int ixj_build_filter_cadence(IXJ *j, IXJ_FILTER_CADENCE __user * cp);
463
464static int SCI_Control(IXJ *j, int control);
465static int SCI_Prepare(IXJ *j);
466static int SCI_WaitHighSCI(IXJ *j);
467static int SCI_WaitLowSCI(IXJ *j);
468static DWORD PCIEE_GetSerialNumber(WORD wAddress);
469static int ixj_PCcontrol_wait(IXJ *j);
470static void ixj_pre_cid(IXJ *j);
471static void ixj_write_cid(IXJ *j);
472static void ixj_write_cid_bit(IXJ *j, int bit);
473static int set_base_frame(IXJ *j, int size);
474static int set_play_codec(IXJ *j, int rate);
475static void set_rec_depth(IXJ *j, int depth);
476static int ixj_mixer(long val, IXJ *j);
477
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491
492static inline void ixj_read_HSR(IXJ *j)
493{
494 j->hsr.bytes.low = inb_p(j->DSPbase + 8);
495 j->hsr.bytes.high = inb_p(j->DSPbase + 9);
496}
497
498static inline int IsControlReady(IXJ *j)
499{
500 ixj_read_HSR(j);
501 return j->hsr.bits.controlrdy ? 1 : 0;
502}
503
504static inline int IsPCControlReady(IXJ *j)
505{
506 j->pccr1.byte = inb_p(j->XILINXbase + 3);
507 return j->pccr1.bits.crr ? 1 : 0;
508}
509
510static inline int IsStatusReady(IXJ *j)
511{
512 ixj_read_HSR(j);
513 return j->hsr.bits.statusrdy ? 1 : 0;
514}
515
516static inline int IsRxReady(IXJ *j)
517{
518 ixj_read_HSR(j);
519 ixj_perfmon(j->rxreadycheck);
520 return j->hsr.bits.rxrdy ? 1 : 0;
521}
522
523static inline int IsTxReady(IXJ *j)
524{
525 ixj_read_HSR(j);
526 ixj_perfmon(j->txreadycheck);
527 return j->hsr.bits.txrdy ? 1 : 0;
528}
529
530static inline void set_play_volume(IXJ *j, int volume)
531{
532 if (ixjdebug & 0x0002)
533 printk(KERN_INFO "IXJ: /dev/phone%d Setting Play Volume to 0x%4.4x\n", j->board, volume);
534 ixj_WriteDSPCommand(0xCF02, j);
535 ixj_WriteDSPCommand(volume, j);
536}
537
538static int set_play_volume_linear(IXJ *j, int volume)
539{
540 int newvolume, dspplaymax;
541
542 if (ixjdebug & 0x0002)
543 printk(KERN_INFO "IXJ: /dev/phone %d Setting Linear Play Volume to 0x%4.4x\n", j->board, volume);
544 if(volume > 100 || volume < 0) {
545 return -1;
546 }
547
548
549 switch (j->cardtype) {
550 case QTI_PHONEJACK:
551 dspplaymax = 0x380;
552 break;
553 case QTI_LINEJACK:
554 if(j->port == PORT_PSTN) {
555 dspplaymax = 0x48;
556 } else {
557 dspplaymax = 0x100;
558 }
559 break;
560 case QTI_PHONEJACK_LITE:
561 dspplaymax = 0x380;
562 break;
563 case QTI_PHONEJACK_PCI:
564 dspplaymax = 0x6C;
565 break;
566 case QTI_PHONECARD:
567 dspplaymax = 0x50;
568 break;
569 default:
570 return -1;
571 }
572 newvolume = (dspplaymax * volume) / 100;
573 set_play_volume(j, newvolume);
574 return 0;
575}
576
577static inline void set_play_depth(IXJ *j, int depth)
578{
579 if (depth > 60)
580 depth = 60;
581 if (depth < 0)
582 depth = 0;
583 ixj_WriteDSPCommand(0x5280 + depth, j);
584}
585
586static inline int get_play_volume(IXJ *j)
587{
588 ixj_WriteDSPCommand(0xCF00, j);
589 return j->ssr.high << 8 | j->ssr.low;
590}
591
592static int get_play_volume_linear(IXJ *j)
593{
594 int volume, newvolume, dspplaymax;
595
596
597 switch (j->cardtype) {
598 case QTI_PHONEJACK:
599 dspplaymax = 0x380;
600 break;
601 case QTI_LINEJACK:
602 if(j->port == PORT_PSTN) {
603 dspplaymax = 0x48;
604 } else {
605 dspplaymax = 0x100;
606 }
607 break;
608 case QTI_PHONEJACK_LITE:
609 dspplaymax = 0x380;
610 break;
611 case QTI_PHONEJACK_PCI:
612 dspplaymax = 0x6C;
613 break;
614 case QTI_PHONECARD:
615 dspplaymax = 100;
616 break;
617 default:
618 return -1;
619 }
620 volume = get_play_volume(j);
621 newvolume = (volume * 100) / dspplaymax;
622 if(newvolume > 100)
623 newvolume = 100;
624 return newvolume;
625}
626
627static inline BYTE SLIC_GetState(IXJ *j)
628{
629 if (j->cardtype == QTI_PHONECARD) {
630 j->pccr1.byte = 0;
631 j->psccr.bits.dev = 3;
632 j->psccr.bits.rw = 1;
633 outw_p(j->psccr.byte << 8, j->XILINXbase + 0x00);
634 ixj_PCcontrol_wait(j);
635 j->pslic.byte = inw_p(j->XILINXbase + 0x00) & 0xFF;
636 ixj_PCcontrol_wait(j);
637 if (j->pslic.bits.powerdown)
638 return PLD_SLIC_STATE_OC;
639 else if (!j->pslic.bits.ring0 && !j->pslic.bits.ring1)
640 return PLD_SLIC_STATE_ACTIVE;
641 else
642 return PLD_SLIC_STATE_RINGING;
643 } else {
644 j->pld_slicr.byte = inb_p(j->XILINXbase + 0x01);
645 }
646 return j->pld_slicr.bits.state;
647}
648
649static bool SLIC_SetState(BYTE byState, IXJ *j)
650{
651 bool fRetVal = false;
652
653 if (j->cardtype == QTI_PHONECARD) {
654 if (j->flags.pcmciasct) {
655 switch (byState) {
656 case PLD_SLIC_STATE_TIPOPEN:
657 case PLD_SLIC_STATE_OC:
658 j->pslic.bits.powerdown = 1;
659 j->pslic.bits.ring0 = j->pslic.bits.ring1 = 0;
660 fRetVal = true;
661 break;
662 case PLD_SLIC_STATE_RINGING:
663 if (j->readers || j->writers) {
664 j->pslic.bits.powerdown = 0;
665 j->pslic.bits.ring0 = 1;
666 j->pslic.bits.ring1 = 0;
667 fRetVal = true;
668 }
669 break;
670 case PLD_SLIC_STATE_OHT:
671
672 case PLD_SLIC_STATE_STANDBY:
673 case PLD_SLIC_STATE_ACTIVE:
674 if (j->readers || j->writers) {
675 j->pslic.bits.powerdown = 0;
676 } else {
677 j->pslic.bits.powerdown = 1;
678 }
679 j->pslic.bits.ring0 = j->pslic.bits.ring1 = 0;
680 fRetVal = true;
681 break;
682 case PLD_SLIC_STATE_APR:
683
684 case PLD_SLIC_STATE_OHTPR:
685
686 default:
687 fRetVal = false;
688 break;
689 }
690 j->psccr.bits.dev = 3;
691 j->psccr.bits.rw = 0;
692 outw_p(j->psccr.byte << 8 | j->pslic.byte, j->XILINXbase + 0x00);
693 ixj_PCcontrol_wait(j);
694 }
695 } else {
696
697 switch (byState) {
698 case PLD_SLIC_STATE_OC:
699 j->pld_slicw.bits.c1 = 0;
700 j->pld_slicw.bits.c2 = 0;
701 j->pld_slicw.bits.c3 = 0;
702 j->pld_slicw.bits.b2en = 0;
703 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
704 fRetVal = true;
705 break;
706 case PLD_SLIC_STATE_RINGING:
707 j->pld_slicw.bits.c1 = 1;
708 j->pld_slicw.bits.c2 = 0;
709 j->pld_slicw.bits.c3 = 0;
710 j->pld_slicw.bits.b2en = 1;
711 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
712 fRetVal = true;
713 break;
714 case PLD_SLIC_STATE_ACTIVE:
715 j->pld_slicw.bits.c1 = 0;
716 j->pld_slicw.bits.c2 = 1;
717 j->pld_slicw.bits.c3 = 0;
718 j->pld_slicw.bits.b2en = 0;
719 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
720 fRetVal = true;
721 break;
722 case PLD_SLIC_STATE_OHT:
723
724 j->pld_slicw.bits.c1 = 1;
725 j->pld_slicw.bits.c2 = 1;
726 j->pld_slicw.bits.c3 = 0;
727 j->pld_slicw.bits.b2en = 0;
728 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
729 fRetVal = true;
730 break;
731 case PLD_SLIC_STATE_TIPOPEN:
732 j->pld_slicw.bits.c1 = 0;
733 j->pld_slicw.bits.c2 = 0;
734 j->pld_slicw.bits.c3 = 1;
735 j->pld_slicw.bits.b2en = 0;
736 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
737 fRetVal = true;
738 break;
739 case PLD_SLIC_STATE_STANDBY:
740 j->pld_slicw.bits.c1 = 1;
741 j->pld_slicw.bits.c2 = 0;
742 j->pld_slicw.bits.c3 = 1;
743 j->pld_slicw.bits.b2en = 1;
744 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
745 fRetVal = true;
746 break;
747 case PLD_SLIC_STATE_APR:
748
749 j->pld_slicw.bits.c1 = 0;
750 j->pld_slicw.bits.c2 = 1;
751 j->pld_slicw.bits.c3 = 1;
752 j->pld_slicw.bits.b2en = 0;
753 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
754 fRetVal = true;
755 break;
756 case PLD_SLIC_STATE_OHTPR:
757
758 j->pld_slicw.bits.c1 = 1;
759 j->pld_slicw.bits.c2 = 1;
760 j->pld_slicw.bits.c3 = 1;
761 j->pld_slicw.bits.b2en = 0;
762 outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
763 fRetVal = true;
764 break;
765 default:
766 fRetVal = false;
767 break;
768 }
769 }
770
771 return fRetVal;
772}
773
774static int ixj_wink(IXJ *j)
775{
776 BYTE slicnow;
777
778 slicnow = SLIC_GetState(j);
779
780 j->pots_winkstart = jiffies;
781 SLIC_SetState(PLD_SLIC_STATE_OC, j);
782
783 msleep(jiffies_to_msecs(j->winktime));
784
785 SLIC_SetState(slicnow, j);
786 return 0;
787}
788
789static void ixj_init_timer(IXJ *j)
790{
791 init_timer(&j->timer);
792 j->timer.function = ixj_timeout;
793 j->timer.data = (unsigned long)j;
794}
795
796static void ixj_add_timer(IXJ *j)
797{
798 j->timer.expires = jiffies + (hertz / samplerate);
799 add_timer(&j->timer);
800}
801
802static void ixj_tone_timeout(IXJ *j)
803{
804 IXJ_TONE ti;
805
806 j->tone_state++;
807 if (j->tone_state == 3) {
808 j->tone_state = 0;
809 if (j->cadence_t) {
810 j->tone_cadence_state++;
811 if (j->tone_cadence_state >= j->cadence_t->elements_used) {
812 switch (j->cadence_t->termination) {
813 case PLAY_ONCE:
814 ixj_cpt_stop(j);
815 break;
816 case REPEAT_LAST_ELEMENT:
817 j->tone_cadence_state--;
818 ixj_play_tone(j, j->cadence_t->ce[j->tone_cadence_state].index);
819 break;
820 case REPEAT_ALL:
821 j->tone_cadence_state = 0;
822 if (j->cadence_t->ce[j->tone_cadence_state].freq0) {
823 ti.tone_index = j->cadence_t->ce[j->tone_cadence_state].index;
824 ti.freq0 = j->cadence_t->ce[j->tone_cadence_state].freq0;
825 ti.gain0 = j->cadence_t->ce[j->tone_cadence_state].gain0;
826 ti.freq1 = j->cadence_t->ce[j->tone_cadence_state].freq1;
827 ti.gain1 = j->cadence_t->ce[j->tone_cadence_state].gain1;
828 ixj_init_tone(j, &ti);
829 }
830 ixj_set_tone_on(j->cadence_t->ce[0].tone_on_time, j);
831 ixj_set_tone_off(j->cadence_t->ce[0].tone_off_time, j);
832 ixj_play_tone(j, j->cadence_t->ce[0].index);
833 break;
834 }
835 } else {
836 if (j->cadence_t->ce[j->tone_cadence_state].gain0) {
837 ti.tone_index = j->cadence_t->ce[j->tone_cadence_state].index;
838 ti.freq0 = j->cadence_t->ce[j->tone_cadence_state].freq0;
839 ti.gain0 = j->cadence_t->ce[j->tone_cadence_state].gain0;
840 ti.freq1 = j->cadence_t->ce[j->tone_cadence_state].freq1;
841 ti.gain1 = j->cadence_t->ce[j->tone_cadence_state].gain1;
842 ixj_init_tone(j, &ti);
843 }
844 ixj_set_tone_on(j->cadence_t->ce[j->tone_cadence_state].tone_on_time, j);
845 ixj_set_tone_off(j->cadence_t->ce[j->tone_cadence_state].tone_off_time, j);
846 ixj_play_tone(j, j->cadence_t->ce[j->tone_cadence_state].index);
847 }
848 }
849 }
850}
851
852static inline void ixj_kill_fasync(IXJ *j, IXJ_SIGEVENT event, int dir)
853{
854 if(j->ixj_signals[event]) {
855 if(ixjdebug & 0x0100)
856 printk("Sending signal for event %d\n", event);
857
858
859 kill_fasync(&(j->async_queue), j->ixj_signals[event], dir);
860 }
861}
862
863static void ixj_pstn_state(IXJ *j)
864{
865 int var;
866 union XOPXR0 XR0, daaint;
867
868 var = 10;
869
870 XR0.reg = j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.reg;
871 daaint.reg = 0;
872 XR0.bitreg.RMR = j->m_DAAShadowRegs.SOP_REGS.SOP.cr1.bitreg.RMR;
873
874 j->pld_scrr.byte = inb_p(j->XILINXbase);
875 if (j->pld_scrr.bits.daaflag) {
876 daa_int_read(j);
877 if(j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.RING) {
878 if(time_after(jiffies, j->pstn_sleeptil) && !(j->flags.pots_pstn && j->hookstate)) {
879 daaint.bitreg.RING = 1;
880 if(ixjdebug & 0x0008) {
881 printk(KERN_INFO "IXJ DAA Ring Interrupt /dev/phone%d at %ld\n", j->board, jiffies);
882 }
883 } else {
884 daa_set_mode(j, SOP_PU_RESET);
885 }
886 }
887 if(j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.Caller_ID) {
888 daaint.bitreg.Caller_ID = 1;
889 j->pstn_cid_intr = 1;
890 j->pstn_cid_received = jiffies;
891 if(ixjdebug & 0x0008) {
892 printk(KERN_INFO "IXJ DAA Caller_ID Interrupt /dev/phone%d at %ld\n", j->board, jiffies);
893 }
894 }
895 if(j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.Cadence) {
896 daaint.bitreg.Cadence = 1;
897 if(ixjdebug & 0x0008) {
898 printk(KERN_INFO "IXJ DAA Cadence Interrupt /dev/phone%d at %ld\n", j->board, jiffies);
899 }
900 }
901 if(j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.VDD_OK != XR0.bitreg.VDD_OK) {
902 daaint.bitreg.VDD_OK = 1;
903 daaint.bitreg.SI_0 = j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.VDD_OK;
904 }
905 }
906 daa_CR_read(j, 1);
907 if(j->m_DAAShadowRegs.SOP_REGS.SOP.cr1.bitreg.RMR != XR0.bitreg.RMR && time_after(jiffies, j->pstn_sleeptil) && !(j->flags.pots_pstn && j->hookstate)) {
908 daaint.bitreg.RMR = 1;
909 daaint.bitreg.SI_1 = j->m_DAAShadowRegs.SOP_REGS.SOP.cr1.bitreg.RMR;
910 if(ixjdebug & 0x0008) {
911 printk(KERN_INFO "IXJ DAA RMR /dev/phone%d was %s for %ld\n", j->board, XR0.bitreg.RMR?"on":"off", jiffies - j->pstn_last_rmr);
912 }
913 j->pstn_prev_rmr = j->pstn_last_rmr;
914 j->pstn_last_rmr = jiffies;
915 }
916 switch(j->daa_mode) {
917 case SOP_PU_SLEEP:
918 if (daaint.bitreg.RING) {
919 if (!j->flags.pstn_ringing) {
920 if (j->daa_mode != SOP_PU_RINGING) {
921 j->pstn_ring_int = jiffies;
922 daa_set_mode(j, SOP_PU_RINGING);
923 }
924 }
925 }
926 break;
927 case SOP_PU_RINGING:
928 if (daaint.bitreg.RMR) {
929 if (ixjdebug & 0x0008) {
930 printk(KERN_INFO "IXJ Ring Cadence a state = %d /dev/phone%d at %ld\n", j->cadence_f[4].state, j->board, jiffies);
931 }
932 if (daaint.bitreg.SI_1) {
933 j->flags.pstn_rmr = 1;
934 j->pstn_ring_start = jiffies;
935 j->pstn_ring_stop = 0;
936 j->ex.bits.pstn_ring = 0;
937 if (j->cadence_f[4].state == 0) {
938 j->cadence_f[4].state = 1;
939 j->cadence_f[4].on1min = jiffies + (long)((j->cadence_f[4].on1 * hertz * (100 - var)) / 10000);
940 j->cadence_f[4].on1dot = jiffies + (long)((j->cadence_f[4].on1 * hertz * (100)) / 10000);
941 j->cadence_f[4].on1max = jiffies + (long)((j->cadence_f[4].on1 * hertz * (100 + var)) / 10000);
942 } else if (j->cadence_f[4].state == 2) {
943 if((time_after(jiffies, j->cadence_f[4].off1min) &&
944 time_before(jiffies, j->cadence_f[4].off1max))) {
945 if (j->cadence_f[4].on2) {
946 j->cadence_f[4].state = 3;
947 j->cadence_f[4].on2min = jiffies + (long)((j->cadence_f[4].on2 * (hertz * (100 - var)) / 10000));
948 j->cadence_f[4].on2dot = jiffies + (long)((j->cadence_f[4].on2 * (hertz * (100)) / 10000));
949 j->cadence_f[4].on2max = jiffies + (long)((j->cadence_f[4].on2 * (hertz * (100 + var)) / 10000));
950 } else {
951 j->cadence_f[4].state = 7;
952 }
953 } else {
954 if (ixjdebug & 0x0008) {
955 printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
956 j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
957 j->cadence_f[4].off1);
958 }
959 j->cadence_f[4].state = 0;
960 }
961 } else if (j->cadence_f[4].state == 4) {
962 if((time_after(jiffies, j->cadence_f[4].off2min) &&
963 time_before(jiffies, j->cadence_f[4].off2max))) {
964 if (j->cadence_f[4].on3) {
965 j->cadence_f[4].state = 5;
966 j->cadence_f[4].on3min = jiffies + (long)((j->cadence_f[4].on3 * (hertz * (100 - var)) / 10000));
967 j->cadence_f[4].on3dot = jiffies + (long)((j->cadence_f[4].on3 * (hertz * (100)) / 10000));
968 j->cadence_f[4].on3max = jiffies + (long)((j->cadence_f[4].on3 * (hertz * (100 + var)) / 10000));
969 } else {
970 j->cadence_f[4].state = 7;
971 }
972 } else {
973 if (ixjdebug & 0x0008) {
974 printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
975 j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
976 j->cadence_f[4].off2);
977 }
978 j->cadence_f[4].state = 0;
979 }
980 } else if (j->cadence_f[4].state == 6) {
981 if((time_after(jiffies, j->cadence_f[4].off3min) &&
982 time_before(jiffies, j->cadence_f[4].off3max))) {
983 j->cadence_f[4].state = 7;
984 } else {
985 if (ixjdebug & 0x0008) {
986 printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
987 j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
988 j->cadence_f[4].off3);
989 }
990 j->cadence_f[4].state = 0;
991 }
992 } else {
993 j->cadence_f[4].state = 0;
994 }
995 } else {
996 j->pstn_ring_start = 0;
997 j->pstn_ring_stop = jiffies;
998 if (j->cadence_f[4].state == 1) {
999 if(!j->cadence_f[4].on1) {
1000 j->cadence_f[4].state = 7;
1001 } else if((time_after(jiffies, j->cadence_f[4].on1min) &&
1002 time_before(jiffies, j->cadence_f[4].on1max))) {
1003 if (j->cadence_f[4].off1) {
1004 j->cadence_f[4].state = 2;
1005 j->cadence_f[4].off1min = jiffies + (long)((j->cadence_f[4].off1 * (hertz * (100 - var)) / 10000));
1006 j->cadence_f[4].off1dot = jiffies + (long)((j->cadence_f[4].off1 * (hertz * (100)) / 10000));
1007 j->cadence_f[4].off1max = jiffies + (long)((j->cadence_f[4].off1 * (hertz * (100 + var)) / 10000));
1008 } else {
1009 j->cadence_f[4].state = 7;
1010 }
1011 } else {
1012 if (ixjdebug & 0x0008) {
1013 printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
1014 j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
1015 j->cadence_f[4].on1);
1016 }
1017 j->cadence_f[4].state = 0;
1018 }
1019 } else if (j->cadence_f[4].state == 3) {
1020 if((time_after(jiffies, j->cadence_f[4].on2min) &&
1021 time_before(jiffies, j->cadence_f[4].on2max))) {
1022 if (j->cadence_f[4].off2) {
1023 j->cadence_f[4].state = 4;
1024 j->cadence_f[4].off2min = jiffies + (long)((j->cadence_f[4].off2 * (hertz * (100 - var)) / 10000));
1025 j->cadence_f[4].off2dot = jiffies + (long)((j->cadence_f[4].off2 * (hertz * (100)) / 10000));
1026 j->cadence_f[4].off2max = jiffies + (long)((j->cadence_f[4].off2 * (hertz * (100 + var)) / 10000));
1027 } else {
1028 j->cadence_f[4].state = 7;
1029 }
1030 } else {
1031 if (ixjdebug & 0x0008) {
1032 printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
1033 j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
1034 j->cadence_f[4].on2);
1035 }
1036 j->cadence_f[4].state = 0;
1037 }
1038 } else if (j->cadence_f[4].state == 5) {
1039 if((time_after(jiffies, j->cadence_f[4].on3min) &&
1040 time_before(jiffies, j->cadence_f[4].on3max))) {
1041 if (j->cadence_f[4].off3) {
1042 j->cadence_f[4].state = 6;
1043 j->cadence_f[4].off3min = jiffies + (long)((j->cadence_f[4].off3 * (hertz * (100 - var)) / 10000));
1044 j->cadence_f[4].off3dot = jiffies + (long)((j->cadence_f[4].off3 * (hertz * (100)) / 10000));
1045 j->cadence_f[4].off3max = jiffies + (long)((j->cadence_f[4].off3 * (hertz * (100 + var)) / 10000));
1046 } else {
1047 j->cadence_f[4].state = 7;
1048 }
1049 } else {
1050 j->cadence_f[4].state = 0;
1051 }
1052 } else {
1053 if (ixjdebug & 0x0008) {
1054 printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
1055 j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
1056 j->cadence_f[4].on3);
1057 }
1058 j->cadence_f[4].state = 0;
1059 }
1060 }
1061 if (ixjdebug & 0x0010) {
1062 printk(KERN_INFO "IXJ Ring Cadence b state = %d /dev/phone%d at %ld\n", j->cadence_f[4].state, j->board, jiffies);
1063 }
1064 if (ixjdebug & 0x0010) {
1065 switch(j->cadence_f[4].state) {
1066 case 1:
1067 printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1068 j->cadence_f[4].on1, j->cadence_f[4].on1min, j->cadence_f[4].on1dot, j->cadence_f[4].on1max);
1069 break;
1070 case 2:
1071 printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1072 j->cadence_f[4].off1, j->cadence_f[4].off1min, j->cadence_f[4].off1dot, j->cadence_f[4].off1max);
1073 break;
1074 case 3:
1075 printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1076 j->cadence_f[4].on2, j->cadence_f[4].on2min, j->cadence_f[4].on2dot, j->cadence_f[4].on2max);
1077 break;
1078 case 4:
1079 printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1080 j->cadence_f[4].off2, j->cadence_f[4].off2min, j->cadence_f[4].off2dot, j->cadence_f[4].off2max);
1081 break;
1082 case 5:
1083 printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1084 j->cadence_f[4].on3, j->cadence_f[4].on3min, j->cadence_f[4].on3dot, j->cadence_f[4].on3max);
1085 break;
1086 case 6:
1087 printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1088 j->cadence_f[4].off3, j->cadence_f[4].off3min, j->cadence_f[4].off3dot, j->cadence_f[4].off3max);
1089 break;
1090 }
1091 }
1092 }
1093 if (j->cadence_f[4].state == 7) {
1094 j->cadence_f[4].state = 0;
1095 j->pstn_ring_stop = jiffies;
1096 j->ex.bits.pstn_ring = 1;
1097 ixj_kill_fasync(j, SIG_PSTN_RING, POLL_IN);
1098 if(ixjdebug & 0x0008) {
1099 printk(KERN_INFO "IXJ Ring int set /dev/phone%d at %ld\n", j->board, jiffies);
1100 }
1101 }
1102 if((j->pstn_ring_int != 0 && time_after(jiffies, j->pstn_ring_int + (hertz * 5)) && !j->flags.pstn_rmr) ||
1103 (j->pstn_ring_stop != 0 && time_after(jiffies, j->pstn_ring_stop + (hertz * 5)))) {
1104 if(ixjdebug & 0x0008) {
1105 printk("IXJ DAA no ring in 5 seconds /dev/phone%d at %ld\n", j->board, jiffies);
1106 printk("IXJ DAA pstn ring int /dev/phone%d at %ld\n", j->board, j->pstn_ring_int);
1107 printk("IXJ DAA pstn ring stop /dev/phone%d at %ld\n", j->board, j->pstn_ring_stop);
1108 }
1109 j->pstn_ring_stop = j->pstn_ring_int = 0;
1110 daa_set_mode(j, SOP_PU_SLEEP);
1111 }
1112 outb_p(j->pld_scrw.byte, j->XILINXbase);
1113 if (j->pstn_cid_intr && time_after(jiffies, j->pstn_cid_received + hertz)) {
1114 ixj_daa_cid_read(j);
1115 j->ex.bits.caller_id = 1;
1116 ixj_kill_fasync(j, SIG_CALLER_ID, POLL_IN);
1117 j->pstn_cid_intr = 0;
1118 }
1119 if (daaint.bitreg.Cadence) {
1120 if(ixjdebug & 0x0008) {
1121 printk("IXJ DAA Cadence interrupt going to sleep /dev/phone%d\n", j->board);
1122 }
1123 daa_set_mode(j, SOP_PU_SLEEP);
1124 j->ex.bits.pstn_ring = 0;
1125 }
1126 break;
1127 case SOP_PU_CONVERSATION:
1128 if (daaint.bitreg.VDD_OK) {
1129 if(!daaint.bitreg.SI_0) {
1130 if (!j->pstn_winkstart) {
1131 if(ixjdebug & 0x0008) {
1132 printk("IXJ DAA possible wink /dev/phone%d %ld\n", j->board, jiffies);
1133 }
1134 j->pstn_winkstart = jiffies;
1135 }
1136 } else {
1137 if (j->pstn_winkstart) {
1138 if(ixjdebug & 0x0008) {
1139 printk("IXJ DAA possible wink end /dev/phone%d %ld\n", j->board, jiffies);
1140 }
1141 j->pstn_winkstart = 0;
1142 }
1143 }
1144 }
1145 if (j->pstn_winkstart && time_after(jiffies, j->pstn_winkstart + ((hertz * j->winktime) / 1000))) {
1146 if(ixjdebug & 0x0008) {
1147 printk("IXJ DAA wink detected going to sleep /dev/phone%d %ld\n", j->board, jiffies);
1148 }
1149 daa_set_mode(j, SOP_PU_SLEEP);
1150 j->pstn_winkstart = 0;
1151 j->ex.bits.pstn_wink = 1;
1152 ixj_kill_fasync(j, SIG_PSTN_WINK, POLL_IN);
1153 }
1154 break;
1155 }
1156}
1157
1158static void ixj_timeout(unsigned long ptr)
1159{
1160 int board;
1161 unsigned long jifon;
1162 IXJ *j = (IXJ *)ptr;
1163 board = j->board;
1164
1165 if (j->DSPbase && atomic_read(&j->DSPWrite) == 0 && test_and_set_bit(board, (void *)&j->busyflags) == 0) {
1166 ixj_perfmon(j->timerchecks);
1167 j->hookstate = ixj_hookstate(j);
1168 if (j->tone_state) {
1169 if (!(j->hookstate)) {
1170 ixj_cpt_stop(j);
1171 if (j->m_hook) {
1172 j->m_hook = 0;
1173 j->ex.bits.hookstate = 1;
1174 ixj_kill_fasync(j, SIG_HOOKSTATE, POLL_IN);
1175 }
1176 clear_bit(board, &j->busyflags);
1177 ixj_add_timer(j);
1178 return;
1179 }
1180 if (j->tone_state == 1)
1181 jifon = ((hertz * j->tone_on_time) * 25 / 100000);
1182 else
1183 jifon = ((hertz * j->tone_on_time) * 25 / 100000) + ((hertz * j->tone_off_time) * 25 / 100000);
1184 if (time_before(jiffies, j->tone_start_jif + jifon)) {
1185 if (j->tone_state == 1) {
1186 ixj_play_tone(j, j->tone_index);
1187 if (j->dsp.low == 0x20) {
1188 clear_bit(board, &j->busyflags);
1189 ixj_add_timer(j);
1190 return;
1191 }
1192 } else {
1193 ixj_play_tone(j, 0);
1194 if (j->dsp.low == 0x20) {
1195 clear_bit(board, &j->busyflags);
1196 ixj_add_timer(j);
1197 return;
1198 }
1199 }
1200 } else {
1201 ixj_tone_timeout(j);
1202 if (j->flags.dialtone) {
1203 ixj_dialtone(j);
1204 }
1205 if (j->flags.busytone) {
1206 ixj_busytone(j);
1207 if (j->dsp.low == 0x20) {
1208 clear_bit(board, &j->busyflags);
1209 ixj_add_timer(j);
1210 return;
1211 }
1212 }
1213 if (j->flags.ringback) {
1214 ixj_ringback(j);
1215 if (j->dsp.low == 0x20) {
1216 clear_bit(board, &j->busyflags);
1217 ixj_add_timer(j);
1218 return;
1219 }
1220 }
1221 if (!j->tone_state) {
1222 ixj_cpt_stop(j);
1223 }
1224 }
1225 }
1226 if (!(j->tone_state && j->dsp.low == 0x20)) {
1227 if (IsRxReady(j)) {
1228 ixj_read_frame(j);
1229 }
1230 if (IsTxReady(j)) {
1231 ixj_write_frame(j);
1232 }
1233 }
1234 if (j->flags.cringing) {
1235 if (j->hookstate & 1) {
1236 j->flags.cringing = 0;
1237 ixj_ring_off(j);
1238 } else if(j->cadence_f[5].enable && ((!j->cadence_f[5].en_filter) || (j->cadence_f[5].en_filter && j->flags.firstring))) {
1239 switch(j->cadence_f[5].state) {
1240 case 0:
1241 j->cadence_f[5].on1dot = jiffies + (long)((j->cadence_f[5].on1 * (hertz * 100) / 10000));
1242 if (time_before(jiffies, j->cadence_f[5].on1dot)) {
1243 if(ixjdebug & 0x0004) {
1244 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1245 }
1246 ixj_ring_on(j);
1247 }
1248 j->cadence_f[5].state = 1;
1249 break;
1250 case 1:
1251 if (time_after(jiffies, j->cadence_f[5].on1dot)) {
1252 j->cadence_f[5].off1dot = jiffies + (long)((j->cadence_f[5].off1 * (hertz * 100) / 10000));
1253 if(ixjdebug & 0x0004) {
1254 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1255 }
1256 ixj_ring_off(j);
1257 j->cadence_f[5].state = 2;
1258 }
1259 break;
1260 case 2:
1261 if (time_after(jiffies, j->cadence_f[5].off1dot)) {
1262 if(ixjdebug & 0x0004) {
1263 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1264 }
1265 ixj_ring_on(j);
1266 if (j->cadence_f[5].on2) {
1267 j->cadence_f[5].on2dot = jiffies + (long)((j->cadence_f[5].on2 * (hertz * 100) / 10000));
1268 j->cadence_f[5].state = 3;
1269 } else {
1270 j->cadence_f[5].state = 7;
1271 }
1272 }
1273 break;
1274 case 3:
1275 if (time_after(jiffies, j->cadence_f[5].on2dot)) {
1276 if(ixjdebug & 0x0004) {
1277 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1278 }
1279 ixj_ring_off(j);
1280 if (j->cadence_f[5].off2) {
1281 j->cadence_f[5].off2dot = jiffies + (long)((j->cadence_f[5].off2 * (hertz * 100) / 10000));
1282 j->cadence_f[5].state = 4;
1283 } else {
1284 j->cadence_f[5].state = 7;
1285 }
1286 }
1287 break;
1288 case 4:
1289 if (time_after(jiffies, j->cadence_f[5].off2dot)) {
1290 if(ixjdebug & 0x0004) {
1291 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1292 }
1293 ixj_ring_on(j);
1294 if (j->cadence_f[5].on3) {
1295 j->cadence_f[5].on3dot = jiffies + (long)((j->cadence_f[5].on3 * (hertz * 100) / 10000));
1296 j->cadence_f[5].state = 5;
1297 } else {
1298 j->cadence_f[5].state = 7;
1299 }
1300 }
1301 break;
1302 case 5:
1303 if (time_after(jiffies, j->cadence_f[5].on3dot)) {
1304 if(ixjdebug & 0x0004) {
1305 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1306 }
1307 ixj_ring_off(j);
1308 if (j->cadence_f[5].off3) {
1309 j->cadence_f[5].off3dot = jiffies + (long)((j->cadence_f[5].off3 * (hertz * 100) / 10000));
1310 j->cadence_f[5].state = 6;
1311 } else {
1312 j->cadence_f[5].state = 7;
1313 }
1314 }
1315 break;
1316 case 6:
1317 if (time_after(jiffies, j->cadence_f[5].off3dot)) {
1318 if(ixjdebug & 0x0004) {
1319 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1320 }
1321 j->cadence_f[5].state = 7;
1322 }
1323 break;
1324 case 7:
1325 if(ixjdebug & 0x0004) {
1326 printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1327 }
1328 j->flags.cidring = 1;
1329 j->cadence_f[5].state = 0;
1330 break;
1331 }
1332 if (j->flags.cidring && !j->flags.cidsent) {
1333 j->flags.cidsent = 1;
1334 if(j->fskdcnt) {
1335 SLIC_SetState(PLD_SLIC_STATE_OHT, j);
1336 ixj_pre_cid(j);
1337 }
1338 j->flags.cidring = 0;
1339 }
1340 clear_bit(board, &j->busyflags);
1341 ixj_add_timer(j);
1342 return;
1343 } else {
1344 if (time_after(jiffies, j->ring_cadence_jif + (hertz / 2))) {
1345 if (j->flags.cidring && !j->flags.cidsent) {
1346 j->flags.cidsent = 1;
1347 if(j->fskdcnt) {
1348 SLIC_SetState(PLD_SLIC_STATE_OHT, j);
1349 ixj_pre_cid(j);
1350 }
1351 j->flags.cidring = 0;
1352 }
1353 j->ring_cadence_t--;
1354 if (j->ring_cadence_t == -1)
1355 j->ring_cadence_t = 15;
1356 j->ring_cadence_jif = jiffies;
1357
1358 if (j->ring_cadence & 1 << j->ring_cadence_t) {
1359 if(j->flags.cidsent && j->cadence_f[5].en_filter)
1360 j->flags.firstring = 1;
1361 else
1362 ixj_ring_on(j);
1363 } else {
1364 ixj_ring_off(j);
1365 if(!j->flags.cidsent)
1366 j->flags.cidring = 1;
1367 }
1368 }
1369 clear_bit(board, &j->busyflags);
1370 ixj_add_timer(j);
1371 return;
1372 }
1373 }
1374 if (!j->flags.ringing) {
1375 if (j->hookstate) {
1376 if (j->dsp.low != 0x20 &&
1377 SLIC_GetState(j) != PLD_SLIC_STATE_ACTIVE) {
1378 SLIC_SetState(PLD_SLIC_STATE_ACTIVE, j);
1379 }
1380 LineMonitor(j);
1381 read_filters(j);
1382 ixj_WriteDSPCommand(0x511B, j);
1383 j->proc_load = j->ssr.high << 8 | j->ssr.low;
1384 if (!j->m_hook && (j->hookstate & 1)) {
1385 j->m_hook = j->ex.bits.hookstate = 1;
1386 ixj_kill_fasync(j, SIG_HOOKSTATE, POLL_IN);
1387 }
1388 } else {
1389 if (j->ex.bits.dtmf_ready) {
1390 j->dtmf_wp = j->dtmf_rp = j->ex.bits.dtmf_ready = 0;
1391 }
1392 if (j->m_hook) {
1393 j->m_hook = 0;
1394 j->ex.bits.hookstate = 1;
1395 ixj_kill_fasync(j, SIG_HOOKSTATE, POLL_IN);
1396 }
1397 }
1398 }
1399 if (j->cardtype == QTI_LINEJACK && !j->flags.pstncheck && j->flags.pstn_present) {
1400 ixj_pstn_state(j);
1401 }
1402 if (j->ex.bytes) {
1403 wake_up_interruptible(&j->poll_q);
1404 }
1405 clear_bit(board, &j->busyflags);
1406 }
1407 ixj_add_timer(j);
1408}
1409
1410static int ixj_status_wait(IXJ *j)
1411{
1412 unsigned long jif;
1413
1414 jif = jiffies + ((60 * hertz) / 100);
1415 while (!IsStatusReady(j)) {
1416 ixj_perfmon(j->statuswait);
1417 if (time_after(jiffies, jif)) {
1418 ixj_perfmon(j->statuswaitfail);
1419 return -1;
1420 }
1421 }
1422 return 0;
1423}
1424
1425static int ixj_PCcontrol_wait(IXJ *j)
1426{
1427 unsigned long jif;
1428
1429 jif = jiffies + ((60 * hertz) / 100);
1430 while (!IsPCControlReady(j)) {
1431 ixj_perfmon(j->pcontrolwait);
1432 if (time_after(jiffies, jif)) {
1433 ixj_perfmon(j->pcontrolwaitfail);
1434 return -1;
1435 }
1436 }
1437 return 0;
1438}
1439
1440static int ixj_WriteDSPCommand(unsigned short cmd, IXJ *j)
1441{
1442 BYTES bytes;
1443 unsigned long jif;
1444
1445 atomic_inc(&j->DSPWrite);
1446 if(atomic_read(&j->DSPWrite) > 1) {
1447 printk("IXJ %d DSP write overlap attempting command 0x%4.4x\n", j->board, cmd);
1448 return -1;
1449 }
1450 bytes.high = (cmd & 0xFF00) >> 8;
1451 bytes.low = cmd & 0x00FF;
1452 jif = jiffies + ((60 * hertz) / 100);
1453 while (!IsControlReady(j)) {
1454 ixj_perfmon(j->iscontrolready);
1455 if (time_after(jiffies, jif)) {
1456 ixj_perfmon(j->iscontrolreadyfail);
1457 atomic_dec(&j->DSPWrite);
1458 if(atomic_read(&j->DSPWrite) > 0) {
1459 printk("IXJ %d DSP overlaped command 0x%4.4x during control ready failure.\n", j->board, cmd);
1460 while(atomic_read(&j->DSPWrite) > 0) {
1461 atomic_dec(&j->DSPWrite);
1462 }
1463 }
1464 return -1;
1465 }
1466 }
1467 outb(bytes.low, j->DSPbase + 6);
1468 outb(bytes.high, j->DSPbase + 7);
1469
1470 if (ixj_status_wait(j)) {
1471 j->ssr.low = 0xFF;
1472 j->ssr.high = 0xFF;
1473 atomic_dec(&j->DSPWrite);
1474 if(atomic_read(&j->DSPWrite) > 0) {
1475 printk("IXJ %d DSP overlaped command 0x%4.4x during status wait failure.\n", j->board, cmd);
1476 while(atomic_read(&j->DSPWrite) > 0) {
1477 atomic_dec(&j->DSPWrite);
1478 }
1479 }
1480 return -1;
1481 }
1482
1483 j->ssr.low = inb_p(j->DSPbase + 2);
1484 j->ssr.high = inb_p(j->DSPbase + 3);
1485 atomic_dec(&j->DSPWrite);
1486 if(atomic_read(&j->DSPWrite) > 0) {
1487 printk("IXJ %d DSP overlaped command 0x%4.4x\n", j->board, cmd);
1488 while(atomic_read(&j->DSPWrite) > 0) {
1489 atomic_dec(&j->DSPWrite);
1490 }
1491 }
1492 return 0;
1493}
1494
1495
1496
1497
1498
1499
1500static inline int ixj_gpio_read(IXJ *j)
1501{
1502 if (ixj_WriteDSPCommand(0x5143, j))
1503 return -1;
1504
1505 j->gpio.bytes.low = j->ssr.low;
1506 j->gpio.bytes.high = j->ssr.high;
1507
1508 return 0;
1509}
1510
1511static inline void LED_SetState(int state, IXJ *j)
1512{
1513 if (j->cardtype == QTI_LINEJACK) {
1514 j->pld_scrw.bits.led1 = state & 0x1 ? 1 : 0;
1515 j->pld_scrw.bits.led2 = state & 0x2 ? 1 : 0;
1516 j->pld_scrw.bits.led3 = state & 0x4 ? 1 : 0;
1517 j->pld_scrw.bits.led4 = state & 0x8 ? 1 : 0;
1518
1519 outb(j->pld_scrw.byte, j->XILINXbase);
1520 }
1521}
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537static int ixj_set_port(IXJ *j, int arg)
1538{
1539 if (j->cardtype == QTI_PHONEJACK_LITE) {
1540 if (arg != PORT_POTS)
1541 return 10;
1542 else
1543 return 0;
1544 }
1545 switch (arg) {
1546 case PORT_POTS:
1547 j->port = PORT_POTS;
1548 switch (j->cardtype) {
1549 case QTI_PHONECARD:
1550 if (j->flags.pcmciasct == 1)
1551 SLIC_SetState(PLD_SLIC_STATE_ACTIVE, j);
1552 else
1553 return 11;
1554 break;
1555 case QTI_PHONEJACK_PCI:
1556 j->pld_slicw.pcib.mic = 0;
1557 j->pld_slicw.pcib.spk = 0;
1558 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1559 break;
1560 case QTI_LINEJACK:
1561 ixj_set_pots(j, 0);
1562 if (ixj_WriteDSPCommand(0xC528, j))
1563
1564 return 2;
1565 j->pld_scrw.bits.daafsyncen = 0;
1566
1567 outb(j->pld_scrw.byte, j->XILINXbase);
1568 j->pld_clock.byte = 0;
1569 outb(j->pld_clock.byte, j->XILINXbase + 0x04);
1570 j->pld_slicw.bits.rly1 = 1;
1571 j->pld_slicw.bits.spken = 0;
1572 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1573 ixj_mixer(0x1200, j);
1574 ixj_mixer(0x1401, j);
1575 ixj_mixer(0x1300, j);
1576 ixj_mixer(0x1501, j);
1577 ixj_mixer(0x0E80, j);
1578 ixj_mixer(0x0F00, j);
1579 ixj_mixer(0x0080, j);
1580 ixj_mixer(0x0180, j);
1581 SLIC_SetState(PLD_SLIC_STATE_STANDBY, j);
1582
1583 break;
1584 case QTI_PHONEJACK:
1585 j->gpio.bytes.high = 0x0B;
1586 j->gpio.bits.gpio6 = 0;
1587 j->gpio.bits.gpio7 = 0;
1588 ixj_WriteDSPCommand(j->gpio.word, j);
1589 break;
1590 }
1591 break;
1592 case PORT_PSTN:
1593 if (j->cardtype == QTI_LINEJACK) {
1594 ixj_WriteDSPCommand(0xC534, j);
1595
1596 j->pld_slicw.bits.rly3 = 0;
1597 j->pld_slicw.bits.rly1 = 1;
1598 j->pld_slicw.bits.spken = 0;
1599 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1600 j->port = PORT_PSTN;
1601 } else {
1602 return 4;
1603 }
1604 break;
1605 case PORT_SPEAKER:
1606 j->port = PORT_SPEAKER;
1607 switch (j->cardtype) {
1608 case QTI_PHONECARD:
1609 if (j->flags.pcmciasct) {
1610 SLIC_SetState(PLD_SLIC_STATE_OC, j);
1611 }
1612 break;
1613 case QTI_PHONEJACK_PCI:
1614 j->pld_slicw.pcib.mic = 1;
1615 j->pld_slicw.pcib.spk = 1;
1616 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1617 break;
1618 case QTI_LINEJACK:
1619 ixj_set_pots(j, 0);
1620 if (ixj_WriteDSPCommand(0xC528, j))
1621
1622 return 2;
1623 j->pld_scrw.bits.daafsyncen = 0;
1624
1625 outb(j->pld_scrw.byte, j->XILINXbase);
1626 j->pld_clock.byte = 0;
1627 outb(j->pld_clock.byte, j->XILINXbase + 0x04);
1628 j->pld_slicw.bits.rly1 = 1;
1629 j->pld_slicw.bits.spken = 1;
1630 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1631 ixj_mixer(0x1201, j);
1632 ixj_mixer(0x1400, j);
1633 ixj_mixer(0x1301, j);
1634 ixj_mixer(0x1500, j);
1635 ixj_mixer(0x0E06, j);
1636 ixj_mixer(0x0F80, j);
1637 ixj_mixer(0x0000, j);
1638 ixj_mixer(0x0100, j);
1639 break;
1640 case QTI_PHONEJACK:
1641 j->gpio.bytes.high = 0x0B;
1642 j->gpio.bits.gpio6 = 0;
1643 j->gpio.bits.gpio7 = 1;
1644 ixj_WriteDSPCommand(j->gpio.word, j);
1645 break;
1646 }
1647 break;
1648 case PORT_HANDSET:
1649 if (j->cardtype != QTI_PHONEJACK) {
1650 return 5;
1651 } else {
1652 j->gpio.bytes.high = 0x0B;
1653 j->gpio.bits.gpio6 = 1;
1654 j->gpio.bits.gpio7 = 0;
1655 ixj_WriteDSPCommand(j->gpio.word, j);
1656 j->port = PORT_HANDSET;
1657 }
1658 break;
1659 default:
1660 return 6;
1661 break;
1662 }
1663 return 0;
1664}
1665
1666static int ixj_set_pots(IXJ *j, int arg)
1667{
1668 if (j->cardtype == QTI_LINEJACK) {
1669 if (arg) {
1670 if (j->port == PORT_PSTN) {
1671 j->pld_slicw.bits.rly1 = 0;
1672 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1673 j->flags.pots_pstn = 1;
1674 return 1;
1675 } else {
1676 j->flags.pots_pstn = 0;
1677 return 0;
1678 }
1679 } else {
1680 j->pld_slicw.bits.rly1 = 1;
1681 outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1682 j->flags.pots_pstn = 0;
1683 return 1;
1684 }
1685 } else {
1686 return 0;
1687 }
1688}
1689
1690static void ixj_ring_on(IXJ *j)
1691{
1692 if (j->dsp.low == 0x20)
1693 {
1694 if (ixjdebug & 0x0004)
1695 printk(KERN_INFO "IXJ Ring On /dev/phone%d\n", j->board);
1696
1697 j->gpio.bytes.high = 0x0B;
1698 j->gpio.bytes.low = 0x00;
1699 j->gpio.bits.gpio1 = 1;
1700 j->gpio.bits.gpio2 = 1;
1701 j->gpio.bits.gpio5 = 0;
1702 ixj_WriteDSPCommand(j->gpio.word, j);
1703 } else
1704 {
1705 if (ixjdebug & 0x0004)
1706 printk(KERN_INFO "IXJ Ring On /dev/phone%d\n", j->board);
1707
1708 SLIC_SetState(PLD_SLIC_STATE_RINGING, j);
1709 }
1710}
1711
1712static int ixj_siadc(IXJ *j, int val)
1713{
1714 if(j->cardtype == QTI_PHONECARD){
1715 if(j->flags.pcmciascp){
1716 if(val == -1)
1717 return j->siadc.bits.rxg;
1718
1719 if(val < 0 || val > 0x1F)
1720 return -1;
1721
1722 j->siadc.bits.hom = 0;
1723 j->siadc.bits.lom = 0;
1724 j->siadc.bits.rxg = val;
1725 j->psccr.bits.addr = 6;
1726 j->psccr.bits.rw = 0;
1727 j->psccr.bits.dev = 0;
1728 outb(j->siadc.byte, j->XILINXbase + 0x00);
1729 outb(j->psccr.byte, j->XILINXbase + 0x01);
1730 ixj_PCcontrol_wait(j);
1731 return j->siadc.bits.rxg;
1732 }
1733 }
1734 return -1;
1735}
1736
1737static int ixj_sidac(IXJ *j, int val)
1738{
1739 if(j->cardtype == QTI_PHONECARD){
1740 if(j->flags.pcmciascp){
1741 if(val == -1)
1742 return j->sidac.bits.txg;
1743
1744 if(val < 0 || val > 0x1F)
1745 return -1;
1746
1747 j->sidac.bits.srm = 1;
1748 j->sidac.bits.slm = 1;
1749 j->sidac.bits.txg = val;
1750 j->psccr.bits.addr = 7;
1751 j->psccr.bits.rw = 0;
1752 j->psccr.bits.dev = 0;
1753 outb(j->sidac.byte, j->XILINXbase + 0x00);
1754 outb(j->psccr.byte, j->XILINXbase + 0x01);
1755 ixj_PCcontrol_wait(j);
1756 return j->sidac.bits.txg;
1757 }
1758 }
1759 return -1;
1760}
1761
1762static int ixj_pcmcia_cable_check(IXJ *j)
1763{
1764 j->pccr1.byte = inb_p(j->XILINXbase + 0x03);
1765 if (!j->flags.pcmciastate) {
1766 j->pccr2.byte = inb_p(j->XILINXbase + 0x02);
1767 if (j->pccr1.bits.drf || j->pccr2.bits.rstc) {
1768 j->flags.pcmciastate = 4;
1769 return 0;
1770 }
1771 if (j->pccr1.bits.ed) {
1772 j->pccr1.bits.ed = 0;
1773 j->psccr.bits.dev = 3;
1774 j->psccr.bits.rw = 1;
1775 outw_p(j->psccr.byte << 8, j->XILINXbase + 0x00);
1776 ixj_PCcontrol_wait(j);
1777 j->pslic.byte = inw_p(j->XILINXbase + 0x00) & 0xFF;
1778 j->pslic.bits.led2 = j->pslic.bits.det ? 1 : 0;
1779 j->psccr.bits.dev = 3;
1780 j->psccr.bits.rw = 0;
1781 outw_p(j->psccr.byte << 8 | j->pslic.byte, j->XILINXbase + 0x00);
1782 ixj_PCcontrol_wait(j);
1783 return j->pslic.bits.led2 ? 1 : 0;
1784 } else if (j->flags.pcmciasct) {
1785 return j->r_hook;
1786 } else {
1787 return 1;
1788 }
1789 } else if (j->flags.pcmciastate == 4) {
1790 if (!j->pccr1.bits.drf) {
1791 j->flags.pcmciastate = 3;
1792 }
1793 return 0;
1794 } else if (j->flags.pcmciastate == 3) {
1795 j->pccr2.bits.pwr = 0;
1796 j->pccr2.bits.rstc = 1;
1797 outb(j->pccr2.byte, j->XILINXbase + 0x02);
1798 j->checkwait = jiffies + (hertz * 2);
1799 j->flags.incheck = 1;
1800 j->flags.pcmciastate = 2;
1801 return 0;
1802 } else if (j->flags.pcmciastate == 2) {
1803 if (j->flags.incheck) {
1804 if (time_before(jiffies, j->checkwait)) {
1805 return 0;
1806 } else {
1807 j->flags.incheck = 0;
1808 }
1809 }
1810 j->pccr2.bits.pwr = 0;
1811 j->pccr2.bits.rstc = 0;
1812 outb_p(j->pccr2.byte, j->XILINXbase + 0x02);
1813 j->flags.pcmciastate = 1;
1814 return 0;
1815 } else if (j->flags.pcmciastate == 1) {
1816 j->flags.pcmciastate = 0;
1817 if (!j->pccr1.bits.drf) {
1818 j->psccr.bits.dev = 3;
1819 j->psccr.bits.rw = 1;
1820 outb_p(j->psccr.byte, j->XILINXbase + 0x01);
1821 ixj_PCcontrol_wait(j);
1822 j->flags.pcmciascp = 1;
1823
1824 j->flags.pcmciasct = (inw_p(j->XILINXbase + 0x00) >> 8) & 0x03;
1825
1826 if (j->flags.pcmciasct == 3) {
1827 j->flags.pcmciastate = 4;
1828 return 0;
1829 } else if (j->flags.pcmciasct == 0) {
1830 j->pccr2.bits.pwr = 1;
1831 j->pccr2.bits.rstc = 0;
1832 outb_p(j->pccr2.byte, j->XILINXbase + 0x02);
1833 j->port = PORT_SPEAKER;
1834 } else {
1835 j->port = PORT_POTS;
1836 }
1837 j->sic1.bits.cpd = 0;
1838 j->sic1.bits.mpd = 0;
1839 j->sic1.bits.hpd = 0;
1840 j->sic1.bits.lpd = 0;
1841 j->sic1.bits.spd = 1;
1842 j->psccr.bits.addr = 1;
1843 j->psccr.bits.rw = 0;
1844 j->psccr.bits.dev = 0;
1845 outb(j->sic1.byte, j->XILINXbase + 0x00);
1846 outb(j->psccr.byte, j->XILINXbase + 0x01);
1847 ixj_PCcontrol_wait(j);
1848
1849 j->sic2.bits.al = 0;
1850 j->sic2.bits.dl2 = 0;
1851 j->sic2.bits.dl1 = 0;
1852 j->sic2.bits.pll = 0;
1853 j->sic2.bits.hpd = 0;
1854 j->psccr.bits.addr = 2;
1855 j->psccr.bits.rw = 0;
1856 j->psccr.bits.dev = 0;
1857 outb(j->sic2.byte, j->XILINXbase + 0x00);
1858 outb(j->psccr.byte, j->XILINXbase + 0x01);
1859 ixj_PCcontrol_wait(j);
1860
1861 j->psccr.bits.addr = 3;
1862 j->psccr.bits.rw = 0;
1863 j->psccr.bits.dev = 0;
1864 outb(0x00, j->XILINXbase + 0x00);
1865 outb(j->psccr.byte, j->XILINXbase + 0x01);
1866 ixj_PCcontrol_wait(j);
1867
1868 j->psccr.bits.addr = 4;
1869 j->psccr.bits.rw = 0;
1870 j->psccr.bits.dev = 0;
1871 outb(0x09, j->XILINXbase + 0x00);
1872 outb(j->psccr.byte, j->XILINXbase + 0x01);
1873 ixj_PCcontrol_wait(j);
1874
1875 j->sirxg.bits.lig = 1;
1876 j->sirxg.bits.lim = 1;
1877 j->sirxg.bits.mcg = 0;
1878 j->sirxg.bits.mcm = 0;
1879 j->sirxg.bits.him = 0;
1880 j->sirxg.bits.iir = 1;
1881 j->psccr.bits.addr = 5;
1882 j->psccr.bits.rw = 0;
1883 j->psccr.bits.dev = 0;
1884 outb(j->sirxg.byte, j->XILINXbase + 0x00);
1885 outb(j->psccr.byte, j->XILINXbase + 0x01);
1886 ixj_PCcontrol_wait(j);
1887
1888 ixj_siadc(j, 0x17);
1889 ixj_sidac(j, 0x1D);
1890
1891 j->siaatt.bits.sot = 0;
1892 j->psccr.bits.addr = 9;
1893 j->psccr.bits.rw = 0;
1894 j->psccr.bits.dev = 0;
1895 outb(j->siaatt.byte, j->XILINXbase + 0x00);
1896 outb(j->psccr.byte, j->XILINXbase + 0x01);
1897 ixj_PCcontrol_wait(j);
1898
1899 if (j->flags.pcmciasct == 1 && !j->readers && !j->writers) {
1900 j->psccr.byte = j->pslic.byte = 0;
1901 j->pslic.bits.powerdown = 1;
1902 j->psccr.bits.dev = 3;
1903 j->psccr.bits.rw = 0;
1904 outw_p(j->psccr.byte << 8 | j->pslic.byte, j->XILINXbase + 0x00);
1905 ixj_PCcontrol_wait(j);
1906 }
1907 }
1908 return 0;
1909 } else {
1910 j->flags.pcmciascp = 0;
1911 return 0;
1912 }
1913 return 0;
1914}
1915
1916static int ixj_hookstate(IXJ *j)
1917{
1918 int fOffHook = 0;
1919
1920 switch (j->cardtype) {
1921 case QTI_PHONEJACK:
1922 ixj_gpio_read(j);
1923 fOffHook = j->gpio.bits.gpio3read ? 1 : 0;
1924 break;
1925 case QTI_LINEJACK:
1926 case QTI_PHONEJACK_LITE:
1927 case QTI_PHONEJACK_PCI:
1928 SLIC_GetState(j);
1929 if(j->cardtype == QTI_LINEJACK && j->flags.pots_pstn == 1 && (j->readers || j->writers)) {
1930 fOffHook = j->pld_slicr.bits.potspstn ? 1 : 0;
1931 if(fOffHook != j->p_hook) {
1932 if(!j->checkwait) {
1933 j->checkwait = jiffies;
1934 }
1935 if(time_before(jiffies, j->checkwait + 2)) {
1936 fOffHook ^= 1;
1937 } else {
1938 j->checkwait = 0;
1939 }
1940 j->p_hook = fOffHook;
1941 printk("IXJ : /dev/phone%d pots-pstn hookstate check %d at %ld\n", j->board, fOffHook, jiffies);
1942 }
1943 } else {
1944 if (j->pld_slicr.bits.state == PLD_SLIC_STATE_ACTIVE ||
1945 j->pld_slicr.bits.state == PLD_SLIC_STATE_STANDBY) {
1946 if (j->flags.ringing || j->flags.cringing) {
1947 if (!in_interrupt()) {
1948 msleep(20);
1949 }
1950 SLIC_GetState(j);
1951 if (j->pld_slicr.bits.state == PLD_SLIC_STATE_RINGING) {
1952 ixj_ring_on(j);
1953 }
1954 }
1955 if (j->cardtype == QTI_PHONEJACK_PCI) {
1956 j->pld_scrr.byte = inb_p(j->XILINXbase);
1957 fOffHook = j->pld_scrr.pcib.det ? 1 : 0;
1958 } else
1959 fOffHook = j->pld_slicr.bits.det ? 1 : 0;
1960 }
1961 }
1962 break;
1963 case QTI_PHONECARD:
1964 fOffHook = ixj_pcmcia_cable_check(j);
1965 break;
1966 }
1967 if (j->r_hook != fOffHook) {
1968 j->r_hook = fOffHook;
1969 if (j->port == PORT_SPEAKER || j->port == PORT_HANDSET) {
1970 j->ex.bits.hookstate = 1;
1971 ixj_kill_fasync(j, SIG_HOOKSTATE, POLL_IN);
1972 } else if (!fOffHook) {
1973 j->flash_end = jiffies + ((60 * hertz) / 100);
1974 }
1975 }
1976 if (fOffHook) {
1977 if(time_before(jiffies, j->flash_end)) {
1978 j->ex.bits.flash = 1;
1979 j->flash_end = 0;
1980 ixj_kill_fasync(j, SIG_FLASH, POLL_IN);
1981 }
1982 } else {
1983 if(time_before(jiffies, j->flash_end)) {
1984 fOffHook = 1;
1985 }
1986 }
1987
1988 if (j->port == PORT_PSTN && j->daa_mode == SOP_PU_CONVERSATION)
1989 fOffHook |= 2;
1990
1991 if (j->port == PORT_SPEAKER) {
1992 if(j->cardtype == QTI_PHONECARD) {
1993 if(j->flags.pcmciascp && j->flags.pcmciasct) {
1994 fOffHook |= 2;
1995 }
1996 } else {
1997 fOffHook |= 2;
1998 }
1999 }
2000
2001 if (j->port == PORT_HANDSET)
2002 fOffHook |= 2;
2003
2004 return fOffHook;
2005}
2006
2007static void ixj_ring_off(IXJ *j)
2008{
2009 if (j->dsp.low == 0x20)
2010 {
2011 if (ixjdebug & 0x0004)
2012 printk(KERN_INFO "IXJ Ring Off\n");
2013 j->gpio.bytes.high = 0x0B;
2014 j->gpio.bytes.low = 0x00;
2015 j->gpio.bits.gpio1 = 0;
2016 j->gpio.bits.gpio2 = 1;
2017 j->gpio.bits.gpio5 = 0;
2018 ixj_WriteDSPCommand(j->gpio.word, j);
2019 } else
2020 {
2021 if (ixjdebug & 0x0004)
2022 printk(KERN_INFO "IXJ Ring Off\n");
2023
2024 if(!j->flags.cidplay)
2025 SLIC_SetState(PLD_SLIC_STATE_STANDBY, j);
2026
2027 SLIC_GetState(j);
2028 }
2029}
2030
2031static void ixj_ring_start(IXJ *j)
2032{
2033 j->flags.cringing = 1;
2034 if (ixjdebug & 0x0004)
2035 printk(KERN_INFO "IXJ Cadence Ringing Start /dev/phone%d\n", j->board);
2036 if (ixj_hookstate(j) & 1) {
2037 if (j->port == PORT_POTS)
2038 ixj_ring_off(j);
2039 j->flags.cringing = 0;
2040 if (ixjdebug & 0x0004)
2041 printk(KERN_INFO "IXJ Cadence Ringing Stopped /dev/phone%d off hook\n", j->board);
2042 } else if(j->cadence_f[5].enable && (!j->cadence_f[5].en_filter)) {
2043 j->ring_cadence_jif = jiffies;
2044 j->flags.cidsent = j->flags.cidring = 0;
2045 j->cadence_f[5].state = 0;
2046 if(j->cadence_f[5].on1)
2047 ixj_ring_on(j);
2048 } else {
2049 j->ring_cadence_jif = jiffies;
2050 j->ring_cadence_t = 15;
2051 if (j->ring_cadence & 1 << j->ring_cadence_t) {
2052 ixj_ring_on(j);
2053 } else {
2054 ixj_ring_off(j);
2055 }
2056 j->flags.cidsent = j->flags.cidring = j->flags.firstring = 0;
2057 }
2058}
2059
2060static int ixj_ring(IXJ *j)
2061{
2062 char cntr;
2063 unsigned long jif;
2064
2065 j->flags.ringing = 1;
2066 if (ixj_hookstate(j) & 1) {
2067 ixj_ring_off(j);
2068 j->flags.ringing = 0;
2069 return 1;
2070 }
2071 for (cntr = 0; cntr < j->maxrings; cntr++) {
2072 jif = jiffies + (1 * hertz);
2073 ixj_ring_on(j);
2074 while (time_before(jiffies, jif)) {
2075 if (ixj_hookstate(j) & 1) {
2076 ixj_ring_off(j);
2077 j->flags.ringing = 0;
2078 return 1;
2079 }
2080 schedule_timeout_interruptible(1);
2081 if (signal_pending(current))
2082 break;
2083 }
2084 jif = jiffies + (3 * hertz);
2085 ixj_ring_off(j);
2086 while (time_before(jiffies, jif)) {
2087 if (ixj_hookstate(j) & 1) {
2088 msleep(10);
2089 if (ixj_hookstate(j) & 1) {
2090 j->flags.ringing = 0;
2091 return 1;
2092 }
2093 }
2094 schedule_timeout_interruptible(1);
2095 if (signal_pending(current))
2096 break;
2097 }
2098 }
2099 ixj_ring_off(j);
2100 j->flags.ringing = 0;
2101 return 0;
2102}
2103
2104static int ixj_open(struct phone_device *p, struct file *file_p)
2105{
2106 IXJ *j = get_ixj(p->board);
2107 file_p->private_data = j;
2108
2109 if (!j->DSPbase)
2110 return -ENODEV;
2111
2112 if (file_p->f_mode & FMODE_READ) {
2113 if(!j->readers) {
2114 j->readers++;
2115 } else {
2116 return -EBUSY;
2117 }
2118 }
2119
2120 if (file_p->f_mode & FMODE_WRITE) {
2121 if(!j->writers) {
2122 j->writers++;
2123 } else {
2124 if (file_p->f_mode & FMODE_READ){
2125 j->readers--;
2126 }
2127 return -EBUSY;
2128 }
2129 }
2130
2131 if (j->cardtype == QTI_PHONECARD) {
2132 j->pslic.bits.powerdown = 0;
2133 j->psccr.bits.dev = 3;
2134 j->psccr.bits.rw = 0;
2135 outw_p(j->psccr.byte << 8 | j->pslic.byte, j->XILINXbase + 0x00);
2136 ixj_PCcontrol_wait(j);
2137 }
2138
2139 j->flags.cidplay = 0;
2140 j->flags.cidcw_ack = 0;
2141
2142 if (ixjdebug & 0x0002)
2143 printk(KERN_INFO "Opening board %d\n", p->board);
2144
2145 j->framesread = j->frameswritten = 0;
2146 return 0;
2147}
2148
2149static int ixj_release(struct inode *inode, struct file *file_p)
2150{
2151 IXJ_TONE ti;
2152 int cnt;
2153 IXJ *j = file_p->private_data;
2154 int board = j->p.board;
2155
2156
2157
2158
2159
2160 while(test_and_set_bit(board, (void *)&j->busyflags) != 0)
2161 schedule_timeout_interruptible(1);
2162 if (ixjdebug & 0x0002)
2163 printk(KERN_INFO "Closing board %d\n", NUM(inode));
2164
2165 if (j->cardtype == QTI_PHONECARD)
2166 ixj_set_port(j, PORT_SPEAKER);
2167 else
2168 ixj_set_port(j, PORT_POTS);
2169
2170 aec_stop(j);
2171 ixj_play_stop(j);
2172 ixj_record_stop(j);
2173 set_play_volume(j, 0x100);
2174 set_rec_volume(j, 0x100);
2175 ixj_ring_off(j);
2176
2177
2178 ti.tone_index = 10;
2179 ti.gain0 = 1;
2180 ti.freq0 = hz941;
2181 ti.gain1 = 0;
2182 ti.freq1 = hz1209;
2183 ixj_init_tone(j, &ti);
2184 ti.tone_index = 11;
2185 ti.gain0 = 1;
2186 ti.freq0 = hz941;
2187 ti.gain1 = 0;
2188 ti.freq1 = hz1336;
2189 ixj_init_tone(j, &ti);
2190 ti.tone_index = 12;
2191 ti.gain0 = 1;
2192 ti.freq0 = hz941;
2193 ti.gain1 = 0;
2194 ti.freq1 = hz1477;
2195 ixj_init_tone(j, &ti);
2196 ti.tone_index = 13;
2197 ti.gain0 = 1;
2198 ti.freq0 = hz800;
2199 ti.gain1 = 0;
2200 ti.freq1 = 0;
2201 ixj_init_tone(j, &ti);
2202 ti.tone_index = 14;
2203 ti.gain0 = 1;
2204 ti.freq0 = hz1000;
2205 ti.gain1 = 0;
2206 ti.freq1 = 0;
2207 ixj_init_tone(j, &ti);
2208 ti.tone_index = 15;
2209 ti.gain0 = 1;
2210 ti.freq0 = hz1250;
2211 ti.gain1 = 0;
2212 ti.freq1 = 0;
2213 ixj_init_tone(j, &ti);
2214 ti.tone_index = 16;
2215 ti.gain0 = 1;
2216 ti.freq0 = hz950;
2217 ti.gain1 = 0;
2218 ti.freq1 = 0;
2219 ixj_init_tone(j, &ti);
2220 ti.tone_index = 17;
2221 ti.gain0 = 1;
2222 ti.freq0 = hz1100;
2223 ti.gain1 = 0;
2224 ti.freq1 = 0;
2225 ixj_init_tone(j, &ti);
2226 ti.tone_index = 18;
2227 ti.gain0 = 1;
2228 ti.freq0 = hz1400;
2229 ti.gain1 = 0;
2230 ti.freq1 = 0;
2231 ixj_init_tone(j, &ti);
2232 ti.tone_index = 19;
2233 ti.gain0 = 1;
2234 ti.freq0 = hz1500;
2235 ti.gain1 = 0;
2236 ti.freq1 = 0;
2237 ixj_init_tone(j, &ti);
2238 ti.tone_index = 20;
2239 ti.gain0 = 1;
2240 ti.freq0 = hz1600;
2241 ti.gain1 = 0;
2242 ti.freq1 = 0;
2243 ixj_init_tone(j, &ti);
2244 ti.tone_index = 21;
2245 ti.gain0 = 1;
2246 ti.freq0 = hz1800;
2247 ti.gain1 = 0;
2248 ti.freq1 = 0;
2249 ixj_init_tone(j, &ti);
2250 ti.tone_index = 22;
2251 ti.gain0 = 1;
2252 ti.freq0 = hz2100;
2253 ti.gain1 = 0;
2254 ti.freq1 = 0;
2255 ixj_init_tone(j, &ti);
2256 ti.tone_index = 23;
2257 ti.gain0 = 1;
2258 ti.freq0 = hz1300;
2259 ti.gain1 = 0;
2260 ti.freq1 = 0;
2261 ixj_init_tone(j, &ti);
2262 ti.tone_index = 24;
2263 ti.gain0 = 1;
2264 ti.freq0 = hz2450;
2265 ti.gain1 = 0;
2266 ti.freq1 = 0;
2267 ixj_init_tone(j, &ti);
2268 ti.tone_index = 25;
2269 ti.gain0 = 1;
2270 ti.freq0 = hz350;
2271 ti.gain1 = 0;
2272 ti.freq1 = hz440;
2273 ixj_init_tone(j, &ti);
2274 ti.tone_index = 26;
2275 ti.gain0 = 1;
2276 ti.freq0 = hz440;
2277 ti.gain1 = 0;
2278 ti.freq1 = hz480;
2279 ixj_init_tone(j, &ti);
2280 ti.tone_index = 27;
2281 ti.gain0 = 1;
2282 ti.freq0 = hz480;
2283 ti.gain1 = 0;
2284 ti.freq1 = hz620;
2285 ixj_init_tone(j, &ti);
2286
2287 set_rec_depth(j, 2);
2288
2289 set_play_depth(j, 2);
2290
2291 j->ex.bits.dtmf_ready = 0;
2292 j->dtmf_state = 0;
2293 j->dtmf_wp = j->dtmf_rp = 0;
2294 j->rec_mode = j->play_mode = -1;
2295 j->flags.ringing = 0;
2296 j->maxrings = MAXRINGS;
2297 j->ring_cadence = USA_RING_CADENCE;
2298 if(j->cadence_f[5].enable) {
2299 j->cadence_f[5].enable = j->cadence_f[5].en_filter = j->cadence_f[5].state = 0;
2300 }
2301 j->drybuffer = 0;
2302 j->winktime = 320;
2303 j->flags.dtmf_oob = 0;
2304 for (cnt = 0; cnt < 4; cnt++)
2305 j->cadence_f[cnt].enable = 0;
2306
2307 idle(j);
2308
2309 if(j->cardtype == QTI_PHONECARD) {
2310 SLIC_SetState(PLD_SLIC_STATE_OC, j);
2311 }
2312
2313 if (file_p->f_mode & FMODE_READ)
2314 j->readers--;
2315 if (file_p->f_mode & FMODE_WRITE)
2316 j->writers--;
2317
2318 if (j->read_buffer && !j->readers) {
2319 kfree(j->read_buffer);
2320 j->read_buffer = NULL;
2321 j->read_buffer_size = 0;
2322 }
2323 if (j->write_buffer && !j->writers) {
2324 kfree(j->write_buffer);
2325 j->write_buffer = NULL;
2326 j->write_buffer_size = 0;
2327 }
2328 j->rec_codec = j->play_codec = 0;
2329 j->rec_frame_size = j->play_frame_size = 0;
2330 j->flags.cidsent = j->flags.cidring = 0;
2331
2332 if(j->cardtype == QTI_LINEJACK && !j->readers && !j->writers) {
2333 ixj_set_port(j, PORT_PSTN);
2334 daa_set_mode(j, SOP_PU_SLEEP);
2335 ixj_set_pots(j, 1);
2336 }
2337 ixj_WriteDSPCommand(0x0FE3, j);
2338
2339
2340 for (cnt = 0; cnt < 35; cnt++)
2341 j->ixj_signals[cnt] = SIGIO;
2342
2343
2344 j->ex_sig.bits.dtmf_ready = j->ex_sig.bits.hookstate = j->ex_sig.bits.flash = j->ex_sig.bits.pstn_ring =
2345 j->ex_sig.bits.caller_id = j->ex_sig.bits.pstn_wink = j->ex_sig.bits.f0 = j->ex_sig.bits.f1 = j->ex_sig.bits.f2 =
2346 j->ex_sig.bits.f3 = j->ex_sig.bits.fc0 = j->ex_sig.bits.fc1 = j->ex_sig.bits.fc2 = j->ex_sig.bits.fc3 = 1;
2347
2348 file_p->private_data = NULL;
2349 clear_bit(board, &j->busyflags);
2350 return 0;
2351}
2352
2353static int read_filters(IXJ *j)
2354{
2355 unsigned short fc, cnt, trg;
2356 int var;
2357
2358 trg = 0;
2359 if (ixj_WriteDSPCommand(0x5144, j)) {
2360 if(ixjdebug & 0x0001) {
2361 printk(KERN_INFO "Read Frame Counter failed!\n");
2362 }
2363 return -1;
2364 }
2365 fc = j->ssr.high << 8 | j->ssr.low;
2366 if (fc == j->frame_count)
2367 return 1;
2368
2369 j->frame_count = fc;
2370
2371 if (j->dtmf_proc)
2372 return 1;
2373
2374 var = 10;
2375
2376 for (cnt = 0; cnt < 4; cnt++) {
2377 if (ixj_WriteDSPCommand(0x5154 + cnt, j)) {
2378 if(ixjdebug & 0x0001) {
2379 printk(KERN_INFO "Select Filter %d failed!\n", cnt);
2380 }
2381 return -1;
2382 }
2383 if (ixj_WriteDSPCommand(0x515C, j)) {
2384 if(ixjdebug & 0x0001) {
2385 printk(KERN_INFO "Read Filter History %d failed!\n", cnt);
2386 }
2387 return -1;
2388 }
2389 j->filter_hist[cnt] = j->ssr.high << 8 | j->ssr.low;
2390
2391 if (j->cadence_f[cnt].enable) {
2392 if (j->filter_hist[cnt] & 3 && !(j->filter_hist[cnt] & 12)) {
2393 if (j->cadence_f[cnt].state == 0) {
2394 j->cadence_f[cnt].state = 1;
2395 j->cadence_f[cnt].on1min = jiffies + (long)((j->cadence_f[cnt].on1 * (hertz * (100 - var)) / 10000));
2396 j->cadence_f[cnt].on1dot = jiffies + (long)((j->cadence_f[cnt].on1 * (hertz * (100)) / 10000));
2397 j->cadence_f[cnt].on1max = jiffies + (long)((j->cadence_f[cnt].on1 * (hertz * (100 + var)) / 10000));
2398 } else if (j->cadence_f[cnt].state == 2 &&
2399 (time_after(jiffies, j->cadence_f[cnt].off1min) &&
2400 time_before(jiffies, j->cadence_f[cnt].off1max))) {
2401 if (j->cadence_f[cnt].on2) {
2402 j->cadence_f[cnt].state = 3;
2403 j->cadence_f[cnt].on2min = jiffies + (long)((j->cadence_f[cnt].on2 * (hertz * (100 - var)) / 10000));
2404 j->cadence_f[cnt].on2dot = jiffies + (long)((j->cadence_f[cnt].on2 * (hertz * (100)) / 10000));
2405 j->cadence_f[cnt].on2max = jiffies + (long)((j->cadence_f[cnt].on2 * (hertz * (100 + var)) / 10000));
2406 } else {
2407 j->cadence_f[cnt].state = 7;
2408 }
2409 } else if (j->cadence_f[cnt].state == 4 &&
2410 (time_after(jiffies, j->cadence_f[cnt].off2min) &&
2411 time_before(jiffies, j->cadence_f[cnt].off2max))) {
2412 if (j->cadence_f[cnt].on3) {
2413 j->cadence_f[cnt].state = 5;
2414 j->cadence_f[cnt].on3min = jiffies + (long)((j->cadence_f[cnt].on3 * (hertz * (100 - var)) / 10000));
2415 j->cadence_f[cnt].on3dot = jiffies + (long)((j->cadence_f[cnt].on3 * (hertz * (100)) / 10000));
2416 j->cadence_f[cnt].on3max = jiffies + (long)((j->cadence_f[cnt].on3 * (hertz * (100 + var)) / 10000));
2417 } else {
2418 j->cadence_f[cnt].state = 7;
2419 }
2420 } else {
2421 j->cadence_f[cnt].state = 0;
2422 }
2423 } else if (j->filter_hist[cnt] & 12 && !(j->filter_hist[cnt] & 3)) {
2424 if (j->cadence_f[cnt].state == 1) {
2425 if(!j->cadence_f[cnt].on1) {
2426 j->cadence_f[cnt].state = 7;
2427 } else if((time_after(jiffies, j->cadence_f[cnt].on1min) &&
2428 time_before(jiffies, j->cadence_f[cnt].on1max))) {
2429 if(j->cadence_f[cnt].off1) {
2430 j->cadence_f[cnt].state = 2;
2431 j->cadence_f[cnt].off1min = jiffies + (long)((j->cadence_f[cnt].off1 * (hertz * (100 - var)) / 10000));
2432 j->cadence_f[cnt].off1dot = jiffies + (long)((j->cadence_f[cnt].off1 * (hertz * (100)) / 10000));
2433 j->cadence_f[cnt].off1max = jiffies + (long)((j->cadence_f[cnt].off1 * (hertz * (100 + var)) / 10000));
2434 } else {
2435 j->cadence_f[cnt].state = 7;
2436 }
2437 } else {
2438 j->cadence_f[cnt].state = 0;
2439 }
2440 } else if (j->cadence_f[cnt].state == 3) {
2441 if((time_after(jiffies, j->cadence_f[cnt].on2min) &&
2442 time_before(jiffies, j->cadence_f[cnt].on2max))) {
2443 if(j->cadence_f[cnt].off2) {
2444 j->cadence_f[cnt].state = 4;
2445 j->cadence_f[cnt].off2min = jiffies + (long)((j->cadence_f[cnt].off2 * (hertz * (100 - var)) / 10000));
2446 j->cadence_f[cnt].off2dot = jiffies + (long)((j->cadence_f[cnt].off2 * (hertz * (100)) / 10000));
2447 j->cadence_f[cnt].off2max = jiffies + (long)((j->cadence_f[cnt].off2 * (hertz * (100 + var)) / 10000));
2448 } else {
2449 j->cadence_f[cnt].state = 7;
2450 }
2451 } else {
2452 j->cadence_f[cnt].state = 0;
2453 }
2454 } else if (j->cadence_f[cnt].state == 5) {
2455 if ((time_after(jiffies, j->cadence_f[cnt].on3min) &&
2456 time_before(jiffies, j->cadence_f[cnt].on3max))) {
2457 if(j->cadence_f[cnt].off3) {
2458 j->cadence_f[cnt].state = 6;
2459 j->cadence_f[cnt].off3min = jiffies + (long)((j->cadence_f[cnt].off3 * (hertz * (100 - var)) / 10000));
2460 j->cadence_f[cnt].off3dot = jiffies + (long)((j->cadence_f[cnt].off3 * (hertz * (100)) / 10000));
2461 j->cadence_f[cnt].off3max = jiffies + (long)((j->cadence_f[cnt].off3 * (hertz * (100 + var)) / 10000));
2462 } else {
2463 j->cadence_f[cnt].state = 7;
2464 }
2465 } else {
2466 j->cadence_f[cnt].state = 0;
2467 }
2468 } else {
2469 j->cadence_f[cnt].state = 0;
2470 }
2471 } else {
2472 switch(j->cadence_f[cnt].state) {
2473 case 1:
2474 if(time_after(jiffies, j->cadence_f[cnt].on1dot) &&
2475 !j->cadence_f[cnt].off1 &&
2476 !j->cadence_f[cnt].on2 && !j->cadence_f[cnt].off2 &&
2477 !j->cadence_f[cnt].on3 && !j->cadence_f[cnt].off3) {
2478 j->cadence_f[cnt].state = 7;
2479 }
2480 break;
2481 case 3:
2482 if(time_after(jiffies, j->cadence_f[cnt].on2dot) &&
2483 !j->cadence_f[cnt].off2 &&
2484 !j->cadence_f[cnt].on3 && !j->cadence_f[cnt].off3) {
2485 j->cadence_f[cnt].state = 7;
2486 }
2487 break;
2488 case 5:
2489 if(time_after(jiffies, j->cadence_f[cnt].on3dot) &&
2490 !j->cadence_f[cnt].off3) {
2491 j->cadence_f[cnt].state = 7;
2492 }
2493 break;
2494 }
2495 }
2496
2497 if (ixjdebug & 0x0040) {
2498 printk(KERN_INFO "IXJ Tone Cadence state = %d /dev/phone%d at %ld\n", j->cadence_f[cnt].state, j->board, jiffies);
2499 switch(j->cadence_f[cnt].state) {
2500 case 0:
2501 printk(KERN_INFO "IXJ /dev/phone%d No Tone detected\n", j->board);
2502 break;
2503 case 1:
2504 printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %u %ld - %ld - %ld\n", j->board,
2505 j->cadence_f[cnt].on1, j->cadence_f[cnt].on1min, j->cadence_f[cnt].on1dot, j->cadence_f[cnt].on1max);
2506 break;
2507 case 2:
2508 printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].off1min,
2509 j->cadence_f[cnt].off1max);
2510 break;
2511 case 3:
2512 printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].on2min,
2513 j->cadence_f[cnt].on2max);
2514 break;
2515 case 4:
2516 printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].off2min,
2517 j->cadence_f[cnt].off2max);
2518 break;
2519 case 5:
2520 printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].on3min,
2521 j->cadence_f[cnt].on3max);
2522 break;
2523 case 6:
2524 printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].off3min,
2525 j->cadence_f[cnt].off3max);
2526 break;
2527 }
2528 }
2529 }
2530 if (j->cadence_f[cnt].state == 7) {
2531 j->cadence_f[cnt].state = 0;
2532 if (j->cadence_f[cnt].enable == 1)
2533 j->cadence_f[cnt].enable = 0;
2534 switch (cnt) {
2535 case 0:
2536 if(ixjdebug & 0x0020) {
2537 printk(KERN_INFO "Filter Cadence 0 triggered %ld\n", jiffies);
2538 }
2539 j->ex.bits.fc0 = 1;
2540 ixj_kill_fasync(j, SIG_FC0, POLL_IN);
2541 break;
2542 case 1:
2543 if(ixjdebug & 0x0020) {
2544 printk(KERN_INFO "Filter Cadence 1 triggered %ld\n", jiffies);
2545 }
2546 j->ex.bits.fc1 = 1;
2547 ixj_kill_fasync(j, SIG_FC1, POLL_IN);
2548 break;
2549 case 2:
2550 if(ixjdebug & 0x0020) {
2551 printk(KERN_INFO "Filter Cadence 2 triggered %ld\n", jiffies);
2552 }
2553 j->ex.bits.fc2 = 1;
2554 ixj_kill_fasync(j, SIG_FC2, POLL_IN);
2555 break;
2556 case 3:
2557 if(ixjdebug & 0x0020) {
2558 printk(KERN_INFO "Filter Cadence 3 triggered %ld\n", jiffies);
2559 }
2560 j->ex.bits.fc3 = 1;
2561 ixj_kill_fasync(j, SIG_FC3, POLL_IN);
2562 break;
2563 }
2564 }
2565 if (j->filter_en[cnt] && ((j->filter_hist[cnt] & 3 && !(j->filter_hist[cnt] & 12)) ||
2566 (j->filter_hist[cnt] & 12 && !(j->filter_hist[cnt] & 3)))) {
2567 if((j->filter_hist[cnt] & 3 && !(j->filter_hist[cnt] & 12))) {
2568 trg = 1;
2569 } else if((j->filter_hist[cnt] & 12 && !(j->filter_hist[cnt] & 3))) {
2570 trg = 0;
2571 }
2572 switch (cnt) {
2573 case 0:
2574 if(ixjdebug & 0x0020) {
2575 printk(KERN_INFO "Filter 0 triggered %d at %ld\n", trg, jiffies);
2576 }
2577 j->ex.bits.f0 = 1;
2578 ixj_kill_fasync(j, SIG_F0, POLL_IN);
2579 break;
2580 case 1:
2581 if(ixjdebug & 0x0020) {
2582 printk(KERN_INFO "Filter 1 triggered %d at %ld\n", trg, jiffies);
2583 }
2584 j->ex.bits.f1 = 1;
2585 ixj_kill_fasync(j, SIG_F1, POLL_IN);
2586 break;
2587 case 2:
2588 if(ixjdebug & 0x0020) {
2589 printk(KERN_INFO "Filter 2 triggered %d at %ld\n", trg, jiffies);
2590 }
2591 j->ex.bits.f2 = 1;
2592 ixj_kill_fasync(j, SIG_F2, POLL_IN);
2593 break;
2594 case 3:
2595 if(ixjdebug & 0x0020) {
2596 printk(KERN_INFO "Filter 3 triggered %d at %ld\n", trg, jiffies);
2597 }
2598 j->ex.bits.f3 = 1;
2599 ixj_kill_fasync(j, SIG_F3, POLL_IN);
2600 break;
2601 }
2602 }
2603 }
2604 return 0;
2605}
2606
2607static int LineMonitor(IXJ *j)
2608{
2609 if (j->dtmf_proc) {
2610 return -1;
2611 }
2612 j->dtmf_proc = 1;
2613
2614 if (ixj_WriteDSPCommand(0x7000, j))
2615 return -1;
2616
2617 j->dtmf.bytes.high = j->ssr.high;
2618 j->dtmf.bytes.low = j->ssr.low;
2619 if (!j->dtmf_state && j->dtmf.bits.dtmf_valid) {
2620 j->dtmf_state = 1;
2621 j->dtmf_current = j->dtmf.bits.digit;
2622 }
2623 if (j->dtmf_state && !j->dtmf.bits.dtmf_valid)
2624 {
2625 if(!j->cidcw_wait) {
2626 j->dtmfbuffer[j->dtmf_wp] = j->dtmf_current;
2627 j->dtmf_wp++;
2628 if (j->dtmf_wp == 79)
2629 j->dtmf_wp = 0;
2630 j->ex.bits.dtmf_ready = 1;
2631 if(j->ex_sig.bits.dtmf_ready) {
2632 ixj_kill_fasync(j, SIG_DTMF_READY, POLL_IN);
2633 }
2634 }
2635 else if(j->dtmf_current == 0x00 || j->dtmf_current == 0x0D) {
2636 if(ixjdebug & 0x0020) {
2637 printk("IXJ phone%d saw CIDCW Ack DTMF %d from display at %ld\n", j->board, j->dtmf_current, jiffies);
2638 }
2639 j->flags.cidcw_ack = 1;
2640 }
2641 j->dtmf_state = 0;
2642 }
2643 j->dtmf_proc = 0;
2644
2645 return 0;
2646}
2647
2648
2649
2650
2651
2652
2653
2654static void ulaw2alaw(unsigned char *buff, unsigned long len)
2655{
2656 static unsigned char table_ulaw2alaw[] =
2657 {
2658 0x2A, 0x2B, 0x28, 0x29, 0x2E, 0x2F, 0x2C, 0x2D,
2659 0x22, 0x23, 0x20, 0x21, 0x26, 0x27, 0x24, 0x25,
2660 0x3A, 0x3B, 0x38, 0x39, 0x3E, 0x3F, 0x3C, 0x3D,
2661 0x32, 0x33, 0x30, 0x31, 0x36, 0x37, 0x34, 0x35,
2662 0x0B, 0x08, 0x09, 0x0E, 0x0F, 0x0C, 0x0D, 0x02,
2663 0x03, 0x00, 0x01, 0x06, 0x07, 0x04, 0x05, 0x1A,
2664 0x1B, 0x18, 0x19, 0x1E, 0x1F, 0x1C, 0x1D, 0x12,
2665 0x13, 0x10, 0x11, 0x16, 0x17, 0x14, 0x15, 0x6B,
2666 0x68, 0x69, 0x6E, 0x6F, 0x6C, 0x6D, 0x62, 0x63,
2667 0x60, 0x61, 0x66, 0x67, 0x64, 0x65, 0x7B, 0x79,
2668 0x7E, 0x7F, 0x7C, 0x7D, 0x72, 0x73, 0x70, 0x71,
2669 0x76, 0x77, 0x74, 0x75, 0x4B, 0x49, 0x4F, 0x4D,
2670 0x42, 0x43, 0x40, 0x41, 0x46, 0x47, 0x44, 0x45,
2671 0x5A, 0x5B, 0x58, 0x59, 0x5E, 0x5F, 0x5C, 0x5D,
2672 0x52, 0x52, 0x53, 0x53, 0x50, 0x50, 0x51, 0x51,
2673 0x56, 0x56, 0x57, 0x57, 0x54, 0x54, 0x55, 0xD5,
2674 0xAA, 0xAB, 0xA8, 0xA9, 0xAE, 0xAF, 0xAC, 0xAD,
2675 0xA2, 0xA3, 0xA0, 0xA1, 0xA6, 0xA7, 0xA4, 0xA5,
2676 0xBA, 0xBB, 0xB8, 0xB9, 0xBE, 0xBF, 0xBC, 0xBD,
2677 0xB2, 0xB3, 0xB0, 0xB1, 0xB6, 0xB7, 0xB4, 0xB5,
2678 0x8B, 0x88, 0x89, 0x8E, 0x8F, 0x8C, 0x8D, 0x82,
2679 0x83, 0x80, 0x81, 0x86, 0x87, 0x84, 0x85, 0x9A,
2680 0x9B, 0x98, 0x99, 0x9E, 0x9F, 0x9C, 0x9D, 0x92,
2681 0x93, 0x90, 0x91, 0x96, 0x97, 0x94, 0x95, 0xEB,
2682 0xE8, 0xE9, 0xEE, 0xEF, 0xEC, 0xED, 0xE2, 0xE3,
2683 0xE0, 0xE1, 0xE6, 0xE7, 0xE4, 0xE5, 0xFB, 0xF9,
2684 0xFE, 0xFF, 0xFC, 0xFD, 0xF2, 0xF3, 0xF0, 0xF1,
2685 0xF6, 0xF7, 0xF4, 0xF5, 0xCB, 0xC9, 0xCF, 0xCD,
2686 0xC2, 0xC3, 0xC0, 0xC1, 0xC6, 0xC7, 0xC4, 0xC5,
2687 0xDA, 0xDB, 0xD8, 0xD9, 0xDE, 0xDF, 0xDC, 0xDD,
2688 0xD2, 0xD2, 0xD3, 0xD3, 0xD0, 0xD0, 0xD1, 0xD1,
2689 0xD6, 0xD6, 0xD7, 0xD7, 0xD4, 0xD4, 0xD5, 0xD5
2690 };
2691
2692 while (len--)
2693 {
2694 *buff = table_ulaw2alaw[*(unsigned char *)buff];
2695 buff++;
2696 }
2697}
2698
2699static void alaw2ulaw(unsigned char *buff, unsigned long len)
2700{
2701 static unsigned char table_alaw2ulaw[] =
2702 {
2703 0x29, 0x2A, 0x27, 0x28, 0x2D, 0x2E, 0x2B, 0x2C,
2704 0x21, 0x22, 0x1F, 0x20, 0x25, 0x26, 0x23, 0x24,
2705 0x39, 0x3A, 0x37, 0x38, 0x3D, 0x3E, 0x3B, 0x3C,
2706 0x31, 0x32, 0x2F, 0x30, 0x35, 0x36, 0x33, 0x34,
2707 0x0A, 0x0B, 0x08, 0x09, 0x0E, 0x0F, 0x0C, 0x0D,
2708 0x02, 0x03, 0x00, 0x01, 0x06, 0x07, 0x04, 0x05,
2709 0x1A, 0x1B, 0x18, 0x19, 0x1E, 0x1F, 0x1C, 0x1D,
2710 0x12, 0x13, 0x10, 0x11, 0x16, 0x17, 0x14, 0x15,
2711 0x62, 0x63, 0x60, 0x61, 0x66, 0x67, 0x64, 0x65,
2712 0x5D, 0x5D, 0x5C, 0x5C, 0x5F, 0x5F, 0x5E, 0x5E,
2713 0x74, 0x76, 0x70, 0x72, 0x7C, 0x7E, 0x78, 0x7A,
2714 0x6A, 0x6B, 0x68, 0x69, 0x6E, 0x6F, 0x6C, 0x6D,
2715 0x48, 0x49, 0x46, 0x47, 0x4C, 0x4D, 0x4A, 0x4B,
2716 0x40, 0x41, 0x3F, 0x3F, 0x44, 0x45, 0x42, 0x43,
2717 0x56, 0x57, 0x54, 0x55, 0x5A, 0x5B, 0x58, 0x59,
2718 0x4F, 0x4F, 0x4E, 0x4E, 0x52, 0x53, 0x50, 0x51,
2719 0xA9, 0xAA, 0xA7, 0xA8, 0xAD, 0xAE, 0xAB, 0xAC,
2720 0xA1, 0xA2, 0x9F, 0xA0, 0xA5, 0xA6, 0xA3, 0xA4,
2721 0xB9, 0xBA, 0xB7, 0xB8, 0xBD, 0xBE, 0xBB, 0xBC,
2722 0xB1, 0xB2, 0xAF, 0xB0, 0xB5, 0xB6, 0xB3, 0xB4,
2723 0x8A, 0x8B, 0x88, 0x89, 0x8E, 0x8F, 0x8C, 0x8D,
2724 0x82, 0x83, 0x80, 0x81, 0x86, 0x87, 0x84, 0x85,
2725 0x9A, 0x9B, 0x98, 0x99, 0x9E, 0x9F, 0x9C, 0x9D,
2726 0x92, 0x93, 0x90, 0x91, 0x96, 0x97, 0x94, 0x95,
2727 0xE2, 0xE3, 0xE0, 0xE1, 0xE6, 0xE7, 0xE4, 0xE5,
2728 0xDD, 0xDD, 0xDC, 0xDC, 0xDF, 0xDF, 0xDE, 0xDE,
2729 0xF4, 0xF6, 0xF0, 0xF2, 0xFC, 0xFE, 0xF8, 0xFA,
2730 0xEA, 0xEB, 0xE8, 0xE9, 0xEE, 0xEF, 0xEC, 0xED,
2731 0xC8, 0xC9, 0xC6, 0xC7, 0xCC, 0xCD, 0xCA, 0xCB,
2732 0xC0, 0xC1, 0xBF, 0xBF, 0xC4, 0xC5, 0xC2, 0xC3,
2733 0xD6, 0xD7, 0xD4, 0xD5, 0xDA, 0xDB, 0xD8, 0xD9,
2734 0xCF, 0xCF, 0xCE, 0xCE, 0xD2, 0xD3, 0xD0, 0xD1
2735 };
2736
2737 while (len--)
2738 {
2739 *buff = table_alaw2ulaw[*(unsigned char *)buff];
2740 buff++;
2741 }
2742}
2743
2744static ssize_t ixj_read(struct file * file_p, char __user *buf, size_t length, loff_t * ppos)
2745{
2746 unsigned long i = *ppos;
2747 IXJ * j = get_ixj(NUM(file_p->f_path.dentry->d_inode));
2748
2749 DECLARE_WAITQUEUE(wait, current);
2750
2751 if (j->flags.inread)
2752 return -EALREADY;
2753
2754 j->flags.inread = 1;
2755
2756 add_wait_queue(&j->read_q, &wait);
2757 set_current_state(TASK_INTERRUPTIBLE);
2758 mb();
2759
2760 while (!j->read_buffer_ready || (j->dtmf_state && j->flags.dtmf_oob)) {
2761 ++j->read_wait;
2762 if (file_p->f_flags & O_NONBLOCK) {
2763 set_current_state(TASK_RUNNING);
2764 remove_wait_queue(&j->read_q, &wait);
2765 j->flags.inread = 0;
2766 return -EAGAIN;
2767 }
2768 if (!ixj_hookstate(j)) {
2769 set_current_state(TASK_RUNNING);
2770 remove_wait_queue(&j->read_q, &wait);
2771 j->flags.inread = 0;
2772 return 0;
2773 }
2774 interruptible_sleep_on(&j->read_q);
2775 if (signal_pending(current)) {
2776 set_current_state(TASK_RUNNING);
2777 remove_wait_queue(&j->read_q, &wait);
2778 j->flags.inread = 0;
2779 return -EINTR;
2780 }
2781 }
2782
2783 remove_wait_queue(&j->read_q, &wait);
2784 set_current_state(TASK_RUNNING);
2785
2786 if(j->rec_codec == ALAW)
2787 ulaw2alaw(j->read_buffer, min(length, j->read_buffer_size));
2788 i = copy_to_user(buf, j->read_buffer, min(length, j->read_buffer_size));
2789 j->read_buffer_ready = 0;
2790 if (i) {
2791 j->flags.inread = 0;
2792 return -EFAULT;
2793 } else {
2794 j->flags.inread = 0;
2795 return min(length, j->read_buffer_size);
2796 }
2797}
2798
2799static ssize_t ixj_enhanced_read(struct file * file_p, char __user *buf, size_t length,
2800 loff_t * ppos)
2801{
2802 int pre_retval;
2803 ssize_t read_retval = 0;
2804 IXJ *j = get_ixj(NUM(file_p->f_path.dentry->d_inode));
2805
2806 pre_retval = ixj_PreRead(j, 0L);
2807 switch (pre_retval) {
2808 case NORMAL:
2809 read_retval = ixj_read(file_p, buf, length, ppos);
2810 ixj_PostRead(j, 0L);
2811 break;
2812 case NOPOST:
2813 read_retval = ixj_read(file_p, buf, length, ppos);
2814 break;
2815 case POSTONLY:
2816 ixj_PostRead(j, 0L);
2817 break;
2818 default:
2819 read_retval = pre_retval;
2820 }
2821 return read_retval;
2822}
2823
2824static ssize_t ixj_write(struct file *file_p, const char __user *buf, size_t count, loff_t * ppos)
2825{
2826 unsigned long i = *ppos;
2827 IXJ *j = file_p->private_data;
2828
2829 DECLARE_WAITQUEUE(wait, current);
2830
2831 if (j->flags.inwrite)
2832 return -EALREADY;
2833
2834 j->flags.inwrite = 1;
2835
2836 add_wait_queue(&j->write_q, &wait);
2837 set_current_state(TASK_INTERRUPTIBLE);
2838 mb();
2839
2840
2841 while (!j->write_buffers_empty) {
2842 ++j->write_wait;
2843 if (file_p->f_flags & O_NONBLOCK) {
2844 set_current_state(TASK_RUNNING);
2845 remove_wait_queue(&j->write_q, &wait);
2846 j->flags.inwrite = 0;
2847 return -EAGAIN;
2848 }
2849 if (!ixj_hookstate(j)) {
2850 set_current_state(TASK_RUNNING);
2851 remove_wait_queue(&j->write_q, &wait);
2852 j->flags.inwrite = 0;
2853 return 0;
2854 }
2855 interruptible_sleep_on(&j->write_q);
2856 if (signal_pending(current)) {
2857 set_current_state(TASK_RUNNING);
2858 remove_wait_queue(&j->write_q, &wait);
2859 j->flags.inwrite = 0;
2860 return -EINTR;
2861 }
2862 }
2863 set_current_state(TASK_RUNNING);
2864 remove_wait_queue(&j->write_q, &wait);
2865 if (j->write_buffer_wp + count >= j->write_buffer_end)
2866 j->write_buffer_wp = j->write_buffer;
2867 i = copy_from_user(j->write_buffer_wp, buf, min(count, j->write_buffer_size));
2868 if (i) {
2869 j->flags.inwrite = 0;
2870 return -EFAULT;
2871 }
2872 if(j->play_codec == ALAW)
2873 alaw2ulaw(j->write_buffer_wp, min(count, j->write_buffer_size));
2874 j->flags.inwrite = 0;
2875 return min(count, j->write_buffer_size);
2876}
2877
2878static ssize_t ixj_enhanced_write(struct file * file_p, const char __user *buf, size_t count, loff_t * ppos)
2879{
2880 int pre_retval;
2881 ssize_t write_retval = 0;
2882
2883 IXJ *j = get_ixj(NUM(file_p->f_path.dentry->d_inode));
2884
2885 pre_retval = ixj_PreWrite(j, 0L);
2886 switch (pre_retval) {
2887 case NORMAL:
2888 write_retval = ixj_write(file_p, buf, count, ppos);
2889 if (write_retval > 0) {
2890 ixj_PostWrite(j, 0L);
2891 j->write_buffer_wp += write_retval;
2892 j->write_buffers_empty--;
2893 }
2894 break;
2895 case NOPOST:
2896 write_retval = ixj_write(file_p, buf, count, ppos);
2897 if (write_retval > 0) {
2898 j->write_buffer_wp += write_retval;
2899 j->write_buffers_empty--;
2900 }
2901 break;
2902 case POSTONLY:
2903 ixj_PostWrite(j, 0L);
2904 break;
2905 default:
2906 write_retval = pre_retval;
2907 }
2908 return write_retval;
2909}
2910
2911static void ixj_read_frame(IXJ *j)
2912{
2913 int cnt, dly;
2914
2915 if (j->read_buffer) {
2916 for (cnt = 0; cnt < j->rec_frame_size * 2; cnt += 2) {
2917 if (!(cnt % 16) && !IsRxReady(j)) {
2918 dly = 0;
2919 while (!IsRxReady(j)) {
2920 if (dly++ > 5) {
2921 dly = 0;
2922 break;
2923 }
2924 udelay(10);
2925 }
2926 }
2927
2928 if (j->rec_codec == G729 && (cnt == 0 || cnt == 10 || cnt == 20)) {
2929 inb_p(j->DSPbase + 0x0E);
2930 inb_p(j->DSPbase + 0x0F);
2931 }
2932 *(j->read_buffer + cnt) = inb_p(j->DSPbase + 0x0E);
2933 *(j->read_buffer + cnt + 1) = inb_p(j->DSPbase + 0x0F);
2934 }
2935 ++j->framesread;
2936 if (j->intercom != -1) {
2937 if (IsTxReady(get_ixj(j->intercom))) {
2938 for (cnt = 0; cnt < j->rec_frame_size * 2; cnt += 2) {
2939 if (!(cnt % 16) && !IsTxReady(j)) {
2940 dly = 0;
2941 while (!IsTxReady(j)) {
2942 if (dly++ > 5) {
2943 dly = 0;
2944 break;
2945 }
2946 udelay(10);
2947 }
2948 }
2949 outb_p(*(j->read_buffer + cnt), get_ixj(j->intercom)->DSPbase + 0x0C);
2950 outb_p(*(j->read_buffer + cnt + 1), get_ixj(j->intercom)->DSPbase + 0x0D);
2951 }
2952 get_ixj(j->intercom)->frameswritten++;
2953 }
2954 } else {
2955 j->read_buffer_ready = 1;
2956 wake_up_interruptible(&j->read_q);
2957
2958 wake_up_interruptible(&j->poll_q);
2959
2960 if(j->ixj_signals[SIG_READ_READY])
2961 ixj_kill_fasync(j, SIG_READ_READY, POLL_OUT);
2962 }
2963 }
2964}
2965
2966static short fsk[][6][20] =
2967{
2968 {
2969 {
2970 0, 17846, 29934, 32364, 24351, 8481, -10126, -25465, -32587, -29196,
2971 -16384, 1715, 19260, 30591, 32051, 23170, 6813, -11743, -26509, -32722
2972 },
2973 {
2974 -28377, -14876, 3425, 20621, 31163, 31650, 21925, 5126, -13328, -27481,
2975 -32767, -27481, -13328, 5126, 21925, 31650, 31163, 20621, 3425, -14876
2976 },
2977 {
2978 -28377, -32722, -26509, -11743, 6813, 23170, 32051, 30591, 19260, 1715,
2979 -16384, -29196, -32587, -25465, -10126, 8481, 24351, 32364, 29934, 17846
2980 },
2981 {
2982 0, -17846, -29934, -32364, -24351, -8481, 10126, 25465, 32587, 29196,
2983 16384, -1715, -19260, -30591, -32051, -23170, -6813, 11743, 26509, 32722
2984 },
2985 {
2986 28377, 14876, -3425, -20621, -31163, -31650, -21925, -5126, 13328, 27481,
2987 32767, 27481, 13328, -5126, -21925, -31650, -31163, -20621, -3425, 14876
2988 },
2989 {
2990 28377, 32722, 26509, 11743, -6813, -23170, -32051, -30591, -19260, -1715,
2991 16384, 29196, 32587, 25465, 10126, -8481, -24351, -32364, -29934, -17846
2992 }
2993 },
2994 {
2995 {
2996 0, 10126, 19260, 26509, 31163, 32767, 31163, 26509, 19260, 10126,
2997 0, -10126, -19260, -26509, -31163, -32767, -31163, -26509, -19260, -10126
2998 },
2999 {
3000 -28377, -21925, -13328, -3425, 6813, 16384, 24351, 29934, 32587, 32051,
3001 28377, 21925, 13328, 3425, -6813, -16384, -24351, -29934, -32587, -32051
3002 },
3003 {
3004 -28377, -32051, -32587, -29934, -24351, -16384, -6813, 3425, 13328, 21925,
3005 28377, 32051, 32587, 29934, 24351, 16384, 6813, -3425, -13328, -21925
3006 },
3007 {
3008 0, -10126, -19260, -26509, -31163, -32767, -31163, -26509, -19260, -10126,
3009 0, 10126, 19260, 26509, 31163, 32767, 31163, 26509, 19260, 10126
3010 },
3011 {
3012 28377, 21925, 13328, 3425, -6813, -16383, -24351, -29934, -32587, -32051,
3013 -28377, -21925, -13328, -3425, 6813, 16383, 24351, 29934, 32587, 32051
3014 },
3015 {
3016 28377, 32051, 32587, 29934, 24351, 16384, 6813, -3425, -13328, -21925,
3017 -28377, -32051, -32587, -29934, -24351, -16384, -6813, 3425, 13328, 21925
3018 }
3019 }
3020};
3021
3022
3023static void ixj_write_cid_bit(IXJ *j, int bit)
3024{
3025 while (j->fskcnt < 20) {
3026 if(j->fskdcnt < (j->fsksize - 1))
3027 j->fskdata[j->fskdcnt++] = fsk[bit][j->fskz][j->fskcnt];
3028
3029 j->fskcnt += 3;
3030 }
3031 j->fskcnt %= 20;
3032
3033 if (!bit)
3034 j->fskz++;
3035 if (j->fskz >= 6)
3036 j->fskz = 0;
3037
3038}
3039
3040static void ixj_write_cid_byte(IXJ *j, char byte)
3041{
3042 IXJ_CBYTE cb;
3043
3044 cb.cbyte = byte;
3045 ixj_write_cid_bit(j, 0);
3046 ixj_write_cid_bit(j, cb.cbits.b0 ? 1 : 0);
3047 ixj_write_cid_bit(j, cb.cbits.b1 ? 1 : 0);
3048 ixj_write_cid_bit(j, cb.cbits.b2 ? 1 : 0);
3049 ixj_write_cid_bit(j, cb.cbits.b3 ? 1 : 0);
3050 ixj_write_cid_bit(j, cb.cbits.b4 ? 1 : 0);
3051 ixj_write_cid_bit(j, cb.cbits.b5 ? 1 : 0);
3052 ixj_write_cid_bit(j, cb.cbits.b6 ? 1 : 0);
3053 ixj_write_cid_bit(j, cb.cbits.b7 ? 1 : 0);
3054 ixj_write_cid_bit(j, 1);
3055}
3056
3057static void ixj_write_cid_seize(IXJ *j)
3058{
3059 int cnt;
3060
3061 for (cnt = 0; cnt < 150; cnt++) {
3062 ixj_write_cid_bit(j, 0);
3063 ixj_write_cid_bit(j, 1);
3064 }
3065 for (cnt = 0; cnt < 180; cnt++) {
3066 ixj_write_cid_bit(j, 1);
3067 }
3068}
3069
3070static void ixj_write_cidcw_seize(IXJ *j)
3071{
3072 int cnt;
3073
3074 for (cnt = 0; cnt < 80; cnt++) {
3075 ixj_write_cid_bit(j, 1);
3076 }
3077}
3078
3079static int ixj_write_cid_string(IXJ *j, char *s, int checksum)
3080{
3081 int cnt;
3082
3083 for (cnt = 0; cnt < strlen(s); cnt++) {
3084 ixj_write_cid_byte(j, s[cnt]);
3085 checksum = (checksum + s[cnt]);
3086 }
3087 return checksum;
3088}
3089
3090static void ixj_pad_fsk(IXJ *j, int pad)
3091{
3092 int cnt;
3093
3094 for (cnt = 0; cnt < pad; cnt++) {
3095 if(j->fskdcnt < (j->fsksize - 1))
3096 j->fskdata[j->fskdcnt++] = 0x0000;
3097 }
3098 for (cnt = 0; cnt < 720; cnt++) {
3099 if(j->fskdcnt < (j->fsksize - 1))
3100 j->fskdata[j->fskdcnt++] = 0x0000;
3101 }
3102}
3103
3104static void ixj_pre_cid(IXJ *j)
3105{
3106 j->cid_play_codec = j->play_codec;
3107 j->cid_play_frame_size = j->play_frame_size;
3108 j->cid_play_volume = get_play_volume(j);
3109 j->cid_play_flag = j->flags.playing;
3110
3111 j->cid_rec_codec = j->rec_codec;
3112 j->cid_rec_volume = get_rec_volume(j);
3113 j->cid_rec_flag = j->flags.recording;
3114
3115 j->cid_play_aec_level = j->aec_level;
3116
3117 switch(j->baseframe.low) {
3118 case 0xA0:
3119 j->cid_base_frame_size = 20;
3120 break;
3121 case 0x50:
3122 j->cid_base_frame_size = 10;
3123 break;
3124 case 0xF0:
3125 j->cid_base_frame_size = 30;
3126 break;
3127 }
3128
3129 ixj_play_stop(j);
3130 ixj_cpt_stop(j);
3131
3132 j->flags.cidplay = 1;
3133
3134 set_base_frame(j, 30);
3135 set_play_codec(j, LINEAR16);
3136 set_play_volume(j, 0x1B);
3137 ixj_play_start(j);
3138}
3139
3140static void ixj_post_cid(IXJ *j)
3141{
3142 ixj_play_stop(j);
3143
3144 if(j->cidsize > 5000) {
3145 SLIC_SetState(PLD_SLIC_STATE_STANDBY, j);
3146 }
3147 j->flags.cidplay = 0;
3148 if(ixjdebug & 0x0200) {
3149 printk("IXJ phone%d Finished Playing CallerID data %ld\n", j->board, jiffies);
3150 }
3151
3152 ixj_fsk_free(j);
3153
3154 j->fskdcnt = 0;
3155 set_base_frame(j, j->cid_base_frame_size);
3156 set_play_codec(j, j->cid_play_codec);
3157 ixj_aec_start(j, j->cid_play_aec_level);
3158 set_play_volume(j, j->cid_play_volume);
3159
3160 set_rec_codec(j, j->cid_rec_codec);
3161 set_rec_volume(j, j->cid_rec_volume);
3162
3163 if(j->cid_rec_flag)
3164 ixj_record_start(j);
3165
3166 if(j->cid_play_flag)
3167 ixj_play_start(j);
3168
3169 if(j->cid_play_flag) {
3170 wake_up_interruptible(&j->write_q);
3171 }
3172}
3173
3174static void ixj_write_cid(IXJ *j)
3175{
3176 char sdmf1[50];
3177 char sdmf2[50];
3178 char sdmf3[80];
3179 char mdmflen, len1, len2, len3;
3180 int pad;
3181
3182 int checksum = 0;
3183
3184 if (j->dsp.low == 0x20 || j->flags.cidplay)
3185 return;
3186
3187 j->fskz = j->fskphase = j->fskcnt = j->fskdcnt = 0;
3188 j->cidsize = j->cidcnt = 0;
3189
3190 ixj_fsk_alloc(j);
3191
3192 strcpy(sdmf1, j->cid_send.month);
3193 strcat(sdmf1, j->cid_send.day);
3194 strcat(sdmf1, j->cid_send.hour);
3195 strcat(sdmf1, j->cid_send.min);
3196 strcpy(sdmf2, j->cid_send.number);
3197 strcpy(sdmf3, j->cid_send.name);
3198
3199 len1 = strlen(sdmf1);
3200 len2 = strlen(sdmf2);
3201 len3 = strlen(sdmf3);
3202 mdmflen = len1 + len2 + len3 + 6;
3203
3204 while(1){
3205 ixj_write_cid_seize(j);
3206
3207 ixj_write_cid_byte(j, 0x80);
3208 checksum = 0x80;
3209 ixj_write_cid_byte(j, mdmflen);
3210 checksum = checksum + mdmflen;
3211
3212 ixj_write_cid_byte(j, 0x01);
3213 checksum = checksum + 0x01;
3214 ixj_write_cid_byte(j, len1);
3215 checksum = checksum + len1;
3216 checksum = ixj_write_cid_string(j, sdmf1, checksum);
3217 if(ixj_hookstate(j) & 1)
3218 break;
3219
3220 ixj_write_cid_byte(j, 0x02);
3221 checksum = checksum + 0x02;
3222 ixj_write_cid_byte(j, len2);
3223 checksum = checksum + len2;
3224 checksum = ixj_write_cid_string(j, sdmf2, checksum);
3225 if(ixj_hookstate(j) & 1)
3226 break;
3227
3228 ixj_write_cid_byte(j, 0x07);
3229 checksum = checksum + 0x07;
3230 ixj_write_cid_byte(j, len3);
3231 checksum = checksum + len3;
3232 checksum = ixj_write_cid_string(j, sdmf3, checksum);
3233 if(ixj_hookstate(j) & 1)
3234 break;
3235
3236 checksum %= 256;
3237 checksum ^= 0xFF;
3238 checksum += 1;
3239
3240 ixj_write_cid_byte(j, (char) checksum);
3241
3242 pad = j->fskdcnt % 240;
3243 if (pad) {
3244 pad = 240 - pad;
3245 }
3246 ixj_pad_fsk(j, pad);
3247 break;
3248 }
3249
3250 ixj_write_frame(j);
3251}
3252
3253static void ixj_write_cidcw(IXJ *j)
3254{
3255 IXJ_TONE ti;
3256
3257 char sdmf1[50];
3258 char sdmf2[50];
3259 char sdmf3[80];
3260 char mdmflen, len1, len2, len3;
3261 int pad;
3262
3263 int checksum = 0;
3264
3265 if (j->dsp.low == 0x20 || j->flags.cidplay)
3266 return;
3267
3268 j->fskz = j->fskphase = j->fskcnt = j->fskdcnt = 0;
3269 j->cidsize = j->cidcnt = 0;
3270
3271 ixj_fsk_alloc(j);
3272
3273 j->flags.cidcw_ack = 0;
3274
3275 ti.tone_index = 23;
3276 ti.gain0 = 1;
3277 ti.freq0 = hz440;
3278 ti.gain1 = 0;
3279 ti.freq1 = 0;
3280 ixj_init_tone(j, &ti);
3281
3282 ixj_set_tone_on(1500, j);
3283 ixj_set_tone_off(32, j);
3284 if(ixjdebug & 0x0200) {
3285 printk("IXJ cidcw phone%d first tone start at %ld\n", j->board, jiffies);
3286 }
3287 ixj_play_tone(j, 23);
3288
3289 clear_bit(j->board, &j->busyflags);
3290 while(j->tone_state)
3291 schedule_timeout_interruptible(1);
3292 while(test_and_set_bit(j->board, (void *)&j->busyflags) != 0)
3293 schedule_timeout_interruptible(1);
3294 if(ixjdebug & 0x0200) {
3295 printk("IXJ cidcw phone%d first tone end at %ld\n", j->board, jiffies);
3296 }
3297
3298 ti.tone_index = 24;
3299 ti.gain0 = 1;
3300 ti.freq0 = hz2130;
3301 ti.gain1 = 0;
3302 ti.freq1 = hz2750;
3303 ixj_init_tone(j, &ti);
3304
3305 ixj_set_tone_off(10, j);
3306 ixj_set_tone_on(600, j);
3307 if(ixjdebug & 0x0200) {
3308 printk("IXJ cidcw phone%d second tone start at %ld\n", j->board, jiffies);
3309 }
3310 ixj_play_tone(j, 24);
3311
3312 clear_bit(j->board, &j->busyflags);
3313 while(j->tone_state)
3314 schedule_timeout_interruptible(1);
3315 while(test_and_set_bit(j->board, (void *)&j->busyflags) != 0)
3316 schedule_timeout_interruptible(1);
3317 if(ixjdebug & 0x0200) {
3318 printk("IXJ cidcw phone%d sent second tone at %ld\n", j->board, jiffies);
3319 }
3320
3321 j->cidcw_wait = jiffies + ((50 * hertz) / 100);
3322
3323 clear_bit(j->board, &j->busyflags);
3324 while(!j->flags.cidcw_ack && time_before(jiffies, j->cidcw_wait))
3325 schedule_timeout_interruptible(1);
3326 while(test_and_set_bit(j->board, (void *)&j->busyflags) != 0)
3327 schedule_timeout_interruptible(1);
3328 j->cidcw_wait = 0;
3329 if(!j->flags.cidcw_ack) {
3330 if(ixjdebug & 0x0200) {
3331 printk("IXJ cidcw phone%d did not receive ACK from display %ld\n", j->board, jiffies);
3332 }
3333 ixj_post_cid(j);
3334 if(j->cid_play_flag) {
3335 wake_up_interruptible(&j->write_q);
3336 }
3337 return;
3338 } else {
3339 ixj_pre_cid(j);
3340 }
3341 j->flags.cidcw_ack = 0;
3342 strcpy(sdmf1, j->cid_send.month);
3343 strcat(sdmf1, j->cid_send.day);
3344 strcat(sdmf1, j->cid_send.hour);
3345 strcat(sdmf1, j->cid_send.min);
3346 strcpy(sdmf2, j->cid_send.number);
3347 strcpy(sdmf3, j->cid_send.name);
3348
3349 len1 = strlen(sdmf1);
3350 len2 = strlen(sdmf2);
3351 len3 = strlen(sdmf3);
3352 mdmflen = len1 + len2 + len3 + 6;
3353
3354 ixj_write_cidcw_seize(j);
3355
3356 ixj_write_cid_byte(j, 0x80);
3357 checksum = 0x80;
3358 ixj_write_cid_byte(j, mdmflen);
3359 checksum = checksum + mdmflen;
3360
3361 ixj_write_cid_byte(j, 0x01);
3362 checksum = checksum + 0x01;
3363 ixj_write_cid_byte(j, len1);
3364 checksum = checksum + len1;
3365 checksum = ixj_write_cid_string(j, sdmf1, checksum);
3366
3367 ixj_write_cid_byte(j, 0x02);
3368 checksum = checksum + 0x02;
3369 ixj_write_cid_byte(j, len2);
3370 checksum = checksum + len2;
3371 checksum = ixj_write_cid_string(j, sdmf2, checksum);
3372
3373 ixj_write_cid_byte(j, 0x07);
3374 checksum = checksum + 0x07;
3375 ixj_write_cid_byte(j, len3);
3376 checksum = checksum + len3;
3377 checksum = ixj_write_cid_string(j, sdmf3, checksum);
3378
3379 checksum %= 256;
3380 checksum ^= 0xFF;
3381 checksum += 1;
3382
3383 ixj_write_cid_byte(j, (char) checksum);
3384
3385 pad = j->fskdcnt % 240;
3386 if (pad) {
3387 pad = 240 - pad;
3388 }
3389 ixj_pad_fsk(j, pad);
3390 if(ixjdebug & 0x0200) {
3391 printk("IXJ cidcw phone%d sent FSK data at %ld\n", j->board, jiffies);
3392 }
3393}
3394
3395static void ixj_write_vmwi(IXJ *j, int msg)
3396{
3397 char mdmflen;
3398 int pad;
3399
3400 int checksum = 0;
3401
3402 if (j->dsp.low == 0x20 || j->flags.cidplay)
3403 return;
3404
3405 j->fskz = j->fskphase = j->fskcnt = j->fskdcnt = 0;
3406 j->cidsize = j->cidcnt = 0;
3407
3408 ixj_fsk_alloc(j);
3409
3410 mdmflen = 3;
3411
3412 if (j->port == PORT_POTS)
3413 SLIC_SetState(PLD_SLIC_STATE_OHT, j);
3414
3415 ixj_write_cid_seize(j);
3416
3417 ixj_write_cid_byte(j, 0x82);
3418 checksum = 0x82;
3419 ixj_write_cid_byte(j, mdmflen);
3420 checksum = checksum + mdmflen;
3421
3422 ixj_write_cid_byte(j, 0x0B);
3423 checksum = checksum + 0x0B;
3424 ixj_write_cid_byte(j, 1);
3425 checksum = checksum + 1;
3426
3427 if(msg) {
3428 ixj_write_cid_byte(j, 0xFF);
3429 checksum = checksum + 0xFF;
3430 }
3431 else {
3432 ixj_write_cid_byte(j, 0x00);
3433 checksum = checksum + 0x00;
3434 }
3435
3436 checksum %= 256;
3437 checksum ^= 0xFF;
3438 checksum += 1;
3439
3440 ixj_write_cid_byte(j, (char) checksum);
3441
3442 pad = j->fskdcnt % 240;
3443 if (pad) {
3444 pad = 240 - pad;
3445 }
3446 ixj_pad_fsk(j, pad);
3447}
3448
3449static void ixj_write_frame(IXJ *j)
3450{
3451 int cnt, frame_count, dly;
3452 IXJ_WORD dat;
3453
3454 frame_count = 0;
3455 if(j->flags.cidplay) {
3456 for(cnt = 0; cnt < 480; cnt++) {
3457 if (!(cnt % 16) && !IsTxReady(j)) {
3458 dly = 0;
3459 while (!IsTxReady(j)) {
3460 if (dly++ > 5) {
3461 dly = 0;
3462 break;
3463 }
3464 udelay(10);
3465 }
3466 }
3467 dat.word = j->fskdata[j->cidcnt++];
3468 outb_p(dat.bytes.low, j->DSPbase + 0x0C);
3469 outb_p(dat.bytes.high, j->DSPbase + 0x0D);
3470 cnt++;
3471 }
3472 if(j->cidcnt >= j->fskdcnt) {
3473 ixj_post_cid(j);
3474 }
3475
3476
3477
3478 if (j->write_buffer_rp > j->write_buffer_wp) {
3479 j->write_buffer_rp += j->cid_play_frame_size * 2;
3480 if (j->write_buffer_rp >= j->write_buffer_end) {
3481 j->write_buffer_rp = j->write_buffer;
3482 }
3483 j->write_buffers_empty++;
3484 wake_up_interruptible(&j->write_q);
3485
3486 wake_up_interruptible(&j->poll_q);
3487 }
3488 } else if (j->write_buffer && j->write_buffers_empty < 1) {
3489 if (j->write_buffer_wp > j->write_buffer_rp) {
3490 frame_count =
3491 (j->write_buffer_wp - j->write_buffer_rp) / (j->play_frame_size * 2);
3492 }
3493 if (j->write_buffer_rp > j->write_buffer_wp) {
3494 frame_count =
3495 (j->write_buffer_wp - j->write_buffer) / (j->play_frame_size * 2) +
3496 (j->write_buffer_end - j->write_buffer_rp) / (j->play_frame_size * 2);
3497 }
3498 if (frame_count >= 1) {
3499 if (j->ver.low == 0x12 && j->play_mode && j->flags.play_first_frame) {
3500 BYTES blankword;
3501
3502 switch (j->play_mode) {
3503 case PLAYBACK_MODE_ULAW:
3504 case PLAYBACK_MODE_ALAW:
3505 blankword.low = blankword.high = 0xFF;
3506 break;
3507 case PLAYBACK_MODE_8LINEAR:
3508 case PLAYBACK_MODE_16LINEAR:
3509 default:
3510 blankword.low = blankword.high = 0x00;
3511 break;
3512 case PLAYBACK_MODE_8LINEAR_WSS:
3513 blankword.low = blankword.high = 0x80;
3514 break;
3515 }
3516 for (cnt = 0; cnt < 16; cnt++) {
3517 if (!(cnt % 16) && !IsTxReady(j)) {
3518 dly = 0;
3519 while (!IsTxReady(j)) {
3520 if (dly++ > 5) {
3521 dly = 0;
3522 break;
3523 }
3524 udelay(10);
3525 }
3526 }
3527 outb_p((blankword.low), j->DSPbase + 0x0C);
3528 outb_p((blankword.high), j->DSPbase + 0x0D);
3529 }
3530 j->flags.play_first_frame = 0;
3531 } else if (j->play_codec == G723_63 && j->flags.play_first_frame) {
3532 for (cnt = 0; cnt < 24; cnt++) {
3533 BYTES blankword;
3534
3535 if(cnt == 12) {
3536 blankword.low = 0x02;
3537 blankword.high = 0x00;
3538 }
3539 else {
3540 blankword.low = blankword.high = 0x00;
3541 }
3542 if (!(cnt % 16) && !IsTxReady(j)) {
3543 dly = 0;
3544 while (!IsTxReady(j)) {
3545 if (dly++ > 5) {
3546 dly = 0;
3547 break;
3548 }
3549 udelay(10);
3550 }
3551 }
3552 outb_p((blankword.low), j->DSPbase + 0x0C);
3553 outb_p((blankword.high), j->DSPbase + 0x0D);
3554 }
3555 j->flags.play_first_frame = 0;
3556 }
3557 for (cnt = 0; cnt < j->play_frame_size * 2; cnt += 2) {
3558 if (!(cnt % 16) && !IsTxReady(j)) {
3559 dly = 0;
3560 while (!IsTxReady(j)) {
3561 if (dly++ > 5) {
3562 dly = 0;
3563 break;
3564 }
3565 udelay(10);
3566 }
3567 }
3568
3569 if (j->play_codec == G729 && (cnt == 0 || cnt == 10 || cnt == 20)) {
3570 if (j->write_buffer_rp[cnt] == 0 &&
3571 j->write_buffer_rp[cnt + 1] == 0 &&
3572 j->write_buffer_rp[cnt + 2] == 0 &&
3573 j->write_buffer_rp[cnt + 3] == 0 &&
3574 j->write_buffer_rp[cnt + 4] == 0 &&
3575 j->write_buffer_rp[cnt + 5] == 0 &&
3576 j->write_buffer_rp[cnt + 6] == 0 &&
3577 j->write_buffer_rp[cnt + 7] == 0 &&
3578 j->write_buffer_rp[cnt + 8] == 0 &&
3579 j->write_buffer_rp[cnt + 9] == 0) {
3580
3581 outb_p(0x00, j->DSPbase + 0x0C);
3582 outb_p(0x00, j->DSPbase + 0x0D);
3583 } else {
3584
3585 outb_p(0x01, j->DSPbase + 0x0C);
3586 outb_p(0x00, j->DSPbase + 0x0D);
3587 }
3588 }
3589 outb_p(*(j->write_buffer_rp + cnt), j->DSPbase + 0x0C);
3590 outb_p(*(j->write_buffer_rp + cnt + 1), j->DSPbase + 0x0D);
3591 *(j->write_buffer_rp + cnt) = 0;
3592 *(j->write_buffer_rp + cnt + 1) = 0;
3593 }
3594 j->write_buffer_rp += j->play_frame_size * 2;
3595 if (j->write_buffer_rp >= j->write_buffer_end) {
3596 j->write_buffer_rp = j->write_buffer;
3597 }
3598 j->write_buffers_empty++;
3599 wake_up_interruptible(&j->write_q);
3600
3601 wake_up_interruptible(&j->poll_q);
3602
3603 ++j->frameswritten;
3604 }
3605 } else {
3606 j->drybuffer++;
3607 }
3608 if(j->ixj_signals[SIG_WRITE_READY]) {
3609 ixj_kill_fasync(j, SIG_WRITE_READY, POLL_OUT);
3610 }
3611}
3612
3613static int idle(IXJ *j)
3614{
3615 if (ixj_WriteDSPCommand(0x0000, j))
3616
3617 return 0;
3618
3619 if (j->ssr.high || j->ssr.low) {
3620 return 0;
3621 } else {
3622 j->play_mode = -1;
3623 j->flags.playing = 0;
3624 j->rec_mode = -1;
3625 j->flags.recording = 0;
3626 return 1;
3627 }
3628}
3629
3630static int set_base_frame(IXJ *j, int size)
3631{
3632 unsigned short cmd;
3633 int cnt;
3634
3635 idle(j);
3636 j->cid_play_aec_level = j->aec_level;
3637 aec_stop(j);
3638 for (cnt = 0; cnt < 10; cnt++) {
3639 if (idle(j))
3640 break;
3641 }
3642 if (j->ssr.high || j->ssr.low)
3643 return -1;
3644 if (j->dsp.low != 0x20) {
3645 switch (size) {
3646 case 30:
3647 cmd = 0x07F0;
3648
3649 break;
3650 case 20:
3651 cmd = 0x07A0;
3652
3653 break;
3654 case 10:
3655 cmd = 0x0750;
3656
3657 break;
3658 default:
3659 return -1;
3660 }
3661 } else {
3662 if (size == 30)
3663 return size;
3664 else
3665 return -1;
3666 }
3667 if (ixj_WriteDSPCommand(cmd, j)) {
3668 j->baseframe.high = j->baseframe.low = 0xFF;
3669 return -1;
3670 } else {
3671 j->baseframe.high = j->ssr.high;
3672 j->baseframe.low = j->ssr.low;
3673
3674 if(j->baseframe.high == 0x00 && j->baseframe.low == 0x00) {
3675 return -1;
3676 }
3677 }
3678 ixj_aec_start(j, j->cid_play_aec_level);
3679 return size;
3680}
3681
3682static int set_rec_codec(IXJ *j, int rate)
3683{
3684 int retval = 0;
3685
3686 j->rec_codec = rate;
3687
3688 switch (rate) {
3689 case G723_63:
3690 if (j->ver.low != 0x12 || ixj_convert_loaded) {
3691 j->rec_frame_size = 12;
3692 j->rec_mode = 0;
3693 } else {
3694 retval = 1;
3695 }
3696 break;
3697 case G723_53:
3698 if (j->ver.low != 0x12 || ixj_convert_loaded) {
3699 j->rec_frame_size = 10;
3700 j->rec_mode = 0;
3701 } else {
3702 retval = 1;
3703 }
3704 break;
3705 case TS85:
3706 if (j->dsp.low == 0x20 || j->flags.ts85_loaded) {
3707 j->rec_frame_size = 16;
3708 j->rec_mode = 0;
3709 } else {
3710 retval = 1;
3711 }
3712 break;
3713 case TS48:
3714 if (j->ver.low != 0x12 || ixj_convert_loaded) {
3715 j->rec_frame_size = 9;
3716 j->rec_mode = 0;
3717 } else {
3718 retval = 1;
3719 }
3720 break;
3721 case TS41:
3722 if (j->ver.low != 0x12 || ixj_convert_loaded) {
3723 j->rec_frame_size = 8;
3724 j->rec_mode = 0;
3725 } else {
3726 retval = 1;
3727 }
3728 break;
3729 case G728:
3730 if (j->dsp.low != 0x20) {
3731 j->rec_frame_size = 48;
3732 j->rec_mode = 0;
3733 } else {
3734 retval = 1;
3735 }
3736 break;
3737 case G729:
3738 if (j->dsp.low != 0x20) {
3739 if (!j->flags.g729_loaded) {
3740 retval = 1;
3741 break;
3742 }
3743 switch (j->baseframe.low) {
3744 case 0xA0:
3745 j->rec_frame_size = 10;
3746 break;
3747 case 0x50:
3748 j->rec_frame_size = 5;
3749 break;
3750 default:
3751 j->rec_frame_size = 15;
3752 break;
3753 }
3754 j->rec_mode = 0;
3755 } else {
3756 retval = 1;
3757 }
3758 break;
3759 case G729B:
3760 if (j->dsp.low != 0x20) {
3761 if (!j->flags.g729_loaded) {
3762 retval = 1;
3763 break;
3764 }
3765 switch (j->baseframe.low) {
3766 case 0xA0:
3767 j->rec_frame_size = 12;
3768 break;
3769 case 0x50:
3770 j->rec_frame_size = 6;
3771 break;
3772 default:
3773 j->rec_frame_size = 18;
3774 break;
3775 }
3776 j->rec_mode = 0;
3777 } else {
3778 retval = 1;
3779 }
3780 break;
3781 case ULAW:
3782 switch (j->baseframe.low) {
3783 case 0xA0:
3784 j->rec_frame_size = 80;
3785 break;
3786 case 0x50:
3787 j->rec_frame_size = 40;
3788 break;
3789 default:
3790 j->rec_frame_size = 120;
3791 break;
3792 }
3793 j->rec_mode = 4;
3794 break;
3795 case ALAW:
3796 switch (j->baseframe.low) {
3797 case 0xA0:
3798 j->rec_frame_size = 80;
3799 break;
3800 case 0x50:
3801 j->rec_frame_size = 40;
3802 break;
3803 default:
3804 j->rec_frame_size = 120;
3805 break;
3806 }
3807 j->rec_mode = 4;
3808 break;
3809 case LINEAR16:
3810 switch (j->baseframe.low) {
3811 case 0xA0:
3812 j->rec_frame_size = 160;
3813 break;
3814 case 0x50:
3815 j->rec_frame_size = 80;
3816 break;
3817 default:
3818 j->rec_frame_size = 240;
3819 break;
3820 }
3821 j->rec_mode = 5;
3822 break;
3823 case LINEAR8:
3824 switch (j->baseframe.low) {
3825 case 0xA0:
3826 j->rec_frame_size = 80;
3827 break;
3828 case 0x50:
3829 j->rec_frame_size = 40;
3830 break;
3831 default:
3832 j->rec_frame_size = 120;
3833 break;
3834 }
3835 j->rec_mode = 6;
3836 break;
3837 case WSS:
3838 switch (j->baseframe.low) {
3839 case 0xA0:
3840 j->rec_frame_size = 80;
3841 break;
3842 case 0x50:
3843 j->rec_frame_size = 40;
3844 break;
3845 default:
3846 j->rec_frame_size = 120;
3847 break;
3848 }
3849 j->rec_mode = 7;
3850 break;
3851 default:
3852 kfree(j->read_buffer);
3853 j->rec_frame_size = 0;
3854 j->rec_mode = -1;
3855 j->read_buffer = NULL;
3856 j->read_buffer_size = 0;
3857 retval = 1;
3858 break;
3859 }
3860 return retval;
3861}
3862
3863static int ixj_record_start(IXJ *j)
3864{
3865 unsigned short cmd = 0x0000;
3866
3867 if (j->read_buffer) {
3868 ixj_record_stop(j);
3869 }
3870 j->flags.recording = 1;
3871 ixj_WriteDSPCommand(0x0FE0, j);
3872
3873 if(ixjdebug & 0x0002)
3874 printk("IXJ %d Starting Record Codec %d at %ld\n", j->board, j->rec_codec, jiffies);
3875
3876 if (!j->rec_mode) {
3877 switch (j->rec_codec) {
3878 case G723_63:
3879 cmd = 0x5131;
3880 break;
3881 case G723_53:
3882 cmd = 0x5132;
3883 break;
3884 case TS85:
3885 cmd = 0x5130;
3886
3887 break;
3888 case TS48:
3889 cmd = 0x5133;
3890
3891 break;
3892 case TS41:
3893 cmd = 0x5134;
3894
3895 break;
3896 case G728:
3897 cmd = 0x5135;
3898 break;
3899 case G729:
3900 case G729B:
3901 cmd = 0x5136;
3902 break;
3903 default:
3904 return 1;
3905 }
3906 if (ixj_WriteDSPCommand(cmd, j))
3907 return -1;
3908 }
3909 if (!j->read_buffer) {
3910 if (!j->read_buffer)
3911 j->read_buffer = kmalloc(j->rec_frame_size * 2, GFP_ATOMIC);
3912 if (!j->read_buffer) {
3913 printk("Read buffer allocation for ixj board %d failed!\n", j->board);
3914 return -ENOMEM;
3915 }
3916 }
3917 j->read_buffer_size = j->rec_frame_size * 2;
3918
3919 if (ixj_WriteDSPCommand(0x5102, j))
3920
3921 return -1;
3922
3923 switch (j->rec_mode) {
3924 case 0:
3925 cmd = 0x1C03;
3926
3927 break;
3928 case 4:
3929 if (j->ver.low == 0x12) {
3930 cmd = 0x1E03;
3931
3932 } else {
3933 cmd = 0x1E01;
3934
3935 }
3936 break;
3937 case 5:
3938 if (j->ver.low == 0x12) {
3939 cmd = 0x1E83;
3940
3941 } else {
3942 cmd = 0x1E81;
3943
3944 }
3945 break;
3946 case 6:
3947 if (j->ver.low == 0x12) {
3948 cmd = 0x1F03;
3949
3950 } else {
3951 cmd = 0x1F01;
3952
3953 }
3954 break;
3955 case 7:
3956 if (j->ver.low == 0x12) {
3957 cmd = 0x1F83;
3958 } else {
3959 cmd = 0x1F81;
3960 }
3961 break;
3962 }
3963 if (ixj_WriteDSPCommand(cmd, j))
3964 return -1;
3965
3966 if (j->flags.playing) {
3967 ixj_aec_start(j, j->aec_level);
3968 }
3969 return 0;
3970}
3971
3972static void ixj_record_stop(IXJ *j)
3973{
3974 if (ixjdebug & 0x0002)
3975 printk("IXJ %d Stopping Record Codec %d at %ld\n", j->board, j->rec_codec, jiffies);
3976
3977 kfree(j->read_buffer);
3978 j->read_buffer = NULL;
3979 j->read_buffer_size = 0;
3980 if (j->rec_mode > -1) {
3981 ixj_WriteDSPCommand(0x5120, j);
3982 j->rec_mode = -1;
3983 }
3984 j->flags.recording = 0;
3985}
3986static void ixj_vad(IXJ *j, int arg)
3987{
3988 if (arg)
3989 ixj_WriteDSPCommand(0x513F, j);
3990 else
3991 ixj_WriteDSPCommand(0x513E, j);
3992}
3993
3994static void set_rec_depth(IXJ *j, int depth)
3995{
3996 if (depth > 60)
3997 depth = 60;
3998 if (depth < 0)
3999 depth = 0;
4000 ixj_WriteDSPCommand(0x5180 + depth, j);
4001}
4002
4003static void set_dtmf_prescale(IXJ *j, int volume)
4004{
4005 ixj_WriteDSPCommand(0xCF07, j);
4006 ixj_WriteDSPCommand(volume, j);
4007}
4008
4009static int get_dtmf_prescale(IXJ *j)
4010{
4011 ixj_WriteDSPCommand(0xCF05, j);
4012 return j->ssr.high << 8 | j->ssr.low;
4013}
4014
4015static void set_rec_volume(IXJ *j, int volume)
4016{
4017 if(j->aec_level == AEC_AGC) {
4018 if (ixjdebug & 0x0002)
4019 printk(KERN_INFO "IXJ: /dev/phone%d Setting AGC Threshold to 0x%4.4x\n", j->board, volume);
4020 ixj_WriteDSPCommand(0xCF96, j);
4021 ixj_WriteDSPCommand(volume, j);
4022 } else {
4023 if (ixjdebug & 0x0002)
4024 printk(KERN_INFO "IXJ: /dev/phone %d Setting Record Volume to 0x%4.4x\n", j->board, volume);
4025 ixj_WriteDSPCommand(0xCF03, j);
4026 ixj_WriteDSPCommand(volume, j);
4027 }
4028}
4029
4030static int set_rec_volume_linear(IXJ *j, int volume)
4031{
4032 int newvolume, dsprecmax;
4033
4034 if (ixjdebug & 0x0002)
4035 printk(KERN_INFO "IXJ: /dev/phone %d Setting Linear Record Volume to 0x%4.4x\n", j->board, volume);
4036 if(volume > 100 || volume < 0) {
4037 return -1;
4038 }
4039
4040
4041 switch (j->cardtype) {
4042 case QTI_PHONEJACK:
4043 dsprecmax = 0x440;
4044 break;
4045 case QTI_LINEJACK:
4046 dsprecmax = 0x180;
4047 ixj_mixer(0x0203, j);
4048 ixj_mixer(0x0303, j);
4049 ixj_mixer(0x0C00, j);
4050 break;
4051 case QTI_PHONEJACK_LITE:
4052 dsprecmax = 0x4C0;
4053 break;
4054 case QTI_PHONEJACK_PCI:
4055 dsprecmax = 0x100;
4056 break;
4057 case QTI_PHONECARD:
4058 dsprecmax = 0x400;
4059 break;
4060 default:
4061 return -1;
4062 }
4063 newvolume = (dsprecmax * volume) / 100;
4064 set_rec_volume(j, newvolume);
4065 return 0;
4066}
4067
4068static int get_rec_volume(IXJ *j)
4069{
4070 if(j->aec_level == AEC_AGC) {
4071 if (ixjdebug & 0x0002)
4072 printk(KERN_INFO "Getting AGC Threshold\n");
4073 ixj_WriteDSPCommand(0xCF86, j);
4074 if (ixjdebug & 0x0002)
4075 printk(KERN_INFO "AGC Threshold is 0x%2.2x%2.2x\n", j->ssr.high, j->ssr.low);
4076 return j->ssr.high << 8 | j->ssr.low;
4077 } else {
4078 if (ixjdebug & 0x0002)
4079 printk(KERN_INFO "Getting Record Volume\n");
4080 ixj_WriteDSPCommand(0xCF01, j);
4081 return j->ssr.high << 8 | j->ssr.low;
4082 }
4083}
4084
4085static int get_rec_volume_linear(IXJ *j)
4086{
4087 int volume, newvolume, dsprecmax;
4088
4089 switch (j->cardtype) {
4090 case QTI_PHONEJACK:
4091 dsprecmax = 0x440;
4092 break;
4093 case QTI_LINEJACK:
4094 dsprecmax = 0x180;
4095 break;
4096 case QTI_PHONEJACK_LITE:
4097 dsprecmax = 0x4C0;
4098 break;
4099 case QTI_PHONEJACK_PCI:
4100 dsprecmax = 0x100;
4101 break;
4102 case QTI_PHONECARD:
4103 dsprecmax = 0x400;
4104 break;
4105 default:
4106 return -1;
4107 }
4108 volume = get_rec_volume(j);
4109 newvolume = (volume * 100) / dsprecmax;
4110 if(newvolume > 100)
4111 newvolume = 100;
4112 return newvolume;
4113}
4114
4115static int get_rec_level(IXJ *j)
4116{
4117 int retval;
4118
4119 ixj_WriteDSPCommand(0xCF88, j);
4120
4121 retval = j->ssr.high << 8 | j->ssr.low;
4122 retval = (retval * 256) / 240;
4123 return retval;
4124}
4125
4126static void ixj_aec_start(IXJ *j, int level)
4127{
4128 j->aec_level = level;
4129 if (ixjdebug & 0x0002)
4130 printk(KERN_INFO "AGC set = 0x%2.2x\n", j->aec_level);
4131 if (!level) {
4132 aec_stop(j);
4133 } else {
4134 if (j->rec_codec == G729 || j->play_codec == G729 || j->rec_codec == G729B || j->play_codec == G729B) {
4135 ixj_WriteDSPCommand(0xE022, j);
4136
4137 ixj_WriteDSPCommand(0x0300, j);
4138 }
4139 ixj_WriteDSPCommand(0xB001, j);
4140
4141 ixj_WriteDSPCommand(0xE013, j);
4142
4143 switch (level) {
4144 case AEC_LOW:
4145 ixj_WriteDSPCommand(0x0000, j);
4146
4147 ixj_WriteDSPCommand(0xE011, j);
4148 ixj_WriteDSPCommand(0xFFFF, j);
4149
4150 ixj_WriteDSPCommand(0xCF97, j);
4151 ixj_WriteDSPCommand(0x0000, j);
4152
4153 break;
4154
4155 case AEC_MED:
4156 ixj_WriteDSPCommand(0x0600, j);
4157
4158 ixj_WriteDSPCommand(0xE011, j);
4159 ixj_WriteDSPCommand(0x0080, j);
4160
4161 ixj_WriteDSPCommand(0xCF97, j);
4162 ixj_WriteDSPCommand(0x0000, j);
4163
4164 break;
4165
4166 case AEC_HIGH:
4167 ixj_WriteDSPCommand(0x0C00, j);
4168
4169 ixj_WriteDSPCommand(0xE011, j);
4170 ixj_WriteDSPCommand(0x0080, j);
4171
4172 ixj_WriteDSPCommand(0xCF97, j);
4173 ixj_WriteDSPCommand(0x0000, j);
4174
4175 break;
4176
4177 case AEC_AGC:
4178
4179 ixj_WriteDSPCommand(0x0002, j);
4180
4181 ixj_WriteDSPCommand(0xE011, j);
4182 ixj_WriteDSPCommand(0x0100, j);
4183
4184 ixj_WriteDSPCommand(0xE012, j);
4185
4186 if(j->cardtype == QTI_LINEJACK || j->cardtype == QTI_PHONECARD)
4187 ixj_WriteDSPCommand(0x0224, j);
4188 else
4189 ixj_WriteDSPCommand(0x1224, j);
4190
4191 ixj_WriteDSPCommand(0xE014, j);
4192 ixj_WriteDSPCommand(0x0003, j);
4193
4194 ixj_WriteDSPCommand(0xE338, j);
4195
4196
4197 ixj_WriteDSPCommand(0xCF90, j);
4198 ixj_WriteDSPCommand(0x0020, j);
4199
4200 ixj_WriteDSPCommand(0xCF91, j);
4201 ixj_WriteDSPCommand(0x1000, j);
4202
4203 ixj_WriteDSPCommand(0xCF92, j);
4204 ixj_WriteDSPCommand(0x0800, j);
4205
4206 ixj_WriteDSPCommand(0xCF93, j);
4207 ixj_WriteDSPCommand(0x1F40, j);
4208
4209 ixj_WriteDSPCommand(0xCF94, j);
4210 ixj_WriteDSPCommand(0x0005, j);
4211
4212 ixj_WriteDSPCommand(0xCF95, j);
4213 ixj_WriteDSPCommand(0x000D, j);
4214
4215 ixj_WriteDSPCommand(0xCF96, j);
4216 ixj_WriteDSPCommand(0x1200, j);
4217
4218 ixj_WriteDSPCommand(0xCF97, j);
4219 ixj_WriteDSPCommand(0x0001, j);
4220
4221 break;
4222
4223 case AEC_AUTO:
4224 ixj_WriteDSPCommand(0x0002, j);
4225
4226 ixj_WriteDSPCommand(0xE011, j);
4227 ixj_WriteDSPCommand(0x0100, j);
4228
4229 ixj_WriteDSPCommand(0xE012, j);
4230
4231 if(j->cardtype == QTI_LINEJACK || j->cardtype == QTI_PHONECARD)
4232 ixj_WriteDSPCommand(0x0224, j);
4233 else
4234 ixj_WriteDSPCommand(0x1224, j);
4235
4236 ixj_WriteDSPCommand(0xE014, j);
4237 ixj_WriteDSPCommand(0x0003, j);
4238
4239 ixj_WriteDSPCommand(0xE338, j);
4240
4241 break;
4242 }
4243 }
4244}
4245
4246static void aec_stop(IXJ *j)
4247{
4248 j->aec_level = AEC_OFF;
4249 if (j->rec_codec == G729 || j->play_codec == G729 || j->rec_codec == G729B || j->play_codec == G729B) {
4250 ixj_WriteDSPCommand(0xE022, j);
4251
4252 ixj_WriteDSPCommand(0x0700, j);
4253 }
4254 if (j->play_mode != -1 && j->rec_mode != -1)
4255 {
4256 ixj_WriteDSPCommand(0xB002, j);
4257 }
4258}
4259
4260static int set_play_codec(IXJ *j, int rate)
4261{
4262 int retval = 0;
4263
4264 j->play_codec = rate;
4265
4266 switch (rate) {
4267 case G723_63:
4268 if (j->ver.low != 0x12 || ixj_convert_loaded) {
4269 j->play_frame_size = 12;
4270 j->play_mode = 0;
4271 } else {
4272 retval = 1;
4273 }
4274 break;
4275 case G723_53:
4276 if (j->ver.low != 0x12 || ixj_convert_loaded) {
4277 j->play_frame_size = 10;
4278 j->play_mode = 0;
4279 } else {
4280 retval = 1;
4281 }
4282 break;
4283 case TS85:
4284 if (j->dsp.low == 0x20 || j->flags.ts85_loaded) {
4285 j->play_frame_size = 16;
4286 j->play_mode = 0;
4287 } else {
4288 retval = 1;
4289 }
4290 break;
4291 case TS48:
4292 if (j->ver.low != 0x12 || ixj_convert_loaded) {
4293 j->play_frame_size = 9;
4294 j->play_mode = 0;
4295 } else {
4296 retval = 1;
4297 }
4298 break;
4299 case TS41:
4300 if (j->ver.low != 0x12 || ixj_convert_loaded) {
4301 j->play_frame_size = 8;
4302 j->play_mode = 0;
4303 } else {
4304 retval = 1;
4305 }
4306 break;
4307 case G728:
4308 if (j->dsp.low != 0x20) {
4309 j->play_frame_size = 48;
4310 j->play_mode = 0;
4311 } else {
4312 retval = 1;
4313 }
4314 break;
4315 case G729:
4316 if (j->dsp.low != 0x20) {
4317 if (!j->flags.g729_loaded) {
4318 retval = 1;
4319 break;
4320 }
4321 switch (j->baseframe.low) {
4322 case 0xA0:
4323 j->play_frame_size = 10;
4324 break;
4325 case 0x50:
4326 j->play_frame_size = 5;
4327 break;
4328 default:
4329 j->play_frame_size = 15;
4330 break;
4331 }
4332 j->play_mode = 0;
4333 } else {
4334 retval = 1;
4335 }
4336 break;
4337 case G729B:
4338 if (j->dsp.low != 0x20) {
4339 if (!j->flags.g729_loaded) {
4340 retval = 1;
4341 break;
4342 }
4343 switch (j->baseframe.low) {
4344 case 0xA0:
4345 j->play_frame_size = 12;
4346 break;
4347 case 0x50:
4348 j->play_frame_size = 6;
4349 break;
4350 default:
4351 j->play_frame_size = 18;
4352 break;
4353 }
4354 j->play_mode = 0;
4355 } else {
4356 retval = 1;
4357 }
4358 break;
4359 case ULAW:
4360 switch (j->baseframe.low) {
4361 case 0xA0:
4362 j->play_frame_size = 80;
4363 break;
4364 case 0x50:
4365 j->play_frame_size = 40;
4366 break;
4367 default:
4368 j->play_frame_size = 120;
4369 break;
4370 }
4371 j->play_mode = 2;
4372 break;
4373 case ALAW:
4374 switch (j->baseframe.low) {
4375 case 0xA0:
4376 j->play_frame_size = 80;
4377 break;
4378 case 0x50:
4379 j->play_frame_size = 40;
4380 break;
4381 default:
4382 j->play_frame_size = 120;
4383 break;
4384 }
4385 j->play_mode = 2;
4386 break;
4387 case LINEAR16:
4388 switch (j->baseframe.low) {
4389 case 0xA0:
4390 j->play_frame_size = 160;
4391 break;
4392 case 0x50:
4393 j->play_frame_size = 80;
4394 break;
4395 default:
4396 j->play_frame_size = 240;
4397 break;
4398 }
4399 j->play_mode = 6;
4400 break;
4401 case LINEAR8:
4402 switch (j->baseframe.low) {
4403 case 0xA0:
4404 j->play_frame_size = 80;
4405 break;
4406 case 0x50:
4407 j->play_frame_size = 40;
4408 break;
4409 default:
4410 j->play_frame_size = 120;
4411 break;
4412 }
4413 j->play_mode = 4;
4414 break;
4415 case WSS:
4416 switch (j->baseframe.low) {
4417 case 0xA0:
4418 j->play_frame_size = 80;
4419 break;
4420 case 0x50:
4421 j->play_frame_size = 40;
4422 break;
4423 default:
4424 j->play_frame_size = 120;
4425 break;
4426 }
4427 j->play_mode = 5;
4428 break;
4429 default:
4430 kfree(j->write_buffer);
4431 j->play_frame_size = 0;
4432 j->play_mode = -1;
4433 j->write_buffer = NULL;
4434 j->write_buffer_size = 0;
4435 retval = 1;
4436 break;
4437 }
4438 return retval;
4439}
4440
4441static int ixj_play_start(IXJ *j)
4442{
4443 unsigned short cmd = 0x0000;
4444
4445 if (j->write_buffer) {
4446 ixj_play_stop(j);
4447 }
4448
4449 if(ixjdebug & 0x0002)
4450 printk("IXJ %d Starting Play Codec %d at %ld\n", j->board, j->play_codec, jiffies);
4451
4452 j->flags.playing = 1;
4453 ixj_WriteDSPCommand(0x0FE0, j);
4454
4455 j->flags.play_first_frame = 1;
4456 j->drybuffer = 0;
4457
4458 if (!j->play_mode) {
4459 switch (j->play_codec) {
4460 case G723_63:
4461 cmd = 0x5231;
4462 break;
4463 case G723_53:
4464 cmd = 0x5232;
4465 break;
4466 case TS85:
4467 cmd = 0x5230;
4468
4469 break;
4470 case TS48:
4471 cmd = 0x5233;
4472
4473 break;
4474 case TS41:
4475 cmd = 0x5234;
4476
4477 break;
4478 case G728:
4479 cmd = 0x5235;
4480 break;
4481 case G729:
4482 case G729B:
4483 cmd = 0x5236;
4484 break;
4485 default:
4486 return 1;
4487 }
4488 if (ixj_WriteDSPCommand(cmd, j))
4489 return -1;
4490 }
4491 j->write_buffer = kmalloc(j->play_frame_size * 2, GFP_ATOMIC);
4492 if (!j->write_buffer) {
4493 printk("Write buffer allocation for ixj board %d failed!\n", j->board);
4494 return -ENOMEM;
4495 }
4496
4497 j->write_buffers_empty = 1;
4498 j->write_buffer_size = j->play_frame_size * 2;
4499 j->write_buffer_end = j->write_buffer + j->play_frame_size * 2;
4500 j->write_buffer_rp = j->write_buffer_wp = j->write_buffer;
4501
4502 if (ixj_WriteDSPCommand(0x5202, j))
4503
4504 return -1;
4505
4506 switch (j->play_mode) {
4507 case 0:
4508 cmd = 0x2C03;
4509 break;
4510 case 2:
4511 if (j->ver.low == 0x12) {
4512 cmd = 0x2C23;
4513 } else {
4514 cmd = 0x2C21;
4515 }
4516 break;
4517 case 4:
4518 if (j->ver.low == 0x12) {
4519 cmd = 0x2C43;
4520 } else {
4521 cmd = 0x2C41;
4522 }
4523 break;
4524 case 5:
4525 if (j->ver.low == 0x12) {
4526 cmd = 0x2C53;
4527 } else {
4528 cmd = 0x2C51;
4529 }
4530 break;
4531 case 6:
4532 if (j->ver.low == 0x12) {
4533 cmd = 0x2C63;
4534 } else {
4535 cmd = 0x2C61;
4536 }
4537 break;
4538 }
4539 if (ixj_WriteDSPCommand(cmd, j))
4540 return -1;
4541
4542 if (ixj_WriteDSPCommand(0x2000, j))
4543 return -1;
4544
4545 if (ixj_WriteDSPCommand(0x2000 + j->play_frame_size, j))
4546 return -1;
4547
4548 if (j->flags.recording) {
4549 ixj_aec_start(j, j->aec_level);
4550 }
4551
4552 return 0;
4553}
4554
4555static void ixj_play_stop(IXJ *j)
4556{
4557 if (ixjdebug & 0x0002)
4558 printk("IXJ %d Stopping Play Codec %d at %ld\n", j->board, j->play_codec, jiffies);
4559
4560 kfree(j->write_buffer);
4561 j->write_buffer = NULL;
4562 j->write_buffer_size = 0;
4563 if (j->play_mode > -1) {
4564 ixj_WriteDSPCommand(0x5221, j);
4565
4566 j->play_mode = -1;
4567 }
4568 j->flags.playing = 0;
4569}
4570
4571static inline int get_play_level(IXJ *j)
4572{
4573 int retval;
4574
4575 ixj_WriteDSPCommand(0xCF8F, j);
4576 return j->ssr.high << 8 | j->ssr.low;
4577 retval = j->ssr.high << 8 | j->ssr.low;
4578 retval = (retval * 256) / 240;
4579 return retval;
4580}
4581
4582static unsigned int ixj_poll(struct file *file_p, poll_table * wait)
4583{
4584 unsigned int mask = 0;
4585
4586 IXJ *j = get_ixj(NUM(file_p->f_path.dentry->d_inode));
4587
4588 poll_wait(file_p, &(j->poll_q), wait);
4589 if (j->read_buffer_ready > 0)
4590 mask |= POLLIN | POLLRDNORM;
4591 if (j->write_buffers_empty > 0)
4592 mask |= POLLOUT | POLLWRNORM;
4593 if (j->ex.bytes)
4594 mask |= POLLPRI;
4595 return mask;
4596}
4597
4598static int ixj_play_tone(IXJ *j, char tone)
4599{
4600 if (!j->tone_state) {
4601 if(ixjdebug & 0x0002) {
4602 printk("IXJ %d starting tone %d at %ld\n", j->board, tone, jiffies);
4603 }
4604 if (j->dsp.low == 0x20) {
4605 idle(j);
4606 }
4607 j->tone_start_jif = jiffies;
4608
4609 j->tone_state = 1;
4610 }
4611
4612 j->tone_index = tone;
4613 if (ixj_WriteDSPCommand(0x6000 + j->tone_index, j))
4614 return -1;
4615
4616 return 0;
4617}
4618
4619static int ixj_set_tone_on(unsigned short arg, IXJ *j)
4620{
4621 j->tone_on_time = arg;
4622
4623 if (ixj_WriteDSPCommand(0x6E04, j))
4624
4625 return -1;
4626
4627 if (ixj_WriteDSPCommand(arg, j))
4628 return -1;
4629
4630 return 0;
4631}
4632
4633static int SCI_WaitHighSCI(IXJ *j)
4634{
4635 int cnt;
4636
4637 j->pld_scrr.byte = inb_p(j->XILINXbase);
4638 if (!j->pld_scrr.bits.sci) {
4639 for (cnt = 0; cnt < 10; cnt++) {
4640 udelay(32);
4641 j->pld_scrr.byte = inb_p(j->XILINXbase);
4642
4643 if ((j->pld_scrr.bits.sci))
4644 return 1;
4645 }
4646 if (ixjdebug & 0x0001)
4647 printk(KERN_INFO "SCI Wait High failed %x\n", j->pld_scrr.byte);
4648 return 0;
4649 } else
4650 return 1;
4651}
4652
4653static int SCI_WaitLowSCI(IXJ *j)
4654{
4655 int cnt;
4656
4657 j->pld_scrr.byte = inb_p(j->XILINXbase);
4658 if (j->pld_scrr.bits.sci) {
4659 for (cnt = 0; cnt < 10; cnt++) {
4660 udelay(32);
4661 j->pld_scrr.byte = inb_p(j->XILINXbase);
4662
4663 if (!(j->pld_scrr.bits.sci))
4664 return 1;
4665 }
4666 if (ixjdebug & 0x0001)
4667 printk(KERN_INFO "SCI Wait Low failed %x\n", j->pld_scrr.byte);
4668 return 0;
4669 } else
4670 return 1;
4671}
4672
4673static int SCI_Control(IXJ *j, int control)
4674{
4675 switch (control) {
4676 case SCI_End:
4677 j->pld_scrw.bits.c0 = 0;
4678
4679 j->pld_scrw.bits.c1 = 0;
4680
4681 break;
4682 case SCI_Enable_DAA:
4683 j->pld_scrw.bits.c0 = 1;
4684
4685 j->pld_scrw.bits.c1 = 0;
4686
4687 break;
4688 case SCI_Enable_Mixer:
4689 j->pld_scrw.bits.c0 = 0;
4690
4691 j->pld_scrw.bits.c1 = 1;
4692
4693 break;
4694 case SCI_Enable_EEPROM:
4695 j->pld_scrw.bits.c0 = 1;
4696
4697 j->pld_scrw.bits.c1 = 1;
4698
4699 break;
4700 default:
4701 return 0;
4702 break;
4703 }
4704 outb_p(j->pld_scrw.byte, j->XILINXbase);
4705
4706 switch (control) {
4707 case SCI_End:
4708 return 1;
4709 break;
4710 case SCI_Enable_DAA:
4711 case SCI_Enable_Mixer:
4712 case SCI_Enable_EEPROM:
4713 if (!SCI_WaitHighSCI(j))
4714 return 0;
4715 break;
4716 default:
4717 return 0;
4718 break;
4719 }
4720 return 1;
4721}
4722
4723static int SCI_Prepare(IXJ *j)
4724{
4725 if (!SCI_Control(j, SCI_End))
4726 return 0;
4727
4728 if (!SCI_WaitLowSCI(j))
4729 return 0;
4730
4731 return 1;
4732}
4733
4734static int ixj_get_mixer(long val, IXJ *j)
4735{
4736 int reg = (val & 0x1F00) >> 8;
4737 return j->mix.vol[reg];
4738}
4739
4740static int ixj_mixer(long val, IXJ *j)
4741{
4742 BYTES bytes;
4743
4744 bytes.high = (val & 0x1F00) >> 8;
4745 bytes.low = val & 0x00FF;
4746
4747
4748 j->mix.vol[bytes.high] = bytes.low;
4749
4750 outb_p(bytes.high & 0x1F, j->XILINXbase + 0x03);
4751
4752 outb_p(bytes.low, j->XILINXbase + 0x02);
4753
4754 SCI_Control(j, SCI_Enable_Mixer);
4755
4756 SCI_Control(j, SCI_End);
4757
4758 return 0;
4759}
4760
4761static int daa_load(BYTES * p_bytes, IXJ *j)
4762{
4763 outb_p(p_bytes->high, j->XILINXbase + 0x03);
4764 outb_p(p_bytes->low, j->XILINXbase + 0x02);
4765 if (!SCI_Control(j, SCI_Enable_DAA))
4766 return 0;
4767 else
4768 return 1;
4769}
4770
4771static int ixj_daa_cr4(IXJ *j, char reg)
4772{
4773 BYTES bytes;
4774
4775 switch (j->daa_mode) {
4776 case SOP_PU_SLEEP:
4777 bytes.high = 0x14;
4778 break;
4779 case SOP_PU_RINGING:
4780 bytes.high = 0x54;
4781 break;
4782 case SOP_PU_CONVERSATION:
4783 bytes.high = 0x94;
4784 break;
4785 case SOP_PU_PULSEDIALING:
4786 bytes.high = 0xD4;
4787 break;
4788 }
4789
4790 j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.reg = reg;
4791
4792 switch (j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGX) {
4793 case 0:
4794 j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGR_Z = 0;
4795 break;
4796 case 1:
4797 j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGR_Z = 2;
4798 break;
4799 case 2:
4800 j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGR_Z = 1;
4801 break;
4802 case 3:
4803 j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGR_Z = 3;
4804 break;
4805 }
4806
4807 bytes.low = j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.reg;
4808
4809 if (!daa_load(&bytes, j))
4810 return 0;
4811
4812 if (!SCI_Prepare(j))
4813 return 0;
4814
4815 return 1;
4816}
4817
4818static char daa_int_read(IXJ *j)
4819{
4820 BYTES bytes;
4821
4822 if (!SCI_Prepare(j))
4823 return 0;
4824
4825 bytes.high = 0x38;
4826 bytes.low = 0x00;
4827 outb_p(bytes.high, j->XILINXbase + 0x03);
4828 outb_p(bytes.low, j->XILINXbase + 0x02);
4829
4830 if (!SCI_Control(j, SCI_Enable_DAA))
4831 return 0;
4832
4833 bytes.high = inb_p(j->XILINXbase + 0x03);
4834 bytes.low = inb_p(j->XILINXbase + 0x02);
4835 if (bytes.low != ALISDAA_ID_BYTE) {
4836 if (ixjdebug & 0x0001)
4837 printk("Cannot read DAA ID Byte high = %d low = %d\n", bytes.high, bytes.low);
4838 return 0;
4839 }
4840 if (!SCI_Control(j, SCI_Enable_DAA))
4841 return 0;
4842 if (!SCI_Control(j, SCI_End))
4843 return 0;
4844
4845 bytes.high = inb_p(j->XILINXbase + 0x03);
4846 bytes.low = inb_p(j->XILINXbase + 0x02);
4847
4848 j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.reg = bytes.high;
4849
4850 return 1;
4851}
4852
4853static char daa_CR_read(IXJ *j, int cr)
4854{
4855 IXJ_WORD wdata;
4856 BYTES bytes;
4857
4858 if (!SCI_Prepare(j))
4859 return 0;
4860
4861 switch (j->daa_mode) {
4862 case SOP_PU_SLEEP:
4863 bytes.high = 0x30 + cr;
4864 break;
4865 case SOP_PU_RINGING:
4866 bytes.high = 0x70 + cr;
4867 break;
4868 case SOP_PU_CONVERSATION:
4869 bytes.high = 0xB0 + cr;
4870 break;
4871 case SOP_PU_PULSEDIALING:
4872 default:
4873 bytes.high = 0xF0 + cr;
4874 break;
4875 }
4876
4877 bytes.low = 0x00;
4878
4879 outb_p(bytes.high, j->XILINXbase + 0x03);
4880 outb_p(bytes.low, j->XILINXbase + 0x02);
4881
4882 if (!SCI_Control(j, SCI_Enable_DAA))
4883 return 0;
4884
4885 bytes.high = inb_p(j->XILINXbase + 0x03);
4886 bytes.low = inb_p(j->XILINXbase + 0x02);
4887 if (bytes.low != ALISDAA_ID_BYTE) {
4888 if (ixjdebug & 0x0001)
4889 printk("Cannot read DAA ID Byte high = %d low = %d\n", bytes.high, bytes.low);
4890 return 0;
4891 }
4892 if (!SCI_Control(j, SCI_Enable_DAA))
4893 return 0;
4894 if (!SCI_Control(j, SCI_End))
4895 return 0;
4896
4897 wdata.word = inw_p(j->XILINXbase + 0x02);
4898
4899 switch(cr){
4900 case 5:
4901 j->m_DAAShadowRegs.SOP_REGS.SOP.cr5.reg = wdata.bytes.high;
4902 break;
4903 case 4:
4904 j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.reg = wdata.bytes.high;
4905 break;
4906 case 3:
4907 j->m_DAAShadowRegs.SOP_REGS.SOP.cr3.reg = wdata.bytes.high;
4908 break;
4909 case 2:
4910 j->m_DAAShadowRegs.SOP_REGS.SOP.cr2.reg = wdata.bytes.high;
4911 break;
4912 case 1:
4913 j->m_DAAShadowRegs.SOP_REGS.SOP.cr1.reg = wdata.bytes.high;
4914 break;
4915 case 0:
4916 j->m_DAAShadowRegs.SOP_REGS.SOP.cr0.reg = wdata.bytes.high;
4917 break;
4918 default:
4919 return 0;
4920 }
4921 return 1;
4922}
4923
4924static int ixj_daa_cid_reset(IXJ *j)
4925{
4926 int i;
4927 BYTES bytes;
4928
