1/* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2008 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7#ifndef __QLA_FW_H 8#define __QLA_FW_H 9 10#define MBS_CHECKSUM_ERROR 0x4010 11#define MBS_INVALID_PRODUCT_KEY 0x4020 12 13/* 14 * Firmware Options. 15 */ 16#define FO1_ENABLE_PUREX BIT_10 17#define FO1_DISABLE_LED_CTRL BIT_6 18#define FO1_ENABLE_8016 BIT_0 19#define FO2_ENABLE_SEL_CLASS2 BIT_5 20#define FO3_NO_ABTS_ON_LINKDOWN BIT_14 21#define FO3_HOLD_STS_IOCB BIT_12 22 23/* 24 * Port Database structure definition for ISP 24xx. 25 */ 26#define PDO_FORCE_ADISC BIT_1 27#define PDO_FORCE_PLOGI BIT_0 28 29 30#define PORT_DATABASE_24XX_SIZE 64 31struct port_database_24xx { 32 uint16_t flags; 33#define PDF_TASK_RETRY_ID BIT_14 34#define PDF_FC_TAPE BIT_7 35#define PDF_ACK0_CAPABLE BIT_6 36#define PDF_FCP2_CONF BIT_5 37#define PDF_CLASS_2 BIT_4 38#define PDF_HARD_ADDR BIT_1 39 40 uint8_t current_login_state; 41 uint8_t last_login_state; 42#define PDS_PLOGI_PENDING 0x03 43#define PDS_PLOGI_COMPLETE 0x04 44#define PDS_PRLI_PENDING 0x05 45#define PDS_PRLI_COMPLETE 0x06 46#define PDS_PORT_UNAVAILABLE 0x07 47#define PDS_PRLO_PENDING 0x09 48#define PDS_LOGO_PENDING 0x11 49#define PDS_PRLI2_PENDING 0x12 50 51 uint8_t hard_address[3]; 52 uint8_t reserved_1; 53 54 uint8_t port_id[3]; 55 uint8_t sequence_id; 56 57 uint16_t port_timer; 58 59 uint16_t nport_handle; /* N_PORT handle. */ 60 61 uint16_t receive_data_size; 62 uint16_t reserved_2; 63 64 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 65 /* Bits 15-0 of word 0 */ 66 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 67 /* Bits 15-0 of word 3 */ 68 69 uint8_t port_name[WWN_SIZE]; 70 uint8_t node_name[WWN_SIZE]; 71 72 uint8_t reserved_3[24]; 73}; 74 75struct vp_database_24xx { 76 uint16_t vp_status; 77 uint8_t options; 78 uint8_t id; 79 uint8_t port_name[WWN_SIZE]; 80 uint8_t node_name[WWN_SIZE]; 81 uint16_t port_id_low; 82 uint16_t port_id_high; 83}; 84 85struct nvram_24xx { 86 /* NVRAM header. */ 87 uint8_t id[4]; 88 uint16_t nvram_version; 89 uint16_t reserved_0; 90 91 /* Firmware Initialization Control Block. */ 92 uint16_t version; 93 uint16_t reserved_1; 94 uint16_t frame_payload_size; 95 uint16_t execution_throttle; 96 uint16_t exchange_count; 97 uint16_t hard_address; 98 99 uint8_t port_name[WWN_SIZE]; 100 uint8_t node_name[WWN_SIZE]; 101 102 uint16_t login_retry_count; 103 uint16_t link_down_on_nos; 104 uint16_t interrupt_delay_timer; 105 uint16_t login_timeout; 106 107 uint32_t firmware_options_1; 108 uint32_t firmware_options_2; 109 uint32_t firmware_options_3; 110 111 /* Offset 56. */ 112 113 /* 114 * BIT 0 = Control Enable 115 * BIT 1-15 = 116 * 117 * BIT 0-7 = Reserved 118 * BIT 8-10 = Output Swing 1G 119 * BIT 11-13 = Output Emphasis 1G 120 * BIT 14-15 = Reserved 121 * 122 * BIT 0-7 = Reserved 123 * BIT 8-10 = Output Swing 2G 124 * BIT 11-13 = Output Emphasis 2G 125 * BIT 14-15 = Reserved 126 * 127 * BIT 0-7 = Reserved 128 * BIT 8-10 = Output Swing 4G 129 * BIT 11-13 = Output Emphasis 4G 130 * BIT 14-15 = Reserved 131 */ 132 uint16_t seriallink_options[4]; 133 134 uint16_t reserved_2[16]; 135 136 /* Offset 96. */ 137 uint16_t reserved_3[16]; 138 139 /* PCIe table entries. */ 140 uint16_t reserved_4[16]; 141 142 /* Offset 160. */ 143 uint16_t reserved_5[16]; 144 145 /* Offset 192. */ 146 uint16_t reserved_6[16]; 147 148 /* Offset 224. */ 149 uint16_t reserved_7[16]; 150 151 /* 152 * BIT 0 = Enable spinup delay 153 * BIT 1 = Disable BIOS 154 * BIT 2 = Enable Memory Map BIOS 155 * BIT 3 = Enable Selectable Boot 156 * BIT 4 = Disable RISC code load 157 * BIT 5 = Disable Serdes 158 * BIT 6 = 159 * BIT 7 = 160 * 161 * BIT 8 = 162 * BIT 9 = 163 * BIT 10 = Enable lip full login 164 * BIT 11 = Enable target reset 165 * BIT 12 = 166 * BIT 13 = 167 * BIT 14 = 168 * BIT 15 = Enable alternate WWN 169 * 170 * BIT 16-31 = 171 */ 172 uint32_t host_p; 173 174 uint8_t alternate_port_name[WWN_SIZE]; 175 uint8_t alternate_node_name[WWN_SIZE]; 176 177 uint8_t boot_port_name[WWN_SIZE]; 178 uint16_t boot_lun_number; 179 uint16_t reserved_8; 180 181 uint8_t alt1_boot_port_name[WWN_SIZE]; 182 uint16_t alt1_boot_lun_number; 183 uint16_t reserved_9; 184 185 uint8_t alt2_boot_port_name[WWN_SIZE]; 186 uint16_t alt2_boot_lun_number; 187 uint16_t reserved_10; 188 189 uint8_t alt3_boot_port_name[WWN_SIZE]; 190 uint16_t alt3_boot_lun_number; 191 uint16_t reserved_11; 192 193 /* 194 * BIT 0 = Selective Login 195 * BIT 1 = Alt-Boot Enable 196 * BIT 2 = Reserved 197 * BIT 3 = Boot Order List 198 * BIT 4 = Reserved 199 * BIT 5 = Selective LUN 200 * BIT 6 = Reserved 201 * BIT 7-31 = 202 */ 203 uint32_t efi_parameters; 204 205 uint8_t reset_delay; 206 uint8_t reserved_12; 207 uint16_t reserved_13; 208 209 uint16_t boot_id_number; 210 uint16_t reserved_14; 211 212 uint16_t max_luns_per_target; 213 uint16_t reserved_15; 214 215 uint16_t port_down_retry_count; 216 uint16_t link_down_timeout; 217 218 /* FCode parameters. */ 219 uint16_t fcode_parameter; 220 221 uint16_t reserved_16[3]; 222 223 /* Offset 352. */ 224 uint8_t prev_drv_ver_major; 225 uint8_t prev_drv_ver_submajob; 226 uint8_t prev_drv_ver_minor; 227 uint8_t prev_drv_ver_subminor; 228 229 uint16_t prev_bios_ver_major; 230 uint16_t prev_bios_ver_minor; 231 232 uint16_t prev_efi_ver_major; 233 uint16_t prev_efi_ver_minor; 234 235 uint16_t prev_fw_ver_major; 236 uint8_t prev_fw_ver_minor; 237 uint8_t prev_fw_ver_subminor; 238 239 uint16_t reserved_17[8]; 240 241 /* Offset 384. */ 242 uint16_t reserved_18[16]; 243 244 /* Offset 416. */ 245 uint16_t reserved_19[16]; 246 247 /* Offset 448. */ 248 uint16_t reserved_20[16]; 249 250 /* Offset 480. */ 251 uint8_t model_name[16]; 252 253 uint16_t reserved_21[2]; 254 255 /* Offset 500. */ 256 /* HW Parameter Block. */ 257 uint16_t pcie_table_sig; 258 uint16_t pcie_table_offset; 259 260 uint16_t subsystem_vendor_id; 261 uint16_t subsystem_device_id; 262 263 uint32_t checksum; 264}; 265 266/* 267 * ISP Initialization Control Block. 268 * Little endian except where noted. 269 */ 270#define ICB_VERSION 1 271struct init_cb_24xx { 272 uint16_t version; 273 uint16_t reserved_1; 274 275 uint16_t frame_payload_size; 276 uint16_t execution_throttle; 277 uint16_t exchange_count; 278 279 uint16_t hard_address; 280 281 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 282 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 283 284 uint16_t response_q_inpointer; 285 uint16_t request_q_outpointer; 286 287 uint16_t login_retry_count; 288 289 uint16_t prio_request_q_outpointer; 290 291 uint16_t response_q_length; 292 uint16_t request_q_length; 293 294 uint16_t link_down_on_nos; /* Milliseconds. */ 295 296 uint16_t prio_request_q_length; 297 298 uint32_t request_q_address[2]; 299 uint32_t response_q_address[2]; 300 uint32_t prio_request_q_address[2]; 301 302 uint8_t reserved_2[8]; 303 304 uint16_t atio_q_inpointer; 305 uint16_t atio_q_length; 306 uint32_t atio_q_address[2]; 307 308 uint16_t interrupt_delay_timer; /* 100us increments. */ 309 uint16_t login_timeout; 310 311 /* 312 * BIT 0 = Enable Hard Loop Id 313 * BIT 1 = Enable Fairness 314 * BIT 2 = Enable Full-Duplex 315 * BIT 3 = Reserved 316 * BIT 4 = Enable Target Mode 317 * BIT 5 = Disable Initiator Mode 318 * BIT 6 = Reserved 319 * BIT 7 = Reserved 320 * 321 * BIT 8 = Reserved 322 * BIT 9 = Non Participating LIP 323 * BIT 10 = Descending Loop ID Search 324 * BIT 11 = Acquire Loop ID in LIPA 325 * BIT 12 = Reserved 326 * BIT 13 = Full Login after LIP 327 * BIT 14 = Node Name Option 328 * BIT 15-31 = Reserved 329 */ 330 uint32_t firmware_options_1; 331 332 /* 333 * BIT 0 = Operation Mode bit 0 334 * BIT 1 = Operation Mode bit 1 335 * BIT 2 = Operation Mode bit 2 336 * BIT 3 = Operation Mode bit 3 337 * BIT 4 = Connection Options bit 0 338 * BIT 5 = Connection Options bit 1 339 * BIT 6 = Connection Options bit 2 340 * BIT 7 = Enable Non part on LIHA failure 341 * 342 * BIT 8 = Enable Class 2 343 * BIT 9 = Enable ACK0 344 * BIT 10 = Reserved 345 * BIT 11 = Enable FC-SP Security 346 * BIT 12 = FC Tape Enable 347 * BIT 13 = Reserved 348 * BIT 14 = Enable Target PRLI Control 349 * BIT 15-31 = Reserved 350 */ 351 uint32_t firmware_options_2; 352 353 /* 354 * BIT 0 = Reserved 355 * BIT 1 = Soft ID only 356 * BIT 2 = Reserved 357 * BIT 3 = Reserved 358 * BIT 4 = FCP RSP Payload bit 0 359 * BIT 5 = FCP RSP Payload bit 1 360 * BIT 6 = Enable Receive Out-of-Order data frame handling 361 * BIT 7 = Disable Automatic PLOGI on Local Loop 362 * 363 * BIT 8 = Reserved 364 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 365 * BIT 10 = Reserved 366 * BIT 11 = Reserved 367 * BIT 12 = Reserved 368 * BIT 13 = Data Rate bit 0 369 * BIT 14 = Data Rate bit 1 370 * BIT 15 = Data Rate bit 2 371 * BIT 16 = Enable 75 ohm Termination Select 372 * BIT 17-31 = Reserved 373 */ 374 uint32_t firmware_options_3; 375 376 uint8_t reserved_3[24]; 377}; 378 379/* 380 * ISP queue - command entry structure definition. 381 */ 382#define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */ 383struct cmd_type_6 { 384 uint8_t entry_type; /* Entry type. */ 385 uint8_t entry_count; /* Entry count. */ 386 uint8_t sys_define; /* System defined. */ 387 uint8_t entry_status; /* Entry Status. */ 388 389 uint32_t handle; /* System handle. */ 390 391 uint16_t nport_handle; /* N_PORT handle. */ 392 uint16_t timeout; /* Command timeout. */ 393 394 uint16_t dseg_count; /* Data segment count. */ 395 396 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */ 397 398 struct scsi_lun lun; /* FCP LUN (BE). */ 399 400 uint16_t control_flags; /* Control flags. */ 401#define CF_DATA_SEG_DESCR_ENABLE BIT_2 402#define CF_READ_DATA BIT_1 403#define CF_WRITE_DATA BIT_0 404 405 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 406 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 407 408 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ 409 410 uint32_t byte_count; /* Total byte count. */ 411 412 uint8_t port_id[3]; /* PortID of destination port. */ 413 uint8_t vp_index; 414 415 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */ 416 uint16_t fcp_data_dseg_len; /* Data segment length. */ 417 uint16_t reserved_1; /* MUST be set to 0. */ 418}; 419 420#define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */ 421struct cmd_type_7 { 422 uint8_t entry_type; /* Entry type. */ 423 uint8_t entry_count; /* Entry count. */ 424 uint8_t sys_define; /* System defined. */ 425 uint8_t entry_status; /* Entry Status. */ 426 427 uint32_t handle; /* System handle. */ 428 429 uint16_t nport_handle; /* N_PORT handle. */ 430 uint16_t timeout; /* Command timeout. */ 431#define FW_MAX_TIMEOUT 0x1999 432 433 uint16_t dseg_count; /* Data segment count. */ 434 uint16_t reserved_1; 435 436 struct scsi_lun lun; /* FCP LUN (BE). */ 437 438 uint16_t task_mgmt_flags; /* Task management flags. */ 439#define TMF_CLEAR_ACA BIT_14 440#define TMF_TARGET_RESET BIT_13 441#define TMF_LUN_RESET BIT_12 442#define TMF_CLEAR_TASK_SET BIT_10 443#define TMF_ABORT_TASK_SET BIT_9 444#define TMF_DSD_LIST_ENABLE BIT_2 445#define TMF_READ_DATA BIT_1 446#define TMF_WRITE_DATA BIT_0 447 448 uint8_t task; 449#define TSK_SIMPLE 0 450#define TSK_HEAD_OF_QUEUE 1 451#define TSK_ORDERED 2 452#define TSK_ACA 4 453#define TSK_UNTAGGED 5 454 455 uint8_t crn; 456 457 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ 458 uint32_t byte_count; /* Total byte count. */ 459 460 uint8_t port_id[3]; /* PortID of destination port. */ 461 uint8_t vp_index; 462 463 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 464 uint32_t dseg_0_len; /* Data segment 0 length. */ 465}; 466 467/* 468 * ISP queue - status entry structure definition. 469 */ 470#define STATUS_TYPE 0x03 /* Status entry. */ 471struct sts_entry_24xx { 472 uint8_t entry_type; /* Entry type. */ 473 uint8_t entry_count; /* Entry count. */ 474 uint8_t sys_define; /* System defined. */ 475 uint8_t entry_status; /* Entry Status. */ 476 477 uint32_t handle; /* System handle. */ 478 479 uint16_t comp_status; /* Completion status. */ 480 uint16_t ox_id; /* OX_ID used by the firmware. */ 481 482 uint32_t residual_len; /* FW calc residual transfer length. */ 483 484 uint16_t reserved_1; 485 uint16_t state_flags; /* State flags. */ 486#define SF_TRANSFERRED_DATA BIT_11 487#define SF_FCP_RSP_DMA BIT_0 488 489 uint16_t reserved_2; 490 uint16_t scsi_status; /* SCSI status. */ 491#define SS_CONFIRMATION_REQ BIT_12 492 493 uint32_t rsp_residual_count; /* FCP RSP residual count. */ 494 495 uint32_t sense_len; /* FCP SENSE length. */ 496 uint32_t rsp_data_len; /* FCP response data length. */ 497 498 uint8_t data[28]; /* FCP response/sense information. */ 499}; 500 501/* 502 * Status entry completion status 503 */ 504#define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */ 505#define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */ 506#define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */ 507#define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */ 508#define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */ 509 510/* 511 * ISP queue - marker entry structure definition. 512 */ 513#define MARKER_TYPE 0x04 /* Marker entry. */ 514struct mrk_entry_24xx { 515 uint8_t entry_type; /* Entry type. */ 516 uint8_t entry_count; /* Entry count. */ 517 uint8_t handle_count; /* Handle count. */ 518 uint8_t entry_status; /* Entry Status. */ 519 520 uint32_t handle; /* System handle. */ 521 522 uint16_t nport_handle; /* N_PORT handle. */ 523 524 uint8_t modifier; /* Modifier (7-0). */ 525#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 526#define MK_SYNC_ID 1 /* Synchronize ID */ 527#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 528 uint8_t reserved_1; 529 530 uint8_t reserved_2; 531 uint8_t vp_index; 532 533 uint16_t reserved_3; 534 535 uint8_t lun[8]; /* FCP LUN (BE). */ 536 uint8_t reserved_4[40]; 537}; 538 539/* 540 * ISP queue - CT Pass-Through entry structure definition. 541 */ 542#define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */ 543struct ct_entry_24xx { 544 uint8_t entry_type; /* Entry type. */ 545 uint8_t entry_count; /* Entry count. */ 546 uint8_t sys_define; /* System Defined. */ 547 uint8_t entry_status; /* Entry Status. */ 548 549 uint32_t handle; /* System handle. */ 550 551 uint16_t comp_status; /* Completion status. */ 552 553 uint16_t nport_handle; /* N_PORT handle. */ 554 555 uint16_t cmd_dsd_count; 556 557 uint8_t vp_index; 558 uint8_t reserved_1; 559 560 uint16_t timeout; /* Command timeout. */ 561 uint16_t reserved_2; 562 563 uint16_t rsp_dsd_count; 564 565 uint8_t reserved_3[10]; 566 567 uint32_t rsp_byte_count; 568 uint32_t cmd_byte_count; 569 570 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 571 uint32_t dseg_0_len; /* Data segment 0 length. */ 572 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 573 uint32_t dseg_1_len; /* Data segment 1 length. */ 574}; 575 576/* 577 * ISP queue - ELS Pass-Through entry structure definition. 578 */ 579#define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */ 580struct els_entry_24xx { 581 uint8_t entry_type; /* Entry type. */ 582 uint8_t entry_count; /* Entry count. */ 583 uint8_t sys_define; /* System Defined. */ 584 uint8_t entry_status; /* Entry Status. */ 585 586 uint32_t handle; /* System handle. */ 587 588 uint16_t reserved_1; 589 590 uint16_t nport_handle; /* N_PORT handle. */ 591 592 uint16_t tx_dsd_count; 593 594 uint8_t vp_index; 595 uint8_t sof_type; 596#define EST_SOFI3 (1 << 4) 597#define EST_SOFI2 (3 << 4) 598 599 uint32_t rx_xchg_address; /* Receive exchange address. */ 600 uint16_t rx_dsd_count; 601 602 uint8_t opcode; 603 uint8_t reserved_2; 604 605 uint8_t port_id[3]; 606 uint8_t reserved_3; 607 608 uint16_t reserved_4; 609 610 uint16_t control_flags; /* Control flags. */ 611#define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13) 612#define EPD_ELS_COMMAND (0 << 13) 613#define EPD_ELS_ACC (1 << 13) 614#define EPD_ELS_RJT (2 << 13) 615#define EPD_RX_XCHG (3 << 13) 616#define ECF_CLR_PASSTHRU_PEND BIT_12 617#define ECF_INCL_FRAME_HDR BIT_11 618 619 uint32_t rx_byte_count; 620 uint32_t tx_byte_count; 621 622 uint32_t tx_address[2]; /* Data segment 0 address. */ 623 uint32_t tx_len; /* Data segment 0 length. */ 624 uint32_t rx_address[2]; /* Data segment 1 address. */ 625 uint32_t rx_len; /* Data segment 1 length. */ 626}; 627 628/* 629 * ISP queue - Mailbox Command entry structure definition. 630 */ 631#define MBX_IOCB_TYPE 0x39 632struct mbx_entry_24xx { 633 uint8_t entry_type; /* Entry type. */ 634 uint8_t entry_count; /* Entry count. */ 635 uint8_t handle_count; /* Handle count. */ 636 uint8_t entry_status; /* Entry Status. */ 637 638 uint32_t handle; /* System handle. */ 639 640 uint16_t mbx[28]; 641}; 642 643 644#define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */ 645struct logio_entry_24xx { 646 uint8_t entry_type; /* Entry type. */ 647 uint8_t entry_count; /* Entry count. */ 648 uint8_t sys_define; /* System defined. */ 649 uint8_t entry_status; /* Entry Status. */ 650 651 uint32_t handle; /* System handle. */ 652 653 uint16_t comp_status; /* Completion status. */ 654#define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */ 655 656 uint16_t nport_handle; /* N_PORT handle. */ 657 658 uint16_t control_flags; /* Control flags. */ 659 /* Modifiers. */ 660#define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */ 661#define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ 662#define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ 663#define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ 664#define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */ 665#define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */ 666#define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */ 667#define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */ 668#define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */ 669#define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */ 670 /* Commands. */ 671#define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */ 672#define LCF_COMMAND_PRLI 0x01 /* PRLI. */ 673#define LCF_COMMAND_PDISC 0x02 /* PDISC. */ 674#define LCF_COMMAND_ADISC 0x03 /* ADISC. */ 675#define LCF_COMMAND_LOGO 0x08 /* LOGO. */ 676#define LCF_COMMAND_PRLO 0x09 /* PRLO. */ 677#define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */ 678 679 uint8_t vp_index; 680 uint8_t reserved_1; 681 682 uint8_t port_id[3]; /* PortID of destination port. */ 683 684 uint8_t rsp_size; /* Response size in 32bit words. */ 685 686 uint32_t io_parameter[11]; /* General I/O parameters. */ 687#define LSC_SCODE_NOLINK 0x01 688#define LSC_SCODE_NOIOCB 0x02 689#define LSC_SCODE_NOXCB 0x03 690#define LSC_SCODE_CMD_FAILED 0x04 691#define LSC_SCODE_NOFABRIC 0x05 692#define LSC_SCODE_FW_NOT_READY 0x07 693#define LSC_SCODE_NOT_LOGGED_IN 0x09 694#define LSC_SCODE_NOPCB 0x0A 695 696#define LSC_SCODE_ELS_REJECT 0x18 697#define LSC_SCODE_CMD_PARAM_ERR 0x19 698#define LSC_SCODE_PORTID_USED 0x1A 699#define LSC_SCODE_NPORT_USED 0x1B 700#define LSC_SCODE_NONPORT 0x1C 701#define LSC_SCODE_LOGGED_IN 0x1D 702#define LSC_SCODE_NOFLOGI_ACC 0x1F 703}; 704 705#define TSK_MGMT_IOCB_TYPE 0x14 706struct tsk_mgmt_entry { 707 uint8_t entry_type; /* Entry type. */ 708 uint8_t entry_count; /* Entry count. */ 709 uint8_t handle_count; /* Handle count. */ 710 uint8_t entry_status; /* Entry Status. */ 711 712 uint32_t handle; /* System handle. */ 713 714 uint16_t nport_handle; /* N_PORT handle. */ 715 716 uint16_t reserved_1; 717 718 uint16_t delay; /* Activity delay in seconds. */ 719 720 uint16_t timeout; /* Command timeout. */ 721 722 struct scsi_lun lun; /* FCP LUN (BE). */ 723 724 uint32_t control_flags; /* Control Flags. */ 725#define TCF_NOTMCMD_TO_TARGET BIT_31 726#define TCF_LUN_RESET BIT_4 727#define TCF_ABORT_TASK_SET BIT_3 728#define TCF_CLEAR_TASK_SET BIT_2 729#define TCF_TARGET_RESET BIT_1 730#define TCF_CLEAR_ACA BIT_0 731 732 uint8_t reserved_2[20]; 733 734 uint8_t port_id[3]; /* PortID of destination port. */ 735 uint8_t vp_index; 736 737 uint8_t reserved_3[12]; 738}; 739 740#define ABORT_IOCB_TYPE 0x33 741struct abort_entry_24xx { 742 uint8_t entry_type; /* Entry type. */ 743 uint8_t entry_count; /* Entry count. */ 744 uint8_t handle_count; /* Handle count. */ 745 uint8_t entry_status; /* Entry Status. */ 746 747 uint32_t handle; /* System handle. */ 748 749 uint16_t nport_handle; /* N_PORT handle. */ 750 /* or Completion status. */ 751 752 uint16_t options; /* Options. */ 753#define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */ 754 755 uint32_t handle_to_abort; /* System handle to abort. */ 756 757 uint8_t reserved_1[32]; 758 759 uint8_t port_id[3]; /* PortID of destination port. */ 760 uint8_t vp_index; 761 762 uint8_t reserved_2[12]; 763}; 764 765/* 766 * ISP I/O Register Set structure definitions. 767 */ 768struct device_reg_24xx { 769 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */ 770#define FARX_DATA_FLAG BIT_31 771#define FARX_ACCESS_FLASH_CONF 0x7FFD0000 772#define FARX_ACCESS_FLASH_DATA 0x7FF00000 773#define FARX_ACCESS_NVRAM_CONF 0x7FFF0000 774#define FARX_ACCESS_NVRAM_DATA 0x7FFE0000 775 776#define FA_NVRAM_FUNC0_ADDR 0x80 777#define FA_NVRAM_FUNC1_ADDR 0x180 778 779#define FA_NVRAM_VPD_SIZE 0x200 780#define FA_NVRAM_VPD0_ADDR 0x00 781#define FA_NVRAM_VPD1_ADDR 0x100 782 783#define FA_BOOT_CODE_ADDR 0x00000 784 /* 785 * RISC code begins at offset 512KB 786 * within flash. Consisting of two 787 * contiguous RISC code segments. 788 */ 789#define FA_RISC_CODE_ADDR 0x20000 790#define FA_RISC_CODE_SEGMENTS 2 791 792#define FA_FLASH_DESCR_ADDR_24 0x11000 793#define FA_FLASH_LAYOUT_ADDR_24 0x11400 794#define FA_NPIV_CONF0_ADDR_24 0x16000 795#define FA_NPIV_CONF1_ADDR_24 0x17000 796 797#define FA_FW_AREA_ADDR 0x40000 798#define FA_VPD_NVRAM_ADDR 0x48000 799#define FA_FEATURE_ADDR 0x4C000 800#define FA_FLASH_DESCR_ADDR 0x50000 801#define FA_FLASH_LAYOUT_ADDR 0x50400 802#define FA_HW_EVENT0_ADDR 0x54000 803#define FA_HW_EVENT1_ADDR 0x54400 804#define FA_HW_EVENT_SIZE 0x200 805#define FA_HW_EVENT_ENTRY_SIZE 4 806#define FA_NPIV_CONF0_ADDR 0x5C000 807#define FA_NPIV_CONF1_ADDR 0x5D000 808 809/* 810 * Flash Error Log Event Codes. 811 */ 812#define HW_EVENT_RESET_ERR 0xF00B 813#define HW_EVENT_ISP_ERR 0xF020 814#define HW_EVENT_PARITY_ERR 0xF022 815#define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023 816#define HW_EVENT_FLASH_FW_ERR 0xF024 817 818 uint32_t flash_data; /* Flash/NVRAM BIOS data. */ 819 820 uint32_t ctrl_status; /* Control/Status. */ 821#define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */ 822#define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */ 823#define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */ 824#define CSRX_FUNCTION BIT_15 /* Function number. */ 825 /* PCI-X Bus Mode. */ 826#define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8) 827#define PBM_PCI_33MHZ (0 << 8) 828#define PBM_PCIX_M1_66MHZ (1 << 8) 829#define PBM_PCIX_M1_100MHZ (2 << 8) 830#define PBM_PCIX_M1_133MHZ (3 << 8) 831#define PBM_PCIX_M2_66MHZ (5 << 8) 832#define PBM_PCIX_M2_100MHZ (6 << 8) 833#define PBM_PCIX_M2_133MHZ (7 << 8) 834#define PBM_PCI_66MHZ (8 << 8) 835 /* Max Write Burst byte count. */ 836#define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4) 837#define MWB_512_BYTES (0 << 4) 838#define MWB_1024_BYTES (1 << 4) 839#define MWB_2048_BYTES (2 << 4) 840#define MWB_4096_BYTES (3 << 4) 841 842#define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */ 843#define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */ 844#define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */ 845 846 uint32_t ictrl; /* Interrupt control. */ 847#define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */ 848 849 uint32_t istatus; /* Interrupt status. */ 850#define ISRX_RISC_INT BIT_3 /* RISC interrupt. */ 851 852 uint32_t unused_1[2]; /* Gap. */ 853 854 /* Request Queue. */ 855 uint32_t req_q_in; /* In-Pointer. */ 856 uint32_t req_q_out; /* Out-Pointer. */ 857 /* Response Queue. */ 858 uint32_t rsp_q_in; /* In-Pointer. */ 859 uint32_t rsp_q_out; /* Out-Pointer. */ 860 /* Priority Request Queue. */ 861 uint32_t preq_q_in; /* In-Pointer. */ 862 uint32_t preq_q_out; /* Out-Pointer. */ 863 864 uint32_t unused_2[2]; /* Gap. */ 865 866 /* ATIO Queue. */ 867 uint32_t atio_q_in; /* In-Pointer. */ 868 uint32_t atio_q_out; /* Out-Pointer. */ 869 870 uint32_t host_status; 871#define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ 872#define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ 873 874 uint32_t hccr; /* Host command & control register. */ 875 /* HCCR statuses. */ 876#define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ 877#define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ 878#define HCCRX_RISC_PAUSE BIT_4 /* RISC Pause mode bit. */ 879 /* HCCR commands. */ 880 /* NOOP. */ 881#define HCCRX_NOOP 0x00000000 882 /* Set RISC Reset. */ 883#define HCCRX_SET_RISC_RESET 0x10000000 884 /* Clear RISC Reset. */ 885#define HCCRX_CLR_RISC_RESET 0x20000000 886 /* Set RISC Pause. */ 887#define HCCRX_SET_RISC_PAUSE 0x30000000 888 /* Releases RISC Pause. */ 889#define HCCRX_REL_RISC_PAUSE 0x40000000 890 /* Set HOST to RISC interrupt. */ 891#define HCCRX_SET_HOST_INT 0x50000000 892 /* Clear HOST to RISC interrupt. */ 893#define HCCRX_CLR_HOST_INT 0x60000000 894 /* Clear RISC to PCI interrupt. */ 895#define HCCRX_CLR_RISC_INT 0xA0000000 896 897 uint32_t gpiod; /* GPIO Data register. */ 898 899 /* LED update mask. */ 900#define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) 901 /* Data update mask. */ 902#define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) 903 /* Data update mask. */ 904#define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 905 /* LED control mask. */ 906#define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) 907 /* LED bit values. Color names as 908 * referenced in fw spec. 909 */ 910#define GPDX_LED_YELLOW_ON BIT_2 911#define GPDX_LED_GREEN_ON BIT_3 912#define GPDX_LED_AMBER_ON BIT_4 913 /* Data in/out. */ 914#define GPDX_DATA_INOUT (BIT_1|BIT_0) 915 916 uint32_t gpioe; /* GPIO Enable register. */ 917 /* Enable update mask. */ 918#define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) 919 /* Enable update mask. */ 920#define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 921 /* Enable. */ 922#define GPEX_ENABLE (BIT_1|BIT_0) 923 924 uint32_t iobase_addr; /* I/O Bus Base Address register. */ 925 926 uint32_t unused_3[10]; /* Gap. */ 927 928 uint16_t mailbox0; 929 uint16_t mailbox1; 930 uint16_t mailbox2; 931 uint16_t mailbox3; 932 uint16_t mailbox4; 933 uint16_t mailbox5; 934 uint16_t mailbox6; 935 uint16_t mailbox7; 936 uint16_t mailbox8; 937 uint16_t mailbox9; 938 uint16_t mailbox10; 939 uint16_t mailbox11; 940 uint16_t mailbox12; 941 uint16_t mailbox13; 942 uint16_t mailbox14; 943 uint16_t mailbox15; 944 uint16_t mailbox16; 945 uint16_t mailbox17; 946 uint16_t mailbox18; 947 uint16_t mailbox19; 948 uint16_t mailbox20; 949 uint16_t mailbox21; 950 uint16_t mailbox22; 951 uint16_t mailbox23; 952 uint16_t mailbox24; 953 uint16_t mailbox25; 954 uint16_t mailbox26; 955 uint16_t mailbox27; 956 uint16_t mailbox28; 957 uint16_t mailbox29; 958 uint16_t mailbox30; 959 uint16_t mailbox31; 960 961 uint32_t iobase_window; 962 uint32_t iobase_c4; 963 uint32_t iobase_c8; 964 uint32_t unused_4_1[6]; /* Gap. */ 965 uint32_t iobase_q; 966 uint32_t unused_5[2]; /* Gap. */ 967 uint32_t iobase_select; 968 uint32_t unused_6[2]; /* Gap. */ 969 uint32_t iobase_sdata; 970}; 971 972/* Trace Control *************************************************************/ 973 974#define TC_AEN_DISABLE 0 975 976#define TC_EFT_ENABLE 4 977#define TC_EFT_DISABLE 5 978 979#define TC_FCE_ENABLE 8 980#define TC_FCE_OPTIONS 0 981#define TC_FCE_DEFAULT_RX_SIZE 2112 982#define TC_FCE_DEFAULT_TX_SIZE 2112 983#define TC_FCE_DISABLE 9 984#define TC_FCE_DISABLE_TRACE BIT_0 985 986/* MID Support ***************************************************************/ 987 988#define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */ 989#define MAX_MULTI_ID_FABRIC 256 /* ... */ 990 991#define for_each_mapped_vp_idx(_ha, _idx) \ 992 for (_idx = find_next_bit((_ha)->vp_idx_map, \ 993 (_ha)->max_npiv_vports + 1, 1); \ 994 _idx <= (_ha)->max_npiv_vports; \ 995 _idx = find_next_bit((_ha)->vp_idx_map, \ 996 (_ha)->max_npiv_vports + 1, _idx + 1)) \ 997 998struct mid_conf_entry_24xx { 999 uint16_t reserved_1; 1000
1001 /* 1002 * BIT 0 = Enable Hard Loop Id 1003 * BIT 1 = Acquire Loop ID in LIPA 1004 * BIT 2 = ID not Acquired 1005 * BIT 3 = Enable VP 1006 * BIT 4 = Enable Initiator Mode 1007 * BIT 5 = Disable Target Mode 1008 * BIT 6-7 = Reserved 1009 */ 1010 uint8_t options; 1011 1012 uint8_t hard_address; 1013 1014 uint8_t port_name[WWN_SIZE]; 1015 uint8_t node_name[WWN_SIZE]; 1016}; 1017 1018struct mid_init_cb_24xx { 1019 struct init_cb_24xx init_cb; 1020 1021 uint16_t count; 1022 uint16_t options; 1023 1024 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; 1025}; 1026 1027 1028struct mid_db_entry_24xx { 1029 uint16_t status; 1030#define MDBS_NON_PARTIC BIT_3 1031#define MDBS_ID_ACQUIRED BIT_1 1032#define MDBS_ENABLED BIT_0 1033 1034 uint8_t options; 1035 uint8_t hard_address; 1036 1037 uint8_t port_name[WWN_SIZE]; 1038 uint8_t node_name[WWN_SIZE]; 1039 1040 uint8_t port_id[3]; 1041 uint8_t reserved_1; 1042}; 1043 1044/* 1045 * Virtual Port Control IOCB 1046 */ 1047#define VP_CTRL_IOCB_TYPE 0x30 /* Vitual Port Control entry. */ 1048struct vp_ctrl_entry_24xx { 1049 uint8_t entry_type; /* Entry type. */ 1050 uint8_t entry_count; /* Entry count. */ 1051 uint8_t sys_define; /* System defined. */ 1052 uint8_t entry_status; /* Entry Status. */ 1053 1054 uint32_t handle; /* System handle. */ 1055 1056 uint16_t vp_idx_failed; 1057 1058 uint16_t comp_status; /* Completion status. */ 1059#define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */ 1060#define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */ 1061#define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */ 1062 1063 uint16_t command; 1064#define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */ 1065#define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */ 1066#define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */ 1067#define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */ 1068#define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */ 1069 1070 uint16_t vp_count; 1071 1072 uint8_t vp_idx_map[16]; 1073 uint16_t flags; 1074 uint16_t id; 1075 uint16_t reserved_4; 1076 uint16_t hopct; 1077 uint8_t reserved_5[24]; 1078}; 1079 1080/* 1081 * Modify Virtual Port Configuration IOCB 1082 */ 1083#define VP_CONFIG_IOCB_TYPE 0x31 /* Vitual Port Config entry. */ 1084struct vp_config_entry_24xx { 1085 uint8_t entry_type; /* Entry type. */ 1086 uint8_t entry_count; /* Entry count. */ 1087 uint8_t handle_count; 1088 uint8_t entry_status; /* Entry Status. */ 1089 1090 uint32_t handle; /* System handle. */ 1091 1092 uint16_t flags; 1093#define CS_VF_BIND_VPORTS_TO_VF BIT_0 1094#define CS_VF_SET_QOS_OF_VPORTS BIT_1 1095#define CS_VF_SET_HOPS_OF_VPORTS BIT_2 1096 1097 uint16_t comp_status; /* Completion status. */ 1098#define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */ 1099#define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */ 1100#define CS_VCT_ERROR 0x03 /* Unknown error. */ 1101#define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */ 1102#define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */ 1103 1104 uint8_t command; 1105#define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */ 1106#define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */ 1107 1108 uint8_t vp_count; 1109 1110 uint8_t vp_index1; 1111 uint8_t vp_index2; 1112 1113 uint8_t options_idx1; 1114 uint8_t hard_address_idx1; 1115 uint16_t reserved_vp1; 1116 uint8_t port_name_idx1[WWN_SIZE]; 1117 uint8_t node_name_idx1[WWN_SIZE]; 1118 1119 uint8_t options_idx2; 1120 uint8_t hard_address_idx2; 1121 uint16_t reserved_vp2; 1122 uint8_t port_name_idx2[WWN_SIZE]; 1123 uint8_t node_name_idx2[WWN_SIZE]; 1124 uint16_t id; 1125 uint16_t reserved_4; 1126 uint16_t hopct; 1127 uint8_t reserved_5; 1128}; 1129 1130#define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */ 1131struct vp_rpt_id_entry_24xx { 1132 uint8_t entry_type; /* Entry type. */ 1133 uint8_t entry_count; /* Entry count. */ 1134 uint8_t sys_define; /* System defined. */ 1135 uint8_t entry_status; /* Entry Status. */ 1136 1137 uint32_t handle; /* System handle. */ 1138 1139 uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */ 1140 /* Format 1 -- | VP count |. */ 1141 uint16_t vp_idx; /* Format 0 -- Reserved. */ 1142 /* Format 1 -- VP status and index. */ 1143 1144 uint8_t port_id[3]; 1145 uint8_t format; 1146 1147 uint8_t vp_idx_map[16]; 1148 1149 uint8_t reserved_4[32]; 1150}; 1151 1152#define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */ 1153struct vf_evfp_entry_24xx { 1154 uint8_t entry_type; /* Entry type. */ 1155 uint8_t entry_count; /* Entry count. */ 1156 uint8_t sys_define; /* System defined. */ 1157 uint8_t entry_status; /* Entry Status. */ 1158 1159 uint32_t handle; /* System handle. */ 1160 uint16_t comp_status; /* Completion status. */ 1161 uint16_t timeout; /* timeout */ 1162 uint16_t adim_tagging_mode; 1163 1164 uint16_t vfport_id; 1165 uint32_t exch_addr; 1166 1167 uint16_t nport_handle; /* N_PORT handle. */ 1168 uint16_t control_flags; 1169 uint32_t io_parameter_0; 1170 uint32_t io_parameter_1; 1171 uint32_t tx_address[2]; /* Data segment 0 address. */ 1172 uint32_t tx_len; /* Data segment 0 length. */ 1173 uint32_t rx_address[2]; /* Data segment 1 address. */ 1174 uint32_t rx_len; /* Data segment 1 length. */ 1175}; 1176 1177/* END MID Support ***********************************************************/ 1178 1179/* Flash Description Table ***************************************************/ 1180 1181struct qla_fdt_layout { 1182 uint8_t sig[4]; 1183 uint16_t version; 1184 uint16_t len; 1185 uint16_t checksum; 1186 uint8_t unused1[2]; 1187 uint8_t model[16]; 1188 uint16_t man_id; 1189 uint16_t id; 1190 uint8_t flags; 1191 uint8_t erase_cmd; 1192 uint8_t alt_erase_cmd; 1193 uint8_t wrt_enable_cmd; 1194 uint8_t wrt_enable_bits; 1195 uint8_t wrt_sts_reg_cmd; 1196 uint8_t unprotect_sec_cmd; 1197 uint8_t read_man_id_cmd; 1198 uint32_t block_size; 1199 uint32_t alt_block_size; 1200 uint32_t flash_size; 1201 uint32_t wrt_enable_data; 1202 uint8_t read_id_addr_len; 1203 uint8_t wrt_disable_bits; 1204 uint8_t read_dev_id_len; 1205 uint8_t chip_erase_cmd; 1206 uint16_t read_timeout; 1207 uint8_t protect_sec_cmd; 1208 uint8_t unused2[65]; 1209}; 1210 1211/* Flash Layout Table ********************************************************/ 1212 1213struct qla_flt_location { 1214 uint8_t sig[4]; 1215 uint32_t start_lo; 1216 uint32_t start_hi; 1217 uint16_t unused; 1218 uint16_t checksum; 1219}; 1220 1221struct qla_flt_header { 1222 uint16_t version; 1223 uint16_t length; 1224 uint16_t checksum; 1225 uint16_t unused; 1226}; 1227 1228#define FLT_REG_FW 0x01 1229#define FLT_REG_BOOT_CODE 0x07 1230#define FLT_REG_VPD_0 0x14 1231#define FLT_REG_NVRAM_0 0x15 1232#define FLT_REG_VPD_1 0x16 1233#define FLT_REG_NVRAM_1 0x17 1234#define FLT_REG_FDT 0x1a 1235#define FLT_REG_FLT 0x1c 1236#define FLT_REG_HW_EVENT_0 0x1d 1237#define FLT_REG_HW_EVENT_1 0x1f 1238#define FLT_REG_NPIV_CONF_0 0x29 1239#define FLT_REG_NPIV_CONF_1 0x2a 1240 1241struct qla_flt_region { 1242 uint32_t code; 1243 uint32_t size; 1244 uint32_t start; 1245 uint32_t end; 1246}; 1247 1248/* Flash NPIV Configuration Table ********************************************/ 1249 1250struct qla_npiv_header { 1251 uint8_t sig[2]; 1252 uint16_t version; 1253 uint16_t entries; 1254 uint16_t unused[4]; 1255 uint16_t checksum; 1256}; 1257 1258struct qla_npiv_entry { 1259 uint16_t flags; 1260 uint16_t vf_id; 1261 uint16_t qos; 1262 uint16_t unused1; 1263 uint8_t port_name[WWN_SIZE]; 1264 uint8_t node_name[WWN_SIZE]; 1265}; 1266 1267/* 84XX Support **************************************************************/ 1268 1269#define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */ 1270#define A84_PANIC_RECOVERY 0x1 1271#define A84_OP_LOGIN_COMPLETE 0x2 1272#define A84_DIAG_LOGIN_COMPLETE 0x3 1273#define A84_GOLD_LOGIN_COMPLETE 0x4 1274 1275#define MBC_ISP84XX_RESET 0x3a /* Reset. */ 1276 1277#define FSTATE_REMOTE_FC_DOWN BIT_0 1278#define FSTATE_NSL_LINK_DOWN BIT_1 1279#define FSTATE_IS_DIAG_FW BIT_2 1280#define FSTATE_LOGGED_IN BIT_3 1281#define FSTATE_WAITING_FOR_VERIFY BIT_4 1282 1283#define VERIFY_CHIP_IOCB_TYPE 0x1B 1284struct verify_chip_entry_84xx { 1285 uint8_t entry_type; 1286 uint8_t entry_count; 1287 uint8_t sys_defined; 1288 uint8_t entry_status; 1289 1290 uint32_t handle; 1291 1292 uint16_t options; 1293#define VCO_DONT_UPDATE_FW BIT_0 1294#define VCO_FORCE_UPDATE BIT_1 1295#define VCO_DONT_RESET_UPDATE BIT_2 1296#define VCO_DIAG_FW BIT_3 1297#define VCO_END_OF_DATA BIT_14 1298#define VCO_ENABLE_DSD BIT_15 1299 1300 uint16_t reserved_1; 1301 1302 uint16_t data_seg_cnt; 1303 uint16_t reserved_2[3]; 1304 1305 uint32_t fw_ver; 1306 uint32_t exchange_address; 1307 1308 uint32_t reserved_3[3]; 1309 uint32_t fw_size; 1310 uint32_t fw_seq_size; 1311 uint32_t relative_offset; 1312 1313 uint32_t dseg_address[2]; 1314 uint32_t dseg_length; 1315}; 1316 1317struct verify_chip_rsp_84xx { 1318 uint8_t entry_type; 1319 uint8_t entry_count; 1320 uint8_t sys_defined; 1321 uint8_t entry_status; 1322 1323 uint32_t handle; 1324 1325 uint16_t comp_status; 1326#define CS_VCS_CHIP_FAILURE 0x3 1327#define CS_VCS_BAD_EXCHANGE 0x8 1328#define CS_VCS_SEQ_COMPLETEi 0x40 1329 1330 uint16_t failure_code; 1331#define VFC_CHECKSUM_ERROR 0x1 1332#define VFC_INVALID_LEN 0x2 1333#define VFC_ALREADY_IN_PROGRESS 0x8 1334 1335 uint16_t reserved_1[4]; 1336 1337 uint32_t fw_ver; 1338 uint32_t exchange_address; 1339 1340 uint32_t reserved_2[6]; 1341}; 1342 1343#define ACCESS_CHIP_IOCB_TYPE 0x2B 1344struct access_chip_84xx { 1345 uint8_t entry_type; 1346 uint8_t entry_count; 1347 uint8_t sys_defined; 1348 uint8_t entry_status; 1349 1350 uint32_t handle; 1351 1352 uint16_t options; 1353#define ACO_DUMP_MEMORY 0x0 1354#define ACO_LOAD_MEMORY 0x1 1355#define ACO_CHANGE_CONFIG_PARAM 0x2 1356#define ACO_REQUEST_INFO 0x3 1357 1358 uint16_t reserved1; 1359 1360 uint16_t dseg_count; 1361 uint16_t reserved2[3]; 1362 1363 uint32_t parameter1; 1364 uint32_t parameter2; 1365 uint32_t parameter3; 1366 1367 uint32_t reserved3[3]; 1368 uint32_t total_byte_cnt; 1369 uint32_t reserved4; 1370 1371 uint32_t dseg_address[2]; 1372 uint32_t dseg_length; 1373}; 1374 1375struct access_chip_rsp_84xx { 1376 uint8_t entry_type; 1377 uint8_t entry_count; 1378 uint8_t sys_defined; 1379 uint8_t entry_status; 1380 1381 uint32_t handle; 1382 1383 uint16_t comp_status; 1384 uint16_t failure_code; 1385 uint32_t residual_count; 1386 1387 uint32_t reserved[12]; 1388}; 1389#endif 1390