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26#ifndef _IPW2100_H
27#define _IPW2100_H
28
29#include <linux/sched.h>
30#include <linux/interrupt.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/list.h>
34#include <linux/delay.h>
35#include <linux/skbuff.h>
36#include <asm/io.h>
37#include <linux/socket.h>
38#include <linux/if_arp.h>
39#include <linux/wireless.h>
40#include <net/iw_handler.h>
41
42#include <net/ieee80211.h>
43
44#ifdef CONFIG_IPW2100_MONITOR
45#include <net/ieee80211_radiotap.h>
46#endif
47
48#include <linux/workqueue.h>
49#include <linux/mutex.h>
50
51struct ipw2100_priv;
52struct ipw2100_tx_packet;
53struct ipw2100_rx_packet;
54
55#define IPW_DL_UNINIT 0x80000000
56#define IPW_DL_NONE 0x00000000
57#define IPW_DL_ALL 0x7FFFFFFF
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84
85#define IPW_DL_ERROR (1<<0)
86#define IPW_DL_WARNING (1<<1)
87#define IPW_DL_INFO (1<<2)
88#define IPW_DL_WX (1<<3)
89#define IPW_DL_HC (1<<5)
90#define IPW_DL_STATE (1<<6)
91
92#define IPW_DL_NOTIF (1<<10)
93#define IPW_DL_SCAN (1<<11)
94#define IPW_DL_ASSOC (1<<12)
95#define IPW_DL_DROP (1<<13)
96
97#define IPW_DL_IOCTL (1<<14)
98#define IPW_DL_RF_KILL (1<<17)
99
100#define IPW_DL_MANAGE (1<<15)
101#define IPW_DL_FW (1<<16)
102
103#define IPW_DL_FRAG (1<<21)
104#define IPW_DL_WEP (1<<22)
105#define IPW_DL_TX (1<<23)
106#define IPW_DL_RX (1<<24)
107#define IPW_DL_ISR (1<<25)
108#define IPW_DL_IO (1<<26)
109#define IPW_DL_TRACE (1<<28)
110
111#define IPW_DEBUG_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
112#define IPW_DEBUG_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
113#define IPW_DEBUG_INFO(f...) IPW_DEBUG(IPW_DL_INFO, ## f)
114#define IPW_DEBUG_WX(f...) IPW_DEBUG(IPW_DL_WX, ## f)
115#define IPW_DEBUG_SCAN(f...) IPW_DEBUG(IPW_DL_SCAN, ## f)
116#define IPW_DEBUG_NOTIF(f...) IPW_DEBUG(IPW_DL_NOTIF, ## f)
117#define IPW_DEBUG_TRACE(f...) IPW_DEBUG(IPW_DL_TRACE, ## f)
118#define IPW_DEBUG_RX(f...) IPW_DEBUG(IPW_DL_RX, ## f)
119#define IPW_DEBUG_TX(f...) IPW_DEBUG(IPW_DL_TX, ## f)
120#define IPW_DEBUG_ISR(f...) IPW_DEBUG(IPW_DL_ISR, ## f)
121#define IPW_DEBUG_MANAGEMENT(f...) IPW_DEBUG(IPW_DL_MANAGE, ## f)
122#define IPW_DEBUG_WEP(f...) IPW_DEBUG(IPW_DL_WEP, ## f)
123#define IPW_DEBUG_HC(f...) IPW_DEBUG(IPW_DL_HC, ## f)
124#define IPW_DEBUG_FRAG(f...) IPW_DEBUG(IPW_DL_FRAG, ## f)
125#define IPW_DEBUG_FW(f...) IPW_DEBUG(IPW_DL_FW, ## f)
126#define IPW_DEBUG_RF_KILL(f...) IPW_DEBUG(IPW_DL_RF_KILL, ## f)
127#define IPW_DEBUG_DROP(f...) IPW_DEBUG(IPW_DL_DROP, ## f)
128#define IPW_DEBUG_IO(f...) IPW_DEBUG(IPW_DL_IO, ## f)
129#define IPW_DEBUG_IOCTL(f...) IPW_DEBUG(IPW_DL_IOCTL, ## f)
130#define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
131#define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
132
133enum {
134 IPW_HW_STATE_DISABLED = 1,
135 IPW_HW_STATE_ENABLED = 0
136};
137
138struct ssid_context {
139 char ssid[IW_ESSID_MAX_SIZE + 1];
140 int ssid_len;
141 unsigned char bssid[ETH_ALEN];
142 int port_type;
143 int channel;
144
145};
146
147extern const char *port_type_str[];
148extern const char *band_str[];
149
150#define NUMBER_OF_BD_PER_COMMAND_PACKET 1
151#define NUMBER_OF_BD_PER_DATA_PACKET 2
152
153#define IPW_MAX_BDS 6
154#define NUMBER_OF_OVERHEAD_BDS_PER_PACKETR 2
155#define NUMBER_OF_BDS_TO_LEAVE_FOR_COMMANDS 1
156
157#define REQUIRED_SPACE_IN_RING_FOR_COMMAND_PACKET \
158 (IPW_BD_QUEUE_W_R_MIN_SPARE + NUMBER_OF_BD_PER_COMMAND_PACKET)
159
160struct bd_status {
161 union {
162 struct {
163 u8 nlf:1, txType:2, intEnabled:1, reserved:4;
164 } fields;
165 u8 field;
166 } info;
167} __attribute__ ((packed));
168
169struct ipw2100_bd {
170 u32 host_addr;
171 u32 buf_length;
172 struct bd_status status;
173
174
175 u8 num_fragments;
176 u8 reserved[6];
177} __attribute__ ((packed));
178
179#define IPW_BD_QUEUE_LENGTH(n) (1<<n)
180#define IPW_BD_ALIGNMENT(L) (L*sizeof(struct ipw2100_bd))
181
182#define IPW_BD_STATUS_TX_FRAME_802_3 0x00
183#define IPW_BD_STATUS_TX_FRAME_NOT_LAST_FRAGMENT 0x01
184#define IPW_BD_STATUS_TX_FRAME_COMMAND 0x02
185#define IPW_BD_STATUS_TX_FRAME_802_11 0x04
186#define IPW_BD_STATUS_TX_INTERRUPT_ENABLE 0x08
187
188struct ipw2100_bd_queue {
189
190 struct ipw2100_bd *drv;
191
192
193 dma_addr_t nic;
194
195
196 u32 size;
197
198
199 u32 entries;
200
201
202 u32 available;
203
204
205
206 u32 oldest;
207
208
209 u32 next;
210};
211
212#define RX_QUEUE_LENGTH 256
213#define TX_QUEUE_LENGTH 256
214#define HW_QUEUE_LENGTH 256
215
216#define TX_PENDED_QUEUE_LENGTH (TX_QUEUE_LENGTH / NUMBER_OF_BD_PER_DATA_PACKET)
217
218#define STATUS_TYPE_MASK 0x0000000f
219#define COMMAND_STATUS_VAL 0
220#define STATUS_CHANGE_VAL 1
221#define P80211_DATA_VAL 2
222#define P8023_DATA_VAL 3
223#define HOST_NOTIFICATION_VAL 4
224
225#define IPW2100_RSSI_TO_DBM (-98)
226
227struct ipw2100_status {
228 u32 frame_size;
229 u16 status_fields;
230 u8 flags;
231#define IPW_STATUS_FLAG_DECRYPTED (1<<0)
232#define IPW_STATUS_FLAG_WEP_ENCRYPTED (1<<1)
233#define IPW_STATUS_FLAG_CRC_ERROR (1<<2)
234 u8 rssi;
235} __attribute__ ((packed));
236
237struct ipw2100_status_queue {
238
239 struct ipw2100_status *drv;
240
241
242 dma_addr_t nic;
243
244
245 u32 size;
246};
247
248#define HOST_COMMAND_PARAMS_REG_LEN 100
249#define CMD_STATUS_PARAMS_REG_LEN 3
250
251#define IPW_WPA_CAPABILITIES 0x1
252#define IPW_WPA_LISTENINTERVAL 0x2
253#define IPW_WPA_AP_ADDRESS 0x4
254
255#define IPW_MAX_VAR_IE_LEN ((HOST_COMMAND_PARAMS_REG_LEN - 4) * sizeof(u32))
256
257struct ipw2100_wpa_assoc_frame {
258 u16 fixed_ie_mask;
259 struct {
260 u16 capab_info;
261 u16 listen_interval;
262 u8 current_ap[ETH_ALEN];
263 } fixed_ies;
264 u32 var_ie_len;
265 u8 var_ie[IPW_MAX_VAR_IE_LEN];
266};
267
268#define IPW_BSS 1
269#define IPW_MONITOR 2
270#define IPW_IBSS 3
271
272
273
274
275
276struct ipw2100_cmd_header {
277 u32 host_command_reg;
278 u32 host_command_reg1;
279 u32 sequence;
280 u32 host_command_len_reg;
281 u32 host_command_params_reg[HOST_COMMAND_PARAMS_REG_LEN];
282 u32 cmd_status_reg;
283 u32 cmd_status_params_reg[CMD_STATUS_PARAMS_REG_LEN];
284 u32 rxq_base_ptr;
285 u32 rxq_next_ptr;
286 u32 rxq_host_ptr;
287 u32 txq_base_ptr;
288 u32 txq_next_ptr;
289 u32 txq_host_ptr;
290 u32 tx_status_reg;
291 u32 reserved;
292 u32 status_change_reg;
293 u32 reserved1[3];
294 u32 *ordinal1_ptr;
295 u32 *ordinal2_ptr;
296} __attribute__ ((packed));
297
298struct ipw2100_data_header {
299 u32 host_command_reg;
300 u32 host_command_reg1;
301 u8 encrypted;
302 u8 needs_encryption;
303 u8 wep_index;
304 u8 key_size;
305 u8 key[16];
306 u8 reserved[10];
307 u8 src_addr[ETH_ALEN];
308 u8 dst_addr[ETH_ALEN];
309 u16 fragment_size;
310} __attribute__ ((packed));
311
312
313struct host_command {
314 u32 host_command;
315 u32 host_command1;
316 u32 host_command_sequence;
317 u32 host_command_length;
318 u32 host_command_parameters[HOST_COMMAND_PARAMS_REG_LEN];
319} __attribute__ ((packed));
320
321typedef enum {
322 POWER_ON_RESET,
323 EXIT_POWER_DOWN_RESET,
324 SW_RESET,
325 EEPROM_RW,
326 SW_RE_INIT
327} ipw2100_reset_event;
328
329enum {
330 COMMAND = 0xCAFE,
331 DATA,
332 RX
333};
334
335struct ipw2100_tx_packet {
336 int type;
337 int index;
338 union {
339 struct {
340 struct ipw2100_cmd_header *cmd;
341 dma_addr_t cmd_phys;
342 } c_struct;
343 struct {
344 struct ipw2100_data_header *data;
345 dma_addr_t data_phys;
346 struct ieee80211_txb *txb;
347 } d_struct;
348 } info;
349 int jiffy_start;
350
351 struct list_head list;
352};
353
354struct ipw2100_rx_packet {
355 struct ipw2100_rx *rxp;
356 dma_addr_t dma_addr;
357 int jiffy_start;
358 struct sk_buff *skb;
359 struct list_head list;
360};
361
362#define FRAG_DISABLED (1<<31)
363#define RTS_DISABLED (1<<31)
364#define MAX_RTS_THRESHOLD 2304U
365#define MIN_RTS_THRESHOLD 1U
366#define DEFAULT_RTS_THRESHOLD 1000U
367
368#define DEFAULT_BEACON_INTERVAL 100U
369#define DEFAULT_SHORT_RETRY_LIMIT 7U
370#define DEFAULT_LONG_RETRY_LIMIT 4U
371
372struct ipw2100_ordinals {
373 u32 table1_addr;
374 u32 table2_addr;
375 u32 table1_size;
376 u32 table2_size;
377};
378
379
380struct ipw2100_notification {
381 u32 hnhdr_subtype;
382 u32 hnhdr_size;
383
384
385} __attribute__ ((packed));
386
387#define MAX_KEY_SIZE 16
388#define MAX_KEYS 8
389
390#define IPW2100_WEP_ENABLE (1<<1)
391#define IPW2100_WEP_DROP_CLEAR (1<<2)
392
393#define IPW_NONE_CIPHER (1<<0)
394#define IPW_WEP40_CIPHER (1<<1)
395#define IPW_TKIP_CIPHER (1<<2)
396#define IPW_CCMP_CIPHER (1<<4)
397#define IPW_WEP104_CIPHER (1<<5)
398#define IPW_CKIP_CIPHER (1<<6)
399
400#define IPW_AUTH_OPEN 0
401#define IPW_AUTH_SHARED 1
402#define IPW_AUTH_LEAP 2
403#define IPW_AUTH_LEAP_CISCO_ID 0x80
404
405struct statistic {
406 int value;
407 int hi;
408 int lo;
409};
410
411#define INIT_STAT(x) do { \
412 (x)->value = (x)->hi = 0; \
413 (x)->lo = 0x7fffffff; \
414} while (0)
415#define SET_STAT(x,y) do { \
416 (x)->value = y; \
417 if ((x)->value > (x)->hi) (x)->hi = (x)->value; \
418 if ((x)->value < (x)->lo) (x)->lo = (x)->value; \
419} while (0)
420#define INC_STAT(x) do { if (++(x)->value > (x)->hi) (x)->hi = (x)->value; } \
421while (0)
422#define DEC_STAT(x) do { if (--(x)->value < (x)->lo) (x)->lo = (x)->value; } \
423while (0)
424
425#define IPW2100_ERROR_QUEUE 5
426
427
428enum {
429#ifdef CONFIG_PM
430 IPW2100_PM_DISABLED = 0,
431 PM_STATE_SIZE = 16,
432#else
433 IPW2100_PM_DISABLED = 1,
434 PM_STATE_SIZE = 0,
435#endif
436};
437
438#define STATUS_POWERED (1<<0)
439#define STATUS_CMD_ACTIVE (1<<1)
440#define STATUS_RUNNING (1<<2)
441#define STATUS_ENABLED (1<<3)
442#define STATUS_STOPPING (1<<4)
443#define STATUS_INITIALIZED (1<<5)
444#define STATUS_ASSOCIATING (1<<9)
445#define STATUS_ASSOCIATED (1<<10)
446#define STATUS_INT_ENABLED (1<<11)
447#define STATUS_RF_KILL_HW (1<<12)
448#define STATUS_RF_KILL_SW (1<<13)
449#define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
450#define STATUS_EXIT_PENDING (1<<14)
451
452#define STATUS_SCAN_PENDING (1<<23)
453#define STATUS_SCANNING (1<<24)
454#define STATUS_SCAN_ABORTING (1<<25)
455#define STATUS_SCAN_COMPLETE (1<<26)
456#define STATUS_WX_EVENT_PENDING (1<<27)
457#define STATUS_RESET_PENDING (1<<29)
458#define STATUS_SECURITY_UPDATED (1<<30)
459
460
461#define IPW_STATE_INITIALIZED (1<<0)
462#define IPW_STATE_COUNTRY_FOUND (1<<1)
463#define IPW_STATE_ASSOCIATED (1<<2)
464#define IPW_STATE_ASSN_LOST (1<<3)
465#define IPW_STATE_ASSN_CHANGED (1<<4)
466#define IPW_STATE_SCAN_COMPLETE (1<<5)
467#define IPW_STATE_ENTERED_PSP (1<<6)
468#define IPW_STATE_LEFT_PSP (1<<7)
469#define IPW_STATE_RF_KILL (1<<8)
470#define IPW_STATE_DISABLED (1<<9)
471#define IPW_STATE_POWER_DOWN (1<<10)
472#define IPW_STATE_SCANNING (1<<11)
473
474#define CFG_STATIC_CHANNEL (1<<0)
475#define CFG_STATIC_ESSID (1<<1)
476#define CFG_STATIC_BSSID (1<<2)
477#define CFG_CUSTOM_MAC (1<<3)
478#define CFG_LONG_PREAMBLE (1<<4)
479#define CFG_ASSOCIATE (1<<6)
480#define CFG_FIXED_RATE (1<<7)
481#define CFG_ADHOC_CREATE (1<<8)
482#define CFG_PASSIVE_SCAN (1<<10)
483#ifdef CONFIG_IPW2100_MONITOR
484#define CFG_CRC_CHECK (1<<11)
485#endif
486
487#define CAP_SHARED_KEY (1<<0)
488#define CAP_PRIVACY_ON (1<<1)
489
490struct ipw2100_priv {
491
492 int stop_hang_check;
493 int stop_rf_kill;
494
495 struct ieee80211_device *ieee;
496 unsigned long status;
497 unsigned long config;
498 unsigned long capability;
499
500
501 int resets;
502 int reset_backoff;
503
504
505 u8 essid[IW_ESSID_MAX_SIZE];
506 u8 essid_len;
507 u8 bssid[ETH_ALEN];
508 u8 channel;
509 int last_mode;
510
511 unsigned long connect_start;
512 unsigned long last_reset;
513
514 u32 channel_mask;
515 u32 fatal_error;
516 u32 fatal_errors[IPW2100_ERROR_QUEUE];
517 u32 fatal_index;
518 int eeprom_version;
519 int firmware_version;
520 unsigned long hw_features;
521 int hangs;
522 u32 last_rtc;
523 int dump_raw;
524 u8 *snapshot[0x30];
525
526 u8 mandatory_bssid_mac[ETH_ALEN];
527 u8 mac_addr[ETH_ALEN];
528
529 int power_mode;
530
531 int messages_sent;
532
533 int short_retry_limit;
534 int long_retry_limit;
535
536 u32 rts_threshold;
537 u32 frag_threshold;
538
539 int in_isr;
540
541 u32 tx_rates;
542 int tx_power;
543 u32 beacon_interval;
544
545 char nick[IW_ESSID_MAX_SIZE + 1];
546
547 struct ipw2100_status_queue status_queue;
548
549 struct statistic txq_stat;
550 struct statistic rxq_stat;
551 struct ipw2100_bd_queue rx_queue;
552 struct ipw2100_bd_queue tx_queue;
553 struct ipw2100_rx_packet *rx_buffers;
554
555 struct statistic fw_pend_stat;
556 struct list_head fw_pend_list;
557
558 struct statistic msg_free_stat;
559 struct statistic msg_pend_stat;
560 struct list_head msg_free_list;
561 struct list_head msg_pend_list;
562 struct ipw2100_tx_packet *msg_buffers;
563
564 struct statistic tx_free_stat;
565 struct statistic tx_pend_stat;
566 struct list_head tx_free_list;
567 struct list_head tx_pend_list;
568 struct ipw2100_tx_packet *tx_buffers;
569
570 struct ipw2100_ordinals ordinals;
571
572 struct pci_dev *pci_dev;
573
574 struct proc_dir_entry *dir_dev;
575
576 struct net_device *net_dev;
577 struct iw_statistics wstats;
578
579 struct iw_public_data wireless_data;
580
581 struct tasklet_struct irq_tasklet;
582
583 struct workqueue_struct *workqueue;
584 struct delayed_work reset_work;
585 struct delayed_work security_work;
586 struct delayed_work wx_event_work;
587 struct delayed_work hang_check;
588 struct delayed_work rf_kill;
589 struct work_struct scan_event_now;
590 struct delayed_work scan_event_later;
591
592 int user_requested_scan;
593
594 u32 interrupts;
595 int tx_interrupts;
596 int rx_interrupts;
597 int inta_other;
598
599 spinlock_t low_lock;
600 struct mutex action_mutex;
601 struct mutex adapter_mutex;
602
603 wait_queue_head_t wait_command_queue;
604};
605
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611
612
613#define HOST_COMPLETE 2
614#define SYSTEM_CONFIG 6
615#define SSID 8
616#define MANDATORY_BSSID 9
617#define AUTHENTICATION_TYPE 10
618#define ADAPTER_ADDRESS 11
619#define PORT_TYPE 12
620#define INTERNATIONAL_MODE 13
621#define CHANNEL 14
622#define RTS_THRESHOLD 15
623#define FRAG_THRESHOLD 16
624#define POWER_MODE 17
625#define TX_RATES 18
626#define BASIC_TX_RATES 19
627#define WEP_KEY_INFO 20
628#define WEP_KEY_INDEX 25
629#define WEP_FLAGS 26
630#define ADD_MULTICAST 27
631#define CLEAR_ALL_MULTICAST 28
632#define BEACON_INTERVAL 29
633#define ATIM_WINDOW 30
634#define CLEAR_STATISTICS 31
635#define SEND 33
636#define TX_POWER_INDEX 36
637#define BROADCAST_SCAN 43
638#define CARD_DISABLE 44
639#define PREFERRED_BSSID 45
640#define SET_SCAN_OPTIONS 46
641#define SCAN_DWELL_TIME 47
642#define SWEEP_TABLE 48
643#define AP_OR_STATION_TABLE 49
644#define GROUP_ORDINALS 50
645#define SHORT_RETRY_LIMIT 51
646#define LONG_RETRY_LIMIT 52
647
648#define HOST_PRE_POWER_DOWN 58
649#define CARD_DISABLE_PHY_OFF 61
650#define MSDU_TX_RATES 62
651
652
653#define SET_STATION_STAT_BITS 64
654#define CLEAR_STATIONS_STAT_BITS 65
655#define LEAP_ROGUE_MODE 66
656#define SET_SECURITY_INFORMATION 67
657#define DISASSOCIATION_BSSID 68
658#define SET_WPA_IE 69
659
660
661#define IPW_CFG_MONITOR 0x00004
662#define IPW_CFG_PREAMBLE_AUTO 0x00010
663#define IPW_CFG_IBSS_AUTO_START 0x00020
664#define IPW_CFG_LOOPBACK 0x00100
665#define IPW_CFG_ANSWER_BCSSID_PROBE 0x00800
666#define IPW_CFG_BT_SIDEBAND_SIGNAL 0x02000
667#define IPW_CFG_802_1x_ENABLE 0x04000
668#define IPW_CFG_BSS_MASK 0x08000
669#define IPW_CFG_IBSS_MASK 0x10000
670
671#define IPW_SCAN_NOASSOCIATE (1<<0)
672#define IPW_SCAN_MIXED_CELL (1<<1)
673
674#define IPW_SCAN_PASSIVE (1<<3)
675
676#define IPW_NIC_FATAL_ERROR 0x2A7F0
677#define IPW_ERROR_ADDR(x) (x & 0x3FFFF)
678#define IPW_ERROR_CODE(x) ((x & 0xFF000000) >> 24)
679#define IPW2100_ERR_C3_CORRUPTION (0x10 << 24)
680#define IPW2100_ERR_MSG_TIMEOUT (0x11 << 24)
681#define IPW2100_ERR_FW_LOAD (0x12 << 24)
682
683#define IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND 0x200
684#define IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x0D80
685
686#define IPW_MEM_HOST_SHARED_RX_BD_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x40)
687#define IPW_MEM_HOST_SHARED_RX_STATUS_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x44)
688#define IPW_MEM_HOST_SHARED_RX_BD_SIZE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x48)
689#define IPW_MEM_HOST_SHARED_RX_READ_INDEX (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0xa0)
690
691#define IPW_MEM_HOST_SHARED_TX_QUEUE_BD_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x00)
692#define IPW_MEM_HOST_SHARED_TX_QUEUE_BD_SIZE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x04)
693#define IPW_MEM_HOST_SHARED_TX_QUEUE_READ_INDEX (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x80)
694
695#define IPW_MEM_HOST_SHARED_RX_WRITE_INDEX \
696 (IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND + 0x20)
697
698#define IPW_MEM_HOST_SHARED_TX_QUEUE_WRITE_INDEX \
699 (IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND)
700
701#define IPW_MEM_HOST_SHARED_ORDINALS_TABLE_1 (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x180)
702#define IPW_MEM_HOST_SHARED_ORDINALS_TABLE_2 (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x184)
703
704#define IPW2100_INTA_TX_TRANSFER (0x00000001)
705#define IPW2100_INTA_RX_TRANSFER (0x00000002)
706#define IPW2100_INTA_TX_COMPLETE (0x00000004)
707#define IPW2100_INTA_EVENT_INTERRUPT (0x00000008)
708#define IPW2100_INTA_STATUS_CHANGE (0x00000010)
709#define IPW2100_INTA_BEACON_PERIOD_EXPIRED (0x00000020)
710#define IPW2100_INTA_SLAVE_MODE_HOST_COMMAND_DONE (0x00010000)
711#define IPW2100_INTA_FW_INIT_DONE (0x01000000)
712#define IPW2100_INTA_FW_CALIBRATION_CALC (0x02000000)
713#define IPW2100_INTA_FATAL_ERROR (0x40000000)
714#define IPW2100_INTA_PARITY_ERROR (0x80000000)
715
716#define IPW_AUX_HOST_RESET_REG_PRINCETON_RESET (0x00000001)
717#define IPW_AUX_HOST_RESET_REG_FORCE_NMI (0x00000002)
718#define IPW_AUX_HOST_RESET_REG_PCI_HOST_CLUSTER_FATAL_NMI (0x00000004)
719#define IPW_AUX_HOST_RESET_REG_CORE_FATAL_NMI (0x00000008)
720#define IPW_AUX_HOST_RESET_REG_SW_RESET (0x00000080)
721#define IPW_AUX_HOST_RESET_REG_MASTER_DISABLED (0x00000100)
722#define IPW_AUX_HOST_RESET_REG_STOP_MASTER (0x00000200)
723
724#define IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY (0x00000001)
725#define IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY (0x00000002)
726#define IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE (0x00000004)
727#define IPW_AUX_HOST_GP_CNTRL_BITS_SYS_CONFIG (0x000007c0)
728#define IPW_AUX_HOST_GP_CNTRL_BIT_BUS_TYPE (0x00000200)
729#define IPW_AUX_HOST_GP_CNTRL_BIT_BAR0_BLOCK_SIZE (0x00000400)
730#define IPW_AUX_HOST_GP_CNTRL_BIT_USB_MODE (0x20000000)
731#define IPW_AUX_HOST_GP_CNTRL_BIT_HOST_FORCES_SYS_CLK (0x40000000)
732#define IPW_AUX_HOST_GP_CNTRL_BIT_FW_FORCES_SYS_CLK (0x80000000)
733
734#define IPW_BIT_GPIO_GPIO1_MASK 0x0000000C
735#define IPW_BIT_GPIO_GPIO3_MASK 0x000000C0
736#define IPW_BIT_GPIO_GPIO1_ENABLE 0x00000008
737#define IPW_BIT_GPIO_RF_KILL 0x00010000
738
739#define IPW_BIT_GPIO_LED_OFF 0x00002000
740
741#define IPW_REG_DOMAIN_0_OFFSET 0x0000
742#define IPW_REG_DOMAIN_1_OFFSET IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND
743
744#define IPW_REG_INTA IPW_REG_DOMAIN_0_OFFSET + 0x0008
745#define IPW_REG_INTA_MASK IPW_REG_DOMAIN_0_OFFSET + 0x000C
746#define IPW_REG_INDIRECT_ACCESS_ADDRESS IPW_REG_DOMAIN_0_OFFSET + 0x0010
747#define IPW_REG_INDIRECT_ACCESS_DATA IPW_REG_DOMAIN_0_OFFSET + 0x0014
748#define IPW_REG_AUTOINCREMENT_ADDRESS IPW_REG_DOMAIN_0_OFFSET + 0x0018
749#define IPW_REG_AUTOINCREMENT_DATA IPW_REG_DOMAIN_0_OFFSET + 0x001C
750#define IPW_REG_RESET_REG IPW_REG_DOMAIN_0_OFFSET + 0x0020
751#define IPW_REG_GP_CNTRL IPW_REG_DOMAIN_0_OFFSET + 0x0024
752#define IPW_REG_GPIO IPW_REG_DOMAIN_0_OFFSET + 0x0030
753#define IPW_REG_FW_TYPE IPW_REG_DOMAIN_1_OFFSET + 0x0188
754#define IPW_REG_FW_VERSION IPW_REG_DOMAIN_1_OFFSET + 0x018C
755#define IPW_REG_FW_COMPATABILITY_VERSION IPW_REG_DOMAIN_1_OFFSET + 0x0190
756
757#define IPW_REG_INDIRECT_ADDR_MASK 0x00FFFFFC
758
759#define IPW_INTERRUPT_MASK 0xC1010013
760
761#define IPW2100_CONTROL_REG 0x220000
762#define IPW2100_CONTROL_PHY_OFF 0x8
763
764#define IPW2100_COMMAND 0x00300004
765#define IPW2100_COMMAND_PHY_ON 0x0
766#define IPW2100_COMMAND_PHY_OFF 0x1
767
768
769#define IPW_REG_DOA_DEBUG_AREA_START IPW_REG_DOMAIN_0_OFFSET + 0x0090
770#define IPW_REG_DOA_DEBUG_AREA_END IPW_REG_DOMAIN_0_OFFSET + 0x00FF
771#define IPW_DATA_DOA_DEBUG_VALUE 0xd55555d5
772
773#define IPW_INTERNAL_REGISTER_HALT_AND_RESET 0x003000e0
774
775#define IPW_WAIT_CLOCK_STABILIZATION_DELAY 50
776#define IPW_WAIT_RESET_ARC_COMPLETE_DELAY 10
777#define IPW_WAIT_RESET_MASTER_ASSERT_COMPLETE_DELAY 10
778
779
780#define IPW_BD_QUEUE_W_R_MIN_SPARE 2
781
782#define IPW_CACHE_LINE_LENGTH_DEFAULT 0x80
783
784#define IPW_CARD_DISABLE_PHY_OFF_COMPLETE_WAIT 100
785#define IPW_PREPARE_POWER_DOWN_COMPLETE_WAIT 100
786
787#define IPW_HEADER_802_11_SIZE sizeof(struct ieee80211_hdr_3addr)
788#define IPW_MAX_80211_PAYLOAD_SIZE 2304U
789#define IPW_MAX_802_11_PAYLOAD_LENGTH 2312
790#define IPW_MAX_ACCEPTABLE_TX_FRAME_LENGTH 1536
791#define IPW_MIN_ACCEPTABLE_RX_FRAME_LENGTH 60
792#define IPW_MAX_ACCEPTABLE_RX_FRAME_LENGTH \
793 (IPW_MAX_ACCEPTABLE_TX_FRAME_LENGTH + IPW_HEADER_802_11_SIZE - \
794 sizeof(struct ethhdr))
795
796#define IPW_802_11_FCS_LENGTH 4
797#define IPW_RX_NIC_BUFFER_LENGTH \
798 (IPW_MAX_802_11_PAYLOAD_LENGTH + IPW_HEADER_802_11_SIZE + \
799 IPW_802_11_FCS_LENGTH)
800
801#define IPW_802_11_PAYLOAD_OFFSET \
802 (sizeof(struct ieee80211_hdr_3addr) + \
803 sizeof(struct ieee80211_snap_hdr))
804
805struct ipw2100_rx {
806 union {
807 unsigned char payload[IPW_RX_NIC_BUFFER_LENGTH];
808 struct ieee80211_hdr_4addr header;
809 u32 status;
810 struct ipw2100_notification notification;
811 struct ipw2100_cmd_header command;
812 } rx_data;
813} __attribute__ ((packed));
814
815
816#define TX_RATE_1_MBIT 0x0001
817#define TX_RATE_2_MBIT 0x0002
818#define TX_RATE_5_5_MBIT 0x0004
819#define TX_RATE_11_MBIT 0x0008
820#define TX_RATE_MASK 0x000F
821#define DEFAULT_TX_RATES 0x000F
822
823#define IPW_POWER_MODE_CAM 0x00
824#define IPW_POWER_INDEX_1 0x01
825#define IPW_POWER_INDEX_2 0x02
826#define IPW_POWER_INDEX_3 0x03
827#define IPW_POWER_INDEX_4 0x04
828#define IPW_POWER_INDEX_5 0x05
829#define IPW_POWER_AUTO 0x06
830#define IPW_POWER_MASK 0x0F
831#define IPW_POWER_ENABLED 0x10
832#define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
833
834#define IPW_TX_POWER_AUTO 0
835#define IPW_TX_POWER_ENHANCED 1
836
837#define IPW_TX_POWER_DEFAULT 32
838#define IPW_TX_POWER_MIN 0
839#define IPW_TX_POWER_MAX 16
840#define IPW_TX_POWER_MIN_DBM (-12)
841#define IPW_TX_POWER_MAX_DBM 16
842
843#define FW_SCAN_DONOT_ASSOCIATE 0x0001
844#define FW_SCAN_PASSIVE 0x0008
845
846#define REG_MIN_CHANNEL 0
847#define REG_MAX_CHANNEL 14
848
849#define REG_CHANNEL_MASK 0x00003FFF
850#define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
851
852#define DIVERSITY_EITHER 0
853#define DIVERSITY_ANTENNA_A 1
854#define DIVERSITY_ANTENNA_B 2
855
856#define HOST_COMMAND_WAIT 0
857#define HOST_COMMAND_NO_WAIT 1
858
859#define LOCK_NONE 0
860#define LOCK_DRIVER 1
861#define LOCK_FW 2
862
863#define TYPE_SWEEP_ORD 0x000D
864#define TYPE_IBSS_STTN_ORD 0x000E
865#define TYPE_BSS_AP_ORD 0x000F
866#define TYPE_RAW_BEACON_ENTRY 0x0010
867#define TYPE_CALIBRATION_DATA 0x0011
868#define TYPE_ROGUE_AP_DATA 0x0012
869#define TYPE_ASSOCIATION_REQUEST 0x0013
870#define TYPE_REASSOCIATION_REQUEST 0x0014
871
872#define HW_FEATURE_RFKILL 0x0001
873#define RF_KILLSWITCH_OFF 1
874#define RF_KILLSWITCH_ON 0
875
876#define IPW_COMMAND_POOL_SIZE 40
877
878#define IPW_START_ORD_TAB_1 1
879#define IPW_START_ORD_TAB_2 1000
880
881#define IPW_ORD_TAB_1_ENTRY_SIZE sizeof(u32)
882
883#define IS_ORDINAL_TABLE_ONE(mgr,id) \
884 ((id >= IPW_START_ORD_TAB_1) && (id < mgr->table1_size))
885#define IS_ORDINAL_TABLE_TWO(mgr,id) \
886 ((id >= IPW_START_ORD_TAB_2) && (id < (mgr->table2_size + IPW_START_ORD_TAB_2)))
887
888#define BSS_ID_LENGTH 6
889
890
891typedef enum _ORDINAL_TABLE_1 {
892
893 IPW_ORD_STAT_TX_HOST_REQUESTS = 1,
894 IPW_ORD_STAT_TX_HOST_COMPLETE,
895 IPW_ORD_STAT_TX_DIR_DATA,
896
897 IPW_ORD_STAT_TX_DIR_DATA1 = 4,
898 IPW_ORD_STAT_TX_DIR_DATA2,
899 IPW_ORD_STAT_TX_DIR_DATA5_5,
900 IPW_ORD_STAT_TX_DIR_DATA11,
901 IPW_ORD_STAT_TX_DIR_DATA22,
902
903 IPW_ORD_STAT_TX_NODIR_DATA1 = 13,
904 IPW_ORD_STAT_TX_NODIR_DATA2,
905 IPW_ORD_STAT_TX_NODIR_DATA5_5,
906 IPW_ORD_STAT_TX_NODIR_DATA11,
907
908 IPW_ORD_STAT_NULL_DATA = 21,
909 IPW_ORD_STAT_TX_RTS,
910 IPW_ORD_STAT_TX_CTS,
911 IPW_ORD_STAT_TX_ACK,
912 IPW_ORD_STAT_TX_ASSN,
913 IPW_ORD_STAT_TX_ASSN_RESP,
914 IPW_ORD_STAT_TX_REASSN,
915 IPW_ORD_STAT_TX_REASSN_RESP,
916 IPW_ORD_STAT_TX_PROBE,
917 IPW_ORD_STAT_TX_PROBE_RESP,
918 IPW_ORD_STAT_TX_BEACON,
919 IPW_ORD_STAT_TX_ATIM,
920 IPW_ORD_STAT_TX_DISASSN,
921 IPW_ORD_STAT_TX_AUTH,
922 IPW_ORD_STAT_TX_DEAUTH,
923
924 IPW_ORD_STAT_TX_TOTAL_BYTES = 41,
925 IPW_ORD_STAT_TX_RETRIES,
926 IPW_ORD_STAT_TX_RETRY1,
927 IPW_ORD_STAT_TX_RETRY2,
928 IPW_ORD_STAT_TX_RETRY5_5,
929 IPW_ORD_STAT_TX_RETRY11,
930
931 IPW_ORD_STAT_TX_FAILURES = 51,
932 IPW_ORD_STAT_TX_ABORT_AT_HOP,
933 IPW_ORD_STAT_TX_MAX_TRIES_IN_HOP,
934 IPW_ORD_STAT_TX_ABORT_LATE_DMA,
935 IPW_ORD_STAT_TX_ABORT_STX,
936 IPW_ORD_STAT_TX_DISASSN_FAIL,
937 IPW_ORD_STAT_TX_ERR_CTS,
938 IPW_ORD_STAT_TX_BPDU,
939 IPW_ORD_STAT_TX_ERR_ACK,
940
941
942 IPW_ORD_STAT_RX_HOST = 61,
943 IPW_ORD_STAT_RX_DIR_DATA,
944 IPW_ORD_STAT_RX_DIR_DATA1,
945 IPW_ORD_STAT_RX_DIR_DATA2,
946 IPW_ORD_STAT_RX_DIR_DATA5_5,
947 IPW_ORD_STAT_RX_DIR_DATA11,
948 IPW_ORD_STAT_RX_DIR_DATA22,
949
950 IPW_ORD_STAT_RX_NODIR_DATA = 71,
951 IPW_ORD_STAT_RX_NODIR_DATA1,
952 IPW_ORD_STAT_RX_NODIR_DATA2,
953 IPW_ORD_STAT_RX_NODIR_DATA5_5,
954 IPW_ORD_STAT_RX_NODIR_DATA11,
955
956 IPW_ORD_STAT_RX_NULL_DATA = 80,
957 IPW_ORD_STAT_RX_POLL,
958 IPW_ORD_STAT_RX_RTS,
959 IPW_ORD_STAT_RX_CTS,
960 IPW_ORD_STAT_RX_ACK,
961 IPW_ORD_STAT_RX_CFEND,
962 IPW_ORD_STAT_RX_CFEND_ACK,
963 IPW_ORD_STAT_RX_ASSN,
964 IPW_ORD_STAT_RX_ASSN_RESP,
965 IPW_ORD_STAT_RX_REASSN,
966 IPW_ORD_STAT_RX_REASSN_RESP,
967 IPW_ORD_STAT_RX_PROBE,
968 IPW_ORD_STAT_RX_PROBE_RESP,
969 IPW_ORD_STAT_RX_BEACON,
970 IPW_ORD_STAT_RX_ATIM,
971 IPW_ORD_STAT_RX_DISASSN,
972 IPW_ORD_STAT_RX_AUTH,
973 IPW_ORD_STAT_RX_DEAUTH,
974
975 IPW_ORD_STAT_RX_TOTAL_BYTES = 101,
976 IPW_ORD_STAT_RX_ERR_CRC,
977 IPW_ORD_STAT_RX_ERR_CRC1,
978 IPW_ORD_STAT_RX_ERR_CRC2,
979 IPW_ORD_STAT_RX_ERR_CRC5_5,
980 IPW_ORD_STAT_RX_ERR_CRC11,
981
982 IPW_ORD_STAT_RX_DUPLICATE1 = 112,
983 IPW_ORD_STAT_RX_DUPLICATE2,
984 IPW_ORD_STAT_RX_DUPLICATE5_5,
985 IPW_ORD_STAT_RX_DUPLICATE11,
986 IPW_ORD_STAT_RX_DUPLICATE = 119,
987
988 IPW_ORD_PERS_DB_LOCK = 120,
989 IPW_ORD_PERS_DB_SIZE,
990 IPW_ORD_PERS_DB_ADDR,
991 IPW_ORD_STAT_RX_INVALID_PROTOCOL,
992 IPW_ORD_SYS_BOOT_TIME,
993 IPW_ORD_STAT_RX_NO_BUFFER,
994 IPW_ORD_STAT_RX_ABORT_LATE_DMA,
995 IPW_ORD_STAT_RX_ABORT_AT_HOP,
996 IPW_ORD_STAT_RX_MISSING_FRAG,
997 IPW_ORD_STAT_RX_ORPHAN_FRAG,
998 IPW_ORD_STAT_RX_ORPHAN_FRAME,
999 IPW_ORD_STAT_RX_FRAG_AGEOUT,
1000 IPW_ORD_STAT_RX_BAD_SSID,
1001 IPW_ORD_STAT_RX_ICV_ERRORS,
1002
1003
1004 IPW_ORD_STAT_PSP_SUSPENSION = 137,
1005 IPW_ORD_STAT_PSP_BCN_TIMEOUT,
1006 IPW_ORD_STAT_PSP_POLL_TIMEOUT,
1007 IPW_ORD_STAT_PSP_NONDIR_TIMEOUT,
1008 IPW_ORD_STAT_PSP_RX_DTIMS,
1009 IPW_ORD_STAT_PSP_RX_TIMS,
1010 IPW_ORD_STAT_PSP_STATION_ID,
1011
1012
1013 IPW_ORD_LAST_ASSN_TIME = 147,
1014 IPW_ORD_STAT_PERCENT_MISSED_BCNS,
1015 IPW_ORD_STAT_PERCENT_RETRIES,
1016 IPW_ORD_ASSOCIATED_AP_PTR,
1017
1018 IPW_ORD_AVAILABLE_AP_CNT,
1019 IPW_ORD_AP_LIST_PTR,
1020 IPW_ORD_STAT_AP_ASSNS,
1021 IPW_ORD_STAT_ASSN_FAIL,
1022 IPW_ORD_STAT_ASSN_RESP_FAIL,
1023 IPW_ORD_STAT_FULL_SCANS,
1024
1025 IPW_ORD_CARD_DISABLED,
1026 IPW_ORD_STAT_ROAM_INHIBIT,
1027 IPW_FILLER_40,
1028 IPW_ORD_RSSI_AT_ASSN = 160,
1029 IPW_ORD_STAT_ASSN_CAUSE1,
1030
1031 IPW_ORD_STAT_ASSN_CAUSE2,
1032 IPW_ORD_STAT_ASSN_CAUSE3,
1033
1034 IPW_ORD_STAT_ASSN_CAUSE4,
1035
1036 IPW_ORD_STAT_ASSN_CAUSE5,
1037 IPW_ORD_STAT_ASSN_CAUSE6,
1038 IPW_FILLER_41,
1039 IPW_FILLER_42,
1040 IPW_FILLER_43,
1041 IPW_ORD_STAT_AUTH_FAIL,
1042 IPW_ORD_STAT_AUTH_RESP_FAIL,
1043 IPW_ORD_STATION_TABLE_CNT,
1044
1045
1046 IPW_ORD_RSSI_AVG_CURR = 173,
1047 IPW_ORD_STEST_RESULTS_CURR,
1048 IPW_ORD_STEST_RESULTS_CUM,
1049 IPW_ORD_SELF_TEST_STATUS,
1050 IPW_ORD_POWER_MGMT_MODE,
1051 IPW_ORD_POWER_MGMT_INDEX,
1052 IPW_ORD_COUNTRY_CODE,
1053 IPW_ORD_COUNTRY_CHANNELS,
1054
1055
1056
1057 IPW_ORD_RESET_CNT,
1058 IPW_ORD_BEACON_INTERVAL,
1059
1060 IPW_ORD_PRINCETON_VERSION = 184,
1061 IPW_ORD_ANTENNA_DIVERSITY,
1062 IPW_ORD_CCA_RSSI,
1063 IPW_ORD_STAT_EEPROM_UPDATE,
1064 IPW_ORD_DTIM_PERIOD,
1065 IPW_ORD_OUR_FREQ,
1066
1067 IPW_ORD_RTC_TIME = 190,
1068 IPW_ORD_PORT_TYPE,
1069 IPW_ORD_CURRENT_TX_RATE,
1070 IPW_ORD_SUPPORTED_RATES,
1071 IPW_ORD_ATIM_WINDOW,
1072 IPW_ORD_BASIC_RATES,
1073 IPW_ORD_NIC_HIGHEST_RATE,
1074 IPW_ORD_AP_HIGHEST_RATE,
1075 IPW_ORD_CAPABILITIES,
1076 IPW_ORD_AUTH_TYPE,
1077 IPW_ORD_RADIO_TYPE,
1078 IPW_ORD_RTS_THRESHOLD = 201,
1079 IPW_ORD_INT_MODE,
1080 IPW_ORD_FRAGMENTATION_THRESHOLD,
1081 IPW_ORD_EEPROM_SRAM_DB_BLOCK_START_ADDRESS,
1082 IPW_ORD_EEPROM_SRAM_DB_BLOCK_SIZE,
1083 IPW_ORD_EEPROM_SKU_CAPABILITY,
1084 IPW_ORD_EEPROM_IBSS_11B_CHANNELS,
1085
1086 IPW_ORD_MAC_VERSION = 209,
1087 IPW_ORD_MAC_REVISION,
1088 IPW_ORD_RADIO_VERSION,
1089 IPW_ORD_NIC_MANF_DATE_TIME,
1090 IPW_ORD_UCODE_VERSION,
1091 IPW_ORD_HW_RF_SWITCH_STATE = 214,
1092} ORDINALTABLE1;
1093
1094
1095
1096#define IPW_FIRST_VARIABLE_LENGTH_ORDINAL 1001
1097
1098typedef enum _ORDINAL_TABLE_2 {
1099 IPW_ORD_STAT_BASE = 1000,
1100 IPW_ORD_STAT_ADAPTER_MAC = 1001,
1101 IPW_ORD_STAT_PREFERRED_BSSID = 1002,
1102 IPW_ORD_STAT_MANDATORY_BSSID = 1003,
1103 IPW_FILL_1,
1104 IPW_ORD_STAT_COUNTRY_TEXT = 1005,
1105 IPW_ORD_STAT_ASSN_SSID = 1006,
1106 IPW_ORD_STATION_TABLE = 1007,
1107 IPW_ORD_STAT_SWEEP_TABLE = 1008,
1108 IPW_ORD_STAT_ROAM_LOG = 1009,
1109 IPW_ORD_STAT_RATE_LOG = 1010,
1110 IPW_ORD_STAT_FIFO = 1011,
1111 IPW_ORD_STAT_FW_VER_NUM = 1012,
1112 IPW_ORD_STAT_FW_DATE = 1013,
1113 IPW_ORD_STAT_ASSN_AP_BSSID = 1014,
1114 IPW_ORD_STAT_DEBUG = 1015,
1115 IPW_ORD_STAT_NIC_BPA_NUM = 1016,
1116 IPW_ORD_STAT_UCODE_DATE = 1017,
1117 IPW_ORD_SECURITY_NGOTIATION_RESULT = 1018,
1118} ORDINALTABLE2;
1119
1120#define IPW_LAST_VARIABLE_LENGTH_ORDINAL 1018
1121
1122#ifndef WIRELESS_SPY
1123#define WIRELESS_SPY
1124#endif
1125
1126#define IPW_HOST_FW_SHARED_AREA0 0x0002f200
1127#define IPW_HOST_FW_SHARED_AREA0_END 0x0002f510
1128
1129#define IPW_HOST_FW_SHARED_AREA1 0x0002f610
1130#define IPW_HOST_FW_SHARED_AREA1_END 0x0002f630
1131
1132#define IPW_HOST_FW_SHARED_AREA2 0x0002fa00
1133#define IPW_HOST_FW_SHARED_AREA2_END 0x0002fa20
1134
1135#define IPW_HOST_FW_SHARED_AREA3 0x0002fc00
1136#define IPW_HOST_FW_SHARED_AREA3_END 0x0002fc10
1137
1138#define IPW_HOST_FW_INTERRUPT_AREA 0x0002ff80
1139#define IPW_HOST_FW_INTERRUPT_AREA_END 0x00030000
1140
1141struct ipw2100_fw_chunk {
1142 unsigned char *buf;
1143 long len;
1144 long pos;
1145 struct list_head list;
1146};
1147
1148struct ipw2100_fw_chunk_set {
1149 const void *data;
1150 unsigned long size;
1151};
1152
1153struct ipw2100_fw {
1154 int version;
1155 struct ipw2100_fw_chunk_set fw;
1156 struct ipw2100_fw_chunk_set uc;
1157 const struct firmware *fw_entry;
1158};
1159
1160#define MAX_FW_VERSION_LEN 14
1161
1162#endif
1163