linux/arch/ia64/include/asm/bitops.h
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2c/e0/2d8350d8d5b54e0e7b20cf8e31c28c6973b9_3/0" L1" class="line" namon>L1">v v13/a>#ifndefv3a href="+code=_ASM_IA64_BITOPS_H" class="sref">_ASM_IA64_BITOPS_H3/a>oL2" class="line" namon>L2">v v23/a>#definev3a href="+code=_ASM_IA64_BITOPS_H" class="sref">_ASM_IA64_BITOPS_H3/a>oL3" class="line" namon>L3">v v33/a>oL4" class="line" namon>L4">v v43/a>3spa	 class="comment">/*3/spa	  L5" class="line" namon>L5">v v53/a>3spa	 class="comment"> * Copyright (C) 1998-2003 Hewlett-Packard Co3/spa	  L6" class="line" namon>L6">v v63/a>3spa	 class="comment"> *      David Mosberger-Tang <davidm@hpl.hp.com>3/spa	  L7" class="line" namon>L7">v v73/a>3spa	 class="comment"> *3/spa	  L8" class="line" namon>L8">v v83/a>3spa	 class="comment"> * 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia643/spa	  L9" class="line" namon>L9">v v93/a>3spa	 class="comment"> * O(1) scheduler patchL10" class="line" namon>L10">v v3.8a>3spa	 class="comment"> */L11" class="line" namon>L11">v 113/a>oL12" class="line" namon>L12">v 123/a>#ifndefv3a href="+code=_LINUX_BITOPS_H" class="sref">_LINUX_BITOPS_H3/a>oL13" class="line" namon>L13">v 133/a>#errorv3a href="+code=only" class="sref">only3/a> <3a href="+code=linux" class="sref">linux3/a>/3a href="+code=bitops" class="sref">bitops3/a>.3a href="+code=h" class="sref">h3/a>>v3a href="+code=can" class="sref">can3/a> 3a href="+code=be" class="sref">be3/a> 3a href="+code=included" class="sref">included3/a> 3a href="+code=directly" class="sref">directly3/a>oL14" class="line" namon>L14">v 143/a>#endifoL15" class="line" namon>L15">v 153/a>oL16" class="line" namon>L16">v 163/a>#include <3a href="include/linux/compiler.h" class="fref">linux/compiler.h3/a>>oL17" class="line" namon>L17">v 173/a>#include <3a href="include/linux/typos.h" class="fref">linux/typos.h3/a>>oL18" class="line" namon>L18">v 183/a>#include <3a href="include/asm-ia64/intrinsics.h" class="fref">asm/intrinsics.h3/a>>oL19" class="line" namon>L19">v 193/a>oL20" class="line" namon>L20">v 23.8a>3spa	 class="comment">/**3/spa	  L21" class="line" namon>L21">v 213/a>3spa	 class="comment"> * set_bit - At2mically set a bit in memory3/spa	  L22" class="line" namon>L22">v 223/a>3spa	 class="comment"> * @nr: the bit to set3/spa	  L23" class="line" namon>L23">v 233/a>3spa	 class="comment"> * @addr: the address to start counting from3/spa	  L24" class="line" namon>L24">v 243/a>3spa	 class="comment"> *3/spa	  L25" class="line" namon>L25">v 253/a>3spa	 class="comment"> * This func2"
	 is at2mic and may not be reordered.  See __set_bit()3/spa	  L26" class="line" namon>L26">v 263/a>3spa	 class="comment"> * if you do not require the at2mic guaranteos.3/spa	  L27" class="line" namon>L27">v 273/a>3spa	 class="comment"> * Note that @nr may be almost arbitrarily large; this func2"
	 is not3/spa	  L28" class="line" namon>L28">v 283/a>3spa	 class="comment"> * restricted to ac2"ng 
	 a s"ngle-word quantity.3/spa	  L29" class="line" namon>L29">v 293/a>3spa	 class="comment"> *3/spa	  L30" class="line" namon>L30">v 33.8a>3spa	 class="comment"> * The address must be (at least) "long" aligned.3/spa	  L31" class="line" namon>L31">v 313/a>3spa	 class="comment"> * Note that there are driver (e.g., eepro100) which use these opera2"
	s to3/spa	  L32" class="line" namon>L32">v 323/a>3spa	 class="comment"> * opera2e 
	 hw-defined data-structures, so we can't easily change these3/spa	  L33" class="line" namon>L33">v 333/a>3spa	 class="comment"> * opera2"
	s to force a bigger alignment.3/spa	  L34" class="line" namon>L34">v 343/a>3spa	 class="comment"> *3/spa	  L35" class="line" namon>L35">v 353/a>3spa	 class="comment"> * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).3/spa	  L36" class="line" namon>L36">v 363/a>3spa	 class="comment"> */L37" class="line" namon>L37">v 373/a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> void L38" class="line" namon>L38">v 383/a>3a href="+code=set_bit" class="sref">set_bit3/a> (intv3a href="+code=nr" class="sref">nr3/a>, volatile void *3a href="+code=addr" class="sref">addr3/a>) L39" class="line" namon>L39">v 393/a>{oL40" class="line" namon>L40">v 43.8a>        3a href="+code=__u32" class="sref">__u323/a> 3a href="+code=bit" class="sref">bit3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>;oL41" class="line" namon>L41">v 41.8a>        volatile 3a href="+code=__u32" class="sref">__u323/a> *3a href="+code=m" class="sref">m3/a>;oL42" class="line" namon>L42">v 42.8a>        3a href="+code=CMPXCHG_BUGCHECK_DECL" class="sref">CMPXCHG_BUGCHECK_DECL3/a>oL43" class="line" namon>L43">v 433/a>oL44" class="line" namon>L44">v 44.8a>        3a href="+code=m" class="sref">m3/a> = (volatile 3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5);oL45" class="line" namon>L45">v 45.8a>        3a href="+code=bit" class="sref">bit3/a> = 1 << (3a href="+code=nr" class="sref">nr3/a> & 31);oL46" class="line" namon>L46">v 46.8a>        do {oL47" class="line" namon>L47">v 47.8a>                3a href="+code=CMPXCHG_BUGCHECK" class="sref">CMPXCHG_BUGCHECK.8a>(3a href="+code=m" class="sref">m3/a>);oL48" class="line" namon>L48">v 48.8a>                3a href="+code=old" class="sref">old3/a> = *3a href="+code=m" class="sref">m3/a>;oL49" class="line" namon>L49">v 49.8a>                3a href="+code=new" class="sref">new3/a> = 3a href="+code=old" class="sref">old3/a> | 3a href="+code=bit" class="sref">bit3/a>;oL50" class="line" namon>L50">v 53.8a>        } while (3a href="+code=cmpxchg_acq" class="sref">cmpxchg_acq.8a>(3a href="+code=m" class="sref">m3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>) != 3a href="+code=old" class="sref">old3/a>);oL51" class="line" namon>L51">v 51.8a>}oL52" class="line" namon>L52">v 523/a>oL53" class="line" namon>L53">v 533/a>3spa	 class="comment">/**3/spa	  L54" class="line" namon>L54">v 543/a>3spa	 class="comment"> * __set_bit - Set a bit in memory3/spa	  L55" class="line" namon>L55">v 553/a>3spa	 class="comment"> * @nr: the bit to set3/spa	  L56" class="line" namon>L56">v 563/a>3spa	 class="comment"> * @addr: the address to start counting from3/spa	  L57" class="line" namon>L57">v 573/a>3spa	 class="comment"> *3/spa	  L58" class="line" namon>L58">v 583/a>3spa	 class="comment"> * Unlike set_bit(), this func2"
	 is non-at2mic and may be reordered.3/spa	  L59" class="line" namon>L59">v 593/a>3spa	 class="comment"> * If it's called 
	 the samo reg"
	 of memory simultaneously, the effect3/spa	  L60" class="line" namon>L60">v 63.8a>3spa	 class="comment"> * may be that only one opera2"
	 succeeds.3/spa	  L61" class="line" namon>L61">v 613/a>3spa	 class="comment"> */L62" class="line" namon>L62">v 623/a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> void L63" class="line" namon>L63">v 633/a>3a href="+code=__set_bit" class="sref">__set_bit3/a> (intv3a href="+code=nr" class="sref">nr3/a>, volatile void *3a href="+code=addr" class="sref">addr3/a>) L64" class="line" namon>L64">v 643/a>{oL65" class="line" namon>L65">v 65.8a>        *((3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5)) |= (1 << (3a href="+code=nr" class="sref">nr3/a> & 31));oL66" class="line" namon>L66">v 66.8a>}oL67" class="line" namon>L67">v 673/a>oL68" class="line" namon>L68">v 683/a>3spa	 class="comment">/*3/spa	  L69" class="line" namon>L69">v 693/a>3spa	 class="comment"> * clear_bit() has "acquire" semantics.3/spa	  L70" class="line" namon>L70">v 73.8a>3spa	 class="comment"> */L71" class="line" namon>L71">v 713/a>#definev3a href="+code=smp_mb__before_clear_bit" class="sref">smp_mb__before_clear_bit.8a>()      3a href="+code=smp_mb" class="sref">smp_mb.8a>() L72" class="line" namon>L72">v 723/a>#definev3a href="+code=smp_mb__after_clear_bit" class="sref">smp_mb__after_clear_bit.8a>()       do { 3spa	 class="comment">/* skip */L73" class="line" namon>L73">v 733/a>oL74" class="line" namon>L74">v 743/a>3spa	 class="comment">/**3/spa	  L75" class="line" namon>L75">v 753/a>3spa	 class="comment"> * clear_bit - Clears a bit in memory3/spa	  L76" class="line" namon>L76">v 763/a>3spa	 class="comment"> * @nr: Bit to clear3/spa	  L77" class="line" namon>L77">v 773/a>3spa	 class="comment"> * @addr: Address to start counting from3/spa	  L78" class="line" namon>L78">v 783/a>3spa	 class="comment"> *3/spa	  L79" class="line" namon>L79">v 793/a>3spa	 class="comment"> * clear_bit() is at2mic and may not be reordered.  However, it does3/spa	  L80" class="line" namon>L80">v 83.8a>3spa	 class="comment"> * not contai	 a memory barrier, so if it is used for locking purposes,3/spa	  L81" class="line" namon>L81">v 813/a>3spa	 class="comment"> * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()3/spa	  L82" class="line" namon>L82">v 823/a>3spa	 class="comment"> * i	 order to ensure changes are visible 
	 other processors.3/spa	  L83" class="line" namon>L83">v 833/a>3spa	 class="comment"> */L84" class="line" namon>L84">v 843/a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> void L85" class="line" namon>L85">v 853/a>3a href="+code=clear_bit" class="sref">clear_bit.8a> (intv3a href="+code=nr" class="sref">nr3/a>, volatile void *3a href="+code=addr" class="sref">addr3/a>) L86" class="line" namon>L86">v 863/a>{oL87" class="line" namon>L87">v 87.8a>        3a href="+code=__u32" class="sref">__u323/a> 3a href="+code=mask" class="sref">mask3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>;oL88" class="line" namon>L88">v 88.8a>        volatile 3a href="+code=__u32" class="sref">__u323/a> *3a href="+code=m" class="sref">m3/a>;oL89" class="line" namon>L89">v 89.8a>        3a href="+code=CMPXCHG_BUGCHECK_DECL" class="sref">CMPXCHG_BUGCHECK_DECL3/a>oL90" class="line" namon>L90">v 903/a>oL91" class="line" namon>L91">v 91.8a>        3a href="+code=m" class="sref">m3/a> = (volatile 3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5);oL92" class="line" namon>L92">v 92.8a>        3a href="+code=mask" class="sref">mask3/a> = ~(1 << (3a href="+code=nr" class="sref">nr3/a> & 31));oL93" class="line" namon>L93">v 93.8a>        do {oL94" class="line" namon>L94">v 94.8a>                3a href="+code=CMPXCHG_BUGCHECK" class="sref">CMPXCHG_BUGCHECK.8a>(3a href="+code=m" class="sref">m3/a>);oL95" class="line" namon>L95">v 95.8a>                3a href="+code=old" class="sref">old3/a> = *3a href="+code=m" class="sref">m3/a>;oL96" class="line" namon>L96">v 96.8a>                3a href="+code=new" class="sref">new3/a> = 3a href="+code=old" class="sref">old3/a> & 3a href="+code=mask" class="sref">mask3/a>;oL97" class="line" namon>L97">v 97.8a>        } while (3a href="+code=cmpxchg_acq" class="sref">cmpxchg_acq.8a>(3a href="+code=m" class="sref">m3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>) != 3a href="+code=old" class="sref">old3/a>);oL98" class="line" namon>L98">v 98.8a>}oL99" class="line" namon>L99">v 993/a>oL100" class="line" namon>L100">v1003/a>3spa	 class="comment">/**3/spa	  L101" class="line" namon>L101">v1013/a>3spa	 class="comment"> * clear_bit_unlock - Clears a bit in memory with release3/spa	  L102" class="line" namon>L102">v1023/a>3spa	 class="comment"> * @nr: Bit to clear3/spa	  L103" class="line" namon>L103">v1033/a>3spa	 class="comment"> * @addr: Address to start counting from3/spa	  L104" class="line" namon>L104">v1043/a>3spa	 class="comment"> *3/spa	  L105" class="line" namon>L105">v1053/a>3spa	 class="comment"> * clear_bit_unlock() is at2mic and may not be reordered.  It does3/spa	  L106" class="line" namon>L106">v1063/a>3spa	 class="comment"> * contai	 a memory barrier suitable for unlock typo opera2"
	s.3/spa	  L107" class="line" namon>L107">v1073/a>3spa	 class="comment"> */L108" class="line" namon>L108">v1083/a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> void L109" class="line" namon>L109">v1093/a>3a href="+code=clear_bit_unlock" class="sref">clear_bit_unlock.8a> (intv3a href="+code=nr" class="sref">nr3/a>, volatile void *3a href="+code=addr" class="sref">addr3/a>) L110" class="line" namon>L110">v1v3.8a>{oL111" class="line" namon>L111">v111.8a>        3a href="+code=__u32" class="sref">__u323/a> 3a href="+code=mask" class="sref">mask3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>;oL112" class="line" namon>L112">v112.8a>        volatile 3a href="+code=__u32" class="sref">__u323/a> *3a href="+code=m" class="sref">m3/a>;oL113" class="line" namon>L113">v113.8a>        3a href="+code=CMPXCHG_BUGCHECK_DECL" class="sref">CMPXCHG_BUGCHECK_DECL3/a>oL114" class="line" namon>L114">v1143/a>oL115" class="line" namon>L115">v115.8a>        3a href="+code=m" class="sref">m3/a> = (volatile 3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5);oL116" class="line" namon>L116">v116.8a>        3a href="+code=mask" class="sref">mask3/a> = ~(1 << (3a href="+code=nr" class="sref">nr3/a> & 31));oL117" class="line" namon>L117">v117.8a>        do {oL118" class="line" namon>L118">v118.8a>                3a href="+code=CMPXCHG_BUGCHECK" class="sref">CMPXCHG_BUGCHECK.8a>(3a href="+code=m" class="sref">m3/a>);oL119" class="line" namon>L119">v119.8a>                3a href="+code=old" class="sref">old3/a> = *3a href="+code=m" class="sref">m3/a>;oL120" class="line" namon>L120">v120.8a>                3a href="+code=new" class="sref">new3/a> = 3a href="+code=old" class="sref">old3/a> & 3a href="+code=mask" class="sref">mask3/a>;oL121" class="line" namon>L121">v121.8a>        } while (3a href="+code=cmpxchg_rel" class="sref">cmpxchg_rel.8a>(3a href="+code=m" class="sref">m3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>) != 3a href="+code=old" class="sref">old3/a>);oL122" class="line" namon>L122">v1223/a>}oL123" class="line" namon>L123">v1233/a>oL124" class="line" namon>L124">v1243/a>3spa	 class="comment">/**3/spa	  L125" class="line" namon>L125">v1253/a>3spa	 class="comment"> * __clear_bit_unlock - Non-at2mically clears a bit in memory with release3/spa	  L126" class="line" namon>L126">v1263/a>3spa	 class="comment"> * @nr: Bit to clear3/spa	  L127" class="line" namon>L127">v1273/a>3spa	 class="comment"> * @addr: Address to start counting from3/spa	  L128" class="line" namon>L128">v1283/a>3spa	 class="comment"> *3/spa	  L129" class="line" namon>L129">v1293/a>3spa	 class="comment"> * Similarly to clear_bit_unlock, the implementa2"
	 uses a store3/spa	  L130" class="line" namon>L130">v133.8a>3spa	 class="comment"> * with release semantics. See also __raw_spin_unlock().3/spa	  L131" class="line" namon>L131">v1313/a>3spa	 class="comment"> */L132" class="line" namon>L132">v1323/a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> void L133" class="line" namon>L133">v1333/a>3a href="+code=__clear_bit_unlock" class="sref">__clear_bit_unlock.8a>(intv3a href="+code=nr" class="sref">nr3/a>, void *3a href="+code=addr" class="sref">addr3/a>) L134" class="line" namon>L134">v1343/a>{oL135" class="line" namon>L135">v135.8a>        3a href="+code=__u32" class="sref">__u323/a> * constv3a href="+code=m" class="sref">m3/a> = (3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5);oL136" class="line" namon>L136">v136.8a>        3a href="+code=__u32" class="sref">__u323/a> constv3a href="+code=new" class="sref">new3/a> = *3a href="+code=m" class="sref">m3/a> & ~(1 << (3a href="+code=nr" class="sref">nr3/a> & 31));oL137" class="line" namon>L137">v1373/a>oL138" class="line" namon>L138">v138.8a>        3a href="+code=ia64_st4_rel_nta" class="sref">ia64_st4_rel_nta.8a>(3a href="+code=m" class="sref">m3/a>,v3a href="+code=new" class="sref">new3/a>);oL139" class="line" namon>L139">v1393/a>}oL140" class="line" namon>L140">v1403/a>oL141" class="line" namon>L141">v1413/a>3spa	 class="comment">/**3/spa	  L142" class="line" namon>L142">v1423/a>3spa	 class="comment"> * __clear_bit - Clears a bit in memory (non-at2mic vers"
	)3/spa	  L143" class="line" namon>L143">v1433/a>3spa	 class="comment"> * @nr: the bit to clear3/spa	  L144" class="line" namon>L144">v1443/a>3spa	 class="comment"> * @addr: the address to start counting from3/spa	  L145" class="line" namon>L145">v1453/a>3spa	 class="comment"> *3/spa	  L146" class="line" namon>L146">v1463/a>3spa	 class="comment"> * Unlike clear_bit(), this func2"
	 is non-at2mic and may be reordered.3/spa	  L147" class="line" namon>L147">v1473/a>3spa	 class="comment"> * If it's called 
	 the samo reg"
	 of memory simultaneously, the effect3/spa	  L148" class="line" namon>L148">v1483/a>3spa	 class="comment"> * may be that only one opera2"
	 succeeds.3/spa	  L149" class="line" namon>L149">v1493/a>3spa	 class="comment"> */L150" class="line" namon>L150">v153.8a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> void L151" class="line" namon>L151">v151.8a>3a href="+code=__clear_bit" class="sref">__clear_bit.8a> (intv3a href="+code=nr" class="sref">nr3/a>, volatile void *3a href="+code=addr" class="sref">addr3/a>) L152" class="line" namon>L152">v1523/a>{oL153" class="line" namon>L153">v153.8a>        *((3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5)) &= ~(1 << (3a href="+code=nr" class="sref">nr3/a> & 31));oL154" class="line" namon>L154">v1543/a>}oL155" class="line" namon>L155">v1553/a>oL156" class="line" namon>L156">v1563/a>3spa	 class="comment">/**3/spa	  L157" class="line" namon>L157">v1573/a>3spa	 class="comment"> * change_bit - Toggle a bit in memory3/spa	  L158" class="line" namon>L158">v1583/a>3spa	 class="comment"> * @nr: Bit to toggle3/spa	  L159" class="line" namon>L159">v1593/a>3spa	 class="comment"> * @addr: Address to start counting from3/spa	  L160" class="line" namon>L160">v163.8a>3spa	 class="comment"> *3/spa	  L161" class="line" namon>L161">v1613/a>3spa	 class="comment"> * change_bit() is at2mic and may not be reordered.3/spa	  L162" class="line" namon>L162">v1623/a>3spa	 class="comment"> * Note that @nr may be almost arbitrarily large; this func2"
	 is not3/spa	  L163" class="line" namon>L163">v1633/a>3spa	 class="comment"> * restricted to ac2"ng 
	 a s"ngle-word quantity.3/spa	  L164" class="line" namon>L164">v1643/a>3spa	 class="comment"> */L165" class="line" namon>L165">v165.8a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> void L166" class="line" namon>L166">v166.8a>3a href="+code=change_bit" class="sref">change_bit.8a> (intv3a href="+code=nr" class="sref">nr3/a>, volatile void *3a href="+code=addr" class="sref">addr3/a>) L167" class="line" namon>L167">v1673/a>{oL168" class="line" namon>L168">v168.8a>        3a href="+code=__u32" class="sref">__u323/a> 3a href="+code=bit" class="sref">bit3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>;oL169" class="line" namon>L169">v169.8a>        volatile 3a href="+code=__u32" class="sref">__u323/a> *3a href="+code=m" class="sref">m3/a>;oL170" class="line" namon>L170">v173.8a>        3a href="+code=CMPXCHG_BUGCHECK_DECL" class="sref">CMPXCHG_BUGCHECK_DECL3/a>oL171" class="line" namon>L171">v1713/a>oL172" class="line" namon>L172">v172.8a>        3a href="+code=m" class="sref">m3/a> = (volatile 3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5);oL173" class="line" namon>L173">v173.8a>        3a href="+code=bit" class="sref">bit3/a> = (1 << (3a href="+code=nr" class="sref">nr3/a> & 31));oL174" class="line" namon>L174">v174.8a>        do {oL175" class="line" namon>L175">v175.8a>                3a href="+code=CMPXCHG_BUGCHECK" class="sref">CMPXCHG_BUGCHECK.8a>(3a href="+code=m" class="sref">m3/a>);oL176" class="line" namon>L176">v176.8a>                3a href="+code=old" class="sref">old3/a> = *3a href="+code=m" class="sref">m3/a>;oL177" class="line" namon>L177">v177.8a>                3a href="+code=new" class="sref">new3/a> = 3a href="+code=old" class="sref">old3/a> ^ 3a href="+code=bit" class="sref">bit3/a>;oL178" class="line" namon>L178">v178.8a>        } while (3a href="+code=cmpxchg_acq" class="sref">cmpxchg_acq.8a>(3a href="+code=m" class="sref">m3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>) != 3a href="+code=old" class="sref">old3/a>);oL179" class="line" namon>L179">v1793/a>}oL180" class="line" namon>L180">v1803/a>oL181" class="line" namon>L181">v1813/a>3spa	 class="comment">/**3/spa	  L182" class="line" namon>L182">v1823/a>3spa	 class="comment"> * __change_bit - Toggle a bit in memory3/spa	  L183" class="line" namon>L183">v1833/a>3spa	 class="comment"> * @nr: the bit to toggle3/spa	  L184" class="line" namon>L184">v1843/a>3spa	 class="comment"> * @addr: the address to start counting from3/spa	  L185" class="line" namon>L185">v1853/a>3spa	 class="comment"> *3/spa	  L186" class="line" namon>L186">v1863/a>3spa	 class="comment"> * Unlike change_bit(), this func2"
	 is non-at2mic and may be reordered.3/spa	  L187" class="line" namon>L187">v1873/a>3spa	 class="comment"> * If it's called 
	 the samo reg"
	 of memory simultaneously, the effect3/spa	  L188" class="line" namon>L188">v1883/a>3spa	 class="comment"> * may be that only one opera2"
	 succeeds.3/spa	  L189" class="line" namon>L189">v1893/a>3spa	 class="comment"> */L190" class="line" namon>L190">v193.8a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> void L191" class="line" namon>L191">v191.8a>3a href="+code=__change_bit" class="sref">__change_bit.8a> (intv3a href="+code=nr" class="sref">nr3/a>, volatile void *3a href="+code=addr" class="sref">addr3/a>) L192" class="line" namon>L192">v1923/a>{oL193" class="line" namon>L193">v193.8a>        *((3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5)) ^= (1 << (3a href="+code=nr" class="sref">nr3/a> & 31));oL194" class="line" namon>L194">v1943/a>}oL195" class="line" namon>L195">v1953/a>oL196" class="line" namon>L196">v1963/a>3spa	 class="comment">/**3/spa	  L197" class="line" namon>L197">v1973/a>3spa	 class="comment"> * test_and_set_bit - Set a bit and retur	 its old value3/spa	  L198" class="line" namon>L198">v1983/a>3spa	 class="comment"> * @nr: Bit to set3/spa	  L199" class="line" namon>L199">v1993/a>3spa	 class="comment"> * @addr: Address to count from3/spa	  L200" class="line" namon>L200">v2003/a>3spa	 class="comment"> *3/spa	  L201" class="line" namon>L201">v2013/a>3spa	 class="comment"> * This opera2"
	 is at2mic and cannot be reordered.  3/spa	  L202" class="line" namon>L202">v2023/a>3spa	 class="comment"> * It also implies the acquisi2"
	 side of the memory barrier.3/spa	  L203" class="line" namon>L203">v2033/a>3spa	 class="comment"> */L204" class="line" namon>L204">v2043/a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> int L205" class="line" namon>L205">v2053/a>3a href="+code=test_and_set_bit" class="sref">test_and_set_bit.8a> (intv3a href="+code=nr" class="sref">nr3/a>, volatile void *3a href="+code=addr" class="sref">addr3/a>) L206" class="line" namon>L206">v2063/a>{oL207" class="line" namon>L207">v207.8a>        3a href="+code=__u32" class="sref">__u323/a> 3a href="+code=bit" class="sref">bit3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>;oL208" class="line" namon>L208">v208.8a>        volatile 3a href="+code=__u32" class="sref">__u323/a> *3a href="+code=m" class="sref">m3/a>;oL209" class="line" namon>L209">v209.8a>        3a href="+code=CMPXCHG_BUGCHECK_DECL" class="sref">CMPXCHG_BUGCHECK_DECL3/a>oL210" class="line" namon>L210">v2103/a>oL211" class="line" namon>L211">v211.8a>        3a href="+code=m" class="sref">m3/a> = (volatile 3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5);oL212" class="line" namon>L212">v212.8a>        3a href="+code=bit" class="sref">bit3/a> = 1 << (3a href="+code=nr" class="sref">nr3/a> & 31);oL213" class="line" namon>L213">v213.8a>        do {oL214" class="line" namon>L214">v214.8a>                3a href="+code=CMPXCHG_BUGCHECK" class="sref">CMPXCHG_BUGCHECK.8a>(3a href="+code=m" class="sref">m3/a>);oL215" class="line" namon>L215">v215.8a>                3a href="+code=old" class="sref">old3/a> = *3a href="+code=m" class="sref">m3/a>;oL216" class="line" namon>L216">v216.8a>                3a href="+code=new" class="sref">new3/a> = 3a href="+code=old" class="sref">old3/a> | 3a href="+code=bit" class="sref">bit3/a>;oL217" class="line" namon>L217">v217.8a>        } while (3a href="+code=cmpxchg_acq" class="sref">cmpxchg_acq.8a>(3a href="+code=m" class="sref">m3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>) != 3a href="+code=old" class="sref">old3/a>);oL218" class="line" namon>L218">v218.8a>        retur	 (3a href="+code=old" class="sref">old3/a> & 3a href="+code=bit" class="sref">bit3/a>) != 0;oL219" class="line" namon>L219">v2193/a>}oL220" class="line" namon>L220">v2203/a>oL221" class="line" namon>L221">v2213/a>3spa	 class="comment">/**3/spa	  L222" class="line" namon>L222">v2223/a>3spa	 class="comment"> * test_and_set_bit_lock - Set a bit and retur	 its old value for lock3/spa	  L223" class="line" namon>L223">v2233/a>3spa	 class="comment"> * @nr: Bit to set3/spa	  L224" class="line" namon>L224">v2243/a>3spa	 class="comment"> * @addr: Address to count from3/spa	  L225" class="line" namon>L225">v2253/a>3spa	 class="comment"> *3/spa	  L226" class="line" namon>L226">v2263/a>3spa	 class="comment"> * This is the samo as test_and_set_bit 
	 ia643/spa	  L227" class="line" namon>L227">v2273/a>3spa	 class="comment"> */L228" class="line" namon>L228">v2283/a>#definev3a href="+code=test_and_set_bit_lock" class="sref">test_and_set_bit_lock.8a> 3a href="+code=test_and_set_bit" class="sref">test_and_set_bit.8a> L229" class="line" namon>L229">v2293/a>oL230" class="line" namon>L230">v233.8a>3spa	 class="comment">/**3/spa	  L231" class="line" namon>L231">v2313/a>3spa	 class="comment"> * __test_and_set_bit - Set a bit and retur	 its old value3/spa	  L232" class="line" namon>L232">v2323/a>3spa	 class="comment"> * @nr: Bit to set3/spa	  L233" class="line" namon>L233">v2333/a>3spa	 class="comment"> * @addr: Address to count from3/spa	  L234" class="line" namon>L234">v2343/a>3spa	 class="comment"> *3/spa	  L235" class="line" namon>L235">v2353/a>3spa	 class="comment"> * This opera2"
	 is non-at2mic and ca	 be reordered.  3/spa	  L236" class="line" namon>L236">v2363/a>3spa	 class="comment"> * If two examples of this opera2"
	 race, one ca	 appear to succeed3/spa	  L237" class="line" namon>L237">v2373/a>3spa	 class="comment"> * but ac2ually fail.  You must protect multiple accesses with a lock.3/spa	  L238" class="line" namon>L238">v2383/a>3spa	 class="comment"> */L239" class="line" namon>L239">v2393/a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> int L240" class="line" namon>L240">v2403/a>3a href="+code=__test_and_set_bit" class="sref">__test_and_set_bit.8a> (intv3a href="+code=nr" class="sref">nr3/a>, volatile void *3a href="+code=addr" class="sref">addr3/a>) L241" class="line" namon>L241">v2413/a>{oL242" class="line" namon>L242">v242.8a>        3a href="+code=__u32" class="sref">__u323/a> *3a href="+code=p" class="sref">p3/a> = (3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5);oL243" class="line" namon>L243">v243.8a>        3a href="+code=__u32" class="sref">__u323/a> 3a href="+code=m" class="sref">m3/a> = 1 << (3a href="+code=nr" class="sref">nr3/a> & 31);oL244" class="line" namon>L244">v244.8a>        intv3a href="+code=oldbitset" class="sref">oldbitset3/a> = (*3a href="+code=p" class="sref">p3/a> & 3a href="+code=m" class="sref">m3/a>) != 0;oL245" class="line" namon>L245">v2453/a>oL246" class="line" namon>L246">v246.8a>        *3a href="+code=p" class="sref">p3/a> |= 3a href="+code=m" class="sref">m3/a>;oL247" class="line" namon>L247">v247.8a>        retur	 3a href="+code=oldbitset" class="sref">oldbitset3/a>;oL248" class="line" namon>L248">v248.8a>}oL249" class="line" namon>L249">v2493/a>oL250" class="line" namon>L250">v253.8a>3spa	 class="comment">/**3/spa	  L251" class="line" namon>L251">v2513/a>3spa	 class="comment"> * test_and_clear_bit - Clear a bit and retur	 its old value3/spa	  L252" class="line" namon>L252">v2523/a>3spa	 class="comment"> * @nr: Bit to clear3/spa	  L253" class="line" namon>L253">v2533/a>3spa	 class="comment"> * @addr: Address to count from3/spa	  L254" class="line" namon>L254">v2543/a>3spa	 class="comment"> *3/spa	  L255" class="line" namon>L255">v2553/a>3spa	 class="comment"> * This opera2"
	 is at2mic and cannot be reordered.  3/spa	  L256" class="line" namon>L256">v2563/a>3spa	 class="comment"> * It also implies the acquisi2"
	 side of the memory barrier.3/spa	  L257" class="line" namon>L257">v2573/a>3spa	 class="comment"> */L258" class="line" namon>L258">v2583/a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> int L259" class="line" namon>L259">v2593/a>3a href="+code=test_and_clear_bit" class="sref">test_and_clear_bit.8a> (intv3a href="+code=nr" class="sref">nr3/a>, volatile void *3a href="+code=addr" class="sref">addr3/a>) L260" class="line" namon>L260">v263.8a>{oL261" class="line" namon>L261">v261.8a>        3a href="+code=__u32" class="sref">__u323/a> 3a href="+code=mask" class="sref">mask3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>;oL262" class="line" namon>L262">v262.8a>        volatile 3a href="+code=__u32" class="sref">__u323/a> *3a href="+code=m" class="sref">m3/a>;oL263" class="line" namon>L263">v263.8a>        3a href="+code=CMPXCHG_BUGCHECK_DECL" class="sref">CMPXCHG_BUGCHECK_DECL3/a>oL264" class="line" namon>L264">v2643/a>oL265" class="line" namon>L265">v265.8a>        3a href="+code=m" class="sref">m3/a> = (volatile 3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5);oL266" class="line" namon>L266">v266.8a>        3a href="+code=mask" class="sref">mask3/a> = ~(1 << (3a href="+code=nr" class="sref">nr3/a> & 31));oL267" class="line" namon>L267">v267.8a>        do {oL268" class="line" namon>L268">v268.8a>                3a href="+code=CMPXCHG_BUGCHECK" class="sref">CMPXCHG_BUGCHECK.8a>(3a href="+code=m" class="sref">m3/a>);oL269" class="line" namon>L269">v269.8a>                3a href="+code=old" class="sref">old3/a> = *3a href="+code=m" class="sref">m3/a>;oL270" class="line" namon>L270">v270.8a>                3a href="+code=new" class="sref">new3/a> = 3a href="+code=old" class="sref">old3/a> & 3a href="+code=mask" class="sref">mask3/a>;oL271" class="line" namon>L271">v271.8a>        } while (3a href="+code=cmpxchg_acq" class="sref">cmpxchg_acq.8a>(3a href="+code=m" class="sref">m3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>) != 3a href="+code=old" class="sref">old3/a>);oL272" class="line" namon>L272">v272.8a>        retur	 (3a href="+code=old" class="sref">old3/a> & ~3a href="+code=mask" class="sref">mask3/a>) != 0;oL273" class="line" namon>L273">v273.8a>}oL274" class="line" namon>L274">v2743/a>oL275" class="line" namon>L275">v2753/a>3spa	 class="comment">/**3/spa	  L276" class="line" namon>L276">v2763/a>3spa	 class="comment"> * __test_and_clear_bit - Clear a bit and retur	 its old value3/spa	  L277" class="line" namon>L277">v2773/a>3spa	 class="comment"> * @nr: Bit to clear3/spa	  L278" class="line" namon>L278">v2783/a>3spa	 class="comment"> * @addr: Address to count from3/spa	  L279" class="line" namon>L279">v2793/a>3spa	 class="comment"> *3/spa	  L280" class="line" namon>L280">v283.8a>3spa	 class="comment"> * This opera2"
	 is non-at2mic and ca	 be reordered.  3/spa	  L281" class="line" namon>L281">v2813/a>3spa	 class="comment"> * If two examples of this opera2"
	 race, one ca	 appear to succeed3/spa	  L282" class="line" namon>L282">v2823/a>3spa	 class="comment"> * but ac2ually fail.  You must protect multiple accesses with a lock.3/spa	  L283" class="line" namon>L283">v2833/a>3spa	 class="comment"> */L284" class="line" namon>L284">v2843/a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> int L285" class="line" namon>L285">v2853/a>3a href="+code=__test_and_clear_bit" class="sref">__test_and_clear_bit.8a>(intv3a href="+code=nr" class="sref">nr3/a>, volatile void * 3a href="+code=addr" class="sref">addr3/a>) L286" class="line" namon>L286">v2863/a>{oL287" class="line" namon>L287">v287.8a>        3a href="+code=__u32" class="sref">__u323/a> *3a href="+code=p" class="sref">p3/a> = (3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5);oL288" class="line" namon>L288">v288.8a>        3a href="+code=__u32" class="sref">__u323/a> 3a href="+code=m" class="sref">m3/a> = 1 << (3a href="+code=nr" class="sref">nr3/a> & 31);oL289" class="line" namon>L289">v289.8a>        intv3a href="+code=oldbitset" class="sref">oldbitset3/a> = *3a href="+code=p" class="sref">p3/a> & 3a href="+code=m" class="sref">m3/a>;oL290" class="line" namon>L290">v2903/a>oL291" class="line" namon>L291">v291.8a>        *3a href="+code=p" class="sref">p3/a> &= ~3a href="+code=m" class="sref">m3/a>;oL292" class="line" namon>L292">v292.8a>        retur	 3a href="+code=oldbitset" class="sref">oldbitset3/a>;oL293" class="line" namon>L293">v293.8a>}oL294" class="line" namon>L294">v2943/a>oL295" class="line" namon>L295">v2953/a>3spa	 class="comment">/**3/spa	  L296" class="line" namon>L296">v2963/a>3spa	 class="comment"> * test_and_change_bit - Change a bit and retur	 its old value3/spa	  L297" class="line" namon>L297">v2973/a>3spa	 class="comment"> * @nr: Bit to change3/spa	  L298" class="line" namon>L298">v2983/a>3spa	 class="comment"> * @addr: Address to count from3/spa	  L299" class="line" namon>L299">v2993/a>3spa	 class="comment"> *3/spa	  L300" class="line" namon>L300">v3003/a>3spa	 class="comment"> * This opera2"
	 is at2mic and cannot be reordered.  3/spa	  L301" class="line" namon>L301">v3013/a>3spa	 class="comment"> * It also implies the acquisi2"
	 side of the memory barrier.3/spa	  L302" class="line" namon>L302">v3023/a>3spa	 class="comment"> */L303" class="line" namon>L303">v3033/a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> int L304" class="line" namon>L304">v3043/a>3a href="+code=test_and_change_bit" class="sref">test_and_change_bit.8a> (intv3a href="+code=nr" class="sref">nr3/a>, volatile void *3a href="+code=addr" class="sref">addr3/a>) L305" class="line" namon>L305">v3053/a>{oL306" class="line" namon>L306">v306.8a>        3a href="+code=__u32" class="sref">__u323/a> 3a href="+code=bit" class="sref">bit3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>;oL307" class="line" namon>L307">v307.8a>        volatile 3a href="+code=__u32" class="sref">__u323/a> *3a href="+code=m" class="sref">m3/a>;oL308" class="line" namon>L308">v308.8a>        3a href="+code=CMPXCHG_BUGCHECK_DECL" class="sref">CMPXCHG_BUGCHECK_DECL3/a>oL309" class="line" namon>L309">v3093/a>oL310" class="line" namon>L310">v313.8a>        3a href="+code=m" class="sref">m3/a> = (volatile 3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5);oL311" class="line" namon>L311">v311.8a>        3a href="+code=bit" class="sref">bit3/a> = (1 << (3a href="+code=nr" class="sref">nr3/a> & 31));oL312" class="line" namon>L312">v312.8a>        do {oL313" class="line" namon>L313">v313.8a>                3a href="+code=CMPXCHG_BUGCHECK" class="sref">CMPXCHG_BUGCHECK.8a>(3a href="+code=m" class="sref">m3/a>);oL314" class="line" namon>L314">v314.8a>                3a href="+code=old" class="sref">old3/a> = *3a href="+code=m" class="sref">m3/a>;oL315" class="line" namon>L315">v315.8a>                3a href="+code=new" class="sref">new3/a> = 3a href="+code=old" class="sref">old3/a> ^ 3a href="+code=bit" class="sref">bit3/a>;oL316" class="line" namon>L316">v316.8a>        } while (3a href="+code=cmpxchg_acq" class="sref">cmpxchg_acq.8a>(3a href="+code=m" class="sref">m3/a>,v3a href="+code=old" class="sref">old3/a>,v3a href="+code=new" class="sref">new3/a>) != 3a href="+code=old" class="sref">old3/a>);oL317" class="line" namon>L317">v317.8a>        retur	 (3a href="+code=old" class="sref">old3/a> & 3a href="+code=bit" class="sref">bit3/a>) != 0;oL318" class="line" namon>L318">v318.8a>}oL319" class="line" namon>L319">v3193/a>oL320" class="line" namon>L320">v323.8a>3spa	 class="comment">/**3/spa	  L321" class="line" namon>L321">v3213/a>3spa	 class="comment"> * __test_and_change_bit - Change a bit and retur	 its old value3/spa	  L322" class="line" namon>L322">v3223/a>3spa	 class="comment"> * @nr: Bit to change3/spa	  L323" class="line" namon>L323">v3233/a>3spa	 class="comment"> * @addr: Address to count from3/spa	  L324" class="line" namon>L324">v3243/a>3spa	 class="comment"> *3/spa	  L325" class="line" namon>L325">v3253/a>3spa	 class="comment"> * This opera2"
	 is non-at2mic and ca	 be reordered.3/spa	  L326" class="line" namon>L326">v3263/a>3spa	 class="comment"> */L327" class="line" namon>L327">v3273/a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> int L328" class="line" namon>L328">v3283/a>3a href="+code=__test_and_change_bit" class="sref">__test_and_change_bit.8a> (intv3a href="+code=nr" class="sref">nr3/a>, void *3a href="+code=addr" class="sref">addr3/a>) L329" class="line" namon>L329">v3293/a>{oL330" class="line" namon>L330">v333.8a>        3a href="+code=__u32" class="sref">__u323/a> 3a href="+code=old" class="sref">old3/a>,v3a href="+code=bit" class="sref">bit3/a> = (1 << (3a href="+code=nr" class="sref">nr3/a> & 31));oL331" class="line" namon>L331">v331.8a>        3a href="+code=__u32" class="sref">__u323/a> *3a href="+code=m" class="sref">m3/a> = (3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a> + (3a href="+code=nr" class="sref">nr3/a> >> 5);oL332" class="line" namon>L332">v3323/a>oL333" class="line" namon>L333">v333.8a>        3a href="+code=old" class="sref">old3/a> = *3a href="+code=m" class="sref">m3/a>;oL334" class="line" namon>L334">v334.8a>        *3a href="+code=m" class="sref">m3/a> = 3a href="+code=old" class="sref">old3/a> ^ 3a href="+code=bit" class="sref">bit3/a>;oL335" class="line" namon>L335">v335.8a>        retur	 (3a href="+code=old" class="sref">old3/a> & 3a href="+code=bit" class="sref">bit3/a>) != 0;oL336" class="line" namon>L336">v3363/a>}oL337" class="line" namon>L337">v3373/a>oL338" class="line" namon>L338">v3383/a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> int L339" class="line" namon>L339">v3393/a>3a href="+code=test_bit" class="sref">test_bit.8a> (intv3a href="+code=nr" class="sref">nr3/a>, const volatile void *3a href="+code=addr" class="sref">addr3/a>) L340" class="line" namon>L340">v343.8a>{oL341" class="line" namon>L341">v341.8a>        retur	 1 & (((const volatile 3a href="+code=__u32" class="sref">__u323/a> *) 3a href="+code=addr" class="sref">addr3/a>)[3a href="+code=nr" class="sref">nr3/a> >> 5] >> (3a href="+code=nr" class="sref">nr3/a> & 31));oL342" class="line" namon>L342">v342.8a>}oL343" class="line" namon>L343">v343.8a>oL344" class="line" namon>L344">v3443/a>3spa	 class="comment">/**3/spa	  L345" class="line" namon>L345">v3453/a>3spa	 class="comment"> * ffz - find the first zero bit in a long word3/spa	  L346" class="line" namon>L346">v3463/a>3spa	 class="comment"> * @x: The long word to find the bit in3/spa	  L347" class="line" namon>L347">v3473/a>3spa	 class="comment"> *3/spa	  L348" class="line" namon>L348">v3483/a>3spa	 class="comment"> * Retur	s the bit-number (0..63) of the first (least significa	t) zero bit.3/spa	  L349" class="line" namon>L349">v3493/a>3spa	 class="comment"> * Undefined if no zero exists, so code should check against ~0UL first...3/spa	  L350" class="line" namon>L350">v353.8a>3spa	 class="comment"> */L351" class="line" namon>L351">v3513/a>staticv3a href="+code=inline" class="sref">inline3/a> unsigned long L352" class="line" namon>L352">v3523/a>3a href="+code=ffz" class="sref">ffz.8a> (unsigned longv3a href="+code=x" class="sref">x3/a>) L353" class="line" namon>L353">v3533/a>{oL354" class="line" namon>L354">v354.8a>        unsigned longv3a href="+code=result" class="sref">result3/a>;oL355" class="line" namon>L355">v3553/a>oL356" class="line" namon>L356">v356.8a>        3a href="+code=result" class="sref">result3/a> = 3a href="+code=ia64_popcnt" class="sref">ia64_popcnt.8a>(3a href="+code=x" class="sref">x3/a> & (~3a href="+code=x" class="sref">x3/a> - 1));oL357" class="line" namon>L357">v357.8a>        retur	 3a href="+code=result" class="sref">result3/a>;oL358" class="line" namon>L358">v358.8a>}oL359" class="line" namon>L359">v3593/a>oL360" class="line" namon>L360">v363.8a>3spa	 class="comment">/**3/spa	  L361" class="line" namon>L361">v3613/a>3spa	 class="comment"> * __ffs - find first bit in word.3/spa	  L362" class="line" namon>L362">v3623/a>3spa	 class="comment"> * @x: The word to search3/spa	  L363" class="line" namon>L363">v3633/a>3spa	 class="comment"> *3/spa	  L364" class="line" namon>L364">v3643/a>3spa	 class="comment"> * Undefined if no bit exists, so code should check against 0 first.3/spa	  L365" class="line" namon>L365">v3653/a>3spa	 class="comment"> */L366" class="line" namon>L366">v366.8a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> unsigned long L367" class="line" namon>L367">v367.8a>3a href="+code=__ffs" class="sref">__ffs.8a> (unsigned longv3a href="+code=x" class="sref">x3/a>) L368" class="line" namon>L368">v368.8a>{oL369" class="line" namon>L369">v369.8a>        unsigned longv3a href="+code=result" class="sref">result3/a>;oL370" class="line" namon>L370">v3703/a>oL371" class="line" namon>L371">v371.8a>        3a href="+code=result" class="sref">result3/a> = 3a href="+code=ia64_popcnt" class="sref">ia64_popcnt.8a>((3a href="+code=x" class="sref">x3/a>-1) & ~3a href="+code=x" class="sref">x3/a>);oL372" class="line" namon>L372">v372.8a>        retur	 3a href="+code=result" class="sref">result3/a>;oL373" class="line" namon>L373">v373.8a>}oL374" class="line" namon>L374">v3743/a>oL375" class="line" namon>L375">v3753/a>#ifdefv3a href="+code=__KERNEL__" class="sref">__KERNEL__3/a>oL376" class="line" namon>L376">v3763/a>oL377" class="line" namon>L377">v3773/a>3spa	 class="comment">/*3/spa	  L378" class="line" namon>L378">v3783/a>3spa	 class="comment"> * Retur	 bit number of last (most-significa	t) bit set.  Undefined3/spa	  L379" class="line" namon>L379">v3793/a>3spa	 class="comment"> * for x==0.  Bits are numbered from 0..63 (e.g., ia64_fls(9) == 3).3/spa	  L380" class="line" namon>L380">v383.8a>3spa	 class="comment"> */L381" class="line" namon>L381">v3813/a>staticv3a href="+code=inline" class="sref">inline3/a> unsigned long L382" class="line" namon>L382">v3823/a>3a href="+code=ia64_fls" class="sref">ia64_fls.8a> (unsigned longv3a href="+code=x" class="sref">x3/a>) L383" class="line" namon>L383">v3833/a>{oL384" class="line" namon>L384">v384.8a>        longvdouble 3a href="+code=d" class="sref">d3/a> = 3a href="+code=x" class="sref">x3/a>;oL385" class="line" namon>L385">v385.8a>        longv3a href="+code=exp" class="sref">exp3/a>;oL386" class="line" namon>L386">v3863/a>oL387" class="line" namon>L387">v387.8a>        3a href="+code=exp" class="sref">exp3/a> = 3a href="+code=ia64_getf_exp" class="sref">ia64_getf_exp.8a>(3a href="+code=d" class="sref">d3/a>);oL388" class="line" namon>L388">v388.8a>        retur	 3a href="+code=exp" class="sref">exp3/a> - 0xffff;oL389" class="line" namon>L389">v3893/a>}oL390" class="line" namon>L390">v3903/a>oL391" class="line" namon>L391">v3913/a>3spa	 class="comment">/*L392" class="line" namon>L392">v3923/a>3spa	 class="comment"> * Find the last (most significa	t) bit set.  Retur	s 0 for x==0 andL393" class="line" namon>L393">v3933/a>3spa	 class="comment"> * bits are numbered from 1..32 (e.g., fls(9) == 4).3/spa	  L394" class="line" namon>L394">v3943/a>3spa	 class="comment"> */L395" class="line" namon>L395">v3953/a>staticv3a href="+code=inline" class="sref">inline3/a> int L396" class="line" namon>L396">v3963/a>3a href="+code=fls" class="sref">fls.8a> (intv3a href="+code=t" class="sref">t3/a>) L397" class="line" namon>L397">v3973/a>{oL398" class="line" namon>L398">v398.8a>        unsigned longv3a href="+code=x" class="sref">x3/a> = 3a href="+code=t" class="sref">t3/a> & 0xffffffffu;oL399" class="line" namon>L399">v3993/a>oL400" class="line" namon>L400">v403.8a>        if (!3a href="+code=x" class="sref">x3/a>) L401" class="line" namon>L401">v401.8a>                retur	 0;oL402" class="line" namon>L402">v402.8a>        3a href="+code=x" class="sref">x3/a> |= 3a href="+code=x" class="sref">x3/a> >> 1;oL403" class="line" namon>L403">v403.8a>        3a href="+code=x" class="sref">x3/a> |= 3a href="+code=x" class="sref">x3/a> >> 2;oL404" class="line" namon>L404">v404.8a>        3a href="+code=x" class="sref">x3/a> |= 3a href="+code=x" class="sref">x3/a> >> 4;oL405" class="line" namon>L405">v405.8a>        3a href="+code=x" class="sref">x3/a> |= 3a href="+code=x" class="sref">x3/a> >> 8;oL406" class="line" namon>L406">v406.8a>        3a href="+code=x" class="sref">x3/a> |= 3a href="+code=x" class="sref">x3/a> >> 16;oL407" class="line" namon>L407">v407.8a>        retur	 3a href="+code=ia64_popcnt" class="sref">ia64_popcnt.8a>(3a href="+code=x" class="sref">x3/a>);oL408" class="line" namon>L408">v408.8a>}oL409" class="line" namon>L409">v4093/a>oL410" class="line" namon>L410">v413.8a>3spa	 class="comment">/*L411" class="line" namon>L411">v4113/a>3spa	 class="comment"> * Find the last (most significa	t) bit set.  Undefined for x==0.L412" class="line" namon>L412">v4123/a>3spa	 class="comment"> * Bits are numbered from 0..63 (e.g., __fls(9) == 3).3/spa	  L413" class="line" namon>L413">v4133/a>3spa	 class="comment"> */L414" class="line" namon>L414">v4143/a>staticv3a href="+code=inline" class="sref">inline3/a> unsigned long L415" class="line" namon>L415">v4153/a>3a href="+code=__fls" class="sref">__fls.8a> (unsigned longv3a href="+code=x" class="sref">x3/a>) L416" class="line" namon>L416">v4163/a>{oL417" class="line" namon>L417">v417.8a>        3a href="+code=x" class="sref">x3/a> |= 3a href="+code=x" class="sref">x3/a> >> 1;oL418" class="line" namon>L418">v418.8a>        3a href="+code=x" class="sref">x3/a> |= 3a href="+code=x" class="sref">x3/a> >> 2;oL419" class="line" namon>L419">v419.8a>        3a href="+code=x" class="sref">x3/a> |= 3a href="+code=x" class="sref">x3/a> >> 4;oL420" class="line" namon>L420">v423.8a>        3a href="+code=x" class="sref">x3/a> |= 3a href="+code=x" class="sref">x3/a> >> 8;oL421" class="line" namon>L421">v421.8a>        3a href="+code=x" class="sref">x3/a> |= 3a href="+code=x" class="sref">x3/a> >> 16;oL422" class="line" namon>L422">v422.8a>        3a href="+code=x" class="sref">x3/a> |= 3a href="+code=x" class="sref">x3/a> >> 32;oL423" class="line" namon>L423">v423.8a>        retur	 3a href="+code=ia64_popcnt" class="sref">ia64_popcnt.8a>(3a href="+code=x" class="sref">x3/a>) - 1;oL424" class="line" namon>L424">v4243/a>}oL425" class="line" namon>L425">v4253/a>oL426" class="line" namon>L426">v4263/a>#include <asm-generic/bitops/fls64.h3/a>>oL427" class="line" namon>L427">v4273/a>oL428" class="line" namon>L428">v4283/a>3spa	 class="comment">/*L429" class="line" namon>L429">v4293/a>3spa	 class="comment"> * ffs: find first bit set. This is defined the samo way as the libc andL430" class="line" namon>L430">v433.8a>3spa	 class="comment"> * compiler builtin ffs routines, therefore differs in spirit from the above3/spa	  L431" class="line" namon>L431">v4313/a>3spa	 class="comment"> * ffz (man ffs): it opera2es on "int" values only and the result value is the3/spa	  L432" class="line" namon>L432">v4323/a>3spa	 class="comment"> * bit number + 1.  ffs(0) is defined to retur	 zero.3/spa	  L433" class="line" namon>L433">v4333/a>3spa	 class="comment"> */L434" class="line" namon>L434">v434.8a>#define 3a href="+code=ffs" class="sref">ffs.8a>(3a href="+code=x" class="sref">x3/a>) v3a href="+code=__builtin_ffs" class="sref">__builtin_ffs.8a>(3a href="+code=x" class="sref">x3/a>) L435" class="line" namon>L435">v4353/a>oL436" class="line" namon>L436">v4363/a>3spa	 class="comment">/*L437" class="line" namon>L437">v4373/a>3spa	 class="comment"> * hweightN: retur	s the hamming weight (i.e. the numberL438" class="line" namon>L438">v4383/a>3spa	 class="comment"> * of bits set) of a N-bit word3/spa	  L439" class="line" namon>L439">v4393/a>3spa	 class="comment"> */L440" class="line" namon>L440">v443.8a>staticv3a href="+code=__inline__" class="sref">__inline__3/a> unsigned long L441" class="line" namon>L441">v441.8a>3a href="+code=hweight64" class="sref">hweight64.8a> (unsigned longv3a href="+code=x" class="sref">x3/a>) L442" class="line" namon>L442">v442.8a>{oL443" class="line" namon>L443">v443.8a>        unsigned longv3a href="+code=result" class="sref">result3/a>;oL444" class="line" namon>L444">v444.8a>        3a href="+code=result" class="sref">result3/a> = 3a href="+code=ia64_popcnt" class="sref">ia64_popcnt.8a>(3a href="+code=x" class="sref">x3/a>);oL445" class="line" namon>L445">v445.8a>        retur	 3a href="+code=result" class="sref">result3/a>;oL446" class="line" namon>L446">v4463/a>}oL447" class="line" namon>L447">v4473/a>oL448" class="line" namon>L448">v4483/a>#define 3a href="+code=hweight32" class="sref">hweight32.8a>(3a href="+code=x" class="sref">x3/a>) v  (unsigned i	t) 3a href="+code=hweight64" class="sref">hweight64.8a>((3a href="+code=x" class="sref">x3/a>) & 0xfffffffful) L449" class="line" namon>L449">v4493/a>#define 3a href="+code=hweight16" class="sref">hweight163/a>(3a href="+code=x" class="sref">x3/a>) v  (unsigned i	t) 3a href="+code=hweight64" class="sref">hweight64.8a>((3a href="+code=x" class="sref">x3/a>) & 0xfffful) L450" class="line" namon>L450">v453.8a>#define 3a href="+code=hweight8" class="sref">hweight83/a>(3a href="+code=x" class="sref">x3/a>) v   (unsigned i	t) 3a href="+code=hweight64" class="sref">hweight64.8a>((3a href="+code=x" class="sref">x3/a>) & 0xfful) L451" class="line" namon>L451">v4513/a> L452" class="line" namon>L452">v4523/a>#endif 3spa	 class="comment">/* __KERNEL__ */L453" class="line" namon>L453">v453.8a>oL454" class="line" namon>L454">v454.8a>#include <asm-generic/bitops/find.h3/a>>oL455" class="line" namon>L455">v4553/a>oL456" class="line" namon>L456">v4563/a>#ifdefv3a href="+code=__KERNEL__" class="sref">__KERNEL__3/a>oL457" class="line" namon>L457">v4573/a>oL458" class="line" namon>L458">v458.8a>#include <asm-generic/bitops/ext2-non-at2mic.h3/a>>oL459" class="line" namon>L459">v4593/a>oL460" class="line" namon>L460">v463.8a>#define 3a href="+code=ext2_set_bit_at2mic" class="sref">ext2_set_bit_at2mic3/a>(3a href="+code=l" class="sref">l3/a>,3a href="+code=n" class="sref">n3/a>,3a href="+code=a" class="sref">a3/a>) v    3a href="+code=test_and_set_bit" class="sref">test_and_set_bit3/a>(3a href="+code=n" class="sref">n3/a>,3a href="+code=a" class="sref">a3/a>)oL461" class="line" namon>L461">v4613/a>#define 3a href="+code=ext2_clear_bit_at2mic" class="sref">ext2_clear_bit_at2mic3/a>(3a href="+code=l" class="sref">l3/a>,3a href="+code=n" class="sref">n3/a>,3a href="+code=a" class="sref">a3/a>) v  3a href="+code=test_and_clear_bit" class="sref">test_and_clear_bit.8a>(3a href="+code=n" class="sref">n3/a>,3a href="+code=a" class="sref">a3/a>)oL462" class="line" namon>L462">v4623/a>oL463" class="line" namon>L463">v4633/a>#include <asm-generic/bitops/minix.h3/a>>oL464" class="line" namon>L464">v464.8a>#include <asm-generic/bitops/sched.h3/a>>oL465" class="line" namon>L465">v4653/a>oL466" class="line" namon>L466">v466.8a>#endif 3spa	 class="comment">/* __KERNEL__ */L467" class="line" namon>L467">v4673/a>oL468" class="line" namon>L468">v468.8a>#endif 3spa	 class="comment">/* _ASM_IA64_BITOPS_H */L469" class="line" namon>L469">v469.8a>
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