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23#ifndef __SOUND_ASOUND_H
24#define __SOUND_ASOUND_H
25
26#ifdef __KERNEL__
27#include <linux/ioctl.h>
28#include <linux/types.h>
29#include <linux/time.h>
30#include <asm/byteorder.h>
31
32#ifdef __LITTLE_ENDIAN
33#define SNDRV_LITTLE_ENDIAN
34#else
35#ifdef __BIG_ENDIAN
36#define SNDRV_BIG_ENDIAN
37#else
38#error "Unsupported endian..."
39#endif
40#endif
41
42#endif
43
44
45
46
47
48#define SNDRV_PROTOCOL_VERSION(major, minor, subminor) (((major)<<16)|((minor)<<8)|(subminor))
49#define SNDRV_PROTOCOL_MAJOR(version) (((version)>>16)&0xffff)
50#define SNDRV_PROTOCOL_MINOR(version) (((version)>>8)&0xff)
51#define SNDRV_PROTOCOL_MICRO(version) ((version)&0xff)
52#define SNDRV_PROTOCOL_INCOMPATIBLE(kversion, uversion) \
53 (SNDRV_PROTOCOL_MAJOR(kversion) != SNDRV_PROTOCOL_MAJOR(uversion) || \
54 (SNDRV_PROTOCOL_MAJOR(kversion) == SNDRV_PROTOCOL_MAJOR(uversion) && \
55 SNDRV_PROTOCOL_MINOR(kversion) != SNDRV_PROTOCOL_MINOR(uversion)))
56
57
58
59
60
61
62
63struct snd_aes_iec958 {
64 unsigned char status[24];
65 unsigned char subcode[147];
66 unsigned char pad;
67 unsigned char dig_subframe[4];
68};
69
70
71
72
73
74
75
76#define SNDRV_HWDEP_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
77
78enum {
79 SNDRV_HWDEP_IFACE_OPL2 = 0,
80 SNDRV_HWDEP_IFACE_OPL3,
81 SNDRV_HWDEP_IFACE_OPL4,
82 SNDRV_HWDEP_IFACE_SB16CSP,
83 SNDRV_HWDEP_IFACE_EMU10K1,
84 SNDRV_HWDEP_IFACE_YSS225,
85 SNDRV_HWDEP_IFACE_ICS2115,
86 SNDRV_HWDEP_IFACE_SSCAPE,
87 SNDRV_HWDEP_IFACE_VX,
88 SNDRV_HWDEP_IFACE_MIXART,
89 SNDRV_HWDEP_IFACE_USX2Y,
90 SNDRV_HWDEP_IFACE_EMUX_WAVETABLE,
91 SNDRV_HWDEP_IFACE_BLUETOOTH,
92 SNDRV_HWDEP_IFACE_USX2Y_PCM,
93 SNDRV_HWDEP_IFACE_PCXHR,
94 SNDRV_HWDEP_IFACE_SB_RC,
95 SNDRV_HWDEP_IFACE_HDA,
96 SNDRV_HWDEP_IFACE_USB_STREAM,
97
98
99 SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_USB_STREAM
100};
101
102struct snd_hwdep_info {
103 unsigned int device;
104 int card;
105 unsigned char id[64];
106 unsigned char name[80];
107 int iface;
108 unsigned char reserved[64];
109};
110
111
112struct snd_hwdep_dsp_status {
113 unsigned int version;
114 unsigned char id[32];
115 unsigned int num_dsps;
116 unsigned int dsp_loaded;
117 unsigned int chip_ready;
118 unsigned char reserved[16];
119};
120
121struct snd_hwdep_dsp_image {
122 unsigned int index;
123 unsigned char name[64];
124 unsigned char __user *image;
125 size_t length;
126 unsigned long driver_data;
127};
128
129enum {
130 SNDRV_HWDEP_IOCTL_PVERSION = _IOR ('H', 0x00, int),
131 SNDRV_HWDEP_IOCTL_INFO = _IOR ('H', 0x01, struct snd_hwdep_info),
132 SNDRV_HWDEP_IOCTL_DSP_STATUS = _IOR('H', 0x02, struct snd_hwdep_dsp_status),
133 SNDRV_HWDEP_IOCTL_DSP_LOAD = _IOW('H', 0x03, struct snd_hwdep_dsp_image)
134};
135
136
137
138
139
140
141
142#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 9)
143
144typedef unsigned long snd_pcm_uframes_t;
145typedef signed long snd_pcm_sframes_t;
146
147enum {
148 SNDRV_PCM_CLASS_GENERIC = 0,
149 SNDRV_PCM_CLASS_MULTI,
150 SNDRV_PCM_CLASS_MODEM,
151 SNDRV_PCM_CLASS_DIGITIZER,
152
153 SNDRV_PCM_CLASS_LAST = SNDRV_PCM_CLASS_DIGITIZER,
154};
155
156enum {
157 SNDRV_PCM_SUBCLASS_GENERIC_MIX = 0,
158 SNDRV_PCM_SUBCLASS_MULTI_MIX,
159
160 SNDRV_PCM_SUBCLASS_LAST = SNDRV_PCM_SUBCLASS_MULTI_MIX,
161};
162
163enum {
164 SNDRV_PCM_STREAM_PLAYBACK = 0,
165 SNDRV_PCM_STREAM_CAPTURE,
166 SNDRV_PCM_STREAM_LAST = SNDRV_PCM_STREAM_CAPTURE,
167};
168
169typedef int __bitwise snd_pcm_access_t;
170#define SNDRV_PCM_ACCESS_MMAP_INTERLEAVED ((__force snd_pcm_access_t) 0)
171#define SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED ((__force snd_pcm_access_t) 1)
172#define SNDRV_PCM_ACCESS_MMAP_COMPLEX ((__force snd_pcm_access_t) 2)
173#define SNDRV_PCM_ACCESS_RW_INTERLEAVED ((__force snd_pcm_access_t) 3)
174#define SNDRV_PCM_ACCESS_RW_NONINTERLEAVED ((__force snd_pcm_access_t) 4)
175#define SNDRV_PCM_ACCESS_LAST SNDRV_PCM_ACCESS_RW_NONINTERLEAVED
176
177typedef int __bitwise snd_pcm_format_t;
178#define SNDRV_PCM_FORMAT_S8 ((__force snd_pcm_format_t) 0)
179#define SNDRV_PCM_FORMAT_U8 ((__force snd_pcm_format_t) 1)
180#define SNDRV_PCM_FORMAT_S16_LE ((__force snd_pcm_format_t) 2)
181#define SNDRV_PCM_FORMAT_S16_BE ((__force snd_pcm_format_t) 3)
182#define SNDRV_PCM_FORMAT_U16_LE ((__force snd_pcm_format_t) 4)
183#define SNDRV_PCM_FORMAT_U16_BE ((__force snd_pcm_format_t) 5)
184#define SNDRV_PCM_FORMAT_S24_LE ((__force snd_pcm_format_t) 6)
185#define SNDRV_PCM_FORMAT_S24_BE ((__force snd_pcm_format_t) 7)
186#define SNDRV_PCM_FORMAT_U24_LE ((__force snd_pcm_format_t) 8)
187#define SNDRV_PCM_FORMAT_U24_BE ((__force snd_pcm_format_t) 9)
188#define SNDRV_PCM_FORMAT_S32_LE ((__force snd_pcm_format_t) 10)
189#define SNDRV_PCM_FORMAT_S32_BE ((__force snd_pcm_format_t) 11)
190#define SNDRV_PCM_FORMAT_U32_LE ((__force snd_pcm_format_t) 12)
191#define SNDRV_PCM_FORMAT_U32_BE ((__force snd_pcm_format_t) 13)
192#define SNDRV_PCM_FORMAT_FLOAT_LE ((__force snd_pcm_format_t) 14)
193#define SNDRV_PCM_FORMAT_FLOAT_BE ((__force snd_pcm_format_t) 15)
194#define SNDRV_PCM_FORMAT_FLOAT64_LE ((__force snd_pcm_format_t) 16)
195#define SNDRV_PCM_FORMAT_FLOAT64_BE ((__force snd_pcm_format_t) 17)
196#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE ((__force snd_pcm_format_t) 18)
197#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE ((__force snd_pcm_format_t) 19)
198#define SNDRV_PCM_FORMAT_MU_LAW ((__force snd_pcm_format_t) 20)
199#define SNDRV_PCM_FORMAT_A_LAW ((__force snd_pcm_format_t) 21)
200#define SNDRV_PCM_FORMAT_IMA_ADPCM ((__force snd_pcm_format_t) 22)
201#define SNDRV_PCM_FORMAT_MPEG ((__force snd_pcm_format_t) 23)
202#define SNDRV_PCM_FORMAT_GSM ((__force snd_pcm_format_t) 24)
203#define SNDRV_PCM_FORMAT_SPECIAL ((__force snd_pcm_format_t) 31)
204#define SNDRV_PCM_FORMAT_S24_3LE ((__force snd_pcm_format_t) 32)
205#define SNDRV_PCM_FORMAT_S24_3BE ((__force snd_pcm_format_t) 33)
206#define SNDRV_PCM_FORMAT_U24_3LE ((__force snd_pcm_format_t) 34)
207#define SNDRV_PCM_FORMAT_U24_3BE ((__force snd_pcm_format_t) 35)
208#define SNDRV_PCM_FORMAT_S20_3LE ((__force snd_pcm_format_t) 36)
209#define SNDRV_PCM_FORMAT_S20_3BE ((__force snd_pcm_format_t) 37)
210#define SNDRV_PCM_FORMAT_U20_3LE ((__force snd_pcm_format_t) 38)
211#define SNDRV_PCM_FORMAT_U20_3BE ((__force snd_pcm_format_t) 39)
212#define SNDRV_PCM_FORMAT_S18_3LE ((__force snd_pcm_format_t) 40)
213#define SNDRV_PCM_FORMAT_S18_3BE ((__force snd_pcm_format_t) 41)
214#define SNDRV_PCM_FORMAT_U18_3LE ((__force snd_pcm_format_t) 42)
215#define SNDRV_PCM_FORMAT_U18_3BE ((__force snd_pcm_format_t) 43)
216#define SNDRV_PCM_FORMAT_LAST SNDRV_PCM_FORMAT_U18_3BE
217
218#ifdef SNDRV_LITTLE_ENDIAN
219#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_LE
220#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_LE
221#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_LE
222#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_LE
223#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_LE
224#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_LE
225#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE
226#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE
227#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE
228#endif
229#ifdef SNDRV_BIG_ENDIAN
230#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE
231#define SNDRV_PCM_FORMAT_U16 SNDRV_PCM_FORMAT_U16_BE
232#define SNDRV_PCM_FORMAT_S24 SNDRV_PCM_FORMAT_S24_BE
233#define SNDRV_PCM_FORMAT_U24 SNDRV_PCM_FORMAT_U24_BE
234#define SNDRV_PCM_FORMAT_S32 SNDRV_PCM_FORMAT_S32_BE
235#define SNDRV_PCM_FORMAT_U32 SNDRV_PCM_FORMAT_U32_BE
236#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE
237#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE
238#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE
239#endif
240
241typedef int __bitwise snd_pcm_subformat_t;
242#define SNDRV_PCM_SUBFORMAT_STD ((__force snd_pcm_subformat_t) 0)
243#define SNDRV_PCM_SUBFORMAT_LAST SNDRV_PCM_SUBFORMAT_STD
244
245#define SNDRV_PCM_INFO_MMAP 0x00000001
246#define SNDRV_PCM_INFO_MMAP_VALID 0x00000002
247#define SNDRV_PCM_INFO_DOUBLE 0x00000004
248#define SNDRV_PCM_INFO_BATCH 0x00000010
249#define SNDRV_PCM_INFO_INTERLEAVED 0x00000100
250#define SNDRV_PCM_INFO_NONINTERLEAVED 0x00000200
251#define SNDRV_PCM_INFO_COMPLEX 0x00000400
252#define SNDRV_PCM_INFO_BLOCK_TRANSFER 0x00010000
253#define SNDRV_PCM_INFO_OVERRANGE 0x00020000
254#define SNDRV_PCM_INFO_RESUME 0x00040000
255#define SNDRV_PCM_INFO_PAUSE 0x00080000
256#define SNDRV_PCM_INFO_HALF_DUPLEX 0x00100000
257#define SNDRV_PCM_INFO_JOINT_DUPLEX 0x00200000
258#define SNDRV_PCM_INFO_SYNC_START 0x00400000
259
260typedef int __bitwise snd_pcm_state_t;
261#define SNDRV_PCM_STATE_OPEN ((__force snd_pcm_state_t) 0)
262#define SNDRV_PCM_STATE_SETUP ((__force snd_pcm_state_t) 1)
263#define SNDRV_PCM_STATE_PREPARED ((__force snd_pcm_state_t) 2)
264#define SNDRV_PCM_STATE_RUNNING ((__force snd_pcm_state_t) 3)
265#define SNDRV_PCM_STATE_XRUN ((__force snd_pcm_state_t) 4)
266#define SNDRV_PCM_STATE_DRAINING ((__force snd_pcm_state_t) 5)
267#define SNDRV_PCM_STATE_PAUSED ((__force snd_pcm_state_t) 6)
268#define SNDRV_PCM_STATE_SUSPENDED ((__force snd_pcm_state_t) 7)
269#define SNDRV_PCM_STATE_DISCONNECTED ((__force snd_pcm_state_t) 8)
270#define SNDRV_PCM_STATE_LAST SNDRV_PCM_STATE_DISCONNECTED
271
272enum {
273 SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000,
274 SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000,
275 SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000,
276};
277
278union snd_pcm_sync_id {
279 unsigned char id[16];
280 unsigned short id16[8];
281 unsigned int id32[4];
282};
283
284struct snd_pcm_info {
285 unsigned int device;
286 unsigned int subdevice;
287 int stream;
288 int card;
289 unsigned char id[64];
290 unsigned char name[80];
291 unsigned char subname[32];
292 int dev_class;
293 int dev_subclass;
294 unsigned int subdevices_count;
295 unsigned int subdevices_avail;
296 union snd_pcm_sync_id sync;
297 unsigned char reserved[64];
298};
299
300typedef int snd_pcm_hw_param_t;
301#define SNDRV_PCM_HW_PARAM_ACCESS 0
302#define SNDRV_PCM_HW_PARAM_FORMAT 1
303#define SNDRV_PCM_HW_PARAM_SUBFORMAT 2
304#define SNDRV_PCM_HW_PARAM_FIRST_MASK SNDRV_PCM_HW_PARAM_ACCESS
305#define SNDRV_PCM_HW_PARAM_LAST_MASK SNDRV_PCM_HW_PARAM_SUBFORMAT
306
307#define SNDRV_PCM_HW_PARAM_SAMPLE_BITS 8
308#define SNDRV_PCM_HW_PARAM_FRAME_BITS 9
309#define SNDRV_PCM_HW_PARAM_CHANNELS 10
310#define SNDRV_PCM_HW_PARAM_RATE 11
311#define SNDRV_PCM_HW_PARAM_PERIOD_TIME 12
312
313
314#define SNDRV_PCM_HW_PARAM_PERIOD_SIZE 13
315
316
317#define SNDRV_PCM_HW_PARAM_PERIOD_BYTES 14
318
319
320#define SNDRV_PCM_HW_PARAM_PERIODS 15
321
322
323#define SNDRV_PCM_HW_PARAM_BUFFER_TIME 16
324
325
326#define SNDRV_PCM_HW_PARAM_BUFFER_SIZE 17
327#define SNDRV_PCM_HW_PARAM_BUFFER_BYTES 18
328#define SNDRV_PCM_HW_PARAM_TICK_TIME 19
329#define SNDRV_PCM_HW_PARAM_FIRST_INTERVAL SNDRV_PCM_HW_PARAM_SAMPLE_BITS
330#define SNDRV_PCM_HW_PARAM_LAST_INTERVAL SNDRV_PCM_HW_PARAM_TICK_TIME
331
332#define SNDRV_PCM_HW_PARAMS_NORESAMPLE (1<<0)
333
334struct snd_interval {
335 unsigned int min, max;
336 unsigned int openmin:1,
337 openmax:1,
338 integer:1,
339 empty:1;
340};
341
342#define SNDRV_MASK_MAX 256
343
344struct snd_mask {
345 u_int32_t bits[(SNDRV_MASK_MAX+31)/32];
346};
347
348struct snd_pcm_hw_params {
349 unsigned int flags;
350 struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK -
351 SNDRV_PCM_HW_PARAM_FIRST_MASK + 1];
352 struct snd_mask mres[5];
353 struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL -
354 SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1];
355 struct snd_interval ires[9];
356 unsigned int rmask;
357 unsigned int cmask;
358 unsigned int info;
359 unsigned int msbits;
360 unsigned int rate_num;
361 unsigned int rate_den;
362 snd_pcm_uframes_t fifo_size;
363 unsigned char reserved[64];
364};
365
366enum {
367 SNDRV_PCM_TSTAMP_NONE = 0,
368 SNDRV_PCM_TSTAMP_ENABLE,
369 SNDRV_PCM_TSTAMP_LAST = SNDRV_PCM_TSTAMP_ENABLE,
370};
371
372struct snd_pcm_sw_params {
373 int tstamp_mode;
374 unsigned int period_step;
375 unsigned int sleep_min;
376 snd_pcm_uframes_t avail_min;
377 snd_pcm_uframes_t xfer_align;
378 snd_pcm_uframes_t start_threshold;
379 snd_pcm_uframes_t stop_threshold;
380 snd_pcm_uframes_t silence_threshold;
381 snd_pcm_uframes_t silence_size;
382 snd_pcm_uframes_t boundary;
383 unsigned char reserved[64];
384};
385
386struct snd_pcm_channel_info {
387 unsigned int channel;
388 off_t offset;
389 unsigned int first;
390 unsigned int step;
391};
392
393struct snd_pcm_status {
394 snd_pcm_state_t state;
395 struct timespec trigger_tstamp;
396 struct timespec tstamp;
397 snd_pcm_uframes_t appl_ptr;
398 snd_pcm_uframes_t hw_ptr;
399 snd_pcm_sframes_t delay;
400 snd_pcm_uframes_t avail;
401 snd_pcm_uframes_t avail_max;
402 snd_pcm_uframes_t overrange;
403 snd_pcm_state_t suspended_state;
404 unsigned char reserved[60];
405};
406
407struct snd_pcm_mmap_status {
408 snd_pcm_state_t state;
409 int pad1;
410 snd_pcm_uframes_t hw_ptr;
411 struct timespec tstamp;
412 snd_pcm_state_t suspended_state;
413};
414
415struct snd_pcm_mmap_control {
416 snd_pcm_uframes_t appl_ptr;
417 snd_pcm_uframes_t avail_min;
418};
419
420#define SNDRV_PCM_SYNC_PTR_HWSYNC (1<<0)
421#define SNDRV_PCM_SYNC_PTR_APPL (1<<1)
422#define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1<<2)
423
424struct snd_pcm_sync_ptr {
425 unsigned int flags;
426 union {
427 struct snd_pcm_mmap_status status;
428 unsigned char reserved[64];
429 } s;
430 union {
431 struct snd_pcm_mmap_control control;
432 unsigned char reserved[64];
433 } c;
434};
435
436struct snd_xferi {
437 snd_pcm_sframes_t result;
438 void __user *buf;
439 snd_pcm_uframes_t frames;
440};
441
442struct snd_xfern {
443 snd_pcm_sframes_t result;
444 void __user * __user *bufs;
445 snd_pcm_uframes_t frames;
446};
447
448enum {
449 SNDRV_PCM_TSTAMP_TYPE_GETTIMEOFDAY = 0,
450 SNDRV_PCM_TSTAMP_TYPE_MONOTONIC,
451 SNDRV_PCM_TSTAMP_TYPE_LAST = SNDRV_PCM_TSTAMP_TYPE_MONOTONIC,
452};
453
454enum {
455 SNDRV_PCM_IOCTL_PVERSION = _IOR('A', 0x00, int),
456 SNDRV_PCM_IOCTL_INFO = _IOR('A', 0x01, struct snd_pcm_info),
457 SNDRV_PCM_IOCTL_TSTAMP = _IOW('A', 0x02, int),
458 SNDRV_PCM_IOCTL_TTSTAMP = _IOW('A', 0x03, int),
459 SNDRV_PCM_IOCTL_HW_REFINE = _IOWR('A', 0x10, struct snd_pcm_hw_params),
460 SNDRV_PCM_IOCTL_HW_PARAMS = _IOWR('A', 0x11, struct snd_pcm_hw_params),
461 SNDRV_PCM_IOCTL_HW_FREE = _IO('A', 0x12),
462 SNDRV_PCM_IOCTL_SW_PARAMS = _IOWR('A', 0x13, struct snd_pcm_sw_params),
463 SNDRV_PCM_IOCTL_STATUS = _IOR('A', 0x20, struct snd_pcm_status),
464 SNDRV_PCM_IOCTL_DELAY = _IOR('A', 0x21, snd_pcm_sframes_t),
465 SNDRV_PCM_IOCTL_HWSYNC = _IO('A', 0x22),
466 SNDRV_PCM_IOCTL_SYNC_PTR = _IOWR('A', 0x23, struct snd_pcm_sync_ptr),
467 SNDRV_PCM_IOCTL_CHANNEL_INFO = _IOR('A', 0x32, struct snd_pcm_channel_info),
468 SNDRV_PCM_IOCTL_PREPARE = _IO('A', 0x40),
469 SNDRV_PCM_IOCTL_RESET = _IO('A', 0x41),
470 SNDRV_PCM_IOCTL_START = _IO('A', 0x42),
471 SNDRV_PCM_IOCTL_DROP = _IO('A', 0x43),
472 SNDRV_PCM_IOCTL_DRAIN = _IO('A', 0x44),
473 SNDRV_PCM_IOCTL_PAUSE = _IOW('A', 0x45, int),
474 SNDRV_PCM_IOCTL_REWIND = _IOW('A', 0x46, snd_pcm_uframes_t),
475 SNDRV_PCM_IOCTL_RESUME = _IO('A', 0x47),
476 SNDRV_PCM_IOCTL_XRUN = _IO('A', 0x48),
477 SNDRV_PCM_IOCTL_FORWARD = _IOW('A', 0x49, snd_pcm_uframes_t),
478 SNDRV_PCM_IOCTL_WRITEI_FRAMES = _IOW('A', 0x50, struct snd_xferi),
479 SNDRV_PCM_IOCTL_READI_FRAMES = _IOR('A', 0x51, struct snd_xferi),
480 SNDRV_PCM_IOCTL_WRITEN_FRAMES = _IOW('A', 0x52, struct snd_xfern),
481 SNDRV_PCM_IOCTL_READN_FRAMES = _IOR('A', 0x53, struct snd_xfern),
482 SNDRV_PCM_IOCTL_LINK = _IOW('A', 0x60, int),
483 SNDRV_PCM_IOCTL_UNLINK = _IO('A', 0x61),
484};
485
486
487#define SNDRV_PCM_IOCTL_REWIND SNDRV_PCM_IOCTL_REWIND
488
489
490
491
492
493
494
495
496
497
498
499#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0)
500
501enum {
502 SNDRV_RAWMIDI_STREAM_OUTPUT = 0,
503 SNDRV_RAWMIDI_STREAM_INPUT,
504 SNDRV_RAWMIDI_STREAM_LAST = SNDRV_RAWMIDI_STREAM_INPUT,
505};
506
507#define SNDRV_RAWMIDI_INFO_OUTPUT 0x00000001
508#define SNDRV_RAWMIDI_INFO_INPUT 0x00000002
509#define SNDRV_RAWMIDI_INFO_DUPLEX 0x00000004
510
511struct snd_rawmidi_info {
512 unsigned int device;
513 unsigned int subdevice;
514 int stream;
515 int card;
516 unsigned int flags;
517 unsigned char id[64];
518 unsigned char name[80];
519 unsigned char subname[32];
520 unsigned int subdevices_count;
521 unsigned int subdevices_avail;
522 unsigned char reserved[64];
523};
524
525struct snd_rawmidi_params {
526 int stream;
527 size_t buffer_size;
528 size_t avail_min;
529 unsigned int no_active_sensing: 1;
530 unsigned char reserved[16];
531};
532
533struct snd_rawmidi_status {
534 int stream;
535 struct timespec tstamp;
536 size_t avail;
537 size_t xruns;
538 unsigned char reserved[16];
539};
540
541enum {
542 SNDRV_RAWMIDI_IOCTL_PVERSION = _IOR('W', 0x00, int),
543 SNDRV_RAWMIDI_IOCTL_INFO = _IOR('W', 0x01, struct snd_rawmidi_info),
544 SNDRV_RAWMIDI_IOCTL_PARAMS = _IOWR('W', 0x10, struct snd_rawmidi_params),
545 SNDRV_RAWMIDI_IOCTL_STATUS = _IOWR('W', 0x20, struct snd_rawmidi_status),
546 SNDRV_RAWMIDI_IOCTL_DROP = _IOW('W', 0x30, int),
547 SNDRV_RAWMIDI_IOCTL_DRAIN = _IOW('W', 0x31, int),
548};
549
550
551
552
553
554#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 5)
555
556enum {
557 SNDRV_TIMER_CLASS_NONE = -1,
558 SNDRV_TIMER_CLASS_SLAVE = 0,
559 SNDRV_TIMER_CLASS_GLOBAL,
560 SNDRV_TIMER_CLASS_CARD,
561 SNDRV_TIMER_CLASS_PCM,
562 SNDRV_TIMER_CLASS_LAST = SNDRV_TIMER_CLASS_PCM,
563};
564
565
566enum {
567 SNDRV_TIMER_SCLASS_NONE = 0,
568 SNDRV_TIMER_SCLASS_APPLICATION,
569 SNDRV_TIMER_SCLASS_SEQUENCER,
570 SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
571 SNDRV_TIMER_SCLASS_LAST = SNDRV_TIMER_SCLASS_OSS_SEQUENCER,
572};
573
574
575#define SNDRV_TIMER_GLOBAL_SYSTEM 0
576#define SNDRV_TIMER_GLOBAL_RTC 1
577#define SNDRV_TIMER_GLOBAL_HPET 2
578
579
580#define SNDRV_TIMER_FLG_SLAVE (1<<0)
581
582struct snd_timer_id {
583 int dev_class;
584 int dev_sclass;
585 int card;
586 int device;
587 int subdevice;
588};
589
590struct snd_timer_ginfo {
591 struct snd_timer_id tid;
592 unsigned int flags;
593 int card;
594 unsigned char id[64];
595 unsigned char name[80];
596 unsigned long reserved0;
597 unsigned long resolution;
598 unsigned long resolution_min;
599 unsigned long resolution_max;
600 unsigned int clients;
601 unsigned char reserved[32];
602};
603
604struct snd_timer_gparams {
605 struct snd_timer_id tid;
606 unsigned long period_num;
607 unsigned long period_den;
608 unsigned char reserved[32];
609};
610
611struct snd_timer_gstatus {
612 struct snd_timer_id tid;
613 unsigned long resolution;
614 unsigned long resolution_num;
615 unsigned long resolution_den;
616 unsigned char reserved[32];
617};
618
619struct snd_timer_select {
620 struct snd_timer_id id;
621 unsigned char reserved[32];
622};
623
624struct snd_timer_info {
625 unsigned int flags;
626 int card;
627 unsigned char id[64];
628 unsigned char name[80];
629 unsigned long reserved0;
630 unsigned long resolution;
631 unsigned char reserved[64];
632};
633
634#define SNDRV_TIMER_PSFLG_AUTO (1<<0)
635#define SNDRV_TIMER_PSFLG_EXCLUSIVE (1<<1)
636#define SNDRV_TIMER_PSFLG_EARLY_EVENT (1<<2)
637
638struct snd_timer_params {
639 unsigned int flags;
640 unsigned int ticks;
641 unsigned int queue_size;
642 unsigned int reserved0;
643 unsigned int filter;
644 unsigned char reserved[60];
645};
646
647struct snd_timer_status {
648 struct timespec tstamp;
649 unsigned int resolution;
650 unsigned int lost;
651 unsigned int overrun;
652 unsigned int queue;
653 unsigned char reserved[64];
654};
655
656enum {
657 SNDRV_TIMER_IOCTL_PVERSION = _IOR('T', 0x00, int),
658 SNDRV_TIMER_IOCTL_NEXT_DEVICE = _IOWR('T', 0x01, struct snd_timer_id),
659 SNDRV_TIMER_IOCTL_TREAD = _IOW('T', 0x02, int),
660 SNDRV_TIMER_IOCTL_GINFO = _IOWR('T', 0x03, struct snd_timer_ginfo),
661 SNDRV_TIMER_IOCTL_GPARAMS = _IOW('T', 0x04, struct snd_timer_gparams),
662 SNDRV_TIMER_IOCTL_GSTATUS = _IOWR('T', 0x05, struct snd_timer_gstatus),
663 SNDRV_TIMER_IOCTL_SELECT = _IOW('T', 0x10, struct snd_timer_select),
664 SNDRV_TIMER_IOCTL_INFO = _IOR('T', 0x11, struct snd_timer_info),
665 SNDRV_TIMER_IOCTL_PARAMS = _IOW('T', 0x12, struct snd_timer_params),
666 SNDRV_TIMER_IOCTL_STATUS = _IOR('T', 0x14, struct snd_timer_status),
667
668 SNDRV_TIMER_IOCTL_START = _IO('T', 0xa0),
669 SNDRV_TIMER_IOCTL_STOP = _IO('T', 0xa1),
670 SNDRV_TIMER_IOCTL_CONTINUE = _IO('T', 0xa2),
671 SNDRV_TIMER_IOCTL_PAUSE = _IO('T', 0xa3),
672};
673
674struct snd_timer_read {
675 unsigned int resolution;
676 unsigned int ticks;
677};
678
679enum {
680 SNDRV_TIMER_EVENT_RESOLUTION = 0,
681 SNDRV_TIMER_EVENT_TICK,
682 SNDRV_TIMER_EVENT_START,
683 SNDRV_TIMER_EVENT_STOP,
684 SNDRV_TIMER_EVENT_CONTINUE,
685 SNDRV_TIMER_EVENT_PAUSE,
686 SNDRV_TIMER_EVENT_EARLY,
687 SNDRV_TIMER_EVENT_SUSPEND,
688 SNDRV_TIMER_EVENT_RESUME,
689
690 SNDRV_TIMER_EVENT_MSTART = SNDRV_TIMER_EVENT_START + 10,
691 SNDRV_TIMER_EVENT_MSTOP = SNDRV_TIMER_EVENT_STOP + 10,
692 SNDRV_TIMER_EVENT_MCONTINUE = SNDRV_TIMER_EVENT_CONTINUE + 10,
693 SNDRV_TIMER_EVENT_MPAUSE = SNDRV_TIMER_EVENT_PAUSE + 10,
694 SNDRV_TIMER_EVENT_MSUSPEND = SNDRV_TIMER_EVENT_SUSPEND + 10,
695 SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10,
696};
697
698struct snd_timer_tread {
699 int event;
700 struct timespec tstamp;
701 unsigned int val;
702};
703
704
705
706
707
708
709
710#define SNDRV_CTL_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 6)
711
712struct snd_ctl_card_info {
713 int card;
714 int pad;
715 unsigned char id[16];
716 unsigned char driver[16];
717 unsigned char name[32];
718 unsigned char longname[80];
719 unsigned char reserved_[16];
720 unsigned char mixername[80];
721 unsigned char components[128];
722};
723
724typedef int __bitwise snd_ctl_elem_type_t;
725#define SNDRV_CTL_ELEM_TYPE_NONE ((__force snd_ctl_elem_type_t) 0)
726#define SNDRV_CTL_ELEM_TYPE_BOOLEAN ((__force snd_ctl_elem_type_t) 1)
727#define SNDRV_CTL_ELEM_TYPE_INTEGER ((__force snd_ctl_elem_type_t) 2)
728#define SNDRV_CTL_ELEM_TYPE_ENUMERATED ((__force snd_ctl_elem_type_t) 3)
729#define SNDRV_CTL_ELEM_TYPE_BYTES ((__force snd_ctl_elem_type_t) 4)
730#define SNDRV_CTL_ELEM_TYPE_IEC958 ((__force snd_ctl_elem_type_t) 5)
731#define SNDRV_CTL_ELEM_TYPE_INTEGER64 ((__force snd_ctl_elem_type_t) 6)
732#define SNDRV_CTL_ELEM_TYPE_LAST SNDRV_CTL_ELEM_TYPE_INTEGER64
733
734typedef int __bitwise snd_ctl_elem_iface_t;
735#define SNDRV_CTL_ELEM_IFACE_CARD ((__force snd_ctl_elem_iface_t) 0)
736#define SNDRV_CTL_ELEM_IFACE_HWDEP ((__force snd_ctl_elem_iface_t) 1)
737#define SNDRV_CTL_ELEM_IFACE_MIXER ((__force snd_ctl_elem_iface_t) 2)
738#define SNDRV_CTL_ELEM_IFACE_PCM ((__force snd_ctl_elem_iface_t) 3)
739#define SNDRV_CTL_ELEM_IFACE_RAWMIDI ((__force snd_ctl_elem_iface_t) 4)
740#define SNDRV_CTL_ELEM_IFACE_TIMER ((__force snd_ctl_elem_iface_t) 5)
741#define SNDRV_CTL_ELEM_IFACE_SEQUENCER ((__force snd_ctl_elem_iface_t) 6)
742#define SNDRV_CTL_ELEM_IFACE_LAST SNDRV_CTL_ELEM_IFACE_SEQUENCER
743
744#define SNDRV_CTL_ELEM_ACCESS_READ (1<<0)
745#define SNDRV_CTL_ELEM_ACCESS_WRITE (1<<1)
746#define SNDRV_CTL_ELEM_ACCESS_READWRITE (SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE)
747#define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1<<2)
748#define SNDRV_CTL_ELEM_ACCESS_TIMESTAMP (1<<3)
749#define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1<<4)
750#define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1<<5)
751#define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ|SNDRV_CTL_ELEM_ACCESS_TLV_WRITE)
752#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1<<6)
753#define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1<<8)
754#define SNDRV_CTL_ELEM_ACCESS_LOCK (1<<9)
755#define SNDRV_CTL_ELEM_ACCESS_OWNER (1<<10)
756#define SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK (1<<28)
757#define SNDRV_CTL_ELEM_ACCESS_USER (1<<29)
758
759
760
761#define SNDRV_CTL_POWER_D0 0x0000
762#define SNDRV_CTL_POWER_D1 0x0100
763#define SNDRV_CTL_POWER_D2 0x0200
764#define SNDRV_CTL_POWER_D3 0x0300
765#define SNDRV_CTL_POWER_D3hot (SNDRV_CTL_POWER_D3|0x0000)
766#define SNDRV_CTL_POWER_D3cold (SNDRV_CTL_POWER_D3|0x0001)
767
768struct snd_ctl_elem_id {
769 unsigned int numid;
770 snd_ctl_elem_iface_t iface;
771 unsigned int device;
772 unsigned int subdevice;
773 unsigned char name[44];
774 unsigned int index;
775};
776
777struct snd_ctl_elem_list {
778 unsigned int offset;
779 unsigned int space;
780 unsigned int used;
781 unsigned int count;
782 struct snd_ctl_elem_id __user *pids;
783 unsigned char reserved[50];
784};
785
786struct snd_ctl_elem_info {
787 struct snd_ctl_elem_id id;
788 snd_ctl_elem_type_t type;
789 unsigned int access;
790 unsigned int count;
791 pid_t owner;
792 union {
793 struct {
794 long min;
795 long max;
796 long step;
797 } integer;
798 struct {
799 long long min;
800 long long max;
801 long long step;
802 } integer64;
803 struct {
804 unsigned int items;
805 unsigned int item;
806 char name[64];
807 } enumerated;
808 unsigned char reserved[128];
809 } value;
810 union {
811 unsigned short d[4];
812 unsigned short *d_ptr;
813 } dimen;
814 unsigned char reserved[64-4*sizeof(unsigned short)];
815};
816
817struct snd_ctl_elem_value {
818 struct snd_ctl_elem_id id;
819 unsigned int indirect: 1;
820 union {
821 union {
822 long value[128];
823 long *value_ptr;
824 } integer;
825 union {
826 long long value[64];
827 long long *value_ptr;
828 } integer64;
829 union {
830 unsigned int item[128];
831 unsigned int *item_ptr;
832 } enumerated;
833 union {
834 unsigned char data[512];
835 unsigned char *data_ptr;
836 } bytes;
837 struct snd_aes_iec958 iec958;
838 } value;
839 struct timespec tstamp;
840 unsigned char reserved[128-sizeof(struct timespec)];
841};
842
843struct snd_ctl_tlv {
844 unsigned int numid;
845 unsigned int length;
846 unsigned int tlv[0];
847};
848
849enum {
850 SNDRV_CTL_IOCTL_PVERSION = _IOR('U', 0x00, int),
851 SNDRV_CTL_IOCTL_CARD_INFO = _IOR('U', 0x01, struct snd_ctl_card_info),
852 SNDRV_CTL_IOCTL_ELEM_LIST = _IOWR('U', 0x10, struct snd_ctl_elem_list),
853 SNDRV_CTL_IOCTL_ELEM_INFO = _IOWR('U', 0x11, struct snd_ctl_elem_info),
854 SNDRV_CTL_IOCTL_ELEM_READ = _IOWR('U', 0x12, struct snd_ctl_elem_value),
855 SNDRV_CTL_IOCTL_ELEM_WRITE = _IOWR('U', 0x13, struct snd_ctl_elem_value),
856 SNDRV_CTL_IOCTL_ELEM_LOCK = _IOW('U', 0x14, struct snd_ctl_elem_id),
857 SNDRV_CTL_IOCTL_ELEM_UNLOCK = _IOW('U', 0x15, struct snd_ctl_elem_id),
858 SNDRV_CTL_IOCTL_SUBSCRIBE_EVENTS = _IOWR('U', 0x16, int),
859 SNDRV_CTL_IOCTL_ELEM_ADD = _IOWR('U', 0x17, struct snd_ctl_elem_info),
860 SNDRV_CTL_IOCTL_ELEM_REPLACE = _IOWR('U', 0x18, struct snd_ctl_elem_info),
861 SNDRV_CTL_IOCTL_ELEM_REMOVE = _IOWR('U', 0x19, struct snd_ctl_elem_id),
862 SNDRV_CTL_IOCTL_TLV_READ = _IOWR('U', 0x1a, struct snd_ctl_tlv),
863 SNDRV_CTL_IOCTL_TLV_WRITE = _IOWR('U', 0x1b, struct snd_ctl_tlv),
864 SNDRV_CTL_IOCTL_TLV_COMMAND = _IOWR('U', 0x1c, struct snd_ctl_tlv),
865 SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE = _IOWR('U', 0x20, int),
866 SNDRV_CTL_IOCTL_HWDEP_INFO = _IOR('U', 0x21, struct snd_hwdep_info),
867 SNDRV_CTL_IOCTL_PCM_NEXT_DEVICE = _IOR('U', 0x30, int),
868 SNDRV_CTL_IOCTL_PCM_INFO = _IOWR('U', 0x31, struct snd_pcm_info),
869 SNDRV_CTL_IOCTL_PCM_PREFER_SUBDEVICE = _IOW('U', 0x32, int),
870 SNDRV_CTL_IOCTL_RAWMIDI_NEXT_DEVICE = _IOWR('U', 0x40, int),
871 SNDRV_CTL_IOCTL_RAWMIDI_INFO = _IOWR('U', 0x41, struct snd_rawmidi_info),
872 SNDRV_CTL_IOCTL_RAWMIDI_PREFER_SUBDEVICE = _IOW('U', 0x42, int),
873 SNDRV_CTL_IOCTL_POWER = _IOWR('U', 0xd0, int),
874 SNDRV_CTL_IOCTL_POWER_STATE = _IOR('U', 0xd1, int),
875};
876
877
878
879
880
881enum sndrv_ctl_event_type {
882 SNDRV_CTL_EVENT_ELEM = 0,
883 SNDRV_CTL_EVENT_LAST = SNDRV_CTL_EVENT_ELEM,
884};
885
886#define SNDRV_CTL_EVENT_MASK_VALUE (1<<0)
887#define SNDRV_CTL_EVENT_MASK_INFO (1<<1)
888#define SNDRV_CTL_EVENT_MASK_ADD (1<<2)
889#define SNDRV_CTL_EVENT_MASK_TLV (1<<3)
890#define SNDRV_CTL_EVENT_MASK_REMOVE (~0U)
891
892struct snd_ctl_event {
893 int type;
894 union {
895 struct {
896 unsigned int mask;
897 struct snd_ctl_elem_id id;
898 } elem;
899 unsigned char data8[60];
900 } data;
901};
902
903
904
905
906
907#define SNDRV_CTL_NAME_NONE ""
908#define SNDRV_CTL_NAME_PLAYBACK "Playback "
909#define SNDRV_CTL_NAME_CAPTURE "Capture "
910
911#define SNDRV_CTL_NAME_IEC958_NONE ""
912#define SNDRV_CTL_NAME_IEC958_SWITCH "Switch"
913#define SNDRV_CTL_NAME_IEC958_VOLUME "Volume"
914#define SNDRV_CTL_NAME_IEC958_DEFAULT "Default"
915#define SNDRV_CTL_NAME_IEC958_MASK "Mask"
916#define SNDRV_CTL_NAME_IEC958_CON_MASK "Con Mask"
917#define SNDRV_CTL_NAME_IEC958_PRO_MASK "Pro Mask"
918#define SNDRV_CTL_NAME_IEC958_PCM_STREAM "PCM Stream"
919#define SNDRV_CTL_NAME_IEC958(expl,direction,what) "IEC958 " expl SNDRV_CTL_NAME_##direction SNDRV_CTL_NAME_IEC958_##what
920
921
922
923
924
925struct snd_xferv {
926 const struct iovec *vector;
927 unsigned long count;
928};
929
930enum {
931 SNDRV_IOCTL_READV = _IOW('K', 0x00, struct snd_xferv),
932 SNDRV_IOCTL_WRITEV = _IOW('K', 0x01, struct snd_xferv),
933};
934
935#endif
936