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13#ifndef _XTENSA_ATOMIC_H
14#define _XTENSA_ATOMIC_H
15
16#include <linux/stringify.h>
17
18typedef struct { volatile int counter; } atomic_t;
19
20#ifdef __KERNEL__
21#include <asm/processor.h>
22#include <asm/system.h>
23
24#define ATOMIC_INIT(i) { (i) }
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50#define atomic_read(v) ((v)->counter)
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59#define atomic_set(v,i) ((v)->counter = (i))
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68static inline void atomic_add(int i, atomic_t * v)
69{
70 unsigned int vval;
71
72 __asm__ __volatile__(
73 "rsil a15, "__stringify(LOCKLEVEL)"\n\t"
74 "l32i %0, %2, 0 \n\t"
75 "add %0, %0, %1 \n\t"
76 "s32i %0, %2, 0 \n\t"
77 "wsr a15, "__stringify(PS)" \n\t"
78 "rsync \n"
79 : "=&a" (vval)
80 : "a" (i), "a" (v)
81 : "a15", "memory"
82 );
83}
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91
92static inline void atomic_sub(int i, atomic_t *v)
93{
94 unsigned int vval;
95
96 __asm__ __volatile__(
97 "rsil a15, "__stringify(LOCKLEVEL)"\n\t"
98 "l32i %0, %2, 0 \n\t"
99 "sub %0, %0, %1 \n\t"
100 "s32i %0, %2, 0 \n\t"
101 "wsr a15, "__stringify(PS)" \n\t"
102 "rsync \n"
103 : "=&a" (vval)
104 : "a" (i), "a" (v)
105 : "a15", "memory"
106 );
107}
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113static inline int atomic_add_return(int i, atomic_t * v)
114{
115 unsigned int vval;
116
117 __asm__ __volatile__(
118 "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
119 "l32i %0, %2, 0 \n\t"
120 "add %0, %0, %1 \n\t"
121 "s32i %0, %2, 0 \n\t"
122 "wsr a15, "__stringify(PS)" \n\t"
123 "rsync \n"
124 : "=&a" (vval)
125 : "a" (i), "a" (v)
126 : "a15", "memory"
127 );
128
129 return vval;
130}
131
132static inline int atomic_sub_return(int i, atomic_t * v)
133{
134 unsigned int vval;
135
136 __asm__ __volatile__(
137 "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
138 "l32i %0, %2, 0 \n\t"
139 "sub %0, %0, %1 \n\t"
140 "s32i %0, %2, 0 \n\t"
141 "wsr a15, "__stringify(PS)" \n\t"
142 "rsync \n"
143 : "=&a" (vval)
144 : "a" (i), "a" (v)
145 : "a15", "memory"
146 );
147
148 return vval;
149}
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160#define atomic_sub_and_test(i,v) (atomic_sub_return((i),(v)) == 0)
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168#define atomic_inc(v) atomic_add(1,(v))
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176#define atomic_inc_return(v) atomic_add_return(1,(v))
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184#define atomic_dec(v) atomic_sub(1,(v))
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192#define atomic_dec_return(v) atomic_sub_return(1,(v))
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202#define atomic_dec_and_test(v) (atomic_sub_return(1,(v)) == 0)
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212#define atomic_inc_and_test(v) (atomic_add_return(1,(v)) == 0)
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223#define atomic_add_negative(i,v) (atomic_add_return((i),(v)) < 0)
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225#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
226#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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237static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
238{
239 int c, old;
240 c = atomic_read(v);
241 for (;;) {
242 if (unlikely(c == (u)))
243 break;
244 old = atomic_cmpxchg((v), c, c + (a));
245 if (likely(old == c))
246 break;
247 c = old;
248 }
249 return c != (u);
250}
251
252#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
253
254static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
255{
256 unsigned int all_f = -1;
257 unsigned int vval;
258
259 __asm__ __volatile__(
260 "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
261 "l32i %0, %2, 0 \n\t"
262 "xor %1, %4, %3 \n\t"
263 "and %0, %0, %4 \n\t"
264 "s32i %0, %2, 0 \n\t"
265 "wsr a15, "__stringify(PS)" \n\t"
266 "rsync \n"
267 : "=&a" (vval), "=a" (mask)
268 : "a" (v), "a" (all_f), "1" (mask)
269 : "a15", "memory"
270 );
271}
272
273static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
274{
275 unsigned int vval;
276
277 __asm__ __volatile__(
278 "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
279 "l32i %0, %2, 0 \n\t"
280 "or %0, %0, %1 \n\t"
281 "s32i %0, %2, 0 \n\t"
282 "wsr a15, "__stringify(PS)" \n\t"
283 "rsync \n"
284 : "=&a" (vval)
285 : "a" (mask), "a" (v)
286 : "a15", "memory"
287 );
288}
289
290
291#define smp_mb__before_atomic_dec() barrier()
292#define smp_mb__after_atomic_dec() barrier()
293#define smp_mb__before_atomic_inc() barrier()
294#define smp_mb__after_atomic_inc() barrier()
295
296#include <asm-generic/atomic.h>
297#endif
298
299#endif
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301