1#ifndef _ASM_M32R_ATOMIC_H
2#define _ASM_M32R_ATOMIC_H
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12#include <asm/assembler.h>
13#include <asm/system.h>
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25typedef struct { volatile int counter; } atomic_t;
26
27#define ATOMIC_INIT(i) { (i) }
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35#define atomic_read(v) ((v)->counter)
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44#define atomic_set(v,i) (((v)->counter) = (i))
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53static __inline__ int atomic_add_return(int i, atomic_t *v)
54{
55 unsigned long flags;
56 int result;
57
58 local_irq_save(flags);
59 __asm__ __volatile__ (
60 "# atomic_add_return \n\t"
61 DCACHE_CLEAR("%0", "r4", "%1")
62 M32R_LOCK" %0, @%1; \n\t"
63 "add %0, %2; \n\t"
64 M32R_UNLOCK" %0, @%1; \n\t"
65 : "=&r" (result)
66 : "r" (&v->counter), "r" (i)
67 : "memory"
68#ifdef CONFIG_CHIP_M32700_TS1
69 , "r4"
70#endif
71 );
72 local_irq_restore(flags);
73
74 return result;
75}
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84static __inline__ int atomic_sub_return(int i, atomic_t *v)
85{
86 unsigned long flags;
87 int result;
88
89 local_irq_save(flags);
90 __asm__ __volatile__ (
91 "# atomic_sub_return \n\t"
92 DCACHE_CLEAR("%0", "r4", "%1")
93 M32R_LOCK" %0, @%1; \n\t"
94 "sub %0, %2; \n\t"
95 M32R_UNLOCK" %0, @%1; \n\t"
96 : "=&r" (result)
97 : "r" (&v->counter), "r" (i)
98 : "memory"
99#ifdef CONFIG_CHIP_M32700_TS1
100 , "r4"
101#endif
102 );
103 local_irq_restore(flags);
104
105 return result;
106}
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115#define atomic_add(i,v) ((void) atomic_add_return((i), (v)))
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124#define atomic_sub(i,v) ((void) atomic_sub_return((i), (v)))
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135#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
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143static __inline__ int atomic_inc_return(atomic_t *v)
144{
145 unsigned long flags;
146 int result;
147
148 local_irq_save(flags);
149 __asm__ __volatile__ (
150 "# atomic_inc_return \n\t"
151 DCACHE_CLEAR("%0", "r4", "%1")
152 M32R_LOCK" %0, @%1; \n\t"
153 "addi %0, #1; \n\t"
154 M32R_UNLOCK" %0, @%1; \n\t"
155 : "=&r" (result)
156 : "r" (&v->counter)
157 : "memory"
158#ifdef CONFIG_CHIP_M32700_TS1
159 , "r4"
160#endif
161 );
162 local_irq_restore(flags);
163
164 return result;
165}
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172
173static __inline__ int atomic_dec_return(atomic_t *v)
174{
175 unsigned long flags;
176 int result;
177
178 local_irq_save(flags);
179 __asm__ __volatile__ (
180 "# atomic_dec_return \n\t"
181 DCACHE_CLEAR("%0", "r4", "%1")
182 M32R_LOCK" %0, @%1; \n\t"
183 "addi %0, #-1; \n\t"
184 M32R_UNLOCK" %0, @%1; \n\t"
185 : "=&r" (result)
186 : "r" (&v->counter)
187 : "memory"
188#ifdef CONFIG_CHIP_M32700_TS1
189 , "r4"
190#endif
191 );
192 local_irq_restore(flags);
193
194 return result;
195}
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203#define atomic_inc(v) ((void)atomic_inc_return(v))
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211#define atomic_dec(v) ((void)atomic_dec_return(v))
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221#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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231#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
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242#define atomic_add_negative(i,v) (atomic_add_return((i), (v)) < 0)
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244#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
245#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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256static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
257{
258 int c, old;
259 c = atomic_read(v);
260 for (;;) {
261 if (unlikely(c == (u)))
262 break;
263 old = atomic_cmpxchg((v), c, c + (a));
264 if (likely(old == c))
265 break;
266 c = old;
267 }
268 return c != (u);
269}
270
271#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
272
273static __inline__ void atomic_clear_mask(unsigned long mask, atomic_t *addr)
274{
275 unsigned long flags;
276 unsigned long tmp;
277
278 local_irq_save(flags);
279 __asm__ __volatile__ (
280 "# atomic_clear_mask \n\t"
281 DCACHE_CLEAR("%0", "r5", "%1")
282 M32R_LOCK" %0, @%1; \n\t"
283 "and %0, %2; \n\t"
284 M32R_UNLOCK" %0, @%1; \n\t"
285 : "=&r" (tmp)
286 : "r" (addr), "r" (~mask)
287 : "memory"
288#ifdef CONFIG_CHIP_M32700_TS1
289 , "r5"
290#endif
291 );
292 local_irq_restore(flags);
293}
294
295static __inline__ void atomic_set_mask(unsigned long mask, atomic_t *addr)
296{
297 unsigned long flags;
298 unsigned long tmp;
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300 local_irq_save(flags);
301 __asm__ __volatile__ (
302 "# atomic_set_mask \n\t"
303 DCACHE_CLEAR("%0", "r5", "%1")
304 M32R_LOCK" %0, @%1; \n\t"
305 "or %0, %2; \n\t"
306 M32R_UNLOCK" %0, @%1; \n\t"
307 : "=&r" (tmp)
308 : "r" (addr), "r" (mask)
309 : "memory"
310#ifdef CONFIG_CHIP_M32700_TS1
311 , "r5"
312#endif
313 );
314 local_irq_restore(flags);
315}
316
317
318#define smp_mb__before_atomic_dec() barrier()
319#define smp_mb__after_atomic_dec() barrier()
320#define smp_mb__before_atomic_inc() barrier()
321#define smp_mb__after_atomic_inc() barrier()
322
323#include <asm-generic/atomic.h>
324#endif
325