linux/drivers/video/matrox/matroxfb_Ti3026.c
<<
>>
Prefs
   1/*
   2 *
   3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
   4 *
   5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
   6 *
   7 * Portions Copyright (c) 2001 Matrox Graphics Inc.
   8 *
   9 * Version: 1.65 2002/08/14
  10 *
  11 * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
  12 *
  13 * Contributors: "menion?" <menion@mindless.com>
  14 *                     Betatesting, fixes, ideas
  15 *
  16 *               "Kurt Garloff" <garloff@suse.de>
  17 *                     Betatesting, fixes, ideas, videomodes, videomodes timmings
  18 *
  19 *               "Tom Rini" <trini@kernel.crashing.org>
  20 *                     MTRR stuff, PPC cleanups, betatesting, fixes, ideas
  21 *
  22 *               "Bibek Sahu" <scorpio@dodds.net>
  23 *                     Access device through readb|w|l and write b|w|l
  24 *                     Extensive debugging stuff
  25 *
  26 *               "Daniel Haun" <haund@usa.net>
  27 *                     Testing, hardware cursor fixes
  28 *
  29 *               "Scott Wood" <sawst46+@pitt.edu>
  30 *                     Fixes
  31 *
  32 *               "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
  33 *                     Betatesting
  34 *
  35 *               "Kelly French" <targon@hazmat.com>
  36 *               "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
  37 *                     Betatesting, bug reporting
  38 *
  39 *               "Pablo Bianucci" <pbian@pccp.com.ar>
  40 *                     Fixes, ideas, betatesting
  41 *
  42 *               "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
  43 *                     Fixes, enhandcements, ideas, betatesting
  44 *
  45 *               "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
  46 *                     PPC betatesting, PPC support, backward compatibility
  47 *
  48 *               "Paul Womar" <Paul@pwomar.demon.co.uk>
  49 *               "Owen Waller" <O.Waller@ee.qub.ac.uk>
  50 *                     PPC betatesting
  51 *
  52 *               "Thomas Pornin" <pornin@bolet.ens.fr>
  53 *                     Alpha betatesting
  54 *
  55 *               "Pieter van Leuven" <pvl@iae.nl>
  56 *               "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
  57 *                     G100 testing
  58 *
  59 *               "H. Peter Arvin" <hpa@transmeta.com>
  60 *                     Ideas
  61 *
  62 *               "Cort Dougan" <cort@cs.nmt.edu>
  63 *                     CHRP fixes and PReP cleanup
  64 *
  65 *               "Mark Vojkovich" <mvojkovi@ucsd.edu>
  66 *                     G400 support
  67 *
  68 * (following author is not in any relation with this code, but his code
  69 *  is included in this driver)
  70 *
  71 * Based on framebuffer driver for VBE 2.0 compliant graphic boards
  72 *     (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
  73 *
  74 * (following author is not in any relation with this code, but his ideas
  75 *  were used when writing this driver)
  76 *
  77 *               FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
  78 *
  79 */
  80
  81
  82#include "matroxfb_Ti3026.h"
  83#include "matroxfb_misc.h"
  84#include "matroxfb_accel.h"
  85#include <linux/matroxfb.h>
  86
  87#ifdef CONFIG_FB_MATROX_MILLENIUM
  88#define outTi3026 matroxfb_DAC_out
  89#define inTi3026 matroxfb_DAC_in
  90
  91#define TVP3026_INDEX           0x00
  92#define TVP3026_PALWRADD        0x00
  93#define TVP3026_PALDATA         0x01
  94#define TVP3026_PIXRDMSK        0x02
  95#define TVP3026_PALRDADD        0x03
  96#define TVP3026_CURCOLWRADD     0x04
  97#define     TVP3026_CLOVERSCAN          0x00
  98#define     TVP3026_CLCOLOR0            0x01
  99#define     TVP3026_CLCOLOR1            0x02
 100#define     TVP3026_CLCOLOR2            0x03
 101#define TVP3026_CURCOLDATA      0x05
 102#define TVP3026_CURCOLRDADD     0x07
 103#define TVP3026_CURCTRL         0x09
 104#define TVP3026_X_DATAREG       0x0A
 105#define TVP3026_CURRAMDATA      0x0B
 106#define TVP3026_CURPOSXL        0x0C
 107#define TVP3026_CURPOSXH        0x0D
 108#define TVP3026_CURPOSYL        0x0E
 109#define TVP3026_CURPOSYH        0x0F
 110
 111#define TVP3026_XSILICONREV     0x01
 112#define TVP3026_XCURCTRL        0x06
 113#define     TVP3026_XCURCTRL_DIS        0x00    /* transparent, transparent, transparent, transparent */
 114#define     TVP3026_XCURCTRL_3COLOR     0x01    /* transparent, 0, 1, 2 */
 115#define     TVP3026_XCURCTRL_XGA        0x02    /* 0, 1, transparent, complement */
 116#define     TVP3026_XCURCTRL_XWIN       0x03    /* transparent, transparent, 0, 1 */
 117#define     TVP3026_XCURCTRL_BLANK2048  0x00
 118#define     TVP3026_XCURCTRL_BLANK4096  0x10
 119#define     TVP3026_XCURCTRL_INTERLACED 0x20
 120#define     TVP3026_XCURCTRL_ODD        0x00 /* ext.signal ODD/\EVEN */
 121#define     TVP3026_XCURCTRL_EVEN       0x40 /* ext.signal EVEN/\ODD */
 122#define     TVP3026_XCURCTRL_INDIRECT   0x00
 123#define     TVP3026_XCURCTRL_DIRECT     0x80
 124#define TVP3026_XLATCHCTRL      0x0F
 125#define     TVP3026_XLATCHCTRL_1_1      0x06
 126#define     TVP3026_XLATCHCTRL_2_1      0x07
 127#define     TVP3026_XLATCHCTRL_4_1      0x06
 128#define     TVP3026_XLATCHCTRL_8_1      0x06
 129#define     TVP3026_XLATCHCTRL_16_1     0x06
 130#define     TVP3026A_XLATCHCTRL_4_3     0x06    /* ??? do not understand... but it works... !!! */
 131#define     TVP3026A_XLATCHCTRL_8_3     0x07
 132#define     TVP3026B_XLATCHCTRL_4_3     0x08
 133#define     TVP3026B_XLATCHCTRL_8_3     0x06    /* ??? do not understand... but it works... !!! */
 134#define TVP3026_XTRUECOLORCTRL  0x18
 135#define     TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_ACCEL     0x00
 136#define     TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_TVP       0x20
 137#define     TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR          0x80
 138#define     TVP3026_XTRUECOLORCTRL_TRUECOLOR            0x40 /* paletized */
 139#define     TVP3026_XTRUECOLORCTRL_DIRECTCOLOR          0x00
 140#define     TVP3026_XTRUECOLORCTRL_24_ALTERNATE         0x08 /* 5:4/5:2 instead of 4:3/8:3 */
 141#define     TVP3026_XTRUECOLORCTRL_RGB_888              0x16 /* 4:3/8:3 (or 5:4/5:2) */
 142#define     TVP3026_XTRUECOLORCTRL_BGR_888              0x17
 143#define     TVP3026_XTRUECOLORCTRL_ORGB_8888            0x06
 144#define     TVP3026_XTRUECOLORCTRL_BGRO_8888            0x07
 145#define     TVP3026_XTRUECOLORCTRL_RGB_565              0x05
 146#define     TVP3026_XTRUECOLORCTRL_ORGB_1555            0x04
 147#define     TVP3026_XTRUECOLORCTRL_RGB_664              0x03
 148#define     TVP3026_XTRUECOLORCTRL_RGBO_4444            0x01
 149#define TVP3026_XMUXCTRL        0x19
 150#define     TVP3026_XMUXCTRL_MEMORY_8BIT                        0x01 /* - */
 151#define     TVP3026_XMUXCTRL_MEMORY_16BIT                       0x02 /* - */
 152#define     TVP3026_XMUXCTRL_MEMORY_32BIT                       0x03 /* 2MB RAM, 512K * 4 */
 153#define     TVP3026_XMUXCTRL_MEMORY_64BIT                       0x04 /* >2MB RAM, 512K * 8 & more */
 154#define     TVP3026_XMUXCTRL_PIXEL_4BIT                         0x40 /* L0,H0,L1,H1... */
 155#define     TVP3026_XMUXCTRL_PIXEL_4BIT_SWAPPED                 0x60 /* H0,L0,H1,L1... */
 156#define     TVP3026_XMUXCTRL_PIXEL_8BIT                         0x48
 157#define     TVP3026_XMUXCTRL_PIXEL_16BIT                        0x50
 158#define     TVP3026_XMUXCTRL_PIXEL_32BIT                        0x58
 159#define     TVP3026_XMUXCTRL_VGA                                0x98 /* VGA MEMORY, 8BIT PIXEL */
 160#define TVP3026_XCLKCTRL        0x1A
 161#define     TVP3026_XCLKCTRL_DIV1       0x00
 162#define     TVP3026_XCLKCTRL_DIV2       0x10
 163#define     TVP3026_XCLKCTRL_DIV4       0x20
 164#define     TVP3026_XCLKCTRL_DIV8       0x30
 165#define     TVP3026_XCLKCTRL_DIV16      0x40
 166#define     TVP3026_XCLKCTRL_DIV32      0x50
 167#define     TVP3026_XCLKCTRL_DIV64      0x60
 168#define     TVP3026_XCLKCTRL_CLKSTOPPED 0x70
 169#define     TVP3026_XCLKCTRL_SRC_CLK0   0x00
 170#define     TVP3026_XCLKCTRL_SRC_CLK1   0x01
 171#define     TVP3026_XCLKCTRL_SRC_CLK2   0x02    /* CLK2 is TTL source*/
 172#define     TVP3026_XCLKCTRL_SRC_NCLK2  0x03    /* not CLK2 is TTL source */
 173#define     TVP3026_XCLKCTRL_SRC_ECLK2  0x04    /* CLK2 and not CLK2 is ECL source */
 174#define     TVP3026_XCLKCTRL_SRC_PLL    0x05
 175#define     TVP3026_XCLKCTRL_SRC_DIS    0x06    /* disable & poweroff internal clock */
 176#define     TVP3026_XCLKCTRL_SRC_CLK0VGA 0x07
 177#define TVP3026_XPALETTEPAGE    0x1C
 178#define TVP3026_XGENCTRL        0x1D
 179#define     TVP3026_XGENCTRL_HSYNC_POS  0x00
 180#define     TVP3026_XGENCTRL_HSYNC_NEG  0x01
 181#define     TVP3026_XGENCTRL_VSYNC_POS  0x00
 182#define     TVP3026_XGENCTRL_VSYNC_NEG  0x02
 183#define     TVP3026_XGENCTRL_LITTLE_ENDIAN 0x00
 184#define     TVP3026_XGENCTRL_BIG_ENDIAN    0x08
 185#define     TVP3026_XGENCTRL_BLACK_0IRE         0x00
 186#define     TVP3026_XGENCTRL_BLACK_75IRE        0x10
 187#define     TVP3026_XGENCTRL_NO_SYNC_ON_GREEN   0x00
 188#define     TVP3026_XGENCTRL_SYNC_ON_GREEN      0x20
 189#define     TVP3026_XGENCTRL_OVERSCAN_DIS       0x00
 190#define     TVP3026_XGENCTRL_OVERSCAN_EN        0x40
 191#define TVP3026_XMISCCTRL       0x1E
 192#define     TVP3026_XMISCCTRL_DAC_PUP   0x00
 193#define     TVP3026_XMISCCTRL_DAC_PDOWN 0x01
 194#define     TVP3026_XMISCCTRL_DAC_EXT   0x00 /* or 8, bit 3 is ignored */
 195#define     TVP3026_XMISCCTRL_DAC_6BIT  0x04
 196#define     TVP3026_XMISCCTRL_DAC_8BIT  0x0C
 197#define     TVP3026_XMISCCTRL_PSEL_DIS  0x00
 198#define     TVP3026_XMISCCTRL_PSEL_EN   0x10
 199#define     TVP3026_XMISCCTRL_PSEL_LOW  0x00 /* PSEL high selects directcolor */
 200#define     TVP3026_XMISCCTRL_PSEL_HIGH 0x20 /* PSEL high selects truecolor or pseudocolor */
 201#define TVP3026_XGENIOCTRL      0x2A
 202#define TVP3026_XGENIODATA      0x2B
 203#define TVP3026_XPLLADDR        0x2C
 204#define     TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX))
 205#define     TVP3026_XPLLDATA_N          0x00
 206#define     TVP3026_XPLLDATA_M          0x01
 207#define     TVP3026_XPLLDATA_P          0x02
 208#define     TVP3026_XPLLDATA_STAT       0x03
 209#define TVP3026_XPIXPLLDATA     0x2D
 210#define TVP3026_XMEMPLLDATA     0x2E
 211#define TVP3026_XLOOPPLLDATA    0x2F
 212#define TVP3026_XCOLKEYOVRMIN   0x30
 213#define TVP3026_XCOLKEYOVRMAX   0x31
 214#define TVP3026_XCOLKEYREDMIN   0x32
 215#define TVP3026_XCOLKEYREDMAX   0x33
 216#define TVP3026_XCOLKEYGREENMIN 0x34
 217#define TVP3026_XCOLKEYGREENMAX 0x35
 218#define TVP3026_XCOLKEYBLUEMIN  0x36
 219#define TVP3026_XCOLKEYBLUEMAX  0x37
 220#define TVP3026_XCOLKEYCTRL     0x38
 221#define     TVP3026_XCOLKEYCTRL_OVR_EN  0x01
 222#define     TVP3026_XCOLKEYCTRL_RED_EN  0x02
 223#define     TVP3026_XCOLKEYCTRL_GREEN_EN 0x04
 224#define     TVP3026_XCOLKEYCTRL_BLUE_EN 0x08
 225#define     TVP3026_XCOLKEYCTRL_NEGATE  0x10
 226#define     TVP3026_XCOLKEYCTRL_ZOOM1   0x00
 227#define     TVP3026_XCOLKEYCTRL_ZOOM2   0x20
 228#define     TVP3026_XCOLKEYCTRL_ZOOM4   0x40
 229#define     TVP3026_XCOLKEYCTRL_ZOOM8   0x60
 230#define     TVP3026_XCOLKEYCTRL_ZOOM16  0x80
 231#define     TVP3026_XCOLKEYCTRL_ZOOM32  0xA0
 232#define TVP3026_XMEMPLLCTRL     0x39
 233#define     TVP3026_XMEMPLLCTRL_DIV(X)  (((X)-1)>>1)    /* 2,4,6,8,10,12,14,16, division applied to LOOP PLL after divide by 2^P */
 234#define     TVP3026_XMEMPLLCTRL_STROBEMKC4      0x08
 235#define     TVP3026_XMEMPLLCTRL_MCLK_DOTCLOCK   0x00    /* MKC4 */
 236#define     TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL    0x10    /* MKC4 */
 237#define     TVP3026_XMEMPLLCTRL_RCLK_PIXPLL     0x00
 238#define     TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL    0x20
 239#define     TVP3026_XMEMPLLCTRL_RCLK_DOTDIVN    0x40    /* dot clock divided by loop pclk N prescaler */
 240#define TVP3026_XSENSETEST      0x3A
 241#define TVP3026_XTESTMODEDATA   0x3B
 242#define TVP3026_XCRCREML        0x3C
 243#define TVP3026_XCRCREMH        0x3D
 244#define TVP3026_XCRCBITSEL      0x3E
 245#define TVP3026_XID             0x3F
 246
 247static const unsigned char DACseq[] =
 248{ TVP3026_XLATCHCTRL, TVP3026_XTRUECOLORCTRL,
 249  TVP3026_XMUXCTRL, TVP3026_XCLKCTRL,
 250  TVP3026_XPALETTEPAGE,
 251  TVP3026_XGENCTRL,
 252  TVP3026_XMISCCTRL,
 253  TVP3026_XGENIOCTRL,
 254  TVP3026_XGENIODATA,
 255  TVP3026_XCOLKEYOVRMIN, TVP3026_XCOLKEYOVRMAX, TVP3026_XCOLKEYREDMIN, TVP3026_XCOLKEYREDMAX,
 256  TVP3026_XCOLKEYGREENMIN, TVP3026_XCOLKEYGREENMAX, TVP3026_XCOLKEYBLUEMIN, TVP3026_XCOLKEYBLUEMAX,
 257  TVP3026_XCOLKEYCTRL,
 258  TVP3026_XMEMPLLCTRL, TVP3026_XSENSETEST, TVP3026_XCURCTRL };
 259
 260#define POS3026_XLATCHCTRL      0
 261#define POS3026_XTRUECOLORCTRL  1
 262#define POS3026_XMUXCTRL        2
 263#define POS3026_XCLKCTRL        3
 264#define POS3026_XGENCTRL        5
 265#define POS3026_XMISCCTRL       6
 266#define POS3026_XMEMPLLCTRL     18
 267#define POS3026_XCURCTRL        20
 268
 269static const unsigned char MGADACbpp32[] =
 270{ TVP3026_XLATCHCTRL_2_1, TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_8888,
 271  0x00, TVP3026_XCLKCTRL_DIV1 | TVP3026_XCLKCTRL_SRC_PLL,
 272  0x00,
 273  TVP3026_XGENCTRL_HSYNC_POS | TVP3026_XGENCTRL_VSYNC_POS | TVP3026_XGENCTRL_LITTLE_ENDIAN | TVP3026_XGENCTRL_BLACK_0IRE | TVP3026_XGENCTRL_NO_SYNC_ON_GREEN | TVP3026_XGENCTRL_OVERSCAN_DIS,
 274  TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_HIGH,
 275  0x00,
 276  0x1E,
 277  0xFF, 0xFF, 0xFF, 0xFF,
 278  0xFF, 0xFF, 0xFF, 0xFF,
 279  TVP3026_XCOLKEYCTRL_ZOOM1,
 280  0x00, 0x00, TVP3026_XCURCTRL_DIS };
 281
 282static int Ti3026_calcclock(CPMINFO unsigned int freq, unsigned int fmax, int* in, int* feed, int* post) {
 283        unsigned int fvco;
 284        unsigned int lin, lfeed, lpost;
 285
 286        DBG(__func__)
 287
 288        fvco = PLL_calcclock(PMINFO freq, fmax, &lin, &lfeed, &lpost);
 289        fvco >>= (*post = lpost);
 290        *in = 64 - lin;
 291        *feed = 64 - lfeed;
 292        return fvco;
 293}
 294
 295static int Ti3026_setpclk(WPMINFO int clk) {
 296        unsigned int f_pll;
 297        unsigned int pixfeed, pixin, pixpost;
 298        struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
 299
 300        DBG(__func__)
 301
 302        f_pll = Ti3026_calcclock(PMINFO clk, ACCESS_FBINFO(max_pixel_clock), &pixin, &pixfeed, &pixpost);
 303
 304        hw->DACclk[0] = pixin | 0xC0;
 305        hw->DACclk[1] = pixfeed;
 306        hw->DACclk[2] = pixpost | 0xB0;
 307
 308        {
 309                unsigned int loopfeed, loopin, looppost, loopdiv, z;
 310                unsigned int Bpp;
 311
 312                Bpp = ACCESS_FBINFO(curr.final_bppShift);
 313
 314                if (ACCESS_FBINFO(fbcon).var.bits_per_pixel == 24) {
 315                        loopfeed = 3;           /* set lm to any possible value */
 316                        loopin = 3 * 32 / Bpp;
 317                } else {
 318                        loopfeed = 4;
 319                        loopin = 4 * 32 / Bpp;
 320                }
 321                z = (110000 * loopin) / (f_pll * loopfeed);
 322                loopdiv = 0; /* div 2 */
 323                if (z < 2)
 324                        looppost = 0;
 325                else if (z < 4)
 326                        looppost = 1;
 327                else if (z < 8)
 328                        looppost = 2;
 329                else {
 330                        looppost = 3;
 331                        loopdiv = z/16;
 332                }
 333                if (ACCESS_FBINFO(fbcon).var.bits_per_pixel == 24) {
 334                        hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
 335                        hw->DACclk[4] = (65 - loopfeed) | 0x80;
 336                        if (ACCESS_FBINFO(accel.ramdac_rev) > 0x20) {
 337                                if (isInterleave(MINFO))
 338                                        hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_8_3;
 339                                else {
 340                                        hw->DACclk[4] &= ~0xC0;
 341                                        hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_4_3;
 342                                }
 343                        } else {
 344                                if (isInterleave(MINFO))
 345                                        ;       /* default... */
 346                                else {
 347                                        hw->DACclk[4] ^= 0xC0;  /* change from 0x80 to 0x40 */
 348                                        hw->DACreg[POS3026_XLATCHCTRL] = TVP3026A_XLATCHCTRL_4_3;
 349                                }
 350                        }
 351                        hw->DACclk[5] = looppost | 0xF8;
 352                        if (ACCESS_FBINFO(devflags.mga_24bpp_fix))
 353                                hw->DACclk[5] ^= 0x40;
 354                } else {
 355                        hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
 356                        hw->DACclk[4] = 65 - loopfeed;
 357                        hw->DACclk[5] = looppost | 0xF0;
 358                }
 359                hw->DACreg[POS3026_XMEMPLLCTRL] = loopdiv | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL;
 360        }
 361        return 0;
 362}
 363
 364static int Ti3026_init(WPMINFO struct my_timming* m) {
 365        u_int8_t muxctrl = isInterleave(MINFO) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT;
 366        struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
 367
 368        DBG(__func__)
 369
 370        memcpy(hw->DACreg, MGADACbpp32, sizeof(hw->DACreg));
 371        switch (ACCESS_FBINFO(fbcon).var.bits_per_pixel) {
 372                case 4: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_16_1;       /* or _8_1, they are same */
 373                        hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
 374                        hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_4BIT;
 375                        hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV8;
 376                        hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
 377                        break;
 378                case 8: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_8_1;        /* or _4_1, they are same */
 379                        hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
 380                        hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_8BIT;
 381                        hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
 382                        hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
 383                        break;
 384                case 16:
 385                        /* XLATCHCTRL should be _4_1 / _2_1... Why is not? (_2_1 is used everytime) */
 386                        hw->DACreg[POS3026_XTRUECOLORCTRL] = (ACCESS_FBINFO(fbcon).var.green.length == 5)? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555 ) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565);
 387                        hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_16BIT;
 388                        hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV2;
 389                        break;
 390                case 24:
 391                        /* XLATCHCTRL is: for (A) use _4_3 (?_8_3 is same? TBD), for (B) it is set in setpclk */
 392                        hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_888;
 393                        hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
 394                        hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
 395                        break;
 396                case 32:
 397                        /* XLATCHCTRL should be _2_1 / _1_1... Why is not? (_2_1 is used everytime) */
 398                        hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
 399                        break;
 400                default:
 401                        return 1;       /* TODO: failed */
 402        }
 403        if (matroxfb_vgaHWinit(PMINFO m)) return 1;
 404
 405        /* set SYNC */
 406        hw->MiscOutReg = 0xCB;
 407        if (m->sync & FB_SYNC_HOR_HIGH_ACT)
 408                hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_HSYNC_NEG;
 409        if (m->sync & FB_SYNC_VERT_HIGH_ACT)
 410                hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_VSYNC_NEG;
 411        if (m->sync & FB_SYNC_ON_GREEN)
 412                hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_SYNC_ON_GREEN;
 413
 414        /* set DELAY */
 415        if (ACCESS_FBINFO(video.len) < 0x400000)
 416                hw->CRTCEXT[3] |= 0x08;
 417        else if (ACCESS_FBINFO(video.len) > 0x400000)
 418                hw->CRTCEXT[3] |= 0x10;
 419
 420        /* set HWCURSOR */
 421        if (m->interlaced) {
 422                hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_INTERLACED;
 423        }
 424        if (m->HTotal >= 1536)
 425                hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_BLANK4096;
 426
 427        /* set interleaving */
 428        hw->MXoptionReg &= ~0x00001000;
 429        if (isInterleave(MINFO)) hw->MXoptionReg |= 0x00001000;
 430
 431        /* set DAC */
 432        Ti3026_setpclk(PMINFO m->pixclock);
 433        return 0;
 434}
 435
 436static void ti3026_setMCLK(WPMINFO int fout){
 437        unsigned int f_pll;
 438        unsigned int pclk_m, pclk_n, pclk_p;
 439        unsigned int mclk_m, mclk_n, mclk_p;
 440        unsigned int rfhcnt, mclk_ctl;
 441        int tmout;
 442
 443        DBG(__func__)
 444
 445        f_pll = Ti3026_calcclock(PMINFO fout, ACCESS_FBINFO(max_pixel_clock), &mclk_n, &mclk_m, &mclk_p);
 446
 447        /* save pclk */
 448        outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
 449        pclk_n = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
 450        outTi3026(PMINFO TVP3026_XPLLADDR, 0xFD);
 451        pclk_m = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
 452        outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
 453        pclk_p = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
 454
 455        /* stop pclk */
 456        outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
 457        outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
 458
 459        /* set pclk to new mclk */
 460        outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
 461        outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_n | 0xC0);
 462        outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_m);
 463        outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_p | 0xB0);
 464
 465        /* wait for PLL to lock */
 466        for (tmout = 500000; tmout; tmout--) {
 467                if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
 468                        break;
 469                udelay(10);
 470        };
 471        if (!tmout)
 472                printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n");
 473
 474        /* output pclk on mclk pin */
 475        mclk_ctl = inTi3026(PMINFO TVP3026_XMEMPLLCTRL);
 476        outTi3026(PMINFO TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7);
 477        outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4);
 478
 479        /* stop MCLK */
 480        outTi3026(PMINFO TVP3026_XPLLADDR, 0xFB);
 481        outTi3026(PMINFO TVP3026_XMEMPLLDATA, 0x00);
 482
 483        /* set mclk to new freq */
 484        outTi3026(PMINFO TVP3026_XPLLADDR, 0xF3);
 485        outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_n | 0xC0);
 486        outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_m);
 487        outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_p | 0xB0);
 488
 489        /* wait for PLL to lock */
 490        for (tmout = 500000; tmout; tmout--) {
 491                if (inTi3026(PMINFO TVP3026_XMEMPLLDATA) & 0x40)
 492                        break;
 493                udelay(10);
 494        }
 495        if (!tmout)
 496                printk(KERN_ERR "matroxfb: Memory PLL not locked after 5 secs\n");
 497
 498        f_pll = f_pll * 333 / (10000 << mclk_p);
 499        if (isMilleniumII(MINFO)) {
 500                rfhcnt = (f_pll - 128) / 256;
 501                if (rfhcnt > 15)
 502                        rfhcnt = 15;
 503        } else {
 504                rfhcnt = (f_pll - 64) / 128;
 505                if (rfhcnt > 15)
 506                        rfhcnt = 0;
 507        }
 508        ACCESS_FBINFO(hw).MXoptionReg = (ACCESS_FBINFO(hw).MXoptionReg & ~0x000F0000) | (rfhcnt << 16);
 509        pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg);
 510
 511        /* output MCLK to MCLK pin */
 512        outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
 513        outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl       ) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_STROBEMKC4);
 514
 515        /* stop PCLK */
 516        outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
 517        outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
 518
 519        /* restore pclk */
 520        outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
 521        outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_n);
 522        outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_m);
 523        outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_p);
 524
 525        /* wait for PLL to lock */
 526        for (tmout = 500000; tmout; tmout--) {
 527                if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
 528                        break;
 529                udelay(10);
 530        }
 531        if (!tmout)
 532                printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
 533}
 534
 535static void ti3026_ramdac_init(WPMINFO2) {
 536
 537        DBG(__func__)
 538
 539        ACCESS_FBINFO(features.pll.vco_freq_min) = 110000;
 540        ACCESS_FBINFO(features.pll.ref_freq)     = 114545;
 541        ACCESS_FBINFO(features.pll.feed_div_min) = 2;
 542        ACCESS_FBINFO(features.pll.feed_div_max) = 24;
 543        ACCESS_FBINFO(features.pll.in_div_min)   = 2;
 544        ACCESS_FBINFO(features.pll.in_div_max)   = 63;
 545        ACCESS_FBINFO(features.pll.post_shift_max) = 3;
 546        if (ACCESS_FBINFO(devflags.noinit))
 547                return;
 548        ti3026_setMCLK(PMINFO 60000);
 549}
 550
 551static void Ti3026_restore(WPMINFO2) {
 552        int i;
 553        unsigned char progdac[6];
 554        struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
 555        CRITFLAGS
 556
 557        DBG(__func__)
 558
 559#ifdef DEBUG
 560        dprintk(KERN_INFO "EXTVGA regs: ");
 561        for (i = 0; i < 6; i++)
 562                dprintk("%02X:", hw->CRTCEXT[i]);
 563        dprintk("\n");
 564#endif
 565
 566        CRITBEGIN
 567
 568        pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
 569
 570        CRITEND
 571
 572        matroxfb_vgaHWrestore(PMINFO2);
 573
 574        CRITBEGIN
 575
 576        ACCESS_FBINFO(crtc1.panpos) = -1;
 577        for (i = 0; i < 6; i++)
 578                mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
 579
 580        for (i = 0; i < 21; i++) {
 581                outTi3026(PMINFO DACseq[i], hw->DACreg[i]);
 582        }
 583
 584        outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
 585        progdac[0] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
 586        progdac[3] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
 587        outTi3026(PMINFO TVP3026_XPLLADDR, 0x15);
 588        progdac[1] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
 589        progdac[4] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
 590        outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
 591        progdac[2] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
 592        progdac[5] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
 593
 594        CRITEND
 595        if (memcmp(hw->DACclk, progdac, 6)) {
 596                /* agrhh... setting up PLL is very slow on Millennium... */
 597                /* Mystique PLL is locked in few ms, but Millennium PLL lock takes about 0.15 s... */
 598                /* Maybe even we should call schedule() ? */
 599
 600                CRITBEGIN
 601                outTi3026(PMINFO TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]);
 602                outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
 603                outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0);
 604                outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0);
 605
 606                outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
 607                for (i = 0; i < 3; i++)
 608                        outTi3026(PMINFO TVP3026_XPIXPLLDATA, hw->DACclk[i]);
 609                /* wait for PLL only if PLL clock requested (always for PowerMode, never for VGA) */
 610                if (hw->MiscOutReg & 0x08) {
 611                        int tmout;
 612                        outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
 613                        for (tmout = 500000; tmout; --tmout) {
 614                                if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
 615                                        break;
 616                                udelay(10);
 617                        }
 618
 619                        CRITEND
 620
 621                        if (!tmout)
 622                                printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
 623                        else
 624                                dprintk(KERN_INFO "PixelPLL: %d\n", 500000-tmout);
 625                        CRITBEGIN
 626                }
 627                outTi3026(PMINFO TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]);
 628                outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
 629                for (i = 3; i < 6; i++)
 630                        outTi3026(PMINFO TVP3026_XLOOPPLLDATA, hw->DACclk[i]);
 631                CRITEND
 632                if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) {
 633                        int tmout;
 634
 635                        CRITBEGIN
 636                        outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
 637                        for (tmout = 500000; tmout; --tmout) {
 638                                if (inTi3026(PMINFO TVP3026_XLOOPPLLDATA) & 0x40)
 639                                        break;
 640                                udelay(10);
 641                        }
 642                        CRITEND
 643                        if (!tmout)
 644                                printk(KERN_ERR "matroxfb: Loop PLL not locked after 5 secs\n");
 645                        else
 646                                dprintk(KERN_INFO "LoopPLL: %d\n", 500000-tmout);
 647                }
 648        }
 649
 650#ifdef DEBUG
 651        dprintk(KERN_DEBUG "3026DACregs ");
 652        for (i = 0; i < 21; i++) {
 653                dprintk("R%02X=%02X ", DACseq[i], hw->DACreg[i]);
 654                if ((i & 0x7) == 0x7) dprintk("\n" KERN_DEBUG "continuing... ");
 655        }
 656        dprintk("\n" KERN_DEBUG "DACclk ");
 657        for (i = 0; i < 6; i++)
 658                dprintk("C%02X=%02X ", i, hw->DACclk[i]);
 659        dprintk("\n");
 660#endif
 661}
 662
 663static void Ti3026_reset(WPMINFO2) {
 664
 665        DBG(__func__)
 666
 667        ti3026_ramdac_init(PMINFO2);
 668}
 669
 670static struct matrox_altout ti3026_output = {
 671        .name    = "Primary output",
 672};
 673
 674static int Ti3026_preinit(WPMINFO2) {
 675        static const int vxres_mill2[] = { 512,        640, 768,  800,  832,  960,
 676                                          1024, 1152, 1280,      1600, 1664, 1920,
 677                                          2048, 0};
 678        static const int vxres_mill1[] = {             640, 768,  800,        960,
 679                                          1024, 1152, 1280,      1600,       1920,
 680                                          2048, 0};
 681        struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
 682
 683        DBG(__func__)
 684
 685        ACCESS_FBINFO(millenium) = 1;
 686        ACCESS_FBINFO(milleniumII) = (ACCESS_FBINFO(pcidev)->device != PCI_DEVICE_ID_MATROX_MIL);
 687        ACCESS_FBINFO(capable.cfb4) = 1;
 688        ACCESS_FBINFO(capable.text) = 1; /* isMilleniumII(MINFO); */
 689        ACCESS_FBINFO(capable.vxres) = isMilleniumII(MINFO)?vxres_mill2:vxres_mill1;
 690
 691        ACCESS_FBINFO(outputs[0]).data = MINFO;
 692        ACCESS_FBINFO(outputs[0]).output = &ti3026_output;
 693        ACCESS_FBINFO(outputs[0]).src = ACCESS_FBINFO(outputs[0]).default_src;
 694        ACCESS_FBINFO(outputs[0]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
 695
 696        if (ACCESS_FBINFO(devflags.noinit))
 697                return 0;
 698        /* preserve VGA I/O, BIOS and PPC */
 699        hw->MXoptionReg &= 0xC0000100;
 700        hw->MXoptionReg |= 0x002C0000;
 701        if (ACCESS_FBINFO(devflags.novga))
 702                hw->MXoptionReg &= ~0x00000100;
 703        if (ACCESS_FBINFO(devflags.nobios))
 704                hw->MXoptionReg &= ~0x40000000;
 705        if (ACCESS_FBINFO(devflags.nopciretry))
 706                hw->MXoptionReg |=  0x20000000;
 707        pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
 708
 709        ACCESS_FBINFO(accel.ramdac_rev) = inTi3026(PMINFO TVP3026_XSILICONREV);
 710
 711        outTi3026(PMINFO TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED);
 712        outTi3026(PMINFO TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR);
 713        outTi3026(PMINFO TVP3026_XMUXCTRL, TVP3026_XMUXCTRL_VGA);
 714
 715        outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
 716        outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0x00);
 717        outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
 718
 719        mga_outb(M_MISC_REG, 0x67);
 720
 721        outTi3026(PMINFO TVP3026_XMEMPLLCTRL, TVP3026_XMEMPLLCTRL_STROBEMKC4 | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
 722
 723        mga_outl(M_RESET, 1);
 724        udelay(250);
 725        mga_outl(M_RESET, 0);
 726        udelay(250);
 727        mga_outl(M_MACCESS, 0x00008000);
 728        udelay(10);
 729        return 0;
 730}
 731
 732struct matrox_switch matrox_millennium = {
 733        Ti3026_preinit, Ti3026_reset, Ti3026_init, Ti3026_restore
 734};
 735EXPORT_SYMBOL(matrox_millennium);
 736#endif
 737MODULE_LICENSE("GPL");
 738
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.