linux/drivers/video/aty/aty128fb.c
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   1/* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
   2 *  linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
   3 *
   4 *  Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
   5 *  Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
   6 *
   7 *                Ani Joshi / Jeff Garzik
   8 *                      - Code cleanup
   9 *
  10 *                Michel Danzer <michdaen@iiic.ethz.ch>
  11 *                      - 15/16 bit cleanup
  12 *                      - fix panning
  13 *
  14 *                Benjamin Herrenschmidt
  15 *                      - pmac-specific PM stuff
  16 *                      - various fixes & cleanups
  17 *
  18 *                Andreas Hundt <andi@convergence.de>
  19 *                      - FB_ACTIVATE fixes
  20 *
  21 *                Paul Mackerras <paulus@samba.org>
  22 *                      - Convert to new framebuffer API,
  23 *                        fix colormap setting at 16 bits/pixel (565)
  24 *
  25 *                Paul Mundt 
  26 *                      - PCI hotplug
  27 *
  28 *                Jon Smirl <jonsmirl@yahoo.com>
  29 *                      - PCI ID update
  30 *                      - replace ROM BIOS search
  31 *
  32 *  Based off of Geert's atyfb.c and vfb.c.
  33 *
  34 *  TODO:
  35 *              - monitor sensing (DDC)
  36 *              - virtual display
  37 *              - other platform support (only ppc/x86 supported)
  38 *              - hardware cursor support
  39 *
  40 *    Please cc: your patches to brad@neruo.com.
  41 */
  42
  43/*
  44 * A special note of gratitude to ATI's devrel for providing documentation,
  45 * example code and hardware. Thanks Nitya.     -atong and brad
  46 */
  47
  48
  49#include <linux/module.h>
  50#include <linux/moduleparam.h>
  51#include <linux/kernel.h>
  52#include <linux/errno.h>
  53#include <linux/string.h>
  54#include <linux/mm.h>
  55#include <linux/slab.h>
  56#include <linux/vmalloc.h>
  57#include <linux/delay.h>
  58#include <linux/interrupt.h>
  59#include <linux/uaccess.h>
  60#include <linux/fb.h>
  61#include <linux/init.h>
  62#include <linux/pci.h>
  63#include <linux/ioport.h>
  64#include <linux/console.h>
  65#include <linux/backlight.h>
  66#include <asm/io.h>
  67
  68#ifdef CONFIG_PPC_PMAC
  69#include <asm/machdep.h>
  70#include <asm/pmac_feature.h>
  71#include <asm/prom.h>
  72#include <asm/pci-bridge.h>
  73#include "../macmodes.h"
  74#endif
  75
  76#ifdef CONFIG_PMAC_BACKLIGHT
  77#include <asm/backlight.h>
  78#endif
  79
  80#ifdef CONFIG_BOOTX_TEXT
  81#include <asm/btext.h>
  82#endif /* CONFIG_BOOTX_TEXT */
  83
  84#ifdef CONFIG_MTRR
  85#include <asm/mtrr.h>
  86#endif
  87
  88#include <video/aty128.h>
  89
  90/* Debug flag */
  91#undef DEBUG
  92
  93#ifdef DEBUG
  94#define DBG(fmt, args...)               printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args);
  95#else
  96#define DBG(fmt, args...)
  97#endif
  98
  99#ifndef CONFIG_PPC_PMAC
 100/* default mode */
 101static struct fb_var_screeninfo default_var __devinitdata = {
 102        /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 103        640, 480, 640, 480, 0, 0, 8, 0,
 104        {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 105        0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 106        0, FB_VMODE_NONINTERLACED
 107};
 108
 109#else /* CONFIG_PPC_PMAC */
 110/* default to 1024x768 at 75Hz on PPC - this will work
 111 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
 112static struct fb_var_screeninfo default_var = {
 113        /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
 114        1024, 768, 1024, 768, 0, 0, 8, 0,
 115        {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 116        0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
 117        FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 118        FB_VMODE_NONINTERLACED
 119};
 120#endif /* CONFIG_PPC_PMAC */
 121
 122/* default modedb mode */
 123/* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
 124static struct fb_videomode defaultmode __devinitdata = {
 125        .refresh =      60,
 126        .xres =         640,
 127        .yres =         480,
 128        .pixclock =     39722,
 129        .left_margin =  48,
 130        .right_margin = 16,
 131        .upper_margin = 33,
 132        .lower_margin = 10,
 133        .hsync_len =    96,
 134        .vsync_len =    2,
 135        .sync =         0,
 136        .vmode =        FB_VMODE_NONINTERLACED
 137};
 138
 139/* Chip generations */
 140enum {
 141        rage_128,
 142        rage_128_pci,
 143        rage_128_pro,
 144        rage_128_pro_pci,
 145        rage_M3,
 146        rage_M3_pci,
 147        rage_M4,
 148        rage_128_ultra,
 149};
 150
 151/* Must match above enum */
 152static const char *r128_family[] __devinitdata = {
 153        "AGP",
 154        "PCI",
 155        "PRO AGP",
 156        "PRO PCI",
 157        "M3 AGP",
 158        "M3 PCI",
 159        "M4 AGP",
 160        "Ultra AGP",
 161};
 162
 163/*
 164 * PCI driver prototypes
 165 */
 166static int aty128_probe(struct pci_dev *pdev,
 167                               const struct pci_device_id *ent);
 168static void aty128_remove(struct pci_dev *pdev);
 169static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state);
 170static int aty128_pci_resume(struct pci_dev *pdev);
 171static int aty128_do_resume(struct pci_dev *pdev);
 172
 173/* supported Rage128 chipsets */
 174static struct pci_device_id aty128_pci_tbl[] = {
 175        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
 176          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
 177        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
 178          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
 179        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
 180          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
 181        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
 182          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
 183        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
 184          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 185        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
 186          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 187        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
 188          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 189        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
 190          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
 191        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
 192          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 193        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
 194          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 195        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
 196          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 197        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
 198          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 199        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
 200          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 201        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
 202          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 203        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
 204          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 205        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
 206          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 207        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
 208          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 209        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
 210          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 211        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
 212          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 213        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
 214          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
 215        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
 216          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 217        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
 218          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
 219        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
 220          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 221        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
 222          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 223        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
 224          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 225        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
 226          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 227        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
 228          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 229        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
 230          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 231        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
 232          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
 233        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
 234          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 235        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
 236          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 237        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
 238          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
 239        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
 240          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 241        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
 242          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 243        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
 244          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
 245        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
 246          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 247        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
 248          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 249        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
 250          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 251        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
 252          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 253        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
 254          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 255        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
 256          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 257        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
 258          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 259        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
 260          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 261        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
 262          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 263        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
 264          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 265        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
 266          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 267        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
 268          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 269        { 0, }
 270};
 271
 272MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
 273
 274static struct pci_driver aty128fb_driver = {
 275        .name           = "aty128fb",
 276        .id_table       = aty128_pci_tbl,
 277        .probe          = aty128_probe,
 278        .remove         = __devexit_p(aty128_remove),
 279        .suspend        = aty128_pci_suspend,
 280        .resume         = aty128_pci_resume,
 281};
 282
 283/* packed BIOS settings */
 284#ifndef CONFIG_PPC
 285typedef struct {
 286        u8 clock_chip_type;
 287        u8 struct_size;
 288        u8 accelerator_entry;
 289        u8 VGA_entry;
 290        u16 VGA_table_offset;
 291        u16 POST_table_offset;
 292        u16 XCLK;
 293        u16 MCLK;
 294        u8 num_PLL_blocks;
 295        u8 size_PLL_blocks;
 296        u16 PCLK_ref_freq;
 297        u16 PCLK_ref_divider;
 298        u32 PCLK_min_freq;
 299        u32 PCLK_max_freq;
 300        u16 MCLK_ref_freq;
 301        u16 MCLK_ref_divider;
 302        u32 MCLK_min_freq;
 303        u32 MCLK_max_freq;
 304        u16 XCLK_ref_freq;
 305        u16 XCLK_ref_divider;
 306        u32 XCLK_min_freq;
 307        u32 XCLK_max_freq;
 308} __attribute__ ((packed)) PLL_BLOCK;
 309#endif /* !CONFIG_PPC */
 310
 311/* onboard memory information */
 312struct aty128_meminfo {
 313        u8 ML;
 314        u8 MB;
 315        u8 Trcd;
 316        u8 Trp;
 317        u8 Twr;
 318        u8 CL;
 319        u8 Tr2w;
 320        u8 LoopLatency;
 321        u8 DspOn;
 322        u8 Rloop;
 323        const char *name;
 324};
 325
 326/* various memory configurations */
 327static const struct aty128_meminfo sdr_128   =
 328        { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
 329static const struct aty128_meminfo sdr_64    =
 330        { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
 331static const struct aty128_meminfo sdr_sgram =
 332        { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
 333static const struct aty128_meminfo ddr_sgram =
 334        { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
 335
 336static struct fb_fix_screeninfo aty128fb_fix __devinitdata = {
 337        .id             = "ATY Rage128",
 338        .type           = FB_TYPE_PACKED_PIXELS,
 339        .visual         = FB_VISUAL_PSEUDOCOLOR,
 340        .xpanstep       = 8,
 341        .ypanstep       = 1,
 342        .mmio_len       = 0x2000,
 343        .accel          = FB_ACCEL_ATI_RAGE128,
 344};
 345
 346static char *mode_option __devinitdata = NULL;
 347
 348#ifdef CONFIG_PPC_PMAC
 349static int default_vmode __devinitdata = VMODE_1024_768_60;
 350static int default_cmode __devinitdata = CMODE_8;
 351#endif
 352
 353static int default_crt_on __devinitdata = 0;
 354static int default_lcd_on __devinitdata = 1;
 355
 356#ifdef CONFIG_MTRR
 357static int mtrr = 1;
 358#endif
 359
 360#ifdef CONFIG_PMAC_BACKLIGHT
 361static int backlight __devinitdata = 1;
 362#else
 363static int backlight __devinitdata = 0;
 364#endif
 365
 366/* PLL constants */
 367struct aty128_constants {
 368        u32 ref_clk;
 369        u32 ppll_min;
 370        u32 ppll_max;
 371        u32 ref_divider;
 372        u32 xclk;
 373        u32 fifo_width;
 374        u32 fifo_depth;
 375};
 376
 377struct aty128_crtc {
 378        u32 gen_cntl;
 379        u32 h_total, h_sync_strt_wid;
 380        u32 v_total, v_sync_strt_wid;
 381        u32 pitch;
 382        u32 offset, offset_cntl;
 383        u32 xoffset, yoffset;
 384        u32 vxres, vyres;
 385        u32 depth, bpp;
 386};
 387
 388struct aty128_pll {
 389        u32 post_divider;
 390        u32 feedback_divider;
 391        u32 vclk;
 392};
 393
 394struct aty128_ddafifo {
 395        u32 dda_config;
 396        u32 dda_on_off;
 397};
 398
 399/* register values for a specific mode */
 400struct aty128fb_par {
 401        struct aty128_crtc crtc;
 402        struct aty128_pll pll;
 403        struct aty128_ddafifo fifo_reg;
 404        u32 accel_flags;
 405        struct aty128_constants constants;  /* PLL and others      */
 406        void __iomem *regbase;              /* remapped mmio       */
 407        u32 vram_size;                      /* onboard video ram   */
 408        int chip_gen;
 409        const struct aty128_meminfo *mem;   /* onboard mem info    */
 410#ifdef CONFIG_MTRR
 411        struct { int vram; int vram_valid; } mtrr;
 412#endif
 413        int blitter_may_be_busy;
 414        int fifo_slots;                 /* free slots in FIFO (64 max) */
 415
 416        int     pm_reg;
 417        int crt_on, lcd_on;
 418        struct pci_dev *pdev;
 419        struct fb_info *next;
 420        int     asleep;
 421        int     lock_blank;
 422
 423        u8      red[32];                /* see aty128fb_setcolreg */
 424        u8      green[64];
 425        u8      blue[32];
 426        u32     pseudo_palette[16];     /* used for TRUECOLOR */
 427};
 428
 429
 430#define round_div(n, d) ((n+(d/2))/d)
 431
 432static int aty128fb_check_var(struct fb_var_screeninfo *var,
 433                              struct fb_info *info);
 434static int aty128fb_set_par(struct fb_info *info);
 435static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 436                              u_int transp, struct fb_info *info);
 437static int aty128fb_pan_display(struct fb_var_screeninfo *var,
 438                           struct fb_info *fb);
 439static int aty128fb_blank(int blank, struct fb_info *fb);
 440static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
 441static int aty128fb_sync(struct fb_info *info);
 442
 443    /*
 444     *  Internal routines
 445     */
 446
 447static int aty128_encode_var(struct fb_var_screeninfo *var,
 448                             const struct aty128fb_par *par);
 449static int aty128_decode_var(struct fb_var_screeninfo *var,
 450                             struct aty128fb_par *par);
 451#if 0
 452static void __devinit aty128_get_pllinfo(struct aty128fb_par *par,
 453                                      void __iomem *bios);
 454static void __devinit __iomem *aty128_map_ROM(struct pci_dev *pdev, const struct aty128fb_par *par);
 455#endif
 456static void aty128_timings(struct aty128fb_par *par);
 457static void aty128_init_engine(struct aty128fb_par *par);
 458static void aty128_reset_engine(const struct aty128fb_par *par);
 459static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
 460static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
 461static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
 462static void wait_for_idle(struct aty128fb_par *par);
 463static u32 depth_to_dst(u32 depth);
 464
 465#ifdef CONFIG_FB_ATY128_BACKLIGHT
 466static void aty128_bl_set_power(struct fb_info *info, int power);
 467#endif
 468
 469#define BIOS_IN8(v)     (readb(bios + (v)))
 470#define BIOS_IN16(v)    (readb(bios + (v)) | \
 471                          (readb(bios + (v) + 1) << 8))
 472#define BIOS_IN32(v)    (readb(bios + (v)) | \
 473                          (readb(bios + (v) + 1) << 8) | \
 474                          (readb(bios + (v) + 2) << 16) | \
 475                          (readb(bios + (v) + 3) << 24))
 476
 477
 478static struct fb_ops aty128fb_ops = {
 479        .owner          = THIS_MODULE,
 480        .fb_check_var   = aty128fb_check_var,
 481        .fb_set_par     = aty128fb_set_par,
 482        .fb_setcolreg   = aty128fb_setcolreg,
 483        .fb_pan_display = aty128fb_pan_display,
 484        .fb_blank       = aty128fb_blank,
 485        .fb_ioctl       = aty128fb_ioctl,
 486        .fb_sync        = aty128fb_sync,
 487        .fb_fillrect    = cfb_fillrect,
 488        .fb_copyarea    = cfb_copyarea,
 489        .fb_imageblit   = cfb_imageblit,
 490};
 491
 492    /*
 493     * Functions to read from/write to the mmio registers
 494     *  - endian conversions may possibly be avoided by
 495     *    using the other register aperture. TODO.
 496     */
 497static inline u32 _aty_ld_le32(volatile unsigned int regindex, 
 498                               const struct aty128fb_par *par)
 499{
 500        return readl (par->regbase + regindex);
 501}
 502
 503static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, 
 504                                const struct aty128fb_par *par)
 505{
 506        writel (val, par->regbase + regindex);
 507}
 508
 509static inline u8 _aty_ld_8(unsigned int regindex,
 510                           const struct aty128fb_par *par)
 511{
 512        return readb (par->regbase + regindex);
 513}
 514
 515static inline void _aty_st_8(unsigned int regindex, u8 val,
 516                             const struct aty128fb_par *par)
 517{
 518        writeb (val, par->regbase + regindex);
 519}
 520
 521#define aty_ld_le32(regindex)           _aty_ld_le32(regindex, par)
 522#define aty_st_le32(regindex, val)      _aty_st_le32(regindex, val, par)
 523#define aty_ld_8(regindex)              _aty_ld_8(regindex, par)
 524#define aty_st_8(regindex, val)         _aty_st_8(regindex, val, par)
 525
 526    /*
 527     * Functions to read from/write to the pll registers
 528     */
 529
 530#define aty_ld_pll(pll_index)           _aty_ld_pll(pll_index, par)
 531#define aty_st_pll(pll_index, val)      _aty_st_pll(pll_index, val, par)
 532
 533
 534static u32 _aty_ld_pll(unsigned int pll_index,
 535                       const struct aty128fb_par *par)
 536{       
 537        aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
 538        return aty_ld_le32(CLOCK_CNTL_DATA);
 539}
 540
 541    
 542static void _aty_st_pll(unsigned int pll_index, u32 val,
 543                        const struct aty128fb_par *par)
 544{
 545        aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
 546        aty_st_le32(CLOCK_CNTL_DATA, val);
 547}
 548
 549
 550/* return true when the PLL has completed an atomic update */
 551static int aty_pll_readupdate(const struct aty128fb_par *par)
 552{
 553        return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
 554}
 555
 556
 557static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
 558{
 559        unsigned long timeout = jiffies + HZ/100; // should be more than enough
 560        int reset = 1;
 561
 562        while (time_before(jiffies, timeout))
 563                if (aty_pll_readupdate(par)) {
 564                        reset = 0;
 565                        break;
 566                }
 567
 568        if (reset)      /* reset engine?? */
 569                printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
 570}
 571
 572
 573/* tell PLL to update */
 574static void aty_pll_writeupdate(const struct aty128fb_par *par)
 575{
 576        aty_pll_wait_readupdate(par);
 577
 578        aty_st_pll(PPLL_REF_DIV,
 579                   aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
 580}
 581
 582
 583/* write to the scratch register to test r/w functionality */
 584static int __devinit register_test(const struct aty128fb_par *par)
 585{
 586        u32 val;
 587        int flag = 0;
 588
 589        val = aty_ld_le32(BIOS_0_SCRATCH);
 590
 591        aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
 592        if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
 593                aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
 594
 595                if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
 596                        flag = 1; 
 597        }
 598
 599        aty_st_le32(BIOS_0_SCRATCH, val);       // restore value
 600        return flag;
 601}
 602
 603
 604/*
 605 * Accelerator engine functions
 606 */
 607static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
 608{
 609        int i;
 610
 611        for (;;) {
 612                for (i = 0; i < 2000000; i++) {
 613                        par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
 614                        if (par->fifo_slots >= entries)
 615                                return;
 616                }
 617                aty128_reset_engine(par);
 618        }
 619}
 620
 621
 622static void wait_for_idle(struct aty128fb_par *par)
 623{
 624        int i;
 625
 626        do_wait_for_fifo(64, par);
 627
 628        for (;;) {
 629                for (i = 0; i < 2000000; i++) {
 630                        if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
 631                                aty128_flush_pixel_cache(par);
 632                                par->blitter_may_be_busy = 0;
 633                                return;
 634                        }
 635                }
 636                aty128_reset_engine(par);
 637        }
 638}
 639
 640
 641static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
 642{
 643        if (par->fifo_slots < entries)
 644                do_wait_for_fifo(64, par);
 645        par->fifo_slots -= entries;
 646}
 647
 648
 649static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
 650{
 651        int i;
 652        u32 tmp;
 653
 654        tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
 655        tmp &= ~(0x00ff);
 656        tmp |= 0x00ff;
 657        aty_st_le32(PC_NGUI_CTLSTAT, tmp);
 658
 659        for (i = 0; i < 2000000; i++)
 660                if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
 661                        break;
 662}
 663
 664
 665static void aty128_reset_engine(const struct aty128fb_par *par)
 666{
 667        u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
 668
 669        aty128_flush_pixel_cache(par);
 670
 671        clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
 672        mclk_cntl = aty_ld_pll(MCLK_CNTL);
 673
 674        aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
 675
 676        gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
 677        aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
 678        aty_ld_le32(GEN_RESET_CNTL);
 679        aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
 680        aty_ld_le32(GEN_RESET_CNTL);
 681
 682        aty_st_pll(MCLK_CNTL, mclk_cntl);
 683        aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
 684        aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
 685
 686        /* use old pio mode */
 687        aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
 688
 689        DBG("engine reset");
 690}
 691
 692
 693static void aty128_init_engine(struct aty128fb_par *par)
 694{
 695        u32 pitch_value;
 696
 697        wait_for_idle(par);
 698
 699        /* 3D scaler not spoken here */
 700        wait_for_fifo(1, par);
 701        aty_st_le32(SCALE_3D_CNTL, 0x00000000);
 702
 703        aty128_reset_engine(par);
 704
 705        pitch_value = par->crtc.pitch;
 706        if (par->crtc.bpp == 24) {
 707                pitch_value = pitch_value * 3;
 708        }
 709
 710        wait_for_fifo(4, par);
 711        /* setup engine offset registers */
 712        aty_st_le32(DEFAULT_OFFSET, 0x00000000);
 713
 714        /* setup engine pitch registers */
 715        aty_st_le32(DEFAULT_PITCH, pitch_value);
 716
 717        /* set the default scissor register to max dimensions */
 718        aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
 719
 720        /* set the drawing controls registers */
 721        aty_st_le32(DP_GUI_MASTER_CNTL,
 722                    GMC_SRC_PITCH_OFFSET_DEFAULT                |
 723                    GMC_DST_PITCH_OFFSET_DEFAULT                |
 724                    GMC_SRC_CLIP_DEFAULT                        |
 725                    GMC_DST_CLIP_DEFAULT                        |
 726                    GMC_BRUSH_SOLIDCOLOR                        |
 727                    (depth_to_dst(par->crtc.depth) << 8)        |
 728                    GMC_SRC_DSTCOLOR                    |
 729                    GMC_BYTE_ORDER_MSB_TO_LSB           |
 730                    GMC_DP_CONVERSION_TEMP_6500         |
 731                    ROP3_PATCOPY                                |
 732                    GMC_DP_SRC_RECT                             |
 733                    GMC_3D_FCN_EN_CLR                   |
 734                    GMC_DST_CLR_CMP_FCN_CLEAR           |
 735                    GMC_AUX_CLIP_CLEAR                  |
 736                    GMC_WRITE_MASK_SET);
 737
 738        wait_for_fifo(8, par);
 739        /* clear the line drawing registers */
 740        aty_st_le32(DST_BRES_ERR, 0);
 741        aty_st_le32(DST_BRES_INC, 0);
 742        aty_st_le32(DST_BRES_DEC, 0);
 743
 744        /* set brush color registers */
 745        aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
 746        aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
 747
 748        /* set source color registers */
 749        aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF);   /* white */
 750        aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000);   /* black */
 751
 752        /* default write mask */
 753        aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
 754
 755        /* Wait for all the writes to be completed before returning */
 756        wait_for_idle(par);
 757}
 758
 759
 760/* convert depth values to their register representation */
 761static u32 depth_to_dst(u32 depth)
 762{
 763        if (depth <= 8)
 764                return DST_8BPP;
 765        else if (depth <= 15)
 766                return DST_15BPP;
 767        else if (depth == 16)
 768                return DST_16BPP;
 769        else if (depth <= 24)
 770                return DST_24BPP;
 771        else if (depth <= 32)
 772                return DST_32BPP;
 773
 774        return -EINVAL;
 775}
 776
 777/*
 778 * PLL informations retreival
 779 */
 780
 781
 782#ifndef __sparc__
 783static void __iomem * __devinit aty128_map_ROM(const struct aty128fb_par *par, struct pci_dev *dev)
 784{
 785        u16 dptr;
 786        u8 rom_type;
 787        void __iomem *bios;
 788        size_t rom_size;
 789
 790        /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
 791        unsigned int temp;
 792        temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
 793        temp &= 0x00ffffffu;
 794        temp |= 0x04 << 24;
 795        aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
 796        temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
 797
 798        bios = pci_map_rom(dev, &rom_size);
 799
 800        if (!bios) {
 801                printk(KERN_ERR "aty128fb: ROM failed to map\n");
 802                return NULL;
 803        }
 804
 805        /* Very simple test to make sure it appeared */
 806        if (BIOS_IN16(0) != 0xaa55) {
 807                printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
 808                        " be 0xaa55\n", BIOS_IN16(0));
 809                goto failed;
 810        }
 811
 812        /* Look for the PCI data to check the ROM type */
 813        dptr = BIOS_IN16(0x18);
 814
 815        /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
 816         * for now, until I've verified this works everywhere. The goal here is more
 817         * to phase out Open Firmware images.
 818         *
 819         * Currently, we only look at the first PCI data, we could iteratre and deal with
 820         * them all, and we should use fb_bios_start relative to start of image and not
 821         * relative start of ROM, but so far, I never found a dual-image ATI card
 822         *
 823         * typedef struct {
 824         *      u32     signature;      + 0x00
 825         *      u16     vendor;         + 0x04
 826         *      u16     device;         + 0x06
 827         *      u16     reserved_1;     + 0x08
 828         *      u16     dlen;           + 0x0a
 829         *      u8      drevision;      + 0x0c
 830         *      u8      class_hi;       + 0x0d
 831         *      u16     class_lo;       + 0x0e
 832         *      u16     ilen;           + 0x10
 833         *      u16     irevision;      + 0x12
 834         *      u8      type;           + 0x14
 835         *      u8      indicator;      + 0x15
 836         *      u16     reserved_2;     + 0x16
 837         * } pci_data_t;
 838         */
 839        if (BIOS_IN32(dptr) !=  (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
 840                printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
 841                       BIOS_IN32(dptr));
 842                goto anyway;
 843        }
 844        rom_type = BIOS_IN8(dptr + 0x14);
 845        switch(rom_type) {
 846        case 0:
 847                printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
 848                break;
 849        case 1:
 850                printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
 851                goto failed;
 852        case 2:
 853                printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
 854                goto failed;
 855        default:
 856                printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", rom_type);
 857                goto failed;
 858        }
 859 anyway:
 860        return bios;
 861
 862 failed:
 863        pci_unmap_rom(dev, bios);
 864        return NULL;
 865}
 866
 867static void __devinit aty128_get_pllinfo(struct aty128fb_par *par, unsigned char __iomem *bios)
 868{
 869        unsigned int bios_hdr;
 870        unsigned int bios_pll;
 871
 872        bios_hdr = BIOS_IN16(0x48);
 873        bios_pll = BIOS_IN16(bios_hdr + 0x30);
 874        
 875        par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
 876        par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
 877        par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
 878        par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
 879        par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
 880
 881        DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
 882                        par->constants.ppll_max, par->constants.ppll_min,
 883                        par->constants.xclk, par->constants.ref_divider,
 884                        par->constants.ref_clk);
 885
 886}           
 887
 888#ifdef CONFIG_X86
 889static void __iomem *  __devinit aty128_find_mem_vbios(struct aty128fb_par *par)
 890{
 891        /* I simplified this code as we used to miss the signatures in
 892         * a lot of case. It's now closer to XFree, we just don't check
 893         * for signatures at all... Something better will have to be done
 894         * if we end up having conflicts
 895         */
 896        u32  segstart;
 897        unsigned char __iomem *rom_base = NULL;
 898                                                
 899        for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
 900                rom_base = ioremap(segstart, 0x10000);
 901                if (rom_base == NULL)
 902                        return NULL;
 903                if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
 904                        break;
 905                iounmap(rom_base);
 906                rom_base = NULL;
 907        }
 908        return rom_base;
 909}
 910#endif
 911#endif /* ndef(__sparc__) */
 912
 913/* fill in known card constants if pll_block is not available */
 914static void __devinit aty128_timings(struct aty128fb_par *par)
 915{
 916#ifdef CONFIG_PPC_OF
 917        /* instead of a table lookup, assume OF has properly
 918         * setup the PLL registers and use their values
 919         * to set the XCLK values and reference divider values */
 920
 921        u32 x_mpll_ref_fb_div;
 922        u32 xclk_cntl;
 923        u32 Nx, M;
 924        unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
 925#endif
 926
 927        if (!par->constants.ref_clk)
 928                par->constants.ref_clk = 2950;
 929
 930#ifdef CONFIG_PPC_OF
 931        x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
 932        xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
 933        Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
 934        M  = x_mpll_ref_fb_div & 0x0000ff;
 935
 936        par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
 937                                        (M * PostDivSet[xclk_cntl]));
 938
 939        par->constants.ref_divider =
 940                aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
 941#endif
 942
 943        if (!par->constants.ref_divider) {
 944                par->constants.ref_divider = 0x3b;
 945
 946                aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
 947                aty_pll_writeupdate(par);
 948        }
 949        aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
 950        aty_pll_writeupdate(par);
 951
 952        /* from documentation */
 953        if (!par->constants.ppll_min)
 954                par->constants.ppll_min = 12500;
 955        if (!par->constants.ppll_max)
 956                par->constants.ppll_max = 25000;    /* 23000 on some cards? */
 957        if (!par->constants.xclk)
 958                par->constants.xclk = 0x1d4d;        /* same as mclk */
 959
 960        par->constants.fifo_width = 128;
 961        par->constants.fifo_depth = 32;
 962
 963        switch (aty_ld_le32(MEM_CNTL) & 0x3) {
 964        case 0:
 965                par->mem = &sdr_128;
 966                break;
 967        case 1:
 968                par->mem = &sdr_sgram;
 969                break;
 970        case 2:
 971                par->mem = &ddr_sgram;
 972                break;
 973        default:
 974                par->mem = &sdr_sgram;
 975        }
 976}
 977
 978
 979
 980/*
 981 * CRTC programming
 982 */
 983
 984/* Program the CRTC registers */
 985static void aty128_set_crtc(const struct aty128_crtc *crtc,
 986                            const struct aty128fb_par *par)
 987{
 988        aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
 989        aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
 990        aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
 991        aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
 992        aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
 993        aty_st_le32(CRTC_PITCH, crtc->pitch);
 994        aty_st_le32(CRTC_OFFSET, crtc->offset);
 995        aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
 996        /* Disable ATOMIC updating.  Is this the right place? */
 997        aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
 998}
 999
1000
1001static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1002                              struct aty128_crtc *crtc,
1003                              const struct aty128fb_par *par)
1004{
1005        u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1006        u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1007        u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1008        u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1009        u32 depth, bytpp;
1010        u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1011
1012        /* input */
1013        xres = var->xres;
1014        yres = var->yres;
1015        vxres   = var->xres_virtual;
1016        vyres   = var->yres_virtual;
1017        xoffset = var->xoffset;
1018        yoffset = var->yoffset;
1019        bpp   = var->bits_per_pixel;
1020        left  = var->left_margin;
1021        right = var->right_margin;
1022        upper = var->upper_margin;
1023        lower = var->lower_margin;
1024        hslen = var->hsync_len;
1025        vslen = var->vsync_len;
1026        sync  = var->sync;
1027        vmode = var->vmode;
1028
1029        if (bpp != 16)
1030                depth = bpp;
1031        else
1032                depth = (var->green.length == 6) ? 16 : 15;
1033
1034        /* check for mode eligibility
1035         * accept only non interlaced modes */
1036        if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1037                return -EINVAL;
1038
1039        /* convert (and round up) and validate */
1040        xres = (xres + 7) & ~7;
1041        xoffset = (xoffset + 7) & ~7;
1042
1043        if (vxres < xres + xoffset)
1044                vxres = xres + xoffset;
1045
1046        if (vyres < yres + yoffset)
1047                vyres = yres + yoffset;
1048
1049        /* convert depth into ATI register depth */
1050        dst = depth_to_dst(depth);
1051
1052        if (dst == -EINVAL) {
1053                printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1054                return -EINVAL;
1055        }
1056
1057        /* convert register depth to bytes per pixel */
1058        bytpp = mode_bytpp[dst];
1059
1060        /* make sure there is enough video ram for the mode */
1061        if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1062                printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1063                return -EINVAL;
1064        }
1065
1066        h_disp = (xres >> 3) - 1;
1067        h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1068
1069        v_disp = yres - 1;
1070        v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1071
1072        /* check to make sure h_total and v_total are in range */
1073        if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1074                printk(KERN_ERR "aty128fb: invalid width ranges\n");
1075                return -EINVAL;
1076        }
1077
1078        h_sync_wid = (hslen + 7) >> 3;
1079        if (h_sync_wid == 0)
1080                h_sync_wid = 1;
1081        else if (h_sync_wid > 0x3f)        /* 0x3f = max hwidth */
1082                h_sync_wid = 0x3f;
1083
1084        h_sync_strt = (h_disp << 3) + right;
1085
1086        v_sync_wid = vslen;
1087        if (v_sync_wid == 0)
1088                v_sync_wid = 1;
1089        else if (v_sync_wid > 0x1f)        /* 0x1f = max vwidth */
1090                v_sync_wid = 0x1f;
1091    
1092        v_sync_strt = v_disp + lower;
1093
1094        h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1095        v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1096    
1097        c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1098
1099        crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1100
1101        crtc->h_total = h_total | (h_disp << 16);
1102        crtc->v_total = v_total | (v_disp << 16);
1103
1104        crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1105                (h_sync_pol << 23);
1106        crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1107                (v_sync_pol << 23);
1108
1109        crtc->pitch = vxres >> 3;
1110
1111        crtc->offset = 0;
1112
1113        if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1114                crtc->offset_cntl = 0x00010000;
1115        else
1116                crtc->offset_cntl = 0;
1117
1118        crtc->vxres = vxres;
1119        crtc->vyres = vyres;
1120        crtc->xoffset = xoffset;
1121        crtc->yoffset = yoffset;
1122        crtc->depth = depth;
1123        crtc->bpp = bpp;
1124
1125        return 0;
1126}
1127
1128
1129static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1130{
1131
1132        /* fill in pixel info */
1133        var->red.msb_right = 0;
1134        var->green.msb_right = 0;
1135        var->blue.offset = 0;
1136        var->blue.msb_right = 0;
1137        var->transp.offset = 0;
1138        var->transp.length = 0;
1139        var->transp.msb_right = 0;
1140        switch (pix_width) {
1141        case CRTC_PIX_WIDTH_8BPP:
1142                var->bits_per_pixel = 8;
1143                var->red.offset = 0;
1144                var->red.length = 8;
1145                var->green.offset = 0;
1146                var->green.length = 8;
1147                var->blue.length = 8;
1148                break;
1149        case CRTC_PIX_WIDTH_15BPP:
1150                var->bits_per_pixel = 16;
1151                var->red.offset = 10;
1152                var->red.length = 5;
1153                var->green.offset = 5;
1154                var->green.length = 5;
1155                var->blue.length = 5;
1156                break;
1157        case CRTC_PIX_WIDTH_16BPP:
1158                var->bits_per_pixel = 16;
1159                var->red.offset = 11;
1160                var->red.length = 5;
1161                var->green.offset = 5;
1162                var->green.length = 6;
1163                var->blue.length = 5;
1164                break;
1165        case CRTC_PIX_WIDTH_24BPP:
1166                var->bits_per_pixel = 24;
1167                var->red.offset = 16;
1168                var->red.length = 8;
1169                var->green.offset = 8;
1170                var->green.length = 8;
1171                var->blue.length = 8;
1172                break;
1173        case CRTC_PIX_WIDTH_32BPP:
1174                var->bits_per_pixel = 32;
1175                var->red.offset = 16;
1176                var->red.length = 8;
1177                var->green.offset = 8;
1178                var->green.length = 8;
1179                var->blue.length = 8;
1180                var->transp.offset = 24;
1181                var->transp.length = 8;
1182                break;
1183        default:
1184                printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1185                return -EINVAL;
1186        }
1187
1188        return 0;
1189}
1190
1191
1192static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1193                              struct fb_var_screeninfo *var)
1194{
1195        u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1196        u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1197        u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1198        u32 pix_width;
1199
1200        /* fun with masking */
1201        h_total     = crtc->h_total & 0x1ff;
1202        h_disp      = (crtc->h_total >> 16) & 0xff;
1203        h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1204        h_sync_dly  = crtc->h_sync_strt_wid & 0x7;
1205        h_sync_wid  = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1206        h_sync_pol  = (crtc->h_sync_strt_wid >> 23) & 0x1;
1207        v_total     = crtc->v_total & 0x7ff;
1208        v_disp      = (crtc->v_total >> 16) & 0x7ff;
1209        v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1210        v_sync_wid  = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1211        v_sync_pol  = (crtc->v_sync_strt_wid >> 23) & 0x1;
1212        c_sync      = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1213        pix_width   = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1214
1215        /* do conversions */
1216        xres  = (h_disp + 1) << 3;
1217        yres  = v_disp + 1;
1218        left  = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1219        right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1220        hslen = h_sync_wid << 3;
1221        upper = v_total - v_sync_strt - v_sync_wid;
1222        lower = v_sync_strt - v_disp;
1223        vslen = v_sync_wid;
1224        sync  = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1225                (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1226                (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1227
1228        aty128_pix_width_to_var(pix_width, var);
1229
1230        var->xres = xres;
1231        var->yres = yres;
1232        var->xres_virtual = crtc->vxres;
1233        var->yres_virtual = crtc->vyres;
1234        var->xoffset = crtc->xoffset;
1235        var->yoffset = crtc->yoffset;
1236        var->left_margin  = left;
1237        var->right_margin = right;
1238        var->upper_margin = upper;
1239        var->lower_margin = lower;
1240        var->hsync_len = hslen;
1241        var->vsync_len = vslen;
1242        var->sync  = sync;
1243        var->vmode = FB_VMODE_NONINTERLACED;
1244
1245        return 0;
1246}
1247
1248static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1249{
1250        if (on) {
1251                aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON);
1252                aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN));
1253        } else
1254                aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON);
1255}
1256
1257static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1258{
1259        u32 reg;
1260#ifdef CONFIG_FB_ATY128_BACKLIGHT
1261        struct fb_info *info = pci_get_drvdata(par->pdev);
1262#endif
1263
1264        if (on) {
1265                reg = aty_ld_le32(LVDS_GEN_CNTL);
1266                reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1267                reg &= ~LVDS_DISPLAY_DIS;
1268                aty_st_le32(LVDS_GEN_CNTL, reg);
1269#ifdef CONFIG_FB_ATY128_BACKLIGHT
1270                aty128_bl_set_power(info, FB_BLANK_UNBLANK);
1271#endif  
1272        } else {
1273#ifdef CONFIG_FB_ATY128_BACKLIGHT
1274                aty128_bl_set_power(info, FB_BLANK_POWERDOWN);
1275#endif  
1276                reg = aty_ld_le32(LVDS_GEN_CNTL);
1277                reg |= LVDS_DISPLAY_DIS;
1278                aty_st_le32(LVDS_GEN_CNTL, reg);
1279                mdelay(100);
1280                reg &= ~(LVDS_ON /*| LVDS_EN*/);
1281                aty_st_le32(LVDS_GEN_CNTL, reg);
1282        }
1283}
1284
1285static void aty128_set_pll(struct aty128_pll *pll, const struct aty128fb_par *par)
1286{
1287        u32 div3;
1288
1289        unsigned char post_conv[] =     /* register values for post dividers */
1290        { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1291
1292        /* select PPLL_DIV_3 */
1293        aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1294
1295        /* reset PLL */
1296        aty_st_pll(PPLL_CNTL,
1297                   aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1298
1299        /* write the reference divider */
1300        aty_pll_wait_readupdate(par);
1301        aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1302        aty_pll_writeupdate(par);
1303
1304        div3 = aty_ld_pll(PPLL_DIV_3);
1305        div3 &= ~PPLL_FB3_DIV_MASK;
1306        div3 |= pll->feedback_divider;
1307        div3 &= ~PPLL_POST3_DIV_MASK;
1308        div3 |= post_conv[pll->post_divider] << 16;
1309
1310        /* write feedback and post dividers */
1311        aty_pll_wait_readupdate(par);
1312        aty_st_pll(PPLL_DIV_3, div3);
1313        aty_pll_writeupdate(par);
1314
1315        aty_pll_wait_readupdate(par);
1316        aty_st_pll(HTOTAL_CNTL, 0);     /* no horiz crtc adjustment */
1317        aty_pll_writeupdate(par);
1318
1319        /* clear the reset, just in case */
1320        aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1321}
1322
1323
1324static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1325                             const struct aty128fb_par *par)
1326{
1327        const struct aty128_constants c = par->constants;
1328        unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1329        u32 output_freq;
1330        u32 vclk;        /* in .01 MHz */
1331        int i = 0;
1332        u32 n, d;
1333
1334        vclk = 100000000 / period_in_ps;        /* convert units to 10 kHz */
1335
1336        /* adjust pixel clock if necessary */
1337        if (vclk > c.ppll_max)
1338                vclk = c.ppll_max;
1339        if (vclk * 12 < c.ppll_min)
1340                vclk = c.ppll_min/12;
1341
1342        /* now, find an acceptable divider */
1343        for (i = 0; i < ARRAY_SIZE(post_dividers); i++) {
1344                output_freq = post_dividers[i] * vclk;
1345                if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
1346                        pll->post_divider = post_dividers[i];
1347                        break;
1348                }
1349        }
1350
1351        if (i == ARRAY_SIZE(post_dividers))
1352                return -EINVAL;
1353
1354        /* calculate feedback divider */
1355        n = c.ref_divider * output_freq;
1356        d = c.ref_clk;
1357
1358        pll->feedback_divider = round_div(n, d);
1359        pll->vclk = vclk;
1360
1361        DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1362            "vclk_per: %d\n", pll->post_divider,
1363            pll->feedback_divider, vclk, output_freq,
1364            c.ref_divider, period_in_ps);
1365
1366        return 0;
1367}
1368
1369
1370static int aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var)
1371{
1372        var->pixclock = 100000000 / pll->vclk;
1373
1374        return 0;
1375}
1376
1377
1378static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1379                            const struct aty128fb_par *par)
1380{
1381        aty_st_le32(DDA_CONFIG, dsp->dda_config);
1382        aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1383}
1384
1385
1386static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1387                          const struct aty128_pll *pll,
1388                          u32 depth,
1389                          const struct aty128fb_par *par)
1390{
1391        const struct aty128_meminfo *m = par->mem;
1392        u32 xclk = par->constants.xclk;
1393        u32 fifo_width = par->constants.fifo_width;
1394        u32 fifo_depth = par->constants.fifo_depth;
1395        s32 x, b, p, ron, roff;
1396        u32 n, d, bpp;
1397
1398        /* round up to multiple of 8 */
1399        bpp = (depth+7) & ~7;
1400
1401        n = xclk * fifo_width;
1402        d = pll->vclk * bpp;
1403        x = round_div(n, d);
1404
1405        ron = 4 * m->MB +
1406                3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1407                2 * m->Trp +
1408                m->Twr +
1409                m->CL +
1410                m->Tr2w +
1411                x;
1412
1413        DBG("x %x\n", x);
1414
1415        b = 0;
1416        while (x) {
1417                x >>= 1;
1418                b++;
1419        }
1420        p = b + 1;
1421
1422        ron <<= (11 - p);
1423
1424        n <<= (11 - p);
1425        x = round_div(n, d);
1426        roff = x * (fifo_depth - 4);
1427
1428        if ((ron + m->Rloop) >= roff) {
1429                printk(KERN_ERR "aty128fb: Mode out of range!\n");
1430                return -EINVAL;
1431        }
1432
1433        DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1434            p, m->Rloop, x, ron, roff);
1435
1436        dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1437        dsp->dda_on_off = ron << 16 | roff;
1438
1439        return 0;
1440}
1441
1442
1443/*
1444 * This actually sets the video mode.
1445 */
1446static int aty128fb_set_par(struct fb_info *info)
1447{ 
1448        struct aty128fb_par *par = info->par;
1449        u32 config;
1450        int err;
1451
1452        if ((err = aty128_decode_var(&info->var, par)) != 0)
1453                return err;
1454
1455        if (par->blitter_may_be_busy)
1456                wait_for_idle(par);
1457
1458        /* clear all registers that may interfere with mode setting */
1459        aty_st_le32(OVR_CLR, 0);
1460        aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1461        aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1462        aty_st_le32(OV0_SCALE_CNTL, 0);
1463        aty_st_le32(MPP_TB_CONFIG, 0);
1464        aty_st_le32(MPP_GP_CONFIG, 0);
1465        aty_st_le32(SUBPIC_CNTL, 0);
1466        aty_st_le32(VIPH_CONTROL, 0);
1467        aty_st_le32(I2C_CNTL_1, 0);         /* turn off i2c */
1468        aty_st_le32(GEN_INT_CNTL, 0);   /* turn off interrupts */
1469        aty_st_le32(CAP0_TRIG_CNTL, 0);
1470        aty_st_le32(CAP1_TRIG_CNTL, 0);
1471
1472        aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1473
1474        aty128_set_crtc(&par->crtc, par);
1475        aty128_set_pll(&par->pll, par);
1476        aty128_set_fifo(&par->fifo_reg, par);
1477
1478        config = aty_ld_le32(CONFIG_CNTL) & ~3;
1479
1480#if defined(__BIG_ENDIAN)
1481        if (par->crtc.bpp == 32)
1482                config |= 2;    /* make aperture do 32 bit swapping */
1483        else if (par->crtc.bpp == 16)
1484                config |= 1;    /* make aperture do 16 bit swapping */
1485#endif
1486
1487        aty_st_le32(CONFIG_CNTL, config);
1488        aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1489
1490        info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1491        info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1492                : FB_VISUAL_DIRECTCOLOR;
1493
1494        if (par->chip_gen == rage_M3) {
1495                aty128_set_crt_enable(par, par->crt_on);
1496                aty128_set_lcd_enable(par, par->lcd_on);
1497        }
1498        if (par->accel_flags & FB_ACCELF_TEXT)
1499                aty128_init_engine(par);
1500
1501#ifdef CONFIG_BOOTX_TEXT
1502        btext_update_display(info->fix.smem_start,
1503                             (((par->crtc.h_total>>16) & 0xff)+1)*8,
1504                             ((par->crtc.v_total>>16) & 0x7ff)+1,
1505                             par->crtc.bpp,
1506                             par->crtc.vxres*par->crtc.bpp/8);
1507#endif /* CONFIG_BOOTX_TEXT */
1508
1509        return 0;
1510}
1511
1512/*
1513 *  encode/decode the User Defined Part of the Display
1514 */
1515
1516static int aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par)
1517{
1518        int err;
1519        struct aty128_crtc crtc;
1520        struct aty128_pll pll;
1521        struct aty128_ddafifo fifo_reg;
1522
1523        if ((err = aty128_var_to_crtc(var, &crtc, par)))
1524                return err;
1525
1526        if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1527                return err;
1528
1529        if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1530                return err;
1531
1532        par->crtc = crtc;
1533        par->pll = pll;
1534        par->fifo_reg = fifo_reg;
1535        par->accel_flags = var->accel_flags;
1536
1537        return 0;
1538}
1539
1540
1541static int aty128_encode_var(struct fb_var_screeninfo *var,
1542                             const struct aty128fb_par *par)
1543{
1544        int err;
1545
1546        if ((err = aty128_crtc_to_var(&par->crtc, var)))
1547                return err;
1548
1549        if ((err = aty128_pll_to_var(&par->pll, var)))
1550                return err;
1551
1552        var->nonstd = 0;
1553        var->activate = 0;
1554
1555        var->height = -1;
1556        var->width = -1;
1557        var->accel_flags = par->accel_flags;
1558
1559        return 0;
1560}           
1561
1562
1563static int aty128fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1564{
1565        struct aty128fb_par par;
1566        int err;
1567
1568        par = *(struct aty128fb_par *)info->par;
1569        if ((err = aty128_decode_var(var, &par)) != 0)
1570                return err;
1571        aty128_encode_var(var, &par);
1572        return 0;
1573}
1574
1575
1576/*
1577 *  Pan or Wrap the Display
1578 */
1579static int aty128fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fb) 
1580{
1581        struct aty128fb_par *par = fb->par;
1582        u32 xoffset, yoffset;
1583        u32 offset;
1584        u32 xres, yres;
1585
1586        xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1587        yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1588
1589        xoffset = (var->xoffset +7) & ~7;
1590        yoffset = var->yoffset;
1591
1592        if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1593                return -EINVAL;
1594
1595        par->crtc.xoffset = xoffset;
1596        par->crtc.yoffset = yoffset;
1597
1598        offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7;
1599
1600        if (par->crtc.bpp == 24)
1601                offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1602
1603        aty_st_le32(CRTC_OFFSET, offset);
1604
1605        return 0;
1606}
1607
1608
1609/*
1610 *  Helper function to store a single palette register
1611 */
1612static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1613                          struct aty128fb_par *par)
1614{
1615        if (par->chip_gen == rage_M3) {
1616#if 0
1617                /* Note: For now, on M3, we set palette on both heads, which may
1618                 * be useless. Can someone with a M3 check this ?
1619                 * 
1620                 * This code would still be useful if using the second CRTC to 
1621                 * do mirroring
1622                 */
1623
1624                aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL);
1625                aty_st_8(PALETTE_INDEX, regno);
1626                aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1627#endif
1628                aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
1629        }
1630
1631        aty_st_8(PALETTE_INDEX, regno);
1632        aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1633}
1634
1635static int aty128fb_sync(struct fb_info *info)
1636{
1637        struct aty128fb_par *par = info->par;
1638
1639        if (par->blitter_may_be_busy)
1640                wait_for_idle(par);
1641        return 0;
1642}
1643
1644#ifndef MODULE
1645static int __devinit aty128fb_setup(char *options)
1646{
1647        char *this_opt;
1648
1649        if (!options || !*options)
1650                return 0;
1651
1652        while ((this_opt = strsep(&options, ",")) != NULL) {
1653                if (!strncmp(this_opt, "lcd:", 4)) {
1654                        default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1655                        continue;
1656                } else if (!strncmp(this_opt, "crt:", 4)) {
1657                        default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1658                        continue;
1659                } else if (!strncmp(this_opt, "backlight:", 10)) {
1660                        backlight = simple_strtoul(this_opt+10, NULL, 0);
1661                        continue;
1662                }
1663#ifdef CONFIG_MTRR
1664                if(!strncmp(this_opt, "nomtrr", 6)) {
1665                        mtrr = 0;
1666                        continue;
1667                }
1668#endif
1669#ifdef CONFIG_PPC_PMAC
1670                /* vmode and cmode deprecated */
1671                if (!strncmp(this_opt, "vmode:", 6)) {
1672                        unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1673                        if (vmode > 0 && vmode <= VMODE_MAX)
1674                                default_vmode = vmode;
1675                        continue;
1676                } else if (!strncmp(this_opt, "cmode:", 6)) {
1677                        unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1678                        switch (cmode) {
1679                        case 0:
1680                        case 8:
1681                                default_cmode = CMODE_8;
1682                                break;
1683                        case 15:
1684                        case 16:
1685                                default_cmode = CMODE_16;
1686                                break;
1687                        case 24:
1688                        case 32:
1689                                default_cmode = CMODE_32;
1690                                break;
1691                        }
1692                        continue;
1693                }
1694#endif /* CONFIG_PPC_PMAC */
1695                mode_option = this_opt;
1696        }
1697        return 0;
1698}
1699#endif  /*  MODULE  */
1700
1701/* Backlight */
1702#ifdef CONFIG_FB_ATY128_BACKLIGHT
1703#define MAX_LEVEL 0xFF
1704
1705static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
1706                int level)
1707{
1708        struct fb_info *info = pci_get_drvdata(par->pdev);
1709        int atylevel;
1710
1711        /* Get and convert the value */
1712        /* No locking of bl_curve since we read a single value */
1713        atylevel = MAX_LEVEL -
1714                (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL);
1715
1716        if (atylevel < 0)
1717                atylevel = 0;
1718        else if (atylevel > MAX_LEVEL)
1719                atylevel = MAX_LEVEL;
1720
1721        return atylevel;
1722}
1723
1724/* We turn off the LCD completely instead of just dimming the backlight.
1725 * This provides greater power saving and the display is useless without
1726 * backlight anyway
1727 */
1728#define BACKLIGHT_LVDS_OFF
1729/* That one prevents proper CRT output with LCD off */
1730#undef BACKLIGHT_DAC_OFF
1731
1732static int aty128_bl_update_status(struct backlight_device *bd)
1733{
1734        struct aty128fb_par *par = bl_get_data(bd);
1735        unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1736        int level;
1737
1738        if (bd->props.power != FB_BLANK_UNBLANK ||
1739            bd->props.fb_blank != FB_BLANK_UNBLANK ||
1740            !par->lcd_on)
1741                level = 0;
1742        else
1743                level = bd->props.brightness;
1744
1745        reg |= LVDS_BL_MOD_EN | LVDS_BLON;
1746        if (level > 0) {
1747                reg |= LVDS_DIGION;
1748                if (!(reg & LVDS_ON)) {
1749                        reg &= ~LVDS_BLON;
1750                        aty_st_le32(LVDS_GEN_CNTL, reg);
1751                        aty_ld_le32(LVDS_GEN_CNTL);
1752                        mdelay(10);
1753                        reg |= LVDS_BLON;
1754                        aty_st_le32(LVDS_GEN_CNTL, reg);
1755                }
1756                reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1757                reg |= (aty128_bl_get_level_brightness(par, level) << LVDS_BL_MOD_LEVEL_SHIFT);
1758#ifdef BACKLIGHT_LVDS_OFF
1759                reg |= LVDS_ON | LVDS_EN;
1760                reg &= ~LVDS_DISPLAY_DIS;
1761#endif
1762                aty_st_le32(LVDS_GEN_CNTL, reg);
1763#ifdef BACKLIGHT_DAC_OFF
1764                aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1765#endif
1766        } else {
1767                reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1768                reg |= (aty128_bl_get_level_brightness(par, 0) << LVDS_BL_MOD_LEVEL_SHIFT);
1769#ifdef BACKLIGHT_LVDS_OFF
1770                reg |= LVDS_DISPLAY_DIS;
1771                aty_st_le32(LVDS_GEN_CNTL, reg);
1772                aty_ld_le32(LVDS_GEN_CNTL);
1773                udelay(10);
1774                reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
1775#endif
1776                aty_st_le32(LVDS_GEN_CNTL, reg);
1777#ifdef BACKLIGHT_DAC_OFF
1778                aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1779#endif
1780        }
1781
1782        return 0;
1783}
1784
1785static int aty128_bl_get_brightness(struct backlight_device *bd)
1786{
1787        return bd->props.brightness;
1788}
1789
1790static struct backlight_ops aty128_bl_data = {
1791        .get_brightness = aty128_bl_get_brightness,
1792        .update_status  = aty128_bl_update_status,
1793};
1794
1795static void aty128_bl_set_power(struct fb_info *info, int power)
1796{
1797        if (info->bl_dev) {
1798                info->bl_dev->props.power = power;
1799                backlight_update_status(info->bl_dev);
1800        }
1801}
1802
1803static void aty128_bl_init(struct aty128fb_par *par)
1804{
1805        struct fb_info *info = pci_get_drvdata(par->pdev);
1806        struct backlight_device *bd;
1807        char name[12];
1808
1809        /* Could be extended to Rage128Pro LVDS output too */
1810        if (par->chip_gen != rage_M3)
1811                return;
1812
1813#ifdef CONFIG_PMAC_BACKLIGHT
1814        if (!pmac_has_backlight_type("ati"))
1815                return;
1816#endif
1817
1818        snprintf(name, sizeof(name), "aty128bl%d", info->node);
1819
1820        bd = backlight_device_register(name, info->dev, par, &aty128_bl_data);
1821        if (IS_ERR(bd)) {
1822                info->bl_dev = NULL;
1823                printk(KERN_WARNING "aty128: Backlight registration failed\n");
1824                goto error;
1825        }
1826
1827        info->bl_dev = bd;
1828        fb_bl_default_curve(info, 0,
1829                 63 * FB_BACKLIGHT_MAX / MAX_LEVEL,
1830                219 * FB_BACKLIGHT_MAX / MAX_LEVEL);
1831
1832        bd->props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
1833        bd->props.brightness = bd->props.max_brightness;
1834        bd->props.power = FB_BLANK_UNBLANK;
1835        backlight_update_status(bd);
1836
1837        printk("aty128: Backlight initialized (%s)\n", name);
1838
1839        return;
1840
1841error:
1842        return;
1843}
1844
1845static void aty128_bl_exit(struct backlight_device *bd)
1846{
1847        backlight_device_unregister(bd);
1848        printk("aty128: Backlight unloaded\n");
1849}
1850#endif /* CONFIG_FB_ATY128_BACKLIGHT */
1851
1852/*
1853 *  Initialisation
1854 */
1855
1856#ifdef CONFIG_PPC_PMAC
1857static void aty128_early_resume(void *data)
1858{
1859        struct aty128fb_par *par = data;
1860
1861        if (try_acquire_console_sem())
1862                return;
1863        aty128_do_resume(par->pdev);
1864        release_console_sem();
1865}
1866#endif /* CONFIG_PPC_PMAC */
1867
1868static int __devinit aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1869{
1870        struct fb_info *info = pci_get_drvdata(pdev);
1871        struct aty128fb_par *par = info->par;
1872        struct fb_var_screeninfo var;
1873        char video_card[50];
1874        u8 chip_rev;
1875        u32 dac;
1876
1877        /* Get the chip revision */
1878        chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1879
1880        strcpy(video_card, "Rage128 XX ");
1881        video_card[8] = ent->device >> 8;
1882        video_card[9] = ent->device & 0xFF;
1883
1884        /* range check to make sure */
1885        if (ent->driver_data < ARRAY_SIZE(r128_family))
1886            strlcat(video_card, r128_family[ent->driver_data], sizeof(video_card));
1887
1888        printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1889
1890        if (par->vram_size % (1024 * 1024) == 0)
1891                printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1892        else
1893                printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1894
1895        par->chip_gen = ent->driver_data;
1896
1897        /* fill in info */
1898        info->fbops = &aty128fb_ops;
1899        info->flags = FBINFO_FLAG_DEFAULT;
1900
1901        par->lcd_on = default_lcd_on;
1902        par->crt_on = default_crt_on;
1903
1904        var = default_var;
1905#ifdef CONFIG_PPC_PMAC
1906        if (machine_is(powermac)) {
1907                /* Indicate sleep capability */
1908                if (par->chip_gen == rage_M3) {
1909                        pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1910                        pmac_set_early_video_resume(aty128_early_resume, par);
1911                }
1912
1913                /* Find default mode */
1914                if (mode_option) {
1915                        if (!mac_find_mode(&var, info, mode_option, 8))
1916                                var = default_var;
1917                } else {
1918                        if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1919                                default_vmode = VMODE_1024_768_60;
1920
1921                        /* iMacs need that resolution
1922                         * PowerMac2,1 first r128 iMacs
1923                         * PowerMac2,2 summer 2000 iMacs
1924                         * PowerMac4,1 january 2001 iMacs "flower power"
1925                         */
1926                        if (machine_is_compatible("PowerMac2,1") ||
1927                            machine_is_compatible("PowerMac2,2") ||
1928                            machine_is_compatible("PowerMac4,1"))
1929                                default_vmode = VMODE_1024_768_75;
1930
1931                        /* iBook SE */
1932                        if (machine_is_compatible("PowerBook2,2"))
1933                                default_vmode = VMODE_800_600_60;
1934
1935                        /* PowerBook Firewire (Pismo), iBook Dual USB */
1936                        if (machine_is_compatible("PowerBook3,1") ||
1937                            machine_is_compatible("PowerBook4,1"))
1938                                default_vmode = VMODE_1024_768_60;
1939
1940                        /* PowerBook Titanium */
1941                        if (machine_is_compatible("PowerBook3,2"))
1942                                default_vmode = VMODE_1152_768_60;
1943        
1944                        if (default_cmode > 16) 
1945                            default_cmode = CMODE_32;
1946                        else if (default_cmode > 8) 
1947                            default_cmode = CMODE_16;
1948                        else 
1949                            default_cmode = CMODE_8;
1950
1951                        if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1952                                var = default_var;
1953                }
1954        } else
1955#endif /* CONFIG_PPC_PMAC */
1956        {
1957                if (mode_option)
1958                        if (fb_find_mode(&var, info, mode_option, NULL, 
1959                                         0, &defaultmode, 8) == 0)
1960                                var = default_var;
1961        }
1962
1963        var.accel_flags &= ~FB_ACCELF_TEXT;
1964//      var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
1965
1966        if (aty128fb_check_var(&var, info)) {
1967                printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1968                return 0;
1969        }
1970
1971        /* setup the DAC the way we like it */
1972        dac = aty_ld_le32(DAC_CNTL);
1973        dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
1974        dac |= DAC_MASK;
1975        if (par->chip_gen == rage_M3)
1976                dac |= DAC_PALETTE2_SNOOP_EN;
1977        aty_st_le32(DAC_CNTL, dac);
1978
1979        /* turn off bus mastering, just in case */
1980        aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
1981
1982        info->var = var;
1983        fb_alloc_cmap(&info->cmap, 256, 0);
1984
1985        var.activate = FB_ACTIVATE_NOW;
1986
1987        aty128_init_engine(par);
1988
1989        par->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
1990        par->pdev = pdev;
1991        par->asleep = 0;
1992        par->lock_blank = 0;
1993
1994#ifdef CONFIG_FB_ATY128_BACKLIGHT
1995        if (backlight)
1996                aty128_bl_init(par);
1997#endif
1998
1999        if (register_framebuffer(info) < 0)
2000                return 0;
2001
2002        printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
2003               info->node, info->fix.id, video_card);
2004
2005        return 1;       /* success! */
2006}
2007
2008#ifdef CONFIG_PCI
2009/* register a card    ++ajoshi */
2010static int __devinit aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2011{
2012        unsigned long fb_addr, reg_addr;
2013        struct aty128fb_par *par;
2014        struct fb_info *info;
2015        int err;
2016#ifndef __sparc__
2017        void __iomem *bios = NULL;
2018#endif
2019
2020        /* Enable device in PCI config */
2021        if ((err = pci_enable_device(pdev))) {
2022                printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
2023                                err);
2024                return -ENODEV;
2025        }
2026
2027        fb_addr = pci_resource_start(pdev, 0);
2028        if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
2029                                "aty128fb FB")) {
2030                printk(KERN_ERR "aty128fb: cannot reserve frame "
2031                                "buffer memory\n");
2032                return -ENODEV;
2033        }
2034
2035        reg_addr = pci_resource_start(pdev, 2);
2036        if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
2037                                "aty128fb MMIO")) {
2038                printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
2039                goto err_free_fb;
2040        }
2041
2042        /* We have the resources. Now virtualize them */
2043        info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
2044        if (info == NULL) {
2045                printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
2046                goto err_free_mmio;
2047        }
2048        par = info->par;
2049
2050        info->pseudo_palette = par->pseudo_palette;
2051
2052        /* Virtualize mmio region */
2053        info->fix.mmio_start = reg_addr;
2054        par->regbase = ioremap(reg_addr, pci_resource_len(pdev, 2));
2055        if (!par->regbase)
2056                goto err_free_info;
2057
2058        /* Grab memory size from the card */
2059        // How does this relate to the resource length from the PCI hardware?
2060        par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
2061
2062        /* Virtualize the framebuffer */
2063        info->screen_base = ioremap(fb_addr, par->vram_size);
2064        if (!info->screen_base)
2065                goto err_unmap_out;
2066
2067        /* Set up info->fix */
2068        info->fix = aty128fb_fix;
2069        info->fix.smem_start = fb_addr;
2070        info->fix.smem_len = par->vram_size;
2071        info->fix.mmio_start = reg_addr;
2072
2073        /* If we can't test scratch registers, something is seriously wrong */
2074        if (!register_test(par)) {
2075                printk(KERN_ERR "aty128fb: Can't write to video register!\n");
2076                goto err_out;
2077        }
2078
2079#ifndef __sparc__
2080        bios = aty128_map_ROM(par, pdev);
2081#ifdef CONFIG_X86
2082        if (bios == NULL)
2083                bios = aty128_find_mem_vbios(par);
2084#endif
2085        if (bios == NULL)
2086                printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
2087        else {
2088                printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
2089                aty128_get_pllinfo(par, bios);
2090                pci_unmap_rom(pdev, bios);
2091        }
2092#endif /* __sparc__ */
2093
2094        aty128_timings(par);
2095        pci_set_drvdata(pdev, info);
2096
2097        if (!aty128_init(pdev, ent))
2098                goto err_out;
2099
2100#ifdef CONFIG_MTRR
2101        if (mtrr) {
2102                par->mtrr.vram = mtrr_add(info->fix.smem_start,
2103                                par->vram_size, MTRR_TYPE_WRCOMB, 1);
2104                par->mtrr.vram_valid = 1;
2105                /* let there be speed */
2106                printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
2107        }
2108#endif /* CONFIG_MTRR */
2109        return 0;
2110
2111err_out:
2112        iounmap(info->screen_base);
2113err_unmap_out:
2114        iounmap(par->regbase);
2115err_free_info:
2116        framebuffer_release(info);
2117err_free_mmio:
2118        release_mem_region(pci_resource_start(pdev, 2),
2119                        pci_resource_len(pdev, 2));
2120err_free_fb:
2121        release_mem_region(pci_resource_start(pdev, 0),
2122                        pci_resource_len(pdev, 0));
2123        return -ENODEV;
2124}
2125
2126static void __devexit aty128_remove(struct pci_dev *pdev)
2127{
2128        struct fb_info *info = pci_get_drvdata(pdev);
2129        struct aty128fb_par *par;
2130
2131        if (!info)
2132                return;
2133
2134        par = info->par;
2135
2136        unregister_framebuffer(info);
2137
2138#ifdef CONFIG_FB_ATY128_BACKLIGHT
2139        aty128_bl_exit(info->bl_dev);
2140#endif
2141
2142#ifdef CONFIG_MTRR
2143        if (par->mtrr.vram_valid)
2144                mtrr_del(par->mtrr.vram, info->fix.smem_start,
2145                         par->vram_size);
2146#endif /* CONFIG_MTRR */
2147        iounmap(par->regbase);
2148        iounmap(info->screen_base);
2149
2150        release_mem_region(pci_resource_start(pdev, 0),
2151                           pci_resource_len(pdev, 0));
2152        release_mem_region(pci_resource_start(pdev, 2),
2153                           pci_resource_len(pdev, 2));
2154        framebuffer_release(info);
2155}
2156#endif /* CONFIG_PCI */
2157
2158
2159
2160    /*
2161     *  Blank the display.
2162     */
2163static int aty128fb_blank(int blank, struct fb_info *fb)
2164{
2165        struct aty128fb_par *par = fb->par;
2166        u8 state;
2167
2168        if (par->lock_blank || par->asleep)
2169                return 0;
2170
2171        switch (blank) {
2172        case FB_BLANK_NORMAL:
2173                state = 4;
2174                break;
2175        case FB_BLANK_VSYNC_SUSPEND:
2176                state = 6;
2177                break;
2178        case FB_BLANK_HSYNC_SUSPEND:
2179                state = 5;
2180                break;
2181        case FB_BLANK_POWERDOWN:
2182                state = 7;
2183                break;
2184        case FB_BLANK_UNBLANK:
2185        default:
2186                state = 0;
2187                break;
2188        }
2189        aty_st_8(CRTC_EXT_CNTL+1, state);
2190
2191        if (par->chip_gen == rage_M3) {
2192                aty128_set_crt_enable(par, par->crt_on && !blank);
2193                aty128_set_lcd_enable(par, par->lcd_on && !blank);
2194        }
2195
2196        return 0;
2197}
2198
2199/*
2200 *  Set a single color register. The values supplied are already
2201 *  rounded down to the hardware's capabilities (according to the
2202 *  entries in the var structure). Return != 0 for invalid regno.
2203 */
2204static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2205                              u_int transp, struct fb_info *info)
2206{
2207        struct aty128fb_par *par = info->par;
2208
2209        if (regno > 255
2210            || (par->crtc.depth == 16 && regno > 63)
2211            || (par->crtc.depth == 15 && regno > 31))
2212                return 1;
2213
2214        red >>= 8;
2215        green >>= 8;
2216        blue >>= 8;
2217
2218        if (regno < 16) {
2219                int i;
2220                u32 *pal = info->pseudo_palette;
2221
2222                switch (par->crtc.depth) {
2223                case 15:
2224                        pal[regno] = (regno << 10) | (regno << 5) | regno;
2225                        break;
2226                case 16:
2227                        pal[regno] = (regno << 11) | (regno << 6) | regno;
2228                        break;
2229                case 24:
2230                        pal[regno] = (regno << 16) | (regno << 8) | regno;
2231                        break;
2232                case 32:
2233                        i = (regno << 8) | regno;
2234                        pal[regno] = (i << 16) | i;
2235                        break;
2236                }
2237        }
2238
2239        if (par->crtc.depth == 16 && regno > 0) {
2240                /*
2241                 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2242                 * have 32 slots for R and B values but 64 slots for G values.
2243                 * Thus the R and B values go in one slot but the G value
2244                 * goes in a different slot, and we have to avoid disturbing
2245                 * the other fields in the slots we touch.
2246                 */
2247                par->green[regno] = green;
2248                if (regno < 32) {
2249                        par->red[regno] = red;
2250                        par->blue[regno] = blue;
2251                        aty128_st_pal(regno * 8, red, par->green[regno*2],
2252                                      blue, par);
2253                }
2254                red = par->red[regno/2];
2255                blue = par->blue[regno/2];
2256                regno <<= 2;
2257        } else if (par->crtc.bpp == 16)
2258                regno <<= 3;
2259        aty128_st_pal(regno, red, green, blue, par);
2260
2261        return 0;
2262}
2263
2264#define ATY_MIRROR_LCD_ON       0x00000001
2265#define ATY_MIRROR_CRT_ON       0x00000002
2266
2267/* out param: u32*      backlight value: 0 to 15 */
2268#define FBIO_ATY128_GET_MIRROR  _IOR('@', 1, __u32)
2269/* in param: u32*       backlight value: 0 to 15 */
2270#define FBIO_ATY128_SET_MIRROR  _IOW('@', 2, __u32)
2271
2272static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
2273{
2274        struct aty128fb_par *par = info->par;
2275        u32 value;
2276        int rc;
2277    
2278        switch (cmd) {
2279        case FBIO_ATY128_SET_MIRROR:
2280                if (par->chip_gen != rage_M3)
2281                        return -EINVAL;
2282                rc = get_user(value, (__u32 __user *)arg);
2283                if (rc)
2284                        return rc;
2285                par->lcd_on = (value & 0x01) != 0;
2286                par->crt_on = (value & 0x02) != 0;
2287                if (!par->crt_on && !par->lcd_on)
2288                        par->lcd_on = 1;
2289                aty128_set_crt_enable(par, par->crt_on);        
2290                aty128_set_lcd_enable(par, par->lcd_on);        
2291                return 0;
2292        case FBIO_ATY128_GET_MIRROR:
2293                if (par->chip_gen != rage_M3)
2294                        return -EINVAL;
2295                value = (par->crt_on << 1) | par->lcd_on;
2296                return put_user(value, (__u32 __user *)arg);
2297        }
2298        return -EINVAL;
2299}
2300
2301#if 0
2302    /*
2303     *  Accelerated functions
2304     */
2305
2306static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2307                                   u_int width, u_int height,
2308                                   struct fb_info_aty128 *par)
2309{
2310    u32 save_dp_datatype, save_dp_cntl, dstval;
2311
2312    if (!width || !height)
2313        return;
2314
2315    dstval = depth_to_dst(par->current_par.crtc.depth);
2316    if (dstval == DST_24BPP) {
2317        srcx *= 3;
2318        dstx *= 3;
2319        width *= 3;
2320    } else if (dstval == -EINVAL) {
2321        printk("aty128fb: invalid depth or RGBA\n");
2322        return;
2323    }
2324
2325    wait_for_fifo(2, par);
2326    save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2327    save_dp_cntl     = aty_ld_le32(DP_CNTL);
2328
2329    wait_for_fifo(6, par);
2330    aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2331    aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2332    aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2333    aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2334
2335    aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2336    aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2337
2338    par->blitter_may_be_busy = 1;
2339
2340    wait_for_fifo(2, par);
2341    aty_st_le32(DP_DATATYPE, save_dp_datatype);
2342    aty_st_le32(DP_CNTL, save_dp_cntl); 
2343}
2344
2345
2346    /*
2347     * Text mode accelerated functions
2348     */
2349
2350static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
2351                        int height, int width)
2352{
2353    sx     *= fontwidth(p);
2354    sy     *= fontheight(p);
2355    dx     *= fontwidth(p);
2356    dy     *= fontheight(p);
2357    width  *= fontwidth(p);
2358    height *= fontheight(p);
2359
2360    aty128_rectcopy(sx, sy, dx, dy, width, height,
2361                        (struct fb_info_aty128 *)p->fb_info);
2362}
2363#endif /* 0 */
2364
2365static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2366{
2367        u32     pmgt;
2368        u16     pwr_command;
2369        struct pci_dev *pdev = par->pdev;
2370
2371        if (!par->pm_reg)
2372                return;
2373                
2374        /* Set the chip into the appropriate suspend mode (we use D2,
2375         * D3 would require a complete re-initialisation of the chip,
2376         * including PCI config registers, clocks, AGP configuration, ...)
2377         */
2378        if (suspend) {
2379                /* Make sure CRTC2 is reset. Remove that the day we decide to
2380                 * actually use CRTC2 and replace it with real code for disabling
2381                 * the CRTC2 output during sleep
2382                 */
2383                aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2384                        ~(CRTC2_EN));
2385
2386                /* Set the power management mode to be PCI based */
2387                /* Use this magic value for now */
2388                pmgt = 0x0c005407;
2389                aty_st_pll(POWER_MANAGEMENT, pmgt);
2390                (void)aty_ld_pll(POWER_MANAGEMENT);
2391                aty_st_le32(BUS_CNTL1, 0x00000010);
2392                aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2393                mdelay(100);
2394                pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2395                /* Switch PCI power management to D2 */
2396                pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL,
2397                        (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2);
2398                pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2399        } else {
2400                /* Switch back PCI power management to D0 */
2401                mdelay(100);
2402                pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 0);
2403                pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2404                mdelay(100);
2405        }
2406}
2407
2408static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2409{
2410        struct fb_info *info = pci_get_drvdata(pdev);
2411        struct aty128fb_par *par = info->par;
2412
2413        /* We don't do anything but D2, for now we return 0, but
2414         * we may want to change that. How do we know if the BIOS
2415         * can properly take care of D3 ? Also, with swsusp, we
2416         * know we'll be rebooted, ...
2417         */
2418#ifndef CONFIG_PPC_PMAC
2419        /* HACK ALERT ! Once I find a proper way to say to each driver
2420         * individually what will happen with it's PCI slot, I'll change
2421         * that. On laptops, the AGP slot is just unclocked, so D2 is
2422         * expected, while on desktops, the card is powered off
2423         */
2424        return 0;
2425#endif /* CONFIG_PPC_PMAC */
2426         
2427        if (state.event == pdev->dev.power.power_state.event)
2428                return 0;
2429
2430        printk(KERN_DEBUG "aty128fb: suspending...\n");
2431        
2432        acquire_console_sem();
2433
2434        fb_set_suspend(info, 1);
2435
2436        /* Make sure engine is reset */
2437        wait_for_idle(par);
2438        aty128_reset_engine(par);
2439        wait_for_idle(par);
2440
2441        /* Blank display and LCD */
2442        aty128fb_blank(FB_BLANK_POWERDOWN, info);
2443
2444        /* Sleep */
2445        par->asleep = 1;
2446        par->lock_blank = 1;
2447
2448#ifdef CONFIG_PPC_PMAC
2449        /* On powermac, we have hooks to properly suspend/resume AGP now,
2450         * use them here. We'll ultimately need some generic support here,
2451         * but the generic code isn't quite ready for that yet
2452         */
2453        pmac_suspend_agp_for_card(pdev);
2454#endif /* CONFIG_PPC_PMAC */
2455
2456        /* We need a way to make sure the fbdev layer will _not_ touch the
2457         * framebuffer before we put the chip to suspend state. On 2.4, I
2458         * used dummy fb ops, 2.5 need proper support for this at the
2459         * fbdev level
2460         */
2461        if (state.event != PM_EVENT_ON)
2462                aty128_set_suspend(par, 1);
2463
2464        release_console_sem();
2465
2466        pdev->dev.power.power_state = state;
2467
2468        return 0;
2469}
2470
2471static int aty128_do_resume(struct pci_dev *pdev)
2472{
2473        struct fb_info *info = pci_get_drvdata(pdev);
2474        struct aty128fb_par *par = info->par;
2475
2476        if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2477                return 0;
2478
2479        /* Wakeup chip */
2480        aty128_set_suspend(par, 0);
2481        par->asleep = 0;
2482
2483        /* Restore display & engine */
2484        aty128_reset_engine(par);
2485        wait_for_idle(par);
2486        aty128fb_set_par(info);
2487        fb_pan_display(info, &info->var);
2488        fb_set_cmap(&info->cmap, info);
2489
2490        /* Refresh */
2491        fb_set_suspend(info, 0);
2492
2493        /* Unblank */
2494        par->lock_blank = 0;
2495        aty128fb_blank(0, info);
2496
2497#ifdef CONFIG_PPC_PMAC
2498        /* On powermac, we have hooks to properly suspend/resume AGP now,
2499         * use them here. We'll ultimately need some generic support here,
2500         * but the generic code isn't quite ready for that yet
2501         */
2502        pmac_resume_agp_for_card(pdev);
2503#endif /* CONFIG_PPC_PMAC */
2504
2505        pdev->dev.power.power_state = PMSG_ON;
2506
2507        printk(KERN_DEBUG "aty128fb: resumed !\n");
2508
2509        return 0;
2510}
2511
2512static int aty128_pci_resume(struct pci_dev *pdev)
2513{
2514        int rc;
2515
2516        acquire_console_sem();
2517        rc = aty128_do_resume(pdev);
2518        release_console_sem();
2519
2520        return rc;
2521}
2522
2523
2524static int __devinit aty128fb_init(void)
2525{
2526#ifndef MODULE
2527        char *option = NULL;
2528
2529        if (fb_get_options("aty128fb", &option))
2530                return -ENODEV;
2531        aty128fb_setup(option);
2532#endif
2533
2534        return pci_register_driver(&aty128fb_driver);
2535}
2536
2537static void __exit aty128fb_exit(void)
2538{
2539        pci_unregister_driver(&aty128fb_driver);
2540}
2541
2542module_init(aty128fb_init);
2543
2544module_exit(aty128fb_exit);
2545
2546MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2547MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2548MODULE_LICENSE("GPL");
2549module_param(mode_option, charp, 0);
2550MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2551#ifdef CONFIG_MTRR
2552module_param_named(nomtrr, mtrr, invbool, 0);
2553MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
2554#endif
2555
2556
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