linux/drivers/parisc/dino.c
<<
>>
Prefs
   1/*
   2**      DINO manager
   3**
   4**      (c) Copyright 1999 Red Hat Software
   5**      (c) Copyright 1999 SuSE GmbH
   6**      (c) Copyright 1999,2000 Hewlett-Packard Company
   7**      (c) Copyright 2000 Grant Grundler
   8**      (c) Copyright 2006 Helge Deller
   9**
  10**      This program is free software; you can redistribute it and/or modify
  11**      it under the terms of the GNU General Public License as published by
  12**      the Free Software Foundation; either version 2 of the License, or
  13**      (at your option) any later version.
  14**
  15**      This module provides access to Dino PCI bus (config/IOport spaces)
  16**      and helps manage Dino IRQ lines.
  17**
  18**      Dino interrupt handling is a bit complicated.
  19**      Dino always writes to the broadcast EIR via irr0 for now.
  20**      (BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
  21**      Only one processor interrupt is used for the 11 IRQ line 
  22**      inputs to dino.
  23**
  24**      The different between Built-in Dino and Card-Mode
  25**      dino is in chip initialization and pci device initialization.
  26**
  27**      Linux drivers can only use Card-Mode Dino if pci devices I/O port
  28**      BARs are configured and used by the driver. Programming MMIO address 
  29**      requires substantial knowledge of available Host I/O address ranges
  30**      is currently not supported.  Port/Config accessor functions are the
  31**      same. "BIOS" differences are handled within the existing routines.
  32*/
  33
  34/*      Changes :
  35**      2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
  36**              - added support for the integrated RS232.       
  37*/
  38
  39/*
  40** TODO: create a virtual address for each Dino HPA.
  41**       GSC code might be able to do this since IODC data tells us
  42**       how many pages are used. PCI subsystem could (must?) do this
  43**       for PCI drivers devices which implement/use MMIO registers.
  44*/
  45
  46#include <linux/delay.h>
  47#include <linux/types.h>
  48#include <linux/kernel.h>
  49#include <linux/pci.h>
  50#include <linux/init.h>
  51#include <linux/ioport.h>
  52#include <linux/slab.h>
  53#include <linux/interrupt.h>    /* for struct irqaction */
  54#include <linux/spinlock.h>     /* for spinlock_t and prototypes */
  55
  56#include <asm/pdc.h>
  57#include <asm/page.h>
  58#include <asm/system.h>
  59#include <asm/io.h>
  60#include <asm/hardware.h>
  61
  62#include "gsc.h"
  63
  64#undef DINO_DEBUG
  65
  66#ifdef DINO_DEBUG
  67#define DBG(x...) printk(x)
  68#else
  69#define DBG(x...)
  70#endif
  71
  72/*
  73** Config accessor functions only pass in the 8-bit bus number
  74** and not the 8-bit "PCI Segment" number. Each Dino will be
  75** assigned a PCI bus number based on "when" it's discovered.
  76**
  77** The "secondary" bus number is set to this before calling
  78** pci_scan_bus(). If any PPB's are present, the scan will
  79** discover them and update the "secondary" and "subordinate"
  80** fields in Dino's pci_bus structure.
  81**
  82** Changes in the configuration *will* result in a different
  83** bus number for each dino.
  84*/
  85
  86#define is_card_dino(id)        ((id)->hw_type == HPHW_A_DMA)
  87#define is_cujo(id)             ((id)->hversion == 0x682)
  88
  89#define DINO_IAR0               0x004
  90#define DINO_IODC_ADDR          0x008
  91#define DINO_IODC_DATA_0        0x008
  92#define DINO_IODC_DATA_1        0x008
  93#define DINO_IRR0               0x00C
  94#define DINO_IAR1               0x010
  95#define DINO_IRR1               0x014
  96#define DINO_IMR                0x018
  97#define DINO_IPR                0x01C
  98#define DINO_TOC_ADDR           0x020
  99#define DINO_ICR                0x024
 100#define DINO_ILR                0x028
 101#define DINO_IO_COMMAND         0x030
 102#define DINO_IO_STATUS          0x034
 103#define DINO_IO_CONTROL         0x038
 104#define DINO_IO_GSC_ERR_RESP    0x040
 105#define DINO_IO_ERR_INFO        0x044
 106#define DINO_IO_PCI_ERR_RESP    0x048
 107#define DINO_IO_FBB_EN          0x05c
 108#define DINO_IO_ADDR_EN         0x060
 109#define DINO_PCI_ADDR           0x064
 110#define DINO_CONFIG_DATA        0x068
 111#define DINO_IO_DATA            0x06c
 112#define DINO_MEM_DATA           0x070   /* Dino 3.x only */
 113#define DINO_GSC2X_CONFIG       0x7b4
 114#define DINO_GMASK              0x800
 115#define DINO_PAMR               0x804
 116#define DINO_PAPR               0x808
 117#define DINO_DAMODE             0x80c
 118#define DINO_PCICMD             0x810
 119#define DINO_PCISTS             0x814
 120#define DINO_MLTIM              0x81c
 121#define DINO_BRDG_FEAT          0x820
 122#define DINO_PCIROR             0x824
 123#define DINO_PCIWOR             0x828
 124#define DINO_TLTIM              0x830
 125
 126#define DINO_IRQS 11            /* bits 0-10 are architected */
 127#define DINO_IRR_MASK   0x5ff   /* only 10 bits are implemented */
 128#define DINO_LOCAL_IRQS (DINO_IRQS+1)
 129
 130#define DINO_MASK_IRQ(x)        (1<<(x))
 131
 132#define PCIINTA   0x001
 133#define PCIINTB   0x002
 134#define PCIINTC   0x004
 135#define PCIINTD   0x008
 136#define PCIINTE   0x010
 137#define PCIINTF   0x020
 138#define GSCEXTINT 0x040
 139/* #define xxx       0x080 - bit 7 is "default" */
 140/* #define xxx    0x100 - bit 8 not used */
 141/* #define xxx    0x200 - bit 9 not used */
 142#define RS232INT  0x400
 143
 144struct dino_device
 145{
 146        struct pci_hba_data     hba;    /* 'C' inheritance - must be first */
 147        spinlock_t              dinosaur_pen;
 148        unsigned long           txn_addr; /* EIR addr to generate interrupt */ 
 149        u32                     txn_data; /* EIR data assign to each dino */ 
 150        u32                     imr;      /* IRQ's which are enabled */ 
 151        int                     global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */
 152#ifdef DINO_DEBUG
 153        unsigned int            dino_irr0; /* save most recent IRQ line stat */
 154#endif
 155};
 156
 157/* Looks nice and keeps the compiler happy */
 158#define DINO_DEV(d) ((struct dino_device *) d)
 159
 160
 161/*
 162 * Dino Configuration Space Accessor Functions
 163 */
 164
 165#define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos)))
 166
 167/*
 168 * keep the current highest bus count to assist in allocating busses.  This
 169 * tries to keep a global bus count total so that when we discover an 
 170 * entirely new bus, it can be given a unique bus number.
 171 */
 172static int dino_current_bus = 0;
 173
 174static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where,
 175                int size, u32 *val)
 176{
 177        struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
 178        u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
 179        u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
 180        void __iomem *base_addr = d->hba.base_addr;
 181        unsigned long flags;
 182
 183        DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
 184                                                                        size);
 185        spin_lock_irqsave(&d->dinosaur_pen, flags);
 186
 187        /* tell HW which CFG address */
 188        __raw_writel(v, base_addr + DINO_PCI_ADDR);
 189
 190        /* generate cfg read cycle */
 191        if (size == 1) {
 192                *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3));
 193        } else if (size == 2) {
 194                *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2));
 195        } else if (size == 4) {
 196                *val = readl(base_addr + DINO_CONFIG_DATA);
 197        }
 198
 199        spin_unlock_irqrestore(&d->dinosaur_pen, flags);
 200        return 0;
 201}
 202
 203/*
 204 * Dino address stepping "feature":
 205 * When address stepping, Dino attempts to drive the bus one cycle too soon
 206 * even though the type of cycle (config vs. MMIO) might be different. 
 207 * The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
 208 */
 209static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where,
 210        int size, u32 val)
 211{
 212        struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
 213        u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
 214        u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
 215        void __iomem *base_addr = d->hba.base_addr;
 216        unsigned long flags;
 217
 218        DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
 219                                                                        size);
 220        spin_lock_irqsave(&d->dinosaur_pen, flags);
 221
 222        /* avoid address stepping feature */
 223        __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
 224        __raw_readl(base_addr + DINO_CONFIG_DATA);
 225
 226        /* tell HW which CFG address */
 227        __raw_writel(v, base_addr + DINO_PCI_ADDR);
 228        /* generate cfg read cycle */
 229        if (size == 1) {
 230                writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3));
 231        } else if (size == 2) {
 232                writew(val, base_addr + DINO_CONFIG_DATA + (where & 2));
 233        } else if (size == 4) {
 234                writel(val, base_addr + DINO_CONFIG_DATA);
 235        }
 236
 237        spin_unlock_irqrestore(&d->dinosaur_pen, flags);
 238        return 0;
 239}
 240
 241static struct pci_ops dino_cfg_ops = {
 242        .read =         dino_cfg_read,
 243        .write =        dino_cfg_write,
 244};
 245
 246
 247/*
 248 * Dino "I/O Port" Space Accessor Functions
 249 *
 250 * Many PCI devices don't require use of I/O port space (eg Tulip,
 251 * NCR720) since they export the same registers to both MMIO and
 252 * I/O port space.  Performance is going to stink if drivers use
 253 * I/O port instead of MMIO.
 254 */
 255
 256#define DINO_PORT_IN(type, size, mask) \
 257static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
 258{ \
 259        u##size v; \
 260        unsigned long flags; \
 261        spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
 262        /* tell HW which IO Port address */ \
 263        __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
 264        /* generate I/O PORT read cycle */ \
 265        v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
 266        spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
 267        return v; \
 268}
 269
 270DINO_PORT_IN(b,  8, 3)
 271DINO_PORT_IN(w, 16, 2)
 272DINO_PORT_IN(l, 32, 0)
 273
 274#define DINO_PORT_OUT(type, size, mask) \
 275static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
 276{ \
 277        unsigned long flags; \
 278        spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
 279        /* tell HW which IO port address */ \
 280        __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
 281        /* generate cfg write cycle */ \
 282        write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
 283        spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
 284}
 285
 286DINO_PORT_OUT(b,  8, 3)
 287DINO_PORT_OUT(w, 16, 2)
 288DINO_PORT_OUT(l, 32, 0)
 289
 290struct pci_port_ops dino_port_ops = {
 291        .inb    = dino_in8,
 292        .inw    = dino_in16,
 293        .inl    = dino_in32,
 294        .outb   = dino_out8,
 295        .outw   = dino_out16,
 296        .outl   = dino_out32
 297};
 298
 299static void dino_disable_irq(unsigned int irq)
 300{
 301        struct irq_desc *desc = irq_to_desc(irq);
 302        struct dino_device *dino_dev = desc->chip_data;
 303        int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
 304
 305        DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, irq);
 306
 307        /* Clear the matching bit in the IMR register */
 308        dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq));
 309        __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
 310}
 311
 312static void dino_enable_irq(unsigned int irq)
 313{
 314        struct irq_desc *desc = irq_to_desc(irq);
 315        struct dino_device *dino_dev = desc->chip_data;
 316        int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
 317        u32 tmp;
 318
 319        DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, irq);
 320
 321        /*
 322        ** clear pending IRQ bits
 323        **
 324        ** This does NOT change ILR state!
 325        ** See comment below for ILR usage.
 326        */
 327        __raw_readl(dino_dev->hba.base_addr+DINO_IPR);
 328
 329        /* set the matching bit in the IMR register */
 330        dino_dev->imr |= DINO_MASK_IRQ(local_irq);      /* used in dino_isr() */
 331        __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
 332
 333        /* Emulate "Level Triggered" Interrupt
 334        ** Basically, a driver is blowing it if the IRQ line is asserted
 335        ** while the IRQ is disabled.  But tulip.c seems to do that....
 336        ** Give 'em a kluge award and a nice round of applause!
 337        **
 338        ** The gsc_write will generate an interrupt which invokes dino_isr().
 339        ** dino_isr() will read IPR and find nothing. But then catch this
 340        ** when it also checks ILR.
 341        */
 342        tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR);
 343        if (tmp & DINO_MASK_IRQ(local_irq)) {
 344                DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n",
 345                                __func__, tmp);
 346                gsc_writel(dino_dev->txn_data, dino_dev->txn_addr);
 347        }
 348}
 349
 350static unsigned int dino_startup_irq(unsigned int irq)
 351{
 352        dino_enable_irq(irq);
 353        return 0;
 354}
 355
 356static struct hw_interrupt_type dino_interrupt_type = {
 357        .typename       = "GSC-PCI",
 358        .startup        = dino_startup_irq,
 359        .shutdown       = dino_disable_irq,
 360        .enable         = dino_enable_irq, 
 361        .disable        = dino_disable_irq,
 362        .ack            = no_ack_irq,
 363        .end            = no_end_irq,
 364};
 365
 366
 367/*
 368 * Handle a Processor interrupt generated by Dino.
 369 *
 370 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
 371 * wedging the CPU. Could be removed or made optional at some point.
 372 */
 373static irqreturn_t dino_isr(int irq, void *intr_dev)
 374{
 375        struct dino_device *dino_dev = intr_dev;
 376        u32 mask;
 377        int ilr_loop = 100;
 378
 379        /* read and acknowledge pending interrupts */
 380#ifdef DINO_DEBUG
 381        dino_dev->dino_irr0 =
 382#endif
 383        mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
 384
 385        if (mask == 0)
 386                return IRQ_NONE;
 387
 388ilr_again:
 389        do {
 390                int local_irq = __ffs(mask);
 391                int irq = dino_dev->global_irq[local_irq];
 392                DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n",
 393                        __func__, irq, intr_dev, mask);
 394                __do_IRQ(irq);
 395                mask &= ~(1 << local_irq);
 396        } while (mask);
 397
 398        /* Support for level triggered IRQ lines.
 399        ** 
 400        ** Dropping this support would make this routine *much* faster.
 401        ** But since PCI requires level triggered IRQ line to share lines...
 402        ** device drivers may assume lines are level triggered (and not
 403        ** edge triggered like EISA/ISA can be).
 404        */
 405        mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
 406        if (mask) {
 407                if (--ilr_loop > 0)
 408                        goto ilr_again;
 409                printk(KERN_ERR "Dino 0x%p: stuck interrupt %d\n", 
 410                       dino_dev->hba.base_addr, mask);
 411                return IRQ_NONE;
 412        }
 413        return IRQ_HANDLED;
 414}
 415
 416static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp)
 417{
 418        int irq = gsc_assign_irq(&dino_interrupt_type, dino);
 419        if (irq == NO_IRQ)
 420                return;
 421
 422        *irqp = irq;
 423        dino->global_irq[local_irq] = irq;
 424}
 425
 426static void dino_choose_irq(struct parisc_device *dev, void *ctrl)
 427{
 428        int irq;
 429        struct dino_device *dino = ctrl;
 430
 431        switch (dev->id.sversion) {
 432                case 0x00084:   irq =  8; break; /* PS/2 */
 433                case 0x0008c:   irq = 10; break; /* RS232 */
 434                case 0x00096:   irq =  8; break; /* PS/2 */
 435                default:        return;          /* Unknown */
 436        }
 437
 438        dino_assign_irq(dino, irq, &dev->irq);
 439}
 440
 441
 442/*
 443 * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de)
 444 * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...)
 445 */
 446static void __devinit quirk_cirrus_cardbus(struct pci_dev *dev)
 447{
 448        u8 new_irq = dev->irq - 1;
 449        printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n",
 450                        pci_name(dev), dev->irq, new_irq);
 451        dev->irq = new_irq;
 452}
 453DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus );
 454
 455
 456static void __init
 457dino_bios_init(void)
 458{
 459        DBG("dino_bios_init\n");
 460}
 461
 462/*
 463 * dino_card_setup - Set up the memory space for a Dino in card mode.
 464 * @bus: the bus under this dino
 465 *
 466 * Claim an 8MB chunk of unused IO space and call the generic PCI routines
 467 * to set up the addresses of the devices on this bus.
 468 */
 469#define _8MB 0x00800000UL
 470static void __init
 471dino_card_setup(struct pci_bus *bus, void __iomem *base_addr)
 472{
 473        int i;
 474        struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
 475        struct resource *res;
 476        char name[128];
 477        int size;
 478
 479        res = &dino_dev->hba.lmmio_space;
 480        res->flags = IORESOURCE_MEM;
 481        size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", 
 482                         bus->bridge->bus_id);
 483        res->name = kmalloc(size+1, GFP_KERNEL);
 484        if(res->name)
 485                strcpy((char *)res->name, name);
 486        else
 487                res->name = dino_dev->hba.lmmio_space.name;
 488        
 489
 490        if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB,
 491                                F_EXTEND(0xf0000000UL) | _8MB,
 492                                F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) {
 493                struct list_head *ln, *tmp_ln;
 494
 495                printk(KERN_ERR "Dino: cannot attach bus %s\n",
 496                       bus->bridge->bus_id);
 497                /* kill the bus, we can't do anything with it */
 498                list_for_each_safe(ln, tmp_ln, &bus->devices) {
 499                        struct pci_dev *dev = pci_dev_b(ln);
 500
 501                        list_del(&dev->bus_list);
 502                }
 503                        
 504                return;
 505        }
 506        bus->resource[1] = res;
 507        bus->resource[0] = &(dino_dev->hba.io_space);
 508
 509        /* Now tell dino what range it has */
 510        for (i = 1; i < 31; i++) {
 511                if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB)))
 512                        break;
 513        }
 514        DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n",
 515            i, res->start, base_addr + DINO_IO_ADDR_EN);
 516        __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
 517}
 518
 519static void __init
 520dino_card_fixup(struct pci_dev *dev)
 521{
 522        u32 irq_pin;
 523
 524        /*
 525        ** REVISIT: card-mode PCI-PCI expansion chassis do exist.
 526        **         Not sure they were ever productized.
 527        **         Die here since we'll die later in dino_inb() anyway.
 528        */
 529        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 530                panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
 531        }
 532
 533        /*
 534        ** Set Latency Timer to 0xff (not a shared bus)
 535        ** Set CACHELINE_SIZE.
 536        */
 537        dino_cfg_write(dev->bus, dev->devfn, 
 538                       PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4); 
 539
 540        /*
 541        ** Program INT_LINE for card-mode devices.
 542        ** The cards are hardwired according to this algorithm.
 543        ** And it doesn't matter if PPB's are present or not since
 544        ** the IRQ lines bypass the PPB.
 545        **
 546        ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
 547        ** The additional "-1" adjusts for skewing the IRQ<->slot.
 548        */
 549        dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin); 
 550        dev->irq = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ;
 551
 552        /* Shouldn't really need to do this but it's in case someone tries
 553        ** to bypass PCI services and look at the card themselves.
 554        */
 555        dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq); 
 556}
 557
 558/* The alignment contraints for PCI bridges under dino */
 559#define DINO_BRIDGE_ALIGN 0x100000
 560
 561
 562static void __init
 563dino_fixup_bus(struct pci_bus *bus)
 564{
 565        struct list_head *ln;
 566        struct pci_dev *dev;
 567        struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
 568        int port_base = HBA_PORT_BASE(dino_dev->hba.hba_num);
 569
 570        DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n",
 571            __func__, bus, bus->secondary,
 572            bus->bridge->platform_data);
 573
 574        /* Firmware doesn't set up card-mode dino, so we have to */
 575        if (is_card_dino(&dino_dev->hba.dev->id)) {
 576                dino_card_setup(bus, dino_dev->hba.base_addr);
 577        } else if(bus->parent == NULL) {
 578                /* must have a dino above it, reparent the resources
 579                 * into the dino window */
 580                int i;
 581                struct resource *res = &dino_dev->hba.lmmio_space;
 582
 583                bus->resource[0] = &(dino_dev->hba.io_space);
 584                for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
 585                        if(res[i].flags == 0)
 586                                break;
 587                        bus->resource[i+1] = &res[i];
 588                }
 589
 590        } else if(bus->self) {
 591                int i;
 592
 593                pci_read_bridge_bases(bus);
 594
 595
 596                for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
 597                        if((bus->self->resource[i].flags & 
 598                            (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
 599                                continue;
 600                        
 601                        if(bus->self->resource[i].flags & IORESOURCE_MEM) {
 602                                /* There's a quirk to alignment of
 603                                 * bridge memory resources: the start
 604                                 * is the alignment and start-end is
 605                                 * the size.  However, firmware will
 606                                 * have assigned start and end, so we
 607                                 * need to take this into account */
 608                                bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN;
 609                                bus->self->resource[i].start = DINO_BRIDGE_ALIGN;
 610                                
 611                        }
 612                                        
 613                        DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n",
 614                            bus->self->dev.bus_id, i,
 615                            bus->self->resource[i].start,
 616                            bus->self->resource[i].end);
 617                        pci_assign_resource(bus->self, i);
 618                        DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n",
 619                            bus->self->dev.bus_id, i,
 620                            bus->self->resource[i].start,
 621                            bus->self->resource[i].end);
 622                }
 623        }
 624
 625
 626        list_for_each(ln, &bus->devices) {
 627                int i;
 628
 629                dev = pci_dev_b(ln);
 630                if (is_card_dino(&dino_dev->hba.dev->id))
 631                        dino_card_fixup(dev);
 632
 633                /*
 634                ** P2PB's only have 2 BARs, no IRQs.
 635                ** I'd like to just ignore them for now.
 636                */
 637                if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
 638                        continue;
 639
 640                /* Adjust the I/O Port space addresses */
 641                for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 642                        struct resource *res = &dev->resource[i];
 643                        if (res->flags & IORESOURCE_IO) {
 644                                res->start |= port_base;
 645                                res->end |= port_base;
 646                        }
 647#ifdef __LP64__
 648                        /* Sign Extend MMIO addresses */
 649                        else if (res->flags & IORESOURCE_MEM) {
 650                                res->start |= F_EXTEND(0UL);
 651                                res->end   |= F_EXTEND(0UL);
 652                        }
 653#endif
 654                }
 655                /* null out the ROM resource if there is one (we don't
 656                 * care about an expansion rom on parisc, since it
 657                 * usually contains (x86) bios code) */
 658                dev->resource[PCI_ROM_RESOURCE].flags = 0;
 659                                
 660                if(dev->irq == 255) {
 661
 662#define DINO_FIX_UNASSIGNED_INTERRUPTS
 663#ifdef DINO_FIX_UNASSIGNED_INTERRUPTS
 664
 665                        /* This code tries to assign an unassigned
 666                         * interrupt.  Leave it disabled unless you
 667                         * *really* know what you're doing since the
 668                         * pin<->interrupt line mapping varies by bus
 669                         * and machine */
 670
 671                        u32 irq_pin;
 672                        
 673                        dino_cfg_read(dev->bus, dev->devfn, 
 674                                      PCI_INTERRUPT_PIN, 1, &irq_pin);
 675                        irq_pin = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ;
 676                        printk(KERN_WARNING "Device %s has undefined IRQ, "
 677                                        "setting to %d\n", pci_name(dev), irq_pin);
 678                        dino_cfg_write(dev->bus, dev->devfn, 
 679                                       PCI_INTERRUPT_LINE, 1, irq_pin);
 680                        dino_assign_irq(dino_dev, irq_pin, &dev->irq);
 681#else
 682                        dev->irq = 65535;
 683                        printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev));
 684#endif
 685                } else {
 686                        /* Adjust INT_LINE for that busses region */
 687                        dino_assign_irq(dino_dev, dev->irq, &dev->irq);
 688                }
 689        }
 690}
 691
 692
 693struct pci_bios_ops dino_bios_ops = {
 694        .init           = dino_bios_init,
 695        .fixup_bus      = dino_fixup_bus
 696};
 697
 698
 699/*
 700 *      Initialise a DINO controller chip
 701 */
 702static void __init
 703dino_card_init(struct dino_device *dino_dev)
 704{
 705        u32 brdg_feat = 0x00784e05;
 706        unsigned long status;
 707
 708        status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS);
 709        if (status & 0x0000ff80) {
 710                __raw_writel(0x00000005,
 711                                dino_dev->hba.base_addr+DINO_IO_COMMAND);
 712                udelay(1);
 713        }
 714
 715        __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
 716        __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
 717        __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
 718
 719#if 1
 720/* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
 721        /*
 722        ** PCX-L processors don't support XQL like Dino wants it.
 723        ** PCX-L2 ignore XQL signal and it doesn't matter.
 724        */
 725        brdg_feat &= ~0x4;      /* UXQL */
 726#endif
 727        __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
 728
 729        /*
 730        ** Don't enable address decoding until we know which I/O range
 731        ** currently is available from the host. Only affects MMIO
 732        ** and not I/O port space.
 733        */
 734        __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
 735
 736        __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
 737        __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
 738        __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
 739
 740        __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
 741        __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
 742        __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
 743
 744        /* Disable PAMR before writing PAPR */
 745        __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
 746        __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
 747        __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
 748
 749        /*
 750        ** Dino ERS encourages enabling FBB (0x6f).
 751        ** We can't until we know *all* devices below us can support it.
 752        ** (Something in device configuration header tells us).
 753        */
 754        __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
 755
 756        /* Somewhere, the PCI spec says give devices 1 second
 757        ** to recover from the #RESET being de-asserted.
 758        ** Experience shows most devices only need 10ms.
 759        ** This short-cut speeds up booting significantly.
 760        */
 761        mdelay(pci_post_reset_delay);
 762}
 763
 764static int __init
 765dino_bridge_init(struct dino_device *dino_dev, const char *name)
 766{
 767        unsigned long io_addr;
 768        int result, i, count=0;
 769        struct resource *res, *prevres = NULL;
 770        /*
 771         * Decoding IO_ADDR_EN only works for Built-in Dino
 772         * since PDC has already initialized this.
 773         */
 774
 775        io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
 776        if (io_addr == 0) {
 777                printk(KERN_WARNING "%s: No PCI devices enabled.\n", name);
 778                return -ENODEV;
 779        }
 780
 781        res = &dino_dev->hba.lmmio_space;
 782        for (i = 0; i < 32; i++) {
 783                unsigned long start, end;
 784
 785                if((io_addr & (1 << i)) == 0)
 786                        continue;
 787
 788                start = F_EXTEND(0xf0000000UL) | (i << 23);
 789                end = start + 8 * 1024 * 1024 - 1;
 790
 791                DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count,
 792                    start, end);
 793
 794                if(prevres && prevres->end + 1 == start) {
 795                        prevres->end = end;
 796                } else {
 797                        if(count >= DINO_MAX_LMMIO_RESOURCES) {
 798                                printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end);
 799                                break;
 800                        }
 801                        prevres = res;
 802                        res->start = start;
 803                        res->end = end;
 804                        res->flags = IORESOURCE_MEM;
 805                        res->name = kmalloc(64, GFP_KERNEL);
 806                        if(res->name)
 807                                snprintf((char *)res->name, 64, "%s LMMIO %d",
 808                                         name, count);
 809                        res++;
 810                        count++;
 811                }
 812        }
 813
 814        res = &dino_dev->hba.lmmio_space;
 815
 816        for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
 817                if(res[i].flags == 0)
 818                        break;
 819
 820                result = ccio_request_resource(dino_dev->hba.dev, &res[i]);
 821                if (result < 0) {
 822                        printk(KERN_ERR "%s: failed to claim PCI Bus address space %d (0x%lx-0x%lx)!\n", name, i, res[i].start, res[i].end);
 823                        return result;
 824                }
 825        }
 826        return 0;
 827}
 828
 829static int __init dino_common_init(struct parisc_device *dev,
 830                struct dino_device *dino_dev, const char *name)
 831{
 832        int status;
 833        u32 eim;
 834        struct gsc_irq gsc_irq;
 835        struct resource *res;
 836
 837        pcibios_register_hba(&dino_dev->hba);
 838
 839        pci_bios = &dino_bios_ops;   /* used by pci_scan_bus() */
 840        pci_port = &dino_port_ops;
 841
 842        /*
 843        ** Note: SMP systems can make use of IRR1/IAR1 registers
 844        **   But it won't buy much performance except in very
 845        **   specific applications/configurations. Note Dino
 846        **   still only has 11 IRQ input lines - just map some of them
 847        **   to a different processor.
 848        */
 849        dev->irq = gsc_alloc_irq(&gsc_irq);
 850        dino_dev->txn_addr = gsc_irq.txn_addr;
 851        dino_dev->txn_data = gsc_irq.txn_data;
 852        eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data;
 853
 854        /* 
 855        ** Dino needs a PA "IRQ" to get a processor's attention.
 856        ** arch/parisc/kernel/irq.c returns an EIRR bit.
 857        */
 858        if (dev->irq < 0) {
 859                printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name);
 860                return 1;
 861        }
 862
 863        status = request_irq(dev->irq, dino_isr, 0, name, dino_dev);
 864        if (status) {
 865                printk(KERN_WARNING "%s: request_irq() failed with %d\n", 
 866                        name, status);
 867                return 1;
 868        }
 869
 870        /* Support the serial port which is sometimes attached on built-in
 871         * Dino / Cujo chips.
 872         */
 873
 874        gsc_fixup_irqs(dev, dino_dev, dino_choose_irq);
 875
 876        /*
 877        ** This enables DINO to generate interrupts when it sees
 878        ** any of its inputs *change*. Just asserting an IRQ
 879        ** before it's enabled (ie unmasked) isn't good enough.
 880        */
 881        __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
 882
 883        /*
 884        ** Some platforms don't clear Dino's IRR0 register at boot time.
 885        ** Reading will clear it now.
 886        */
 887        __raw_readl(dino_dev->hba.base_addr+DINO_IRR0);
 888
 889        /* allocate I/O Port resource region */
 890        res = &dino_dev->hba.io_space;
 891        if (!is_cujo(&dev->id)) {
 892                res->name = "Dino I/O Port";
 893        } else {
 894                res->name = "Cujo I/O Port";
 895        }
 896        res->start = HBA_PORT_BASE(dino_dev->hba.hba_num);
 897        res->end = res->start + (HBA_PORT_SPACE_SIZE - 1);
 898        res->flags = IORESOURCE_IO; /* do not mark it busy ! */
 899        if (request_resource(&ioport_resource, res) < 0) {
 900                printk(KERN_ERR "%s: request I/O Port region failed "
 901                       "0x%lx/%lx (hpa 0x%p)\n",
 902                       name, res->start, res->end, dino_dev->hba.base_addr);
 903                return 1;
 904        }
 905
 906        return 0;
 907}
 908
 909#define CUJO_RAVEN_ADDR         F_EXTEND(0xf1000000UL)
 910#define CUJO_FIREHAWK_ADDR      F_EXTEND(0xf1604000UL)
 911#define CUJO_RAVEN_BADPAGE      0x01003000UL
 912#define CUJO_FIREHAWK_BADPAGE   0x01607000UL
 913
 914static const char *dino_vers[] = {
 915        "2.0",
 916        "2.1",
 917        "3.0",
 918        "3.1"
 919};
 920
 921static const char *cujo_vers[] = {
 922        "1.0",
 923        "2.0"
 924};
 925
 926void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp);
 927
 928/*
 929** Determine if dino should claim this chip (return 0) or not (return 1).
 930** If so, initialize the chip appropriately (card-mode vs bridge mode).
 931** Much of the initialization is common though.
 932*/
 933static int __init dino_probe(struct parisc_device *dev)
 934{
 935        struct dino_device *dino_dev;   // Dino specific control struct
 936        const char *version = "unknown";
 937        char *name;
 938        int is_cujo = 0;
 939        struct pci_bus *bus;
 940        unsigned long hpa = dev->hpa.start;
 941
 942        name = "Dino";
 943        if (is_card_dino(&dev->id)) {
 944                version = "3.x (card mode)";
 945        } else {
 946                if (!is_cujo(&dev->id)) {
 947                        if (dev->id.hversion_rev < 4) {
 948                                version = dino_vers[dev->id.hversion_rev];
 949                        }
 950                } else {
 951                        name = "Cujo";
 952                        is_cujo = 1;
 953                        if (dev->id.hversion_rev < 2) {
 954                                version = cujo_vers[dev->id.hversion_rev];
 955                        }
 956                }
 957        }
 958
 959        printk("%s version %s found at 0x%lx\n", name, version, hpa);
 960
 961        if (!request_mem_region(hpa, PAGE_SIZE, name)) {
 962                printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%ld)!\n",
 963                        hpa);
 964                return 1;
 965        }
 966
 967        /* Check for bugs */
 968        if (is_cujo && dev->id.hversion_rev == 1) {
 969#ifdef CONFIG_IOMMU_CCIO
 970                printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n");
 971                if (hpa == (unsigned long)CUJO_RAVEN_ADDR) {
 972                        ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE);
 973                } else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) {
 974                        ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE);
 975                } else {
 976                        printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa);
 977                }
 978#endif
 979        } else if (!is_cujo && !is_card_dino(&dev->id) &&
 980                        dev->id.hversion_rev < 3) {
 981                printk(KERN_WARNING
 982"The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
 983"data corruption.  See Service Note Numbers: A4190A-01, A4191A-01.\n"
 984"Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
 985"Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
 986                        dev->id.hversion_rev);
 987/* REVISIT: why are C200/C240 listed in the README table but not
 988**   "Models affected"? Could be an omission in the original literature.
 989*/
 990        }
 991
 992        dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL);
 993        if (!dino_dev) {
 994                printk("dino_init_chip - couldn't alloc dino_device\n");
 995                return 1;
 996        }
 997
 998        dino_dev->hba.dev = dev;
 999        dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096);
1000        dino_dev->hba.lmmio_space_offset = 0;   /* CPU addrs == bus addrs */
1001        spin_lock_init(&dino_dev->dinosaur_pen);
1002        dino_dev->hba.iommu = ccio_get_iommu(dev);
1003
1004        if (is_card_dino(&dev->id)) {
1005                dino_card_init(dino_dev);
1006        } else {
1007                dino_bridge_init(dino_dev, name);
1008        }
1009
1010        if (dino_common_init(dev, dino_dev, name))
1011                return 1;
1012
1013        dev->dev.platform_data = dino_dev;
1014
1015        /*
1016        ** It's not used to avoid chicken/egg problems
1017        ** with configuration accessor functions.
1018        */
1019        bus = pci_scan_bus_parented(&dev->dev, dino_current_bus,
1020                                    &dino_cfg_ops, NULL);
1021        if(bus) {
1022                pci_bus_add_devices(bus);
1023                /* This code *depends* on scanning being single threaded
1024                 * if it isn't, this global bus number count will fail
1025                 */
1026                dino_current_bus = bus->subordinate + 1;
1027                pci_bus_assign_resources(bus);
1028        } else {
1029                printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (probably duplicate bus number %d)\n", dev->dev.bus_id, dino_current_bus);
1030                /* increment the bus number in case of duplicates */
1031                dino_current_bus++;
1032        }
1033        dino_dev->hba.hba_bus = bus;
1034        return 0;
1035}
1036
1037/*
1038 * Normally, we would just test sversion.  But the Elroy PCI adapter has
1039 * the same sversion as Dino, so we have to check hversion as well.
1040 * Unfortunately, the J2240 PDC reports the wrong hversion for the first
1041 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
1042 * For card-mode Dino, most machines report an sversion of 9D.  But 715
1043 * and 725 firmware misreport it as 0x08080 for no adequately explained
1044 * reason.
1045 */
1046static struct parisc_device_id dino_tbl[] = {
1047        { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */
1048        { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */
1049        { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */
1050        { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */
1051        { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */
1052        { 0, }
1053};
1054
1055static struct parisc_driver dino_driver = {
1056        .name =         "dino",
1057        .id_table =     dino_tbl,
1058        .probe =        dino_probe,
1059};
1060
1061/*
1062 * One time initialization to let the world know Dino is here.
1063 * This is the only routine which is NOT static.
1064 * Must be called exactly once before pci_init().
1065 */
1066int __init dino_init(void)
1067{
1068        register_parisc_driver(&dino_driver);
1069        return 0;
1070}
1071
1072
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.